CN106024036A - FPGA-based multi-channel audio data format conversion method - Google Patents
FPGA-based multi-channel audio data format conversion method Download PDFInfo
- Publication number
- CN106024036A CN106024036A CN201610316969.9A CN201610316969A CN106024036A CN 106024036 A CN106024036 A CN 106024036A CN 201610316969 A CN201610316969 A CN 201610316969A CN 106024036 A CN106024036 A CN 106024036A
- Authority
- CN
- China
- Prior art keywords
- fpga
- data
- write
- conversion method
- shift registers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10527—Audio or video recording; Data buffering arrangements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10527—Audio or video recording; Data buffering arrangements
- G11B2020/10537—Audio or video recording
- G11B2020/10592—Audio or video recording specifically adapted for recording or reproducing multichannel signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10527—Audio or video recording; Data buffering arrangements
- G11B2020/1062—Data buffering arrangements, e.g. recording or playback buffers
- G11B2020/10675—Data buffering arrangements, e.g. recording or playback buffers aspects of buffer control
- G11B2020/10685—Data buffering arrangements, e.g. recording or playback buffers aspects of buffer control input interface, i.e. the way data enter the buffer, e.g. by informing the sender that the buffer is busy
Abstract
The invention discloses an FPGA-based multi-channel audio data format conversion method. A device for implementing the conversion method comprises an FPGA, and a processor and at least two audio chips in communication connection with the FPGA. The FPGA receives multiple channels of serial audio data output by the audio chips, converts the serial audio data into parallel audio data, and sends the parallel audio data to the processor. The audio chips carry out analog-to-digital conversion under control of the FPGA in order to output multiple channels of serial audio data. According to the invention, an FPGA is used to complete audio data collection, processing and conversion, the method is easy to implement, and the problem that the processor has insufficient chip channels and cannot collect or process multiple channels of audio data in the prior art is overcome.
Description
Technical field
The present invention relates to voice data format conversion techniques field, be specifically related to a kind of based on FPGA
Multi-path audio-frequency data format conversion method.
Background technology
The expansion technique traditional method of audio interface is to utilize discrete component to be extended, i.e. according to system
Requirement draw the logical relation between each signal, by simplifying methods such as karnaugh method by system
Turn to the simplest, then according to the simplest logical expression by control signal, shift register, trigger,
The discrete component such as enumerator forms, and is finally integrated into complete system.
The shortcoming of above way is that circuit structure is complicated, cost high, power consumption is big, very flexible, stable
Property is poor, simultaneously because be connected with each other in the way of wire between discrete component so that the work of whole system
Working frequency is restricted, it is impossible to meet the requirement of Modern High-Speed digital circuit, so using discrete component
The scheme designing Audio Data Acquisition System is faded out the visual field of people the most gradually.
The most advanced technological means is to carry out the extension of audio interface by logic development and protect
Demonstrate,prove its performance, i.e. use field programmable gate array (Field Programmable Gate Array,
FPGA) as the hardware carrier of design, develop by special design tool.
FPGA occurs as a kind of semi-custom circuit in special IC field, has programming spirit
Live, integrated level is high, the cycle of designing and developing is short, scope of application width, developing instrument are advanced, manufacture and design
Low cost, standardized product low to the hardware skill requirement of designer are without test, strong security, valency
The features such as lattice are popular, had both solved the deficiency of custom circuit, had overcome again original programming device door
The shortcoming that circuit number is limited, is that small lot system improves level of integrated system, reliability and motility
One of good selection.
In prior art, the processor chips number of channel is not enough, it is impossible to realize multi-path audio-frequency data collection.
Summary of the invention
The invention provides a kind of multi-path audio-frequency data format conversion method based on FPGA, overcome existing
There is the processor chips number of channel in technology not enough, it is impossible to realize asking of multi-path audio-frequency data acquisition process
Topic.
A kind of multi-path audio-frequency data format conversion method based on FPGA, it is achieved described conversion method
Device includes FPGA and the processor communicated to connect with FPGA and at least two audio chip, described
FPGA receives the multi-path audio-frequency data of the serial form of audio chip output, by the audio frequency of serial form
After data are converted to the voice data of parallel form, send to processor.
Use the voice data format conversion method that the present invention provides, it is possible to realize multi-path audio-frequency data
Form is changed, and efficiency is high, and stable and reliable in work.In the present invention, audio chip is exported by FPGA
The multi-path audio-frequency data of serial form be converted to the voice data of parallel form by road, and be buffered in
In FPGA, it is then sent to processor and does the process of further voice data.
FPGA controls audio chip and carries out analog digital conversion, to export the multi-path audio-frequency data of serial form.
FPGA includes the two-port RAM for caching parallel form voice data, and FPGA controls dual-port
The reading of parallel form voice data and write in RAM.
As preferably, the voice data of parallel form is write in two-port RAM by FPGA, simultaneously to
Processor sends interrupt signal, has no progeny in processor response, and FPGA is by lattice parallel in two-port RAM
The voice data of formula sends to processor.
As preferably, the voice data of serial form is converted to parallel form voice data time,
With the monocycle of serial form data output clock for operation beat, using channel selecting clock as data
Logic with shift enters left channel data flow process or the foundation of right channel data flow process.
As preferably, FPGA arranges N number of left channel shift registers for left channel data flow process, for
Right channel data flow process arranges N number of right channel shift registers, when ws signal level height, by WS
N number of channel data serial bit after signal saltus step moves into left channel shift registers, and left channel shift is posted
When data expire in storage, reset left channel shift enabler flags, retain current registrar data, wait
In the two-port RAM of write FPGA；
When ws signal level is low, the N number of channel data serial bit after ws signal saltus step is moved into the right side
Channel shift registers, when data expire in right channel shift registers, resets right channel shift and enables
Mark, retains current registrar data, waits in the two-port RAM of FPGA to be written.
The quantity of left channel shift registers and right channel shift registers can be selected as required
Select.Ws signal is the signal that low and high level is spaced apart, the distribution frequency of low and high level and height
Value is provided by audio chip, and high level and low level according to ws signal select left and right passage number
According to process.
As preferably, the write of two-port RAM controls with monocycle of analog digital conversion work clock for behaviour
Make beat, enter left channel data write flow process or the right side using channel selecting clock as data write logic
The foundation of channel data write flow process.
As preferably, when ws signal level is low, post being deposited with left channel shift before ws signal saltus step
In data write two-port RAM in storage, when data all in left channel shift registers complete to write
After entering, reset left passage write enabler flags, forbid that left channel data writes；
During ws signal level height, it is deposited with the number in right channel shift registers by before ws signal saltus step
According in write two-port RAM, after data all in right channel shift registers complete write, reset
Right passage write enabler flags, forbids that right channel data writes.
The present invention uses FPGA to complete the collection of voice data, process and change, it is easy to accomplish, and
The processor chips number of channel in prior art can be overcome not enough, it is impossible to realize multi-path audio-frequency data collection
The problem processed.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of present invention multi-path audio-frequency data based on FPGA format conversion apparatus；
Fig. 2 is the operational flowchart of serioparallel exchange of the present invention；
Fig. 3 is the operational flowchart of two-port RAM of the present invention write.
Detailed description of the invention
Multi-path audio-frequency data format conversion method based on FPGA to the present invention enters below in conjunction with the accompanying drawings
Row describes in detail.
As it is shown in figure 1, multi-path audio-frequency data format conversion apparatus based on FPGA include FPGA with
And with FPGA communication connection multiple audio chips and a processor, the audio frequency core in FPGA
Sheet controller sends control signal and clock signal to audio chip, controls the data of MCVF multichannel voice frequency chip
Gathering and analog digital conversion, audio chip is to the voice data of FPGA input multi-path serial form, FPGA
The voice data of serial form is converted to the voice data of parallel data, and is incited somebody to action by Memory Controller Hub
The voice data of parallel form is sent to processor.
FPGA achieves the conversion of multi-path audio-frequency data form, solves the processor number of channel not enough, nothing
Method realizes problem and the defect that multi-path audio-frequency data gathers.
As in figure 2 it is shown, whole serioparallel exchange logic is with A/D serial form voice data output clock (i.e.
BCK bit clock) monocycle for operation beat, using channel selecting clock as data logic with shift
Enter left channel data displacement flow process or the selection gist of right channel data displacement flow process.
FPGA is the left channel shift registers of left channel data displacement nine 16bit of flow setting,
The right channel shift registers of nine 16bit of flow setting is shifted, when BCK position for right channel data
When clock is in rising edge, according to the height of WS level and low selection enter left channel data displacement flow process or
Right channel data displacement flow process, when ws signal level height by 9 port numbers after ws signal saltus step
Move into left channel shift registers according to front 16bit serial bit, when ws signal level is low, WS is believed
Before 9 channel datas after number saltus step, 16bit serial bit moves into right channel register.
When left/right channel register has been moved into 16bit data, then reset left/right channel shift and enable mark
Will, forbids proceeding the operation of left/right channel shift, retains current registrar numerical value and waits that RAM write enters
Control module is written in the two-port RAM within FPGA, enables right/left channel shift simultaneously
Enabler flags, starts right/left channel data shifting function after WS level saltus step.
During as it is shown on figure 3, two-port RAM write control logic works with A/D in Memory Controller Hub
The monocycle of clock (i.e. SYSCLK) is operation beat, writes logic with channel selecting clock for data
Enter left channel data write flow process or the selection gist of right channel data write flow process.
9 left channel shift registers will be deposited with before ws signal saltus step when ws signal level is low
In the data write internal two-port RAM of FPGA, when ws signal level height by ws signal
The data internal two-port RAM of write FPGA being deposited with before saltus step in 9 right channel registers.
When 9 left/right channel datas complete after RAM write enters, to reset the write of left/right passage and enable mark
Will, forbids that left/right channel data continues to write to operation, enables right/left passage write enabler flags simultaneously,
After WS level saltus step, start right/left channel data RAM write enter operation.
Claims (8)
1. a multi-path audio-frequency data format conversion method based on FPGA, it is characterised in that realize
The device of described conversion method includes FPGA and the processor and at least two with FPGA communication connection
Individual audio chip, described FPGA receives the multi-path audio-frequency data of the serial form of audio chip output,
After the voice data of serial form is converted to the voice data of parallel form, send to processor.
2. multi-path audio-frequency data format conversion method based on FPGA as claimed in claim 1, its
Being characterised by, FPGA controls audio chip and carries out analog digital conversion, to export the multichannel sound of serial form
Frequency evidence.
3. multi-path audio-frequency data format conversion method based on FPGA as claimed in claim 2, its
Being characterised by, FPGA includes the two-port RAM for caching parallel form voice data, FPGA
Control reading and the write of parallel form voice data in two-port RAM.
4. multi-path audio-frequency data format conversion method based on FPGA as claimed in claim 3, its
Being characterised by, the voice data of parallel form is write in two-port RAM by FPGA, simultaneously to process
Device sends interrupt signal, has no progeny in processor response, and FPGA is by parallel form in two-port RAM
Voice data sends to processor.
5. multi-path audio-frequency data format conversion method based on FPGA as claimed in claim 4, its
Be characterised by, the voice data of serial form is converted to parallel form voice data time, with string
The monocycle of row format data output clock is operation beat, shifts using channel selecting clock as data
Logic enters left channel data flow process or the foundation of right channel data flow process.
6. multi-path audio-frequency data format conversion method based on FPGA as claimed in claim 5, its
It is characterised by, FPGA arranges N number of left channel shift registers for left channel data flow process, lead to for the right side
The N number of right channel shift registers of track data flow setting, when ws signal level height, by ws signal
N number of channel data serial bit after saltus step moves into left channel shift registers, left channel shift registers
When middle data expire, reset left channel shift enabler flags, retain current registrar data, wait to be written
In the two-port RAM of FPGA；
When ws signal level is low, the N number of channel data serial bit after ws signal saltus step is moved into the right side
Channel shift registers, when data expire in right channel shift registers, resets right channel shift and enables
Mark, retains current registrar data, waits in the two-port RAM of FPGA to be written.
7. multi-path audio-frequency data format conversion method based on FPGA as claimed in claim 6, its
Being characterised by, the write of two-port RAM controls to save with the monocycle of analog digital conversion work clock for operation
Clap, enter left channel data write flow process or right passage using channel selecting clock as data write logic
The foundation of data write flow process.
8. multi-path audio-frequency data format conversion method based on FPGA as claimed in claim 7, its
It is characterised by, when ws signal level is low, is deposited with left channel shift registers by before ws signal saltus step
In data write two-port RAM in, when data all in left channel shift registers complete write
After, reset left passage write enabler flags, forbid that left channel data writes；
During ws signal level height, it is deposited with the number in right channel shift registers by before ws signal saltus step
According in write two-port RAM, after data all in right channel shift registers complete write, reset
Right passage write enabler flags, forbids that right channel data writes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610316969.9A CN106024036A (en) | 2016-05-12 | 2016-05-12 | FPGA-based multi-channel audio data format conversion method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610316969.9A CN106024036A (en) | 2016-05-12 | 2016-05-12 | FPGA-based multi-channel audio data format conversion method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106024036A true CN106024036A (en) | 2016-10-12 |
Family
ID=57100662
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610316969.9A Pending CN106024036A (en) | 2016-05-12 | 2016-05-12 | FPGA-based multi-channel audio data format conversion method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106024036A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106875952A (en) * | 2016-12-23 | 2017-06-20 | 伟乐视讯科技股份有限公司 | The soft encoding mechanism of MCVF multichannel voice frequency based on FPGA embedded systems |
| CN108989730A (en) * | 2018-08-08 | 2018-12-11 | 京东方科技集团股份有限公司 | Video format conversion method and its device, field programmable gate array |
| CN110349584A (en) * | 2019-07-31 | 2019-10-18 | 北京声智科技有限公司 | A kind of audio data transmission method, device and speech recognition system |
| CN114281298A (en) * | 2021-12-22 | 2022-04-05 | 中航洛阳光电技术有限公司 | Airborne embedded audio interface control system based on CPU + FPGA and control method thereof |
| CN114879931A (en) * | 2022-07-11 | 2022-08-09 | 南京芯驰半导体科技有限公司 | Onboard audio path management method and system supporting multiple operating systems |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102831090A (en) * | 2012-05-07 | 2012-12-19 | 中国科学院空间科学与应用研究中心 | Address line for space-borne DSP (Digital Signal Processor) and FPGA (Field Programmable Gate Array) communication interfaces and optimization method for address line |
| CN103686338A (en) * | 2013-08-15 | 2014-03-26 | 深圳Tcl新技术有限公司 | A method for processing audio data, an apparatus thereof and a television set |
| CN203747934U (en) * | 2014-02-20 | 2014-07-30 | 深圳市同洲电子股份有限公司 | Audio-video synchronization device |
| CN204288801U (en) * | 2014-10-16 | 2015-04-22 | 北京海格神舟通信科技有限公司 | A kind of low rate speech coding/decoding module based on DSP |
| CN105321522A (en) * | 2014-08-06 | 2016-02-10 | 航天恒星科技有限公司 | Audio data processing and transmitting method and device |
| CN105513603A (en) * | 2014-10-16 | 2016-04-20 | 北京海格神舟通信科技有限公司 | DSP-based low-speed voice coding and decoding module |
-
2016
- 2016-05-12 CN CN201610316969.9A patent/CN106024036A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102831090A (en) * | 2012-05-07 | 2012-12-19 | 中国科学院空间科学与应用研究中心 | Address line for space-borne DSP (Digital Signal Processor) and FPGA (Field Programmable Gate Array) communication interfaces and optimization method for address line |
| CN103686338A (en) * | 2013-08-15 | 2014-03-26 | 深圳Tcl新技术有限公司 | A method for processing audio data, an apparatus thereof and a television set |
| CN203747934U (en) * | 2014-02-20 | 2014-07-30 | 深圳市同洲电子股份有限公司 | Audio-video synchronization device |
| CN105321522A (en) * | 2014-08-06 | 2016-02-10 | 航天恒星科技有限公司 | Audio data processing and transmitting method and device |
| CN204288801U (en) * | 2014-10-16 | 2015-04-22 | 北京海格神舟通信科技有限公司 | A kind of low rate speech coding/decoding module based on DSP |
| CN105513603A (en) * | 2014-10-16 | 2016-04-20 | 北京海格神舟通信科技有限公司 | DSP-based low-speed voice coding and decoding module |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106875952A (en) * | 2016-12-23 | 2017-06-20 | 伟乐视讯科技股份有限公司 | The soft encoding mechanism of MCVF multichannel voice frequency based on FPGA embedded systems |
| CN108989730A (en) * | 2018-08-08 | 2018-12-11 | 京东方科技集团股份有限公司 | Video format conversion method and its device, field programmable gate array |
| CN108989730B (en) * | 2018-08-08 | 2021-01-22 | 京东方科技集团股份有限公司 | Video format conversion method and device and field programmable gate array |
| CN110349584A (en) * | 2019-07-31 | 2019-10-18 | 北京声智科技有限公司 | A kind of audio data transmission method, device and speech recognition system |
| CN114281298A (en) * | 2021-12-22 | 2022-04-05 | 中航洛阳光电技术有限公司 | Airborne embedded audio interface control system based on CPU + FPGA and control method thereof |
| CN114281298B (en) * | 2021-12-22 | 2024-03-01 | 中航洛阳光电技术有限公司 | CPU+FPGA-based airborne embedded audio interface control system and control method thereof |
| CN114879931A (en) * | 2022-07-11 | 2022-08-09 | 南京芯驰半导体科技有限公司 | Onboard audio path management method and system supporting multiple operating systems |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106024036A (en) | FPGA-based multi-channel audio data format conversion method | |
| CN103376400B (en) | Chip detecting method and chip | |
| CN204087204U (en) | Based on the Large Copacity multi-channel synchronous high-speed data acquisition card of FPGA | |
| CN104062937B (en) | Sixty-four-way low-speed high-precision analog acquisition realizing method | |
| CN100373388C (en) | Method for fast generating logical circuit | |
| CN103777529A (en) | Fast varying signal collector | |
| CN110348091A (en) | A kind of signal delay simulator and the simulator using the device | |
| CN107133407A (en) | The FPGA implementation method of DDR RAM Interface bandwidth is improved under a kind of high bandwidth | |
| CN203086778U (en) | Led drive circuit and control system | |
| CN206248785U (en) | Volume production test module of the inside with analog-to-digital conversion interface chip | |
| CN206211976U (en) | A kind of digital DLL controls circuit of SECO | |
| CN105068950A (en) | Pin multiplexing system and method | |
| CN104078078B (en) | A kind of read-write control circuit based on half floating-gate memory | |
| CN106650128B (en) | A kind of method of graphic software platform timing topology and timing dependence | |
| CN103198854B (en) | There is in FPGA the Block RAM of multiple write mode | |
| CN109782723A (en) | A kind of configurable multifunction control system and method towards nonspecific AD | |
| CN104331145A (en) | Realization method for reducing DDR3 memory write operation power consumption | |
| CN106571156B (en) | A kind of interface circuit and method of high-speed read-write RAM | |
| CN103500585B (en) | A kind of control circuit and its control method for being used to control single programmable memory | |
| CN102955872B (en) | There is the emulator of parameter propagation function | |
| CN205959618U (en) | Memory device | |
| CN109189404A (en) | Data programming device, programming method and computer storage medium | |
| CN204100994U (en) | A kind of two-phase Linear Array CCD Data Acquisition and disposal system | |
| CN2833104Y (en) | Data acquisition circuit and control module | |
| CN207301682U (en) | A kind of input/output expander based on SPI interface |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20161012 |