CN204288801U

CN204288801U - A kind of low rate speech coding/decoding module based on DSP

Info

Publication number: CN204288801U
Application number: CN201420596835.3U
Authority: CN
Inventors: 吴克平; 王友文
Original assignee: BEIJING HAIGE SHENZHOU COMMUNICATIONS TECHNOLOGY Co Ltd
Current assignee: BEIJING HAIGE SHENZHOU COMMUNICATIONS TECHNOLOGY Co Ltd
Priority date: 2014-10-16
Filing date: 2014-10-16
Publication date: 2015-04-22
Anticipated expiration: 2024-10-16

Abstract

The utility model relate to a kind of low rate speech coding/decoding module based on DSP, comprise AD/DA unit, DSP processing unit, FLASH memory, sends out Audio processing unit, receives Audio processing unit, FPGA auxiliary processing unit, clock unit and power supply processing unit, be connected by asynchronous EMIF between DSP processing unit with FPGA auxiliary processing unit, is connected between DSP processing unit with AD/DA unit by McBsp.The utility model possesses DSP processing unit, the audio A/D/DA unit of superior performance under less physical dimension, external interface is responsible for by FPGA auxiliary processing unit, improve Speech processing ability, possess good reliability and dirigibility, voice coding/decoding algorithms process and the realization of multiple speed can be met.

Description

A kind of low rate speech coding/decoding module based on DSP

Technical field

The utility model relates to a kind of low rate speech coding/decoding module based on DSP, belongs to voice process technology field.

Background technology

Speech processing is ingredient indispensable in modern communications, more and more higher along with to QoS requirement, needs to obtain synthetic speech quality as well as possible with alap numeric code rate.

In the existing technology of field of voice signal, encoding and decoding speech generally adopts dedicated voice codec chip and processor cooperation, the method being simultaneously aided with external audio AD/DA chip realizes, and has that module integration degree is low, volume is large, the shortcoming such as speed low not (minimum reach 2kbps).

So, existing encoding and decoding speech module process and implementation complexity higher, the voice coding/decoding algorithms aspect that rate requirement is lower is difficult to the growth requirement reaching modern speech signal transacting.

Utility model content

The purpose of this utility model is exactly provide a kind of low rate speech coding/decoding module based on DSP to solve the problem.

The utility model is achieved through the following technical solutions above-mentioned purpose.

The utility model comprises sends out Audio processing unit, receipts Audio processing unit, AD/DA unit, DSP processing unit, FPGA auxiliary processing unit, power supply processing unit, also comprises the FLASH memory and external clock that are connected with DSP processing unit.

Wherein, described DSP processing unit adopts model to be the dsp chip of TMS320VC5510, substitute dedicated voice codec chip of the prior art and processor, be mainly used in the realization of low rate speech code decode algorithm, and undertaken controlling and data transmit-receive by McBsp (Multichannel Buffered Serial Ports, multichannel buffer serial line interface) interface connection AD/DA unit; Connected, for transmitting steering order and VoP by asynchronous EMIF (External Memory Interface, external memory interface) interface between DSP processing unit and FPGA auxiliary processing unit; Also data interaction is carried out by asynchronous EMIF interface between DSP processing unit and FLASH memory.

Described FPGA auxiliary processing unit is mainly used in data between DSP parallel data and outer CPU asynchronous serial port and changes, and can be encrypted by FPGA program to transceiving data.

Described FLASH memory is for storing dsp operation program, and when module powers on, DSP processing unit loads start-up routine from FLASH memory.

In the utility model, when voice send, low rate speech coding/decoding module receives analog voice signal, after sending out Audio processing unit, AD sampling is carried out by AD/DA unit, after converting digital signal to, deliver to DSP processing unit and carry out low-speed speech encode, by the parallel data mouth of DSP processing unit, data are delivered to FPGA auxiliary processing unit, break into packet by FPGA auxiliary processing unit and sent by asynchronous serial port.During phonetic incepting, FPGA auxiliary processing unit receives the VoP that asynchronous serial port is sent here, deliver to after DSP processing unit carries out tone decoding by parallel data mouth, by carrying out analog to digital conversion by AD/DA unit, changing into simulating signal and sending through receiving after Audio processing unit amplifies.

Technical advantage of the present utility model is:

From the above, the utility model have employed and adopts model to be the dsp chip of TMS320VC5510, substitute dedicated voice codec chip of the prior art and processor, low rate speech encoding and decoding are realized by low rate speech code decode algorithm, reduce hardware complexity, improve module integration degree, and improve Speech processing ability (speed can low 1200bps and 600bps), therefore there is good reliability and dirigibility.

Accompanying drawing explanation

Fig. 1: the utility model structured flowchart.

Fig. 2: the utility model is applied to the structured flowchart of certain system.

Embodiment

Below in conjunction with accompanying drawing, the utility model is further described in detail.

As shown in Figure 1, the utility model comprises sends out Audio processing unit, receipts Audio processing unit, AD/DA unit, DSP processing unit, FPGA auxiliary processing unit, power supply processing unit, also comprises the FLASH memory and clock unit that are connected with DSP processing unit.

After module powers on, described DSP processing unit start-up routine from flash storage.When voice send: analog voice signal is after sending out Audio processing path, undertaken after AD sample conversion becomes digital signal by AD/DA unit, deliver to DSP processing unit and carry out low-speed speech encode, by the parallel data mouth of DSP processing unit, data are delivered to FPGA auxiliary processing unit, break into serial data packet by FPGA auxiliary processing unit and sent by asynchronous serial port.During phonetic incepting: FPGA auxiliary processing unit receives the VoP sent here from asynchronous serial port, deliver to after DSP processing unit carries out tone decoding by parallel data mouth, carry out digital-to-analog conversion by AD/DA unit, change into simulating signal and give earphone microphone group through receiving after Audio processing unit amplifies.

As shown in Figure 2, Fig. 2 is the structured flowchart that the utility model is applied to certain communication station.Communication station realizes digital voice communications function by the low rate speech coding/decoding module based on DSP.During transmitting, based on the simulated voice of the low rate speech coding/decoding module receiving interface control module of DSP, after over-sampling, voice coding, deliver to that Comprehensive Signal Processing module carries out modulating, deliver to channel module after upconversion process, gone out by antenna transmission after blasting is amplified; During reception, after the signal channel module reception process that antenna receives, deliver to Comprehensive Signal Processing module and carry out demodulation, again give the low rate speech coding/decoding module based on DSP after framing, deliver to interface control module by the simulated voice after the low rate speech coding/decoding module based on DSP carries out tone decoding, digital-to-analog conversion.

Claims

1. a kind of low rate speech coding/decoding module based on DSP of the utility model, comprise DSP processing unit, AD/DA unit, FPGA auxiliary processing unit, FLASH memory, it is characterized in that, also comprise transmitting-receiving Audio processing unit, the external clock of DSP processing unit and FPGA auxiliary processing unit and the power supply processing unit of module, module size is 60mm × 40mm × 6mm.

2. a kind of low rate speech coding/decoding module based on DSP according to claim 1, it is characterized in that: encoding and decoding speech module can carry out the rear encoding and decoding of speech transmitting-receiving by the direct frames connecting with headphone microphone group of sending and receiving Audio processing unit, and adopts universal asynchronous serial transmission coding/decoding data.

3. a kind of low rate speech coding/decoding module based on DSP according to claim 1, it is characterized in that: by asynchronous EMIF(External Memory Interface between described DSP processing unit and described FPGA auxiliary processing unit, external memory interface) interface connection, for transmitting steering order and VoP.

4. a kind of low rate speech coding/decoding module based on DSP according to claim 3, it is characterized in that: FPGA auxiliary processing unit is mainly used in changing between DSP parallel data and external serial data, also carries out transceiving data encryption by FPGA auxiliary processing unit.