CN105991115A

CN105991115A - Transmitter circuit, semiconductor apparatus and data transmission method

Info

Publication number: CN105991115A
Application number: CN201610152473.2A
Authority: CN
Inventors: 武田晃; 武田晃一; 长濑宽和; 渡部真平
Original assignee: Renesas Electronics Corp
Current assignee: Renesas Electronics Corp
Priority date: 2015-03-17
Filing date: 2016-03-17
Publication date: 2016-10-05
Anticipated expiration: 2036-03-17
Also published as: TW201705730A; TWI692226B; CN105991115B; JP2016174346A; KR20160111863A; JP6557562B2

Abstract

The present invention relates to a transmitter circuit, a semiconductor apparatus and a data transmission method. The transmitter circuit according to one embodiment includes a pulse generating circuit generating a pulse signal based on edges of input data, a first output driver outputting, based on the pulse signal, a first output pulse signal according to one of the edges to a first end of an external insulating coupling element, a second output driver outputting, based on the pulse signal, a second output pulse signal according to other one of the edges to a second end of the insulating coupling element, and an output stop circuit stopping the first and second output pulse signals from being output for a prescribed period from when a power supply voltage is turned on.

Description

Transmitter circuit, semiconductor device and data transmission method for uplink

Technical field

The present invention relates to transmitter circuit, semiconductor device and data transmission method for uplink.

Background technology

Exchange between multiple semiconductor chips that supply voltage is different from each other in the case of signal, When exchanging signal, described semiconductor chip must be carried out with insulation coupling element each other Electric insulation.Known insulation coupling element includes: use the AC coupling of capacitor, coil etc. Element；And optical coupling element (photoelectrical coupler).Japanese Unexamined Patent application is open Number 2013-229812 discloses one, and to employ coils as insulation coupling element (the most miniature Isolator) exchange the semiconductor device of signal.

In Japanese Unexamined Patent application publication number 2013-229812 disclosure, from Transmitter circuit sends the pulse signal of the edging trigger of data signal.Herein, from transmitter electricity Road sends can the rising edge of distinguishes data signal and the pulse signal of trailing edge.Therefore, connecing Receive and can reconstruct this data signal at device circuit.

Meanwhile, Japanese Unexamined Patent application publication number 2005-045100 and 2012-253241 And Japanese Patent No. 4750746 each discloses a kind of electrostatic being arranged between power supply and ground Discharge protection circuit.Install this ESD protection circuit in order to protect semiconductor device in The harm of the high-voltage pulse that portion's circuit produces from static discharge.Japanese Unexamined Patent application ESD protection circuit disclosed in publication number 2005-045100 and 2012-253241 is once felt Measure supply voltage to be increased dramatically and i.e. connect nmos pass transistor.Japanese Patent No. 4750746 Disclosed ESD protection circuit (GGNMOS: gate grounding NMOS) is reaching certain The parasitic bipolar transistor of nmos pass transistor is connected during the power supply potential of level.By above-mentioned behaviour Make, each ESD protection circuit power supply potential reach internal circuit breakdown voltage it Front operation.Thus, supply voltage increases and is suppressed, and internal circuit is protected.

Summary of the invention

Present inventor have found that and there is problems with.

For instance, it has been found that, when using such as Japanese Unexamined Patent application publication number Micro-isolator disclosed in 2013-229812 carries out HBM (anthropometric dummy) test, and (electrostatic is put One of electric injury test) time, it may occur that such as transmitter circuit punctures or the coupling element that insulate damages The fault of evil idea etc.Supply voltage is caused to exceed given voltage also it has been found that apply dash current Cause transmitter circuit output error pulse, ultimately result in above-mentioned fault.

High speed operability, low-power consumption, area occupied is little and noise immunity is micro-isolator Important performance indexes.The scheme improving these performances is: make big electric current at short notice from Transmitter circuit flows to transformator (insulation coupling element).Such as, Japanese Unexamined Patent The transmitter circuit of micro-isolator disclosed in application publication number 2013-229812 is by exporting short pulse The impulse generating unit of punching and the output driver unit with high driveability are constituted.The opposing party Face, impulse generating unit has a problem in that: after switching on power, and constitutes this pulse and produces Internal node in the delay element of raw unit is in an unsure state, and thereby results in this pulse Generation unit is prone to output error pulse.And, output driver unit is designed to generally make example Electric current such as 100mA flows through transformator with given voltage (such as 5V).Herein, output is driven Dynamic device unit has a problem in that: when applying the supply voltage far above given voltage, flow through behaviour Driver or the electric current of transformator when making are more than permissible value.

Although element exists respective problem, but said two problem is not under normal circumstances Can occur simultaneously, the most not constitute challenge.But, when carrying out HBM between power supply and ground During test, the state of entrance is: power supply is with the voltage far above given voltage (such as, more than ten Volt) connect.Then, during impulse generating unit produces bursts of error, more than permissible value Electric current (the most hundreds of milliampere) flows through driver or transformator, causes such as transmitter circuit to hit Wear or the fault of coupling element damage etc of insulating.

Use Japanese Unexamined Patent application publication number 2005-045100 and 2012-253241 And ESD protection circuit disclosed in Japanese Patent No. 4750746, although can suppress by Increase in the supply voltage applying dash current and cause, make supply voltage be less than breakdown voltage (example As, lying prostrate ten more), it can be difficult to suppress this dash current close to given voltage (such as, 5V). And, it is impossible to prevent from constituting the impulse generating unit output error pulse of transmitter circuit.Cause This, result is: higher than given voltage supply voltage by bursts of error be transported to driver and Transformator, causes fault as above.

As it has been described above, the ESD protection circuit of routine cannot effectively suppress to put carrying out electrostatic Fault during electric injury test.

By description and the accompanying drawing of this specification, other problem and novel characteristics will become apparent from.

Transmitter circuit according to an embodiment includes exporting halt circuit, and this output stops electricity Rise during the self-closing supply voltage of road in stipulated time section, stop the first output pulse signal and second The output of output pulse signal.

According to one embodiment, the fault in electrostatic discharge damage test can be suppressed.

Accompanying drawing explanation

In conjunction with accompanying drawing, by the following explanation to some embodiments, foregoing and other side, Advantage and feature will become more fully apparent, in the accompanying drawings:

Fig. 1 shows the block diagram of the structure of the semiconductor device according to first embodiment,

Fig. 2 shows the diagram of the installation example of the semiconductor device according to first embodiment,

Fig. 3 shows the particular circuit configurations of the transmitter circuit TX1 according to first embodiment The circuit diagram of example,

One of the operation that Fig. 4 shows the transmitter circuit TX1 according to first embodiment is shown The sequential chart of example,

Fig. 5 shows the particular circuit configurations of the acceptor circuit RX1 according to first embodiment The circuit diagram of example,

One of the operation that Fig. 6 shows the acceptor circuit RX1 according to first embodiment is shown The sequential chart of example,

Fig. 7 shows the transmitter circuit TX10's of the comparative examples according to first embodiment The circuit diagram of one example of particular circuit configurations,

Fig. 8 is to carry out HBM for description with the transmitter circuit TX10 according to comparative examples The sequential chart of the mechanism that fault occurs during test,

Fig. 9 is suppression fault when description transmitter circuit TX1 carries out HBM test The sequential chart of mechanism,

Figure 10 shows the physical circuit knot of the output halt circuit 10 according to first embodiment The circuit diagram of one example of structure,

Figure 11 be for describe when switch on power voltage time stop according to the output of first embodiment The sequential chart of the operation of circuit 10,

Figure 12 shows the circuit of the modification of the transmitter circuit TX1 according to first embodiment Figure,

Figure 13 shows the circuit of the modification of the transmitter circuit TX1 according to first embodiment Figure,

Figure 14 shows the electricity of the modification of the pulse-generating circuit PGC according to first embodiment Lu Tu,

Figure 15 shows the physical circuit knot of the output halt circuit 20 according to the second embodiment The circuit diagram of one example of structure,

Figure 16 be for describe when switch on power voltage time stop according to the output of the second embodiment The sequential chart of the operation of circuit 20,

Figure 17 shows the physical circuit knot of the output halt circuit 30 according to the 3rd embodiment The circuit diagram of one example of structure,

Figure 18 be for describe when switch on power voltage time stop according to the output of the 3rd embodiment The sequential chart of the operation of circuit 30,

Figure 19 shows the frame of the structure of the semiconductor device system 2 according to the 3rd embodiment Figure,

Figure 20 shows the diagram of DC-to-AC converter, wherein said semiconductor device system 2 It is applied to described DC-to-AC converter,

Figure 21 shows the described inverter dress wherein applying described semiconductor device system 2 The sequential chart of the operation put,

Figure 22 is that capacitor is used as the peace of semiconductor device in the case of insulation coupling element Dress example, and

Figure 23 is as the semiconductor device in the case of insulation coupling element by GMR element Installation example.

Detailed description of the invention

Provide the detailed description to specific embodiment below with reference to accompanying drawings.It should be noted that for saying Bright clearly purpose, takes the circumstances into consideration the accompanying drawing of following description and reference is omitted or simplified.And, The element being shown as performing the functional device of various process in the drawings both can pass through CPU, memorizer Or other circuit realiration is hardware, it is also possible to be embodied as by the program being loaded in memorizer etc. Software.Therefore, it will be appreciated by those skilled in the art that these functional devices can be real in every way Existing, realized by hardware the most completely, realized by software completely or real by the combination of the two Existing, and the invention is not restricted to one of them.It should be noted that in the accompanying drawings, identical accompanying drawing mark The element that note instruction is identical, and the repetitive description thereof will be omitted if desired.

(first embodiment)

First, with reference to Fig. 1, the description to the semiconductor device according to first embodiment will be provided. Fig. 1 shows the block diagram of the structure of the semiconductor device 1 according to first embodiment.According to The semiconductor device 1 of one embodiment includes transmitter circuit TX1, primary coil L11, secondary Coil L12 and acceptor circuit RX1, and constitute micro-isolator.

Transmitter circuit TX1 is formed on semiconductor chip CHP1.It should be noted that semiconductor core Sheet CHP1 is by the first power supply (supply voltage VDD1, the ground connection electricity belonging to the first power-supply system Pressure GND1；Potential difference VDD1-GND1 is such as 5V) drive.

Primary coil L11, secondary coil L12 and acceptor circuit RX1 are formed at quasiconductor On chip CHP2.It should be noted that semiconductor chip CHP2 by belong to be different from described first electricity Second source (supply voltage VDD2, the ground voltage of the second source system of origin system GND2；Potential difference VDD2-GND2 e.g. 5V) drive.

Primary coil L11 and secondary coil L12 constitutes insulation coupling element, and described insulation couples Element is via magnetic field or field coupling supply voltage two semiconductor chip CHP1 different from each other And CHP2, make semiconductor chip CHP1 and CHP2 be electrically insulated from each other simultaneously.By insulation Coupling element, data signal can send by the transmitter circuit TX1 from semiconductor chip CHP1 To supply voltage different (potential difference VDD1-VDD2 is such as to bear a few hectovolt to several hectovolts) Acceptor circuit RX1 on semiconductor chip CHP2.

Herein, with reference to Fig. 2, the explanation of installation example that will be given semiconductor device 1.Fig. 2 Show the diagram of the installation example of semiconductor device 1.It should be noted that Fig. 2 mainly explains to send out Send device circuit TX1, acceptor circuit RX1 and be arranged on transmitter circuit TX1 and reception Primary coil L11 between device circuit RX1 and the installation example of secondary coil L12.

In installation example as shown in Figure 2, two semiconductor chip CHP1 and CHP2 peaces It is contained in semiconductor packages PKG.Semiconductor chip CHP1 and CHP2 each has pad Pd.Then, the pad Pd of semiconductor chip CHP1 and CHP2 is via unshowned joint Wire is connected to multiple lead terminals (external terminal) T being arranged in semiconductor packages PKG.

As in figure 2 it is shown, transmitter circuit TX1 is formed on semiconductor chip CHP1.Receive Device circuit RX1, primary coil L11 and secondary coil L12 are formed at semiconductor chip CHP2 Place.And, the pad of the outfan being connected to transmitter circuit TX1 is also formed in semiconductor core At sheet CHP1.The pad of the opposite end being respectively connecting to primary coil L11 is formed at partly leads At body chip CHP2.Then, transmitter circuit TX1 via pad and engages wire BW even It is connected to the primary coil L11 being formed at semiconductor chip CHP2.

It should be noted that in the illustrated example shown in fig. 2, primary coil L11 and secondary coil L12 divides It is not formed at the first interconnection layer and the second interconnection layer, described first interconnection layer and described second mutual Even layer is stacked in semiconductor chip CHP2 along top-down direction.And, primary coil L11 and secondary coil L12 can be formed at the semiconductor chip with transmitter circuit TX1 On CHP1.Alternately, primary coil L11 and secondary coil L12 can be formed on In semiconductor chip CHP1 (wherein forming transmitter circuit TX1) and semiconductor chip CHP2 On the 3rd semiconductor chip between (wherein forming acceptor circuit RX1).

And, primary coil L11 and transmitter circuit TX1 may be formed at semiconductor chip At CHP1, and secondary coil L12 and acceptor circuit RX1 may be formed at semiconductor chip At CHP2.Then, semiconductor chip CHP1 and semiconductor chip CHP2 can connect each other Close.

Alternately, transmitter circuit TX1, acceptor circuit RX1, primary coil L11 May be formed on a semiconductor chip with secondary coil L12.In this case, setting is sent out The region sending device circuit TX1 and the region arranging acceptor circuit RX1 are passed through at semiconductor core The insulating barrier formed in sheet comes insulated from each other.

Refer back to Fig. 1, the explanation of example arrangement that will provide semiconductor device 1.Send out The device circuit TX1 the first power supply based on belonging to the first power-supply system is sent to operate.On the other hand, Acceptor circuit RX1 operates based on the second source belonging to second source system.

Transmitter circuit TX1 include pulse-generating circuit PGC, output driver OD1 and OD2 and output halt circuit 10.

Pulse-generating circuit PGC produces pulse signal according to the edge of input data signal Din1 P10。

Output pulse signal P11 is exported extremely by output driver OD1 based on pulse signal P10 First end of primary coil L11.Output pulse signal P11 is for sending input data letter The pulse signal of the rising edge of number Din1.

Output pulse signal P12 is exported extremely by output driver OD2 based on pulse signal P10 Second end of primary coil L11.Output pulse signal P12 is for sending input data signal The pulse signal of the trailing edge of Din1.

Rise during output halt circuit 10 self-closing supply voltage described in stopping in stipulated time section The output of output pulse signal P11 and P12.In the example of fig. 1, from output halt circuit The stopping signal STP of 10 outputs is input to output driver OD1 and OD2.That is, pass through Stop from output driver OD1 from the stopping signal STP of output halt circuit 10 output and OD2 exports described output pulse signal P11 and P12.

The output that primary coil L11 and secondary coil L12 will export from transmitter circuit TX1 Pulse signal P11 and P12 is converted to receive signal VR and sent by this reception signal VR To acceptor circuit RX1.Specifically, by the transformation to output pulse signal P11 and P12, Change the electric current flowing through primary coil L11.Receive the signal VR (phase of secondary coil L12 Voltage between two ends) change the most therewith.

Acceptor circuit RX1 reception based on secondary coil L12 signal VR reconstructs input number The signal of this reconstruct is also exported by the number of it is believed that Din1 as outputting data signals Dout1.

Transmitter circuit TX1 according to first embodiment includes exporting halt circuit 10, and this is defeated Rise when going out halt circuit 10 self-closing supply voltage VDD1 described in stopping in stipulated time section Output pulse signal P11 and the output of described output pulse signal P12.Therefore, it can suppression With the output connecting the bursts of error that described supply voltage VDD1 is associated.Carry out static discharge During damage measure, the increase of supply voltage VDD1 is analogous to connect described supply voltage VDD1 Physical phenomenon.Therefore, use the transmitter circuit TX1 according to first embodiment, carrying out During electrostatic discharge damage test, described output halt circuit 10 starts, and can suppress and power supply Voltage VDD1 increases any fault that the bursts of error being associated is caused.

It follows that with reference to Fig. 3, particular circuit configurations to transmitter circuit TX1 will be provided Describe.Circuit structure shown below is only example.Fig. 3 shows according to described first real Execute the circuit diagram of the example of the particular circuit configurations of the transmitter circuit TX1 of example.Such as Fig. 1 and Tu Shown in 3, this transmitter circuit TX1 includes pulse-generating circuit PGC, output driver OD1 With OD2 and output halt circuit 10.

As it is shown on figure 3, pulse-generating circuit PGC includes a phase inverter IN10, on two Rise along testing circuit RED1 and RED2 and one or an OR1.Herein, rising edge detection The circuit structure of circuit RED1 with RED2 is the most similar.Rising edge testing circuit RED1 bag Include delay circuit DC1, phase inverter IN11 and with door AN11.Rising edge testing circuit RED2 Including delay circuit DC2, phase inverter IN12 and with door AN12.

As it is shown on figure 3, the circuit structure basic simlarity that output driver OD1, OD2 are each other. Output driver OD1 includes and door AN1, buffer circuit B1 and phase inverter IN1.Output Driver OD2 includes and door AN2, buffer circuit B2 and phase inverter IN2.

It should be noted that as it is shown on figure 3, the difference between output driver OD1 and OD2 is: When input data signal Din1 is input to output driver OD1, this input data signal The inversion signal of Din1 is input to output driver OD2.That is, it is included in use with door AN2 Phase inverter at the input terminal of input data signal Din1.

Annexation will be illustrated below.

Input data signal Din1 is input to rising edge testing circuit RED1.Rising edge detects Circuit RED1 exports edge pulse signal EP1 at the rising edge of input data signal Din1. Specifically, input data signal Din1 is postponed and by phase inverter IN11 by delay circuit DC1 Anti-phase.From inverse delayed data signal DDB of phase inverter IN11 output together with input data letter Number Din1 is input to and door AN11 together.Then, with door AN11 output edge pulse letter Number EP1.

On the other hand, input data signal Din1 via phase inverter IN10 inversion signal (under Literary composition is referred to as anti-phase data signal DB) input to rising edge testing circuit RED2.Rising edge detects Circuit RED2 at the rising edge of anti-phase data signal DB (that is, at input data signal Din1 Trailing edge) output edge pulse signal EP2.Specifically, anti-phase data signal DB is by prolonging Circuit DC2 postpones late, and is come anti-phase by phase inverter IN12, becomes normal delay data letter Number DD.Believe together with oppisite phase data from normal delay data signal DD of phase inverter IN12 output Number DB is input to and door AN12 together.Then, with door AN12 output edge pulse signal EP2。

Edge pulse signal EP1 from two rising edge testing circuit RED1 and RED2 outputs All it is input to EP2 or door OR1.Or door OR1 will send described input data signal Din1 Rising edge and trailing edge pulse signal P10 as pulse-generating circuit PGC output believe Number output.

By pulse signal P10 input to respectively constitute output driver OD1 and OD2 with door AN1 and AN2.And, input data signal Din1 is input to and door AN1.The opposing party Face, the inversion signal of input data signal Din1 is input to and door AN2.

Result is, with door AN1 output for sending the rising of described input data signal Din1 H (high) the effective impulse signal on edge.This pulse signal inputs to instead via buffer circuit B1 Phase device IN1.Then, phase inverter IN1 sends described input data signal Din1's by being used for Rise L (low) the effectively output pulse signal P11 output letter as output driver OD1 on edge Number output.

On the other hand, will be used for sending the decline of described input data signal Din1 with door AN2 The high effective impulse signal output on edge.This pulse signal is the most anti-phase via buffer circuit B2 input Device IN2.Then, phase inverter IN2 will be used for sending the decline of described input data signal Din1 Low effective output pulse signal P12 on edge exports as the output signal of output driver OD2.

Herein, the stopping signal STP from output halt circuit 10 output inputs to respectively constituting Output driver OD1 and OD2 with door AN1 and AN2.It is low stopping signal STP During the time period of level, respectively from the output pulse of output driver OD1 and OD2 output The output of signal P11 and P12 always high level.That is, stop signal STP be low level During time period, although outputing pulse signal P10 from pulse-generating circuit PGC, but from defeated Go out driver OD1 and OD2 is defeated not out of output pulse signal P11 and P12.

It should be noted that pulse-generating circuit PGC can not include or door OR1.In this situation Under, respectively edge pulse signal EP1, EP2 are directly inputted into and door AN1, AN2.Only Should by edge pulse signal EP1 and stop signal STP input to door AN1, it is not necessary to by institute State input data signal Din1 input to door AN1.And, only should be by edge pulse signal EP2 and stop signal STP input to door AN2, it is not necessary to by described input data signal Din1 Inversion signal input to door AN2.

It follows that with reference to Fig. 4, the explanation of normal operating that will be given transmitter circuit TX1. Fig. 4 shows the one of the normal operating of the transmitter circuit TX1 according to described first embodiment The sequential chart of individual example.It should be noted that output stops under normal manipulation mode as shown in Figure 4 Stop circuit 10 and be not turned on.

Fig. 4 starts from top to show input data signal Din1, inverse delayed data in order Signal DDB, edge pulse signal EP1, anti-phase data signal DB, normal delay data are believed Number DD, edge pulse signal EP2, pulse signal P10, output pulse signal P11 and defeated Go out pulse signal P12.

Inverse delayed data signal DDB shown in the second layer is by the input shown in top layer Data signal Din1 carries out anti-phase and is delayed the signal obtained by after Td time delay.

Edge pulse signal EP1 shown in third layer is to have width Td and represent shown in top layer The pulse signal of rising edge of input data signal Din1.Edge pulse signal EP1 is logical Cross the input data signal Din1 shown in top layer and the inverse delayed data shown in the second layer Signal DDB carries out obtaining with logic.

4th layer of shown anti-phase data signal DB is the input data signal Din1 shown in top layer Inversion signal.

Normal delay data signal DD shown in layer 5 is by the input number shown in top layer The signal that the number of it is believed that Din1 is obtained after being delayed Td time delay.

Edge pulse signal EP2 shown in layer 6 is to have width Td and represent shown in top layer The pulse signal of trailing edge of input data signal Din1.Edge pulse signal EP2 is logical Cross the normal delay data shown in the 4th layer of shown anti-phase data signal DB and layer 5 Signal DD carries out obtaining with logic.

Pulse signal P10 shown in layer 7 is to represent the input data signal Din1 shown in top layer Rising edge and the pulse signal of trailing edge.Pulse signal P10 is by shown in third layer Edge pulse signal EP2 shown in edge pulse signal EP1 and layer 6 carry out or logic and Obtain.

8th layer of shown output pulse signal P11 is to represent the input data signal shown in top layer The low effective impulse signal of the rising edge of Din1.Output pulse signal P11 is by top layer institute Pulse signal P10 shown in the input data signal Din1 shown and layer 7 is carried out and logic The signal obtained carry out anti-phase after the signal that obtains.

Output pulse signal P12 shown in bottom is to represent the input data signal shown in top layer The low effective impulse signal of the trailing edge of Din1.Output pulse signal P12 is by the 4th layer Pulse signal P10 shown in shown anti-phase data signal DB and layer 7 is carried out and logic The signal obtained carry out anti-phase after the signal that obtains.

It follows that the explanation to sequential will be provided.

It is transformed into height from low level at time point t1, the input data signal Din1 shown in top layer Level (that is, rising edge).Therefore, the edge pulse signal EP1 shown in third layer and Seven layers of shown pulse signal P10 is transformed into high level from low level, and the 8th layer shown defeated Go out pulse signal P11 and be transformed into low level from high level.

At time point t2, inverse delayed data signal DDB shown in the second layer turns from high level Become low level.Therefore, shown in the edge pulse signal EP1 shown in third layer and layer 7 Pulse signal P10 be transformed into low level from high level, and the 8th layer of shown output pulse letter Number P11 is transformed into high level from low level.

At time point t3, the input data signal Din1 shown in top layer is transformed into low from high level Level (i.e. trailing edge), and the 4th layer of shown anti-phase data signal DB is from low level transformation Become high level.Therefore, shown in the edge pulse signal EP2 shown in layer 6 and layer 7 Pulse signal P10 is transformed into high level from low level, and the output pulse signal shown in bottom P12 is transformed into low level from high level.

At time point t4, normal delay data signal DD shown in layer 5 changes from high level Become low level.Therefore, shown in the edge pulse signal EP2 shown in layer 6 and layer 7 Pulse signal P10 is transformed into low level from high level, and the output pulse signal shown in bottom P12 is transformed into high level from low level.

It follows that with reference to Fig. 5, particular circuit configurations to acceptor circuit RX1 will be provided Explanation.Circuit structure shown below is only example.Fig. 5 shows according to described first real Execute the circuit diagram of the example of the particular circuit configurations of the acceptor circuit RX1 of example.As it is shown in figure 5, Acceptor circuit RX1 includes pulse-detecting circuit PDC, two pulse-stretching circuit PWC1 With PWC2, sequential logical circuit SLC and or door OR2.

Below, annexation will be illustrated.

Exist in response to described output pulse signal P11, the P12 exported from transmitter circuit TX1 The reception signal VR produced between the opposite end of secondary coil L12 is input to pulse detection Circuit PDC.Pulse-detecting circuit PDC exports positive pulse detection letter when positive pulse being detected Number PPD1 also exports negative pulse detection signal NPD1 when negative pulse being detected.Specifically, When output pulse signal P11, P12 export from transmitter circuit TX1, no matter export is Which kind of signal, all can export a pair positive pulse detection signal PPD1 and negative pulse detection signal NPD1.But, the difference between output pulse signal P11 and output pulse signal P12 exists In, positive pulse detection signal PPD1 and the output reversed order of negative pulse detection signal NPD1. In the present embodiment, when exporting described output pulse signal P11, first output positive pulse inspection Survey signal PPD1；When exporting described output pulse signal P12, first output negative pulse inspection Survey signal NPD1.

Positive pulse detection signal PPD1 is input to pulse-stretching circuit PWC1, and negative pulse Detection signal NPD1 is input to pulse-stretching circuit PWC2.Pulse-stretching circuit PWC1, PWC2 widens the positive pulse detection signal PPD1 received and negative pulse detection signal respectively NPD1 also exports positive pulse detection signal PPD2 and negative pulse detection signal NPD2.Herein, Pulse-stretching circuit PWC1 and PWC2 only postpones positive pulse detection signal PPD1 and negative pulse The detection respective trailing edge of signal NPD1, and do not change rising edge.Therefore, positive pulse detection The high level time section of signal PPD2 and the high level time section of negative pulse detection signal NPD2 Partially overlap each other.

Positive pulse detection signal PPD2 and negative pulse detection signal NPD2 is input to sequential and patrols Collect circuit SLC.Sequential logical circuit SLC identifies and receives positive pulse detection signal PPD2 and bear The order of pulse detection signals NPD2, and export outputting data signals Dout1.Specifically, When being firstly received positive pulse detection signal PPD2, sequential logical circuit SLC is by high level Export as outputting data signals Dout1.On the other hand, when being firstly received negative pulse detection During signal NPD2, sequential logical circuit SLC using low level as outputting data signals Dout1 Output.

And, positive pulse detection signal PPD2 and negative pulse detection signal NPD2 is input to Or door OR2.Or door OR2 exports pulse detection signals PD1.Subsequently will be in the 3rd embodiment Middle explanation, this pulse detection signals PD1 can serve as such as measuring from exporting this arteries and veins The reset signal of the timer of the time period risen during punching detection signal PD1.It should be noted that from Fig. 5 Can be seen that, or door OR2 is dispensable for generating described outputting data signals Dout1.

It follows that with reference to Fig. 6, the explanation of operation that will be given acceptor circuit RX1.Figure One of 6 operations showing the described acceptor circuit RX1 according to described first embodiment The sequential chart of example.Fig. 6 starts to show in order the input of transmitter circuit TX1 from top Data signal Din1, from transmitter circuit TX1 output output pulse signal P11 and P12, The reception signal VR of secondary coil L12, positive pulse detection signal PPD1, negative pulse detection letter Number NPD1, positive pulse detection signal PPD2, negative pulse detection signal NPD2, output data Signal Dout1 and pulse detection signals PD1.

According at the output pulse signal P11 shown in the second layer and in the output shown in third layer Pulse signal P12, in the reception signal VR of the 4th layer of shown secondary coil L12, produces Downward projection of negative pulse in the positive pulse projected upwards in raw figure and figure.Specifically, in output Positive arteries and veins is produced at the falling edge of pulse signal P11 and the rising edge of output pulse signal P12 Punching.On the other hand, at the rising edge of output pulse signal P11 and output pulse signal P12 Falling edge produce negative pulse.

At the moment of the positive pulse in producing described reception signal VR, output is in layer 5 institute The positive pulse detection signal PPD1 shown.

At the moment of the negative pulse in producing described reception signal VR, output is in layer 6 institute The negative pulse detection signal NPD1 shown.

Detecting signal PPD2 in the positive pulse shown in layer 7 is by pulse-stretching circuit The signal postponing the described positive pulse detection trailing edge of signal PPD1 at PWC1 and widen.

Detecting signal NPD2 the 8th layer of shown negative pulse is by pulse-stretching circuit The signal postponing the described negative pulse detection trailing edge of signal NPD1 at PWC2 and widen.

Pulse detection signals PD1 shown in bottom is whenever exporting described output pulse signal P11 The signal exported with a period of time of described output pulse signal P12.As it has been described above, pulse detection letter Number PD1 produces from positive pulse detection signal PPD2 and negative pulse detection signal NPD2.

It follows that the explanation to sequential will be provided.

At time point t1, owing to described output pulse signal P11 is transformed into low electricity from high level Flat, in described reception signal VR, therefore produce positive pulse.Therefore, at time point t1, Positive pulse detection signal PPD1 and PPD2 is transformed into high level from low level.Due to positive pulse Detection signal PPD2 is transformed into high level from low level, using high level as outputting data signals Dout1 exports.

At time point t2, owing to described output pulse signal P11 is transformed into high electricity from low level Flat, in described reception signal VR, therefore produce negative pulse.Therefore, at time point t2, Negative pulse detection signal NPD1 and NPD2 is transformed into high level from low level.That is, in the time Point t2 place, although negative pulse detects signal NPD2 and is transformed into high level from low level, but just Pulse detection signals PPD2 is still within high level.Therefore, not using low level as output Data signal Dout1 exports, but maintains high level.That is, signal PPD2 is detected in positive pulse While high level, when negative pulse detection signal NPD2 is transformed into high level from low level, Outputting data signals Dout1 does not changes.

At time point t3, owing to described output pulse signal P12 is transformed into low electricity from high level Flat, in described reception signal VR, therefore produce negative pulse.Therefore, at time point t3, Negative pulse detection signal NPD1 and NPD2 is transformed into high level from low level.Negative pulse detects The result that signal NPD2 is transformed into high level from low level is, therefore using low level as output Data signal Dout1 exports.

At time point t4, owing to described output pulse signal P12 is transformed into high electricity from low level Flat, in described reception signal VR, therefore produce positive pulse.Therefore, at time point t4, Positive pulse detection signal PPD1 and PPD2 is transformed into high level from low level.That is, in the time At some t4, although positive pulse detection signal PPD2 is transformed into high level from low level, but negative Pulse detection signals NPD2 is still within high level.Therefore, not using high level as output Data signal Dout1 exports, but maintains low level.That is, signal NPD2 is detected in negative pulse While high level, when positive pulse detection signal PPD2 is transformed into high level from low level, Outputting data signals Dout1 does not changes.

It follows that with reference to Fig. 7, will be given the comparative examples according to described first embodiment The explanation of transmitter circuit TX10.Fig. 7 shows the contrast according to described first embodiment The circuit diagram of one example of the particular circuit configurations of the transmitter circuit TX10 of example.Such as figure Shown in 7, transmitter circuit TX10 and the transmitter electricity according to the first embodiment shown in Fig. 3 The difference of road TX1 is that transmitter circuit TX10 does not comprise output halt circuit 10.Its It is similar to that the knot of the transmitter circuit TX1 according to the described first embodiment shown in Fig. 3 Structure.

It follows that with reference to Fig. 8, will be given using the transmitter circuit according to comparative examples The explanation of the mechanism that fault when TX10 carries out HBM test occurs.Fig. 8 is for describing use The machine that fault when transmitter circuit TX10 according to comparative examples carries out HBM test occurs The sequential chart of reason.Fig. 8 starts from top to show supply voltage VDD1, input number in order The number of it is believed that Din1, pulse signal P10, output pulse signal P1 and output pulse signal P2.

As shown in top layer, by applying dash current, supply voltage VDD1 persistently increases and surpasses Cross given voltage.In the example depicted in fig. 8, limiter (not shown) it is provided with so that Supply voltage VDD1 is not over upper voltage limit.Therefore, apply dash current in a moment, electricity Source voltage VDD1 is constant at upper voltage limit.

As shown in the second layer, input data signal Din1 is maintained at low level.

As shown in third layer, according to the increase of supply voltage VDD1, from pulse-generating circuit The pulse signal P10 of PGC output may produce bursts of error.In the example of fig. 8, produce Two bursts of error are given birth to.With the connection pattern similarity of supply voltage VDD1, deferred telegram The signal electricity of internal node in the output signal of road DC1 and DC2 and pulse-generating circuit PGC Flat labile state causes such bursts of error.It should be noted that the wrong arteries and veins shown in Fig. 8 Punching is only example, and single error pulse is it is possible to cause fault.

Result is, creates bursts of error in the output pulse signal P2 shown in layer 5. On the other hand, in the 4th layer of shown output pulse signal P1, bursts of error is not produced. That is, between output pulse signal P1 and output pulse signal P2, potential difference is occurred in that, and Big electric current is had to flow through primary coil L11.Result is, it may occur however that such as output driver OD1 Puncture with OD2 or the fault of primary coil L11 damage etc.

It follows that with reference to Fig. 9, will be given using sending out according to the present embodiment shown in Fig. 3 Device circuit TX1 is sent to carry out the explanation of the mechanism of suppression fault during HBM test.Fig. 9 be for Description transmitter circuit TX1 carries out the sequential chart of the mechanism of suppression fault during HBM test.

Fig. 9 starts from top to show supply voltage VDD1, input data signal in order Din1, pulse signal P10, stopping signal STP and output pulse signal P11 and P12.Top Input data signal Din1 and the 3rd shown in supply voltage VDD1 shown in Ceng, the second layer Supply voltage VDD1 in pulse signal P10 Yu Fig. 8 shown in Ceng, input data signal Din1 And pulse signal P10 is identical.

As it is shown on figure 3, include exporting halt circuit according to the transmitter circuit TX1 of the present embodiment 10, rise in stipulated time section during this output halt circuit 10 self-closing supply voltage VDD1 Stop the output of described output pulse signal P11 and P12.Export from output halt circuit 10 Stopping signal STP be input to output driver OD1 and OD2 with door AN1 and AN2.Therefore, during stopping signal STP is the low level time period, output pulse signal P11 and P12 maintains high level.In other words, stop signal STP be low level During time period, stop the output of described output pulse signal P11 and P12.

As shown in Fig. 9 the 4th layer, with the connection pattern similarity of supply voltage VDD1, stop Signal STP is tested by HBM and starting to increase when regulation from supply voltage VDD1 Between become low level in section.

Therefore, as shown in layer 5, the waveform of output pulse signal P11 and P12 becomes each other Identical, and in output pulse signal P11 and P12, the most do not produce bursts of error.That is, Output pulse signal P11 and P12 realizes identical current potential, and does not has electric current to flow through primary line Circle L11.As a result, it is possible to suppress such as output driver OD1 and OD2 to puncture or primary The fault of coil L11 damage etc.

As it has been described above, include that output stops according to the transmitter circuit TX1 of described first embodiment Circuit 10, rises in the stipulated time during this output halt circuit 10 self-closing supply voltage VDD1 Described output pulse signal P11 and the output of described output pulse signal P12 is stopped in section.Cause This, can suppress the output of the bursts of error being associated with the voltage VDD1 that switches on power.Carry out During electrostatic discharge damage test, the increase of supply voltage VDD1 is analogous to connect described power supply electricity The physical phenomenon of pressure VDD1.Therefore, the transmitter circuit according to described first embodiment is used TX1, when carrying out electrostatic discharge damage test, described output halt circuit 10 also starts, and Can suppress to increase any event that the bursts of error being associated is caused with supply voltage VDD1 Barrier.

It follows that with reference to Figure 10, the output according to described first embodiment is stopped electricity by providing The explanation of the particular circuit configurations on road 10.Circuit structure shown below is only example.Figure 10 Show the particular circuit configurations exporting halt circuit 10 according to described first embodiment The circuit diagram of one example.As shown in Figure 10, output halt circuit 10 includes resistor element R1, capacitor element C1 and phase inverter IN21.

The input N1 of phase inverter IN21 is connected to power supply via capacitor element C1.And, The input N1 of phase inverter IN21 is via resistor element R1 ground connection (being connected to ground).That is, The input N1 of phase inverter IN21 be in capacitor element C1 and resistor element R1 it Between connection node.Then, signal STP is stopped from phase inverter IN21 output.

It should be noted that stopping signal STP can also be by by capacitor element C1 ground connection and by electricity Resistance device element R1 is connected to power supply and produces.In this case, another phase inverter should be added Outfan to described phase inverter IN21.

It follows that with reference to Figure 11, will be given to switch on power voltage time according to described first enforcement The explanation of the operation of the output halt circuit 10 of example.Figure 11 is for describing when switching on power electricity The sequential chart of operation of output halt circuit 10 according to described first embodiment during pressure.Figure 11 Start to show in order the input N1 of supply voltage VDD1, phase inverter IN21 from top Voltage and stop signal STP voltage.

As shown in top layer, when making supply voltage VDD1 from ground voltage GND by switching on power When increasing to given voltage VDD, as shown in the second layer, it is connected to via capacitor element C1 The voltage of the input N1 of the phase inverter IN21 of power supply also increases to given voltage VDD.Phase Ying Di, as shown in third layer, the stopping signal STP as the output of phase inverter IN21 is connecing Low level is become during logical supply voltage VDD1.

As shown in the second layer, by discharging via resistor element R1, phase inverter IN21 The voltage of input N1 be gradually lowered.When the voltage of the input N1 of phase inverter IN21 reaches During to the logic threshold voltage Vth of phase inverter IN21, the output of phase inverter IN21 is from low level It is transformed into high level.Accordingly, as shown in third layer, stop signal STP and be transformed into from low level High level.During stopping signal STP is the low level time period, stop described output pulse The output of signal P11 and P12.

Dwell time section depends on resistor element R1 and the time constant of capacitor element C1.

Figure 12 and Figure 13 shows the transmitter circuit TX1's according to described first embodiment The circuit diagram of modification.

In the transmitter circuit TX1 shown in Fig. 3, stop signal STP and be input to respectively Constitute output driver OD1 and OD2 with door AN1 and AN2.

On the other hand, in the transmitter circuit TX1 shown in Figure 12, with door AN21 and AN22 It is arranged on the prime of phase inverter IN1 and IN2 respectively constituting output driver OD1 and OD2, And stop signal STP to be input to and door AN21 and AN22.

And, in the transmitter circuit TX1 shown in Figure 13, stop signal STP and be transfused to To respectively constitute rising edge testing circuit RED1 and RED2 with door AN11 and AN12.

It is with the circuit structure shown in Figure 12 and Figure 13, similar with the circuit structure shown in Fig. 3, Stopping output pulse signal in stipulated time section can also be played during self-closing supply voltage VDD1 P11 and the output of output pulse signal P12.

It should be noted that employing circuit structure shown in Figure 13, it is suppressed that from pulse-generating circuit PGC The pulse signal P10 of output itself produces any bursts of error.

Figure 14 shows the described pulse-generating circuit PGC's according to described first embodiment The circuit diagram of modification.In the pulse-generating circuit PGC shown in Figure 14, delay circuit DC1 It is connected to power supply via capacitor element C11 and C21 respectively with the outfan of DC2.And, The outfan of phase inverter IN11 and IN12 is respectively via capacitor element C12 and C22 ground connection.

When switch on power voltage time input data signal Din1 be low level time, with door The output of AN11 becomes low level.

In this case, an input with door AN12 is anti-phase data signal DB, therefore Reach high level.But, the outfan of delay circuit DC2 is via capacitor element C21 It is connected to power supply, and the outfan of phase inverter IN12 is via capacitor element C22 ground connection. Become consistently accordingly, as the output with the phase inverter IN12 of another input of door AN12 Low level.Correspondingly, the output with door AN12 becomes low level.

When switch on power voltage time input data signal Din1 be high level when, with door One input of AN11 becomes high level.But, the outfan of delay circuit DC1 is via electricity Container component C11 is connected to power supply, and the outfan of phase inverter IN11 is via capacitor element C12 ground connection.Accordingly, as the output with the phase inverter IN11 of another input of door AN11 Stably become low level.Correspondingly, the output with door AN11 also becomes low level.

In this case, an input with door AN12 is anti-phase data signal DB, therefore It is low level, and also becomes low level with the output of door AN12.

By this way, the pulse-generating circuit PGC shown in Figure 14 is used can to suppress at arteries and veins Rush the bursts of error produced in signal P10 itself.Correspondingly, such pulses generation electricity is used Road PGC also combines output halt circuit 10, can more efficiently suppress to put carrying out electrostatic The fault that the bursts of error produced during electric injury test is caused.

It should be noted that in the case of delay circuit DC1 and DC2 is to be made up of multiple phase inverters, The outfan of each phase inverter is alternately connected to power supply via capacitor element and ground is preferred 's.

(the second embodiment)

It follows that with reference to Figure 15, will be given the transmitter circuit TX1 according to the second embodiment Explanation.Figure 15 shows the tool of the output halt circuit 20 according to described second embodiment The circuit diagram of one example of body circuit structure.As shown in figure 15, output halt circuit 20 wraps Include nmos pass transistor NM1, PMOS transistor PM1, capacitor element C1 and C2 And phase inverter IN21.This transmitter circuit TX1 is similar to that according to described first real Execute the structure of the transmitter circuit TX1 of example, in addition to output halt circuit 20.

In output halt circuit 20, the off-resistances of nmos pass transistor NM1 is used to take For the resistor element R1 in the output halt circuit 10 shown in Figure 10.Source ground The drain electrode of nmos pass transistor NM1 is connected to power supply via capacitor element C1.NMOS The drain electrode of transistor NM1 is connected to the input N1 of phase inverter IN21.

On the other hand, source electrode is connected to the drain electrode of PMOS transistor PM1 of power supply via electricity Container component C2 ground connection.That is, for polarity angle, PMOS transistor PM1 and electric capacity Annexation between device element C2 and nmos pass transistor NM1 and capacitor element C1 Between annexation be reverse.The grid N2 of nmos pass transistor NM1 is connected to The drain electrode of PMOS transistor PM1.And, the grid of PMOS transistor PM1 is connected to The drain electrode (that is, the input N1 of phase inverter IN21) of nmos pass transistor NM1.

Then, stop signal STP to export from phase inverter IN21.

It follows that with reference to Figure 16, will be given to switch on power voltage time according to described second enforcement The explanation of the operation of the output halt circuit 20 of example.Figure 16 is for describing when switching on power electricity The sequential chart of operation of output halt circuit 20 according to described second embodiment during pressure.Figure 16 Start to show in order the input N1 of supply voltage VDD1, phase inverter IN21 from top (that is, the grid of PMOS transistor PM1) and the grid N2 of nmos pass transistor NM1 Voltage and stop signal STP.

As shown in top layer, when supply voltage VDD1 is according to switching on power voltage VDD1 and from connecing When ground voltage GND increases to given voltage VDD, as the second layer is shown in solid, via electric capacity Device element C1 is connected to the voltage of the input N1 of the phase inverter IN21 of power supply and also increases to refer to Determine voltage VDD.Correspondingly, as shown in third layer, as the stopping of output of phase inverter IN21 Stop signal STP becomes low level when switching on power voltage VDD1.

When switch on power voltage VDD1 time, due to phase inverter IN21 input N1 (i.e., The grid of PMOS transistor PM1) voltage be high level, therefore PMOS transistor PM1 It is in cut-off state.The voltage of the grid N2 being additionally, since nmos pass transistor NM1 is Low level, therefore nmos pass transistor NM1 is also at cut-off state.

As the second layer is shown in solid, due to nmos pass transistor NM1 cut-off leakage current and It is gradually lowered the voltage of the input N1 of phase inverter IN21.On the other hand, such as second layer point Shown in line, it is gradually increased due to the cut-off leakage current of PMOS transistor PM1 The voltage of the grid N2 of nmos pass transistor NM1.

Input N1 (that is, the grid of PMOS transistor PM1) as phase inverter IN21 Or the voltage of the grid N2 of nmos pass transistor NM1 is when reaching threshold voltage, NMOS is brilliant Body pipe NM1 and PMOS transistor PM1 enter on-state.Then, phase inverter IN21 The voltage of input N1 be latched at low level, and the grid of nmos pass transistor NM1 The voltage of N2 is latched at high level.

As shown in third layer, stop signal STP and be transformed into high level from low level accordingly.Stopping During stop signal STP is the low level time period, stop described output pulse signal P11 and The output of P12.

With the transmitter circuit TX1 according to described first embodiment similarly, according to described The transmitter circuit TX1 of two embodiments includes rising when regulation during self-closing supply voltage VDD1 Between stop the defeated of described output pulse signal P11 and described output pulse signal P12 output in section Go out halt circuit 20.Therefore, it can the mistake that suppression is associated with the voltage VDD1 that switches on power The output of pulse.It is similar for carrying out the increase of supply voltage VDD1 during electrostatic discharge damage test In the physical phenomenon connecting described supply voltage VDD1.Correspondingly, static discharge damage is being carried out During wound test, described output halt circuit 20 also starts, and can suppress and supply voltage VDD1 increases any fault that the bursts of error being associated is caused.

Meanwhile, the output halt circuit 10 according to described first embodiment, dwell time section are used Depend on resistor element R1 and the time constant of capacitor element C1.Therefore, in order to ensure The dwell time section of a few μ s, the size of resistor element R1 and capacitor element C1 must be big, Thus result in chip area to increase.

On the other hand, for the output halt circuit 20, NMOS according to described second embodiment The off-resistances of transistor NM1 is used for replacing resistor element R1.Therefore, resistance value can To increase in the case of the size of nmos pass transistor NM1 is little, and capacitor element C1 Size can also reduce.Similarly, PMOS transistor PM1 and capacitor element C2 Size can also reduce.Therefore, with the output halt circuit 10 according to described first embodiment Compare, although number of elements adds, but chip entire area but can reduce.

And, with the output halt circuit 20 according to described second embodiment, stop when releasing output After Zhi, stopping signal STP can be by nmos pass transistor NM1 and PMOS transistor PM1 Connection resistance maintain high level.This improves the noise immunity in normal operating.

(the 3rd embodiment)

It follows that with reference to Figure 17, will be given the transmitter circuit TX1 according to the 3rd embodiment Explanation.Figure 17 shows the tool of the output halt circuit 30 according to described 3rd embodiment The circuit diagram of one example of body circuit structure.As shown in figure 17, output halt circuit 30 wraps Include NAND gate ND, capacitor element C1 and C2, phase inverter IN21 and IN22 and counting Device CTR1.This transmitter circuit TX1 is similar to that sending out according to described first embodiment Send the structure of device circuit TX1, in addition to output halt circuit 30.

The input N2 of phase inverter IN22 is via capacitor element C2 ground connection.Phase inverter IN22 Outfan be connected to power supply via capacitor element C1.The outfan of phase inverter IN22 connects Input N1 to phase inverter IN21.

And, the output (i.e. the input N1 of phase inverter IN21) of phase inverter IN22 is transfused to To NAND gate ND.The outfan of NAND gate ND is connected to the input N2 of phase inverter IN22. That is, phase inverter IN22 and NAND gate ND latch cicuit is constituted.

In other words, the memory node N1 of latch cicuit is connected to electricity via capacitor element C1 Source, and memory node N2 is via capacitor element C2 ground connection.The memory node of latch cicuit N1 and N2 keeps the most anti-phase voltage respectively.

From enumerator CTR1 output regular request signal RT12 inversion signal input to Not gate ND.

Then, signal STP is stopped from phase inverter IN21 output.

It should be noted that regular request signal RT12 e.g. switches on power after voltage VDD1 periodically The high effective pulse signal of output.But, from the signal of enumerator CTR1 output can be High effective arteries and veins once is only exported after playing specified time intervals during self-closing supply voltage VDD1 Rush signal, or can be to be transformed into high level from low level and maintain the enable letter of high level Number.And, although the logic class enabling signal is similar to stop signal STP, enable signal permissible Such as by mistake become low level by variations in temperature.Will be described in more detail after a while, In this case, the value stopping signal STP is maintained at high level with being also latched circuit stability.

It follows that with reference to Figure 18, will be given to switch on power voltage time according to described 3rd enforcement The explanation of the operation of the output halt circuit 30 of example.Figure 18 is for describing when switching on power electricity The sequential chart of the operation of described output halt circuit 30 according to described 3rd embodiment during pressure.Figure 18 start to show supply voltage VDD1, the electricity of memory node N1 and N2 in order from top Pressure, regular request signal RT12 and stopping signal STP.

As shown in top layer, when owing to switching on power voltage and supply voltage VDD1 is from ground voltage When GND increases to given voltage VDD, as the second layer is shown in solid, via capacitor element The voltage of the memory node N1 that C1 is connected to power supply also increases to given voltage VDD.Accordingly Ground, as shown in third layer, the stopping signal STP as the output of phase inverter IN21 is connecting Low level is become during supply voltage VDD1.

Switch on power after voltage VDD1, as the second layer is shown in solid, by phase inverter IN22 and The voltage of the memory node N1 of the latch cicuit that NAND gate ND is constituted is maintained at high level.Separately On the one hand, as shown in second layer chain-dotted line, the voltage of the memory node N2 of latch cicuit keeps In low level.

As shown in third layer, after playing specified time intervals section during self-closing supply voltage VDD1, When regular request signal RT12 is temporarily changed high level, the voltage of memory node N2 changes Become high level.Therefore, the voltage of memory node N1 is transformed into low level.Then, by instead Phase device IN22 and NAND gate ND, the voltage of memory node N1 is latched at low level, and deposits The voltage of storage node N2 is latched at high level.Signal regardless of regular request signal RT12 Level how, and this state all can maintain.

As shown in the 4th layer, stop signal STP accordingly and be transformed into high level from low level.Stopping During stop signal STP is the low level time period, stop described output pulse signal P11 and The output of P12.When stopping signal STP and being transformed into high level, release described output pulse letter The output of number P11 and P12 stops.

In such a way, the latch cicuit sensing electricity being made up of phase inverter IN22 and NAND gate ND The startup of source voltage, and described stopping signal STP is maintained low level.Then, electricity is latched Road according to from as timer enumerator CTR1 export regular request signal RT12 by institute State stopping signal STP and be transformed into high level.

Similar to the transmitter circuit TX1 according to first embodiment, sending out according to the 3rd embodiment Send device circuit TX1 to include during self-closing supply voltage VDD1 and play stopping institute in stipulated time section State the output halt circuit of output pulse signal P11 and described output pulse signal P12 output 30.Therefore, it can the output of the bursts of error that suppression is associated with the voltage VDD1 that switches on power. Carry out the increase of supply voltage VDD1 during electrostatic discharge damage test to be analogous to connect described electricity The physical phenomenon of source voltage VDD1.Correspondingly, described in when carrying out electrostatic discharge damage test Output halt circuit 30 also starts, and can suppress to increase relevant to supply voltage VDD1 Any fault that the bursts of error of connection is caused.

Use the output halt circuit 30 according to described 3rd embodiment, owing to dwell time section takes Certainly in the enumerator CTR1 as timer, the change of described dwell time section can be reduced.And And, owing to dwell time section is not affected by capacitor element C1 and C2, therefore can realize Size is reduced.Such as, can be by the grid capacitance of transistor be used as described capacitor element C1 With C2 and further size reduction.Moreover, it is not necessary to newly arrange timer, and can use Some elements.Therefore, chip entire area can be reduced.

It is additionally, since phase inverter IN22 and NAND gate ND after releasing output stopping stopping Signal STP is latched in high level, therefore shows the noise immunity of brilliance in normal operating.

It follows that with reference to Figure 19, will be given using the transmitter according to described 3rd embodiment The explanation of the semiconductor device system 2 of circuit TX1.Figure 19 shows according to the described 3rd The block diagram of the structure of the semiconductor device system 2 of embodiment.According to described 3rd embodiment half Conductor apparatus system 2 include two transmitter circuit TX1 and TX2, primary coil L11 and L21, secondary coil L12 and L22, two acceptor circuit RX1 and RX2, two vibrations Device circuit OSC1 and OSC2, two enumerator CTR1 and CTR2, two timer TM1 With TM2, two under-voltage locking (UVLO) circuit U VLO1 and UVLO2, two with Door A1 and A2 and six or an O1-O6.

Herein, transmitter circuit TX1 and TX2 with according to the described with reference to Fig. 3 The transmitter circuit TX1 of one embodiment has similar structure.Herein, transmitter circuit TX1 The output halt circuit according to described 3rd embodiment shown in Figure 17 is each included with TX2 30.And, the institute that acceptor circuit RX1 and RX2 had described with reference to Fig. 5 with basis The acceptor circuit RX1 stating first embodiment has similar structure.Implement according to the described 3rd The semiconductor device system 2 of example is applied to the micro-isolator of the control system of power transistor Example.

First, basic structure and signal stream will be illustrated.

From control signal CNT1 of microcomputer MCU output as input data signal Din1 is input to transmitter circuit TX1.And, export from UVLO circuit U VLO1 Irregular request signal RT11 and from enumerator CTR1 output regular request signal RT12 is also input to transmitter circuit TX1.

From described output pulse signal P11 and P12 of transmitter circuit TX1 output via just Level coil L11 and secondary coil L12 is sent to acceptor circuit RX1.Acceptor circuit RX1 According to the signal reconstruction data signal received, and using data signal as outputting data signals Dout1 exports.This outputting data signals Dout1 is input to merit as control signal CNT2 Rate transistor driver PTD.

That is, from control signal CNT1 of microcomputer MCU output via transmitter circuit TX1 and acceptor circuit RX1 inputs to power transistor drives as control signal CNT2 Device PTD.

On the other hand, from the erroneous detection signal ED1 conduct of error detect circuit EDC output Input data signal Din2 is input to transmitter circuit TX2.And, from UVLO circuit UVLO2 output irregular request signal RT21 and from enumerator CTR2 output regular Request signal RT22 is also input to transmitter circuit TX2.

From described output pulse signal P21 and P22 of transmitter circuit TX2 output via just Level coil L21 and secondary coil L22 is sent to acceptor circuit RX2.Acceptor circuit RX2 According to the signal reconstruction data signal received, and using data signal as outputting data signals Dout2 exports.Outputting data signals Dout2 is input to micro-as erroneous detection signal ED2 Type computer MCU.

That is, from the erroneous detection signal ED1 of error detect circuit EDC output via transmitter Circuit TX2 and acceptor circuit RX2 is input to microcomputer as erroneous detection signal ED2 Calculation machine MCU.

Hereinafter detailed construction and signal stream will be illustrated.

From microcomputer MCU output control signal CNT1 via with door A1 as defeated Enter data signal Din1 and be input to transmitter circuit TX1.Herein, from UVLO circuit The inversion signal of the irregular request signal RT11 of UVLO1 output is also input to and door A1.

Irregularly request signal RT11 is low level in normal state, and drops at supply voltage High level is become under low abnormality.That is, it is low level at irregular request signal RT11 Normal condition under, from microcomputer MCU output control signal CNT1 as input Data signal Din1 is input to transmitter circuit TX1.On the other hand, in irregularly request Signal RT11 is under the abnormality of high level, from the control of microcomputer MCU output Signal CNT1 is stopped with door A1 and can not be inputted to transmitter circuit TX1.

And, irregular request signal RT11 is also input to transmitter circuit TX1.Not Regular request signal RT11 is transformed into high level from low level or is transformed into low level from high level Time, the value of input data signal Din1 (control signal CNT1) is from transmitter circuit TX1 Resend to acceptor circuit RX1.I.e., not only when supply voltage declines, and at electricity Source voltage by connect and when rising and be converted to normal value, the value of the data signal of sending side with And the value receiving the data signal of side is synchronized.

It is input to transmitter circuit from the regular request signal RT12 of enumerator CTR1 output TX1.Regular request signal RT12 is the clock signal example from pierce circuit OSC1 output As often counted the signal just becoming high level 10 times.Such as, when from pierce circuit OSC1 When exporting the clock signal of 10MHz, enumerator CTR1 produces the cycle 1 μ s (1MHz) Regular request signal RT12.By regular request signal RT12, even if when data value does not become During change, often counting just resends data value 10 times.Therefore, even if when by acceptor circuit When the data value of RX1 reconstruct is anti-phase due to noise etc., it is also possible to fast quick-recovery right value.

And, as it has been described above, from the regular request signal RT12 quilt of enumerator CTR1 output Input is to the NAND gate exporting halt circuit 30 according to described 3rd embodiment shown in Figure 17 ND。

Enumerator CTR1 exports not by pulse signal P10 or from UVLO circuit U VLO1 Regular request signal RT11 resets.That is, enumerator CTR1 by from or door O1 output answer Position signal RST1 resets, and described or door O1 input is pulse signal P10 and irregularly please Seek signal RT11.

Transmitter circuit TX1 exports described output pulse signal based on input data signal Din1 P11 and P12.Described output pulse signal P11 and P12 is via primary coil L11 and secondary Coil L12 is input to acceptor circuit RX1.Acceptor circuit RX1 reconstructed data signal And described data signal is exported as outputting data signals Dout1.It should be noted that details such as Described in one embodiment.

Outputting data signals Dout1 is input to power transistor drives device via with door A2 PTD.Herein, from the irregular request signal RT21's of UVLO circuit U VLO2 output Inversion signal is input to and door A2.And, from the timeout signal TO1 of timer TM1 output Inversion signal be input to and door A2.

Irregularly request signal RT21 is low level in normal state, and when under supply voltage High level is become during fall.And, timeout signal TO1 is the most also low level, and And it is not detected by pulse detection signals PD1 after the counting (such as 40 times countings) of interval regulation Then become high level.That is, it is low electricity at irregular request signal RT21 and timeout signal TO1 Under flat normal condition, outputting data signals Dout1 is input to power transistor drives device PTD.On the other hand, it is transformed into height as irregular request signal RT21 or timeout signal TO1 During level, described outputting data signals Dout1 is stopped with door A2 and can not be inputted to power Transistor driver PTD.And, acceptor circuit RX1 is carried out multiple by timeout signal TO1 Position.It should be noted that in a normal operation mode, often counting 10 times, just by regular request signal RT12 resends data value from transmitter circuit TX1, and defeated from acceptor circuit RX1 Go out pulse detection signals PD1.Therefore, timer TM1 will not reach 40 countings.Separately On the one hand, when transmitter circuit TX1 stops waiting, output overtime signal TO1.Logical Cross regular request signal RT12, it is possible to the exception in transmitter circuit TX1 operation detected.

Herein, the clock signal exported from pierce circuit OSC2 is carried out by timer TM1 Counting.And, the pulse detection signals that timer TM1 is exported from acceptor circuit RX1 PD1 or the irregular request signal RT21 from the output of UVLO circuit U VLO2 resets.That is, Timer TM1 by from or door O2 output reset signal RST2 reset, described or door O2 Input be pulse detection signals PD1 and irregular request signal RT21.

On the other hand, from error detect circuit EDC output erroneous detection signal ED1 via Or door O5 is input to transmitter circuit TX2 as input data signal Din2.Error detection Signal ED1 is low level in normal state, and under the abnormality any mistake being detected Become high level.Herein, from the irregular request signal of UVLO circuit U VLO2 output RT21 is also input to or door O5.Irregularly request signal RT21 is low in normal state Level, and become high level under the abnormality that supply voltage reduces.I.e., irregularly ask Signal RT21 also serves as rub-out signal and is input to send together with erroneous detection signal ED1 Device circuit TX2.

And, irregular request signal RT21 is also input to transmitter circuit TX2.Not Regular request signal RT21 is transformed into high level from low level or is transformed into low level from high level Time, the value of input data signal Din2 resends to receptor electricity from transmitter circuit TX2 Road RX2.I.e., not only when supply voltage declines, and supply voltage due to connection on When rising and be converted to normal value, the value of the data signal of sending side and the data signal of reception side Value be synchronized.

And, it is input to send from the regular request signal RT22 of enumerator CTR2 output Device circuit TX2.Regular request signal RT22 is the clock from pierce circuit OSC2 output Signal the most often counts the signal just becoming high level 10 times.By regular request signal RT22, Even if when data value is not changed in, often counting also resends data value 10 times.Therefore, i.e. Make when the data value reconstructed by acceptor circuit RX2 is anti-phase due to noise, also can be the most extensive Multiple right value.

And, enumerator CTR2 is by pulse signal P20 or defeated from UVLO circuit U VLO2 The irregular request signal RT21 gone out resets.That is, enumerator CTR2 by from or door O3 defeated Reset signal RST3 that goes out resets, and described or door O3 input is pulse signal P20 and not Regular request signal RT21.

Transmitter circuit TX2 exports described output pulse signal based on input data signal Din2 P21 and P22.Described output pulse signal P21 and P22 is via primary coil L21 and secondary Coil L22 is input to acceptor circuit RX2.Acceptor circuit RX2 reconstructed data signal And described data signal is exported as outputting data signals Dout2.

Outputting data signals Dout2 via or door O6 be input to microcomputer MCU.This Place, from UVLO circuit U VLO1 output irregular request signal RT11 be input to or Door O6.And, it is input to or door O6 from the timeout signal TO2 of timer TM2 output. That is, irregular request signal RT11 and timeout signal TO2 is as erroneous detection signal ED2 It is input to microcomputer MCU together with outputting data signals Dout2.

Herein, timeout signal TO2 is low level in normal state, and in interval regulation It is not detected by pulse detection signals PD2 after counting (such as 40 times countings) and then becomes high level. And, acceptor circuit RX2 is resetted by timeout signal TO2.It should be noted that normally Under operator scheme, often counting 10 times, by regular request signal RT22 from transmitter circuit TX2 resends data value, and exports pulse detection signals from acceptor circuit RX2 PD2.Therefore, timer TM2 will not reach 40 countings.On the other hand, sending When device circuit TX2 stops waiting, output overtime signal TO2.By regular request signal RT22 can detect the exception in transmitter circuit TX2 operation.

Herein, the clock signal exported from pierce circuit OSC1 is carried out by timer TM2 Counting.And, the pulse detection signals that timer TM2 is exported from acceptor circuit RX2 PD2 or the irregular request signal RT11 from the output of UVLO circuit U VLO1 resets.That is, Timer TM2 by from or door O4 output reset signal RST4 reset, described or door O4 Input be pulse detection signals PD2 and irregular request signal RT11.

The control object of semiconductor device system 2 is such as by insulated gate bipolar transistor (IGBT) power transistor represented.In this case, semiconductor device system 2 basis The outputting data signals Dout1 regenerated by acceptor circuit RX1 controls power transistor ON/OFF, to control the conducting state between power supply and load.

Specifically, it is applied to such as drive according to the semiconductor device system 2 of described 3rd embodiment The DC-to-AC converter of dynamic threephase motor (load) as shown in figure 20.Figure 20 shows Described semiconductor device system 2 is applied to the diagram of DC-to-AC converter.Inversion shown in Figure 20 In its high side and downside, device device each includes that three correspond respectively to u-phase, v-phase and w-phase Error detect circuit EDC (total of six) and three power transistor drives device PTD.

From the control signal (such as UH and UL) of microcomputer MCU output via transmission Device circuit TX1, coil and acceptor circuit RX1 are sent to power transistor drives device PTD, And the ON/OFF as the IGBT of control object is controlled.On the other hand, by error detection The rub-out signal that circuit EDC detects is via transmitter circuit TX2, coil and receptor electricity Road RX2 is sent to microcomputer MCU.

Herein, Figure 21 shows and wherein applies the described inverse of described semiconductor device system 2 Become the sequential chart of the operation of device device.As shown in the curve chart of Figure 21, from microcomputer MCU The control signal (such as UH and UL) of output is pwm control signal, and flows through electronic The electric current (such as IU) of machine is the most controlled.Herein, control signal (such as UH And UL) corresponding to input data signal Din1.

(other embodiments)

The installation example of semiconductor device is not limited to the installation example shown in Fig. 2.Below in conjunction with figure 22 and Figure 23 to semiconductor device other typical case installation example illustrate.Figure 22 is electric capacity Device is as the installation example of described semiconductor device in the case of described insulation coupling element.Figure 23 It is shown in which GMR (giant magnetoresistance) element is used as the described of described insulation coupling element The installation example of semiconductor device.

In fig. 22, replace the installation example shown in Fig. 2 is used as insulation coupling with capacitor The coil of element.More specifically, primary coil is replaced with an electrode PL1 of capacitor L11, and replace secondary coil L12 with another electrode PL2 of capacitor.

In fig 23, the installation shown in Fig. 2 is replaced to show with GMR (giant magnetoresistance) element Example is used as the coil of insulation coupling element.More specifically, although primary coil L11 keeps Constant, but secondary coil L12 replaces with GMR element R12.And show in this installation In example, the pad being connected to transmitter circuit TX1 outfan is formed at semiconductor chip CHP1 On, and the pad being respectively connecting to primary coil L11 opposite end is formed at semiconductor chip On CHP2.Then, transmitter circuit TX1 is connected to shape via pad and joint wire BW Become the primary coil L11 at semiconductor chip CHP2.

As it has been described above, the type of insulation coupling element and layout are not particularly limited.It should be noted that Although having been described above insulation coupling element to be formed on a semiconductor die, but described insulation coupling Element may be alternatively formed to the parts of outside attachment.

Hereinbefore, although have been based on the present invention that inventor made by embodiment and carry out Specifically describe, but the invention is not restricted to above-described embodiment, and self-evidently, not Run counter in the scope of spirit of the present invention, various change can be carried out.

Such as, for the semiconductor device according to described embodiment, Semiconductor substrate, quasiconductor The conduction type (p-type or N-shaped) of layer and diffusion layer (diffusion region) etc. can invert. Therefore, a conduction type in N-shaped and p-type is the first conduction type and another conduction In the case of type is the second conduction type, the first conduction type can be p-type, and second leads Electricity type can be N-shaped.Otherwise, the first conduction type can be N-shaped, and the second conductive-type Type can be p-type.

Those of ordinary skill in the art can as required by the first to the 3rd embodiment and other Embodiment combines.

The although angle from some embodiments describes the present invention, but this area It will be recognized that within spirit and scope of the appended claims, can be with various Modification puts into practice the present invention, and the invention is not restricted to above-mentioned example.

And, the scope of described claim is not restricted to the described embodiments.

Furthermore, it is noted that, it is intended that comprise all authority requirement key element etc. Jljl, even if being modified it in course of the review subsequently.

Claims

1. a transmitter circuit, including:

Pulse-generating circuit, edges based on input data produce pulse signal；

First output driver, based on described pulse signal by according in described edge First end of the insulation coupling element that one output pulse signal output is outside；

Second output driver, based on described pulse signal by according to another in described edge Second end of the second output pulse signal output extremely described insulation coupling element；And

Output halt circuit, rises during self-closing supply voltage and stops described first in stipulated time section Output pulse signal and the output of described second output pulse signal.

Transmitter circuit the most according to claim 1, wherein said output halt circuit bag Include:

Latch cicuit, senses the connection of described supply voltage and maintains the described first output pulse of stopping Signal and the output of described second output pulse signal；And

Timer, wherein

The signal that exports from described timer of response, described latch cicuit release stop described first defeated Go out pulse signal and the output of described second output pulse signal.

Transmitter circuit the most according to claim 2, wherein

Described output halt circuit also includes the first capacitor element and the second capacitor element,

Described latch cicuit has and is connected to the first of power supply via described first capacitor element and deposits Storage node, and there is the second memory node via described second capacitor element ground connection,

Described latch cicuit keeps respectively at described first memory node and described second memory node Voltage inverting each other, and

By be maintained at the voltage response of described first memory node and described second memory node from Described timer output signal and change, described latch cicuit release stop described first output Pulse signal and the output of described second output pulse signal.

Transmitter circuit the most according to claim 1, wherein

Described output halt circuit includes:

First capacitor element and the second capacitor element；

N-type transistor, has the source electrode of ground connection and is connected to electricity via described first capacitor element The drain electrode in source；And

P-type transistor, has and is connected to the source electrode of power supply and connects via described second capacitor element The drain electrode on ground, wherein

The grid of described n-type transistor is connected to the drain electrode of described p-type transistor, and described p-type is brilliant The grid of body pipe is connected to the drain electrode of described n-type transistor, and

Gate voltage and the gate voltage of described p-type transistor according to described n-type transistor release and stop Only described first output pulse signal and the output of described second output pulse signal.

Transmitter circuit the most according to claim 1, wherein

Described output halt circuit includes:

The capacitor element of be connected in power supply and ground；And

It is connected to another the resistor element in described power supply and described ground, wherein

Come according to the voltage connecting node between described capacitor element and described resistor element Release and stop described first output pulse signal and the output of described second output pulse signal.

Transmitter circuit the most according to claim 1, wherein

Supply voltage described in described output halt circuit self-closing rises in stipulated time section by stopping Only the described pulse signal of described pulse-generating circuit generation stops described first output pulse signal Output with described second output pulse signal.

7. a semiconductor device, including:

Transmitter circuit, sends the first output pulse signal and the second output pulse based on input data Signal；

Acceptor circuit, receives described first output pulse signal and described second output pulse signal And reconstruct described input data；And

Primary insulation coupling element and time class B insulation coupling element, make described transmitter circuit and described Acceptor circuit is mutually magnetically coupled, wherein

Described transmitter circuit includes:

Pulse-generating circuit, edges based on described input data produce pulse signal；

First output driver, based on described pulse signal by according in described edge First end of one output pulse signal output extremely described primary insulation coupling element；

Second output driver, based on described pulse signal by according to another in described edge Second end of the second output pulse signal output extremely described primary insulation coupling element；And

Semiconductor device the most according to claim 7, wherein

Described output halt circuit includes:

Timer, wherein

In response to the signal exported from described timer, described latch cicuit releases and stops described first Output pulse signal and the output of described second output pulse signal.

Semiconductor device the most according to claim 8, wherein

Described latch cicuit has and is connected to the first of power supply via described first capacitor element and deposits Storage node, and there is the second memory node via described second capacitor element ground connection；

Described latch cicuit keeps respectively at described first memory node and described second memory node Voltage inverting each other；And

Semiconductor device the most according to claim 7, wherein

Described output halt circuit includes:

First capacitor element and the second capacitor element；

11. semiconductor devices according to claim 7, wherein

Described output halt circuit includes:

The capacitor element of be connected in power supply and ground；And

12. semiconductor devices according to claim 7, wherein

13. semiconductor devices according to claim 7, wherein

Described primary insulation coupling element and described class B insulation coupling element are to be respectively formed at two Coil in individual interconnection layer, said two interconnection layer is stacked on quasiconductor along top-down direction In chip.

14. 1 kinds of data transmission method for uplink, including:

Edges based on input data produce pulse signal；

Based on described pulse signal by the first output pulse signal according in described edge First end of output extremely insulation coupling element, and by according to another second in described edge Second end of output pulse signal output extremely described insulation coupling element；And

Rise during self-closing supply voltage in stipulated time section, stop described first output pulse signal Output with described second output pulse signal.

15. data transmission method for uplink according to claim 14, wherein

When stopping the output of described first output pulse signal and described second output pulse signal,

Sense the connection of described supply voltage and maintain described first output pulse signal of stopping and institute State the output of the second output pulse signal, and

Respond the signal from timer output, release and stop described first output pulse signal and described The output of the second output pulse signal.