CN105990360B - Nonvolatile memory and its manufacturing method - Google Patents
Nonvolatile memory and its manufacturing method Download PDFInfo
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- CN105990360B CN105990360B CN201510060039.7A CN201510060039A CN105990360B CN 105990360 B CN105990360 B CN 105990360B CN 201510060039 A CN201510060039 A CN 201510060039A CN 105990360 B CN105990360 B CN 105990360B
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Abstract
The present invention provides a kind of nonvolatile memory, has storage unit.Storage unit has stacked structure, floating grid, tunnel dielectric layer, gate dielectric layer of erasing, auxiliary gate dielectric layer, source area, drain region, controls dielectric layer between grid and grid.Stacked structure has gate dielectric layer, auxiliary grid, insulating layer and the grid of erasing being set in sequence.Floating grid is set to the side wall of the first side of stacked structure.Tunnel dielectric layer is set under floating grid.Gate dielectric layer of erasing, which is set to, erases between grid and floating grid.Auxiliary gate dielectric layer is set between auxiliary grid and floating grid.Source area and drain region are respectively arranged at stacked structure and floating grid two sides.Control grid is set on source area and floating grid.Dielectric layer is set between control grid and floating grid between grid.
Description
Technical field
The invention relates to a kind of semiconductor element and its manufacturing methods, and deposit in particular to one kind is non-volatile
Reservoir and its manufacturing method.
Background technique
Nonvolatile memory movement, and the number being stored in such as can repeatedly carry out the deposit of data, read, erase due to having
It the advantages of according to that will not disappear after a loss of power, has been widely used in PC and electronic equipment.
A kind of typical nonvolatile memory designs at stack type grid (Stack-Gate) structure, including
It is sequentially arranged at dielectric layer and control grid between the tunnel oxide in substrate, floating grid (Floating gate), grid
(Control Gate).It is respectively at source area, drain region when carrying out sequencing or erase to this flash memory component and operating
Apply appropriate voltage on control grid, so that in electron injection polysilicon floating gate, or by electronics from polysilicon floating grid
It is pulled out in extremely.
Grid coupling efficiency (Gate- in the operation of nonvolatile memory, between usual floating grid and control grid
Coupling Ratio, GCR) it is bigger, operating voltage needed for operation will be lower, and the service speed of flash memory and effect
Rate will be promoted greatly.The method for wherein increasing grid coupling efficiency includes the weight for increasing floating grid and control gate interpolar
Folded area (Overlap Area), the thickness for reducing floating grid and the dielectric layer of control gate interpolar and increase floating grid
Dielectric constant (the Dielectric Constant of dielectric layer between grid between control grid；K) etc..
However, as integrated circuit is just being developed with the element of higher integrated level towards miniaturization, so must reduce non-
The memory cell size of volatile memory is to promote its integrated level.Wherein, the size for reducing storage unit can be deposited by reduction
The methods of interval of the grid length of storage unit and bit line is reached.But grid length, which becomes smaller, can shorten tunnel oxide
The passage length (Channel Length) of layer lower section be easy to cause between drain electrode and source electrode and abnormal electrically perforation occurs
(Punch Through), so will seriously affect the electrical performance of this storage unit.Moreover, in sequencing and or storage of erasing
When unit, electronics repeats to pass over tunnel oxide, will consume tunnel oxide, leads to the reduction of memory component reliability.
Summary of the invention
The present invention provides a kind of nonvolatile memory and its manufacturing method, can be operated with low operating voltage, and then increases
The reliability of semiconductor element.
The present invention provides a kind of nonvolatile memory and its manufacturing method, and the integrated level of element can be improved.
The present invention proposes a kind of nonvolatile memory, has the first storage unit, is set in substrate.This first storage
Unit have stacked structure, floating grid, tunnel dielectric layer, gate dielectric layer of erasing, auxiliary gate dielectric layer, source area, drain region,
Dielectric layer between grid and grid is controlled, wherein stacked structure has the gate dielectric layer being sequentially arranged in substrate, auxiliary grid, absolutely
Edge layer and grid of erasing.Floating grid is set to the side wall of the first side of stacked structure, and the top of floating grid has and turns
Corner, the neighbouring grid of erasing of corner portion, and corner portion height is fallen between erasing gate height.Tunnel dielectric layer is set to floating grid
Between pole and substrate.Gate dielectric layer of erasing, which is set to, erases between grid and floating grid.Auxiliary gate dielectric layer is set to auxiliary
Between grid and floating grid.Source area and drain region are respectively arranged in the substrate of stacked structure and floating grid two sides,
The adjacent floating grid of middle source area, second side of the adjacent stacked structure in drain region, the first side are opposite with second side.Control grid is set
It is placed on source area and floating grid.Dielectric layer is set between control grid and floating grid between grid.
In one embodiment of this invention, above-mentioned nonvolatile memory has more the second storage unit.Second storage is single
Member is set in substrate, and the structure of the second storage unit is identical as the structure of the first storage unit, the second storage unit and the
One storage unit is mirrored into configuration, common source polar region or drain region.
In one embodiment of this invention, above-mentioned first storage unit and the second above-mentioned storage unit share control gate
Pole, and control grid and fill up the opening between the first storage unit and the second storage unit.
In one embodiment of this invention, above-mentioned nonvolatile memory has more third storage unit.Third storage is single
Member is set in substrate, and the structure of third storage unit is identical as the structure of the first storage unit, common source polar region, supplementary gate
Pole, erase grid and control grid, and control grid and fill up between the first storage unit and third storage unit.
In one embodiment of this invention, above-mentioned tunnel dielectric layer is more set between control grid and source area.
In one embodiment of this invention, above-mentioned nonvolatile memory is with more auxiliary gate dielectric layer.Supplementary gate dielectric
Layer is set between floating grid and auxiliary grid, wherein the material of auxiliary gate dielectric layer includes silica/silicon nitride, oxidation
Silicon/nitridation silicon/oxidative silicon or silica.
In one embodiment of this invention, the material of above-mentioned insulating layer includes silica.The material of dielectric layer between above-mentioned grid
Material (dielectric constant k > 4) including silicon oxide/silicon nitride/silicon oxide or nitridation silicon/oxidative silicon or other high dielectric constants.
In one embodiment of this invention, the material of above-mentioned tunnel dielectric layer includes silica, the thickness of tunnel dielectric layer
Between 60 angstroms to 200 angstroms.
In one embodiment of this invention, the material of above-mentioned gate dielectric layer includes silica, and the thickness of gate dielectric layer is less than
Or the thickness equal to tunnel dielectric layer.The material of above-mentioned gate dielectric layer of erasing includes silica, and the thickness for gate dielectric layer of erasing is situated between
Between 100 angstroms to 180 angstroms.
In one embodiment of this invention, the top of above-mentioned floating grid has corner portion, and corner portion angle is less than or waits
In 90 degree.
In one embodiment of this invention, the width of above-mentioned auxiliary grid is greater than the width for grid of erasing, and ties stacking
First side of structure forms stepped profile.Above-mentioned floating grid includes positioned at the first part of auxiliary grid side wall and positioned at erasing
The second part of gate lateral wall.
The present invention provides a kind of manufacturing method of nonvolatile memory, includes the following steps.Firstly, providing substrate.It connects
, in forming at least two stacked structures in substrate, each stacked structure sequentially includes gate dielectric layer, auxiliary grid, absolutely by substrate
Edge layer and grid of erasing.Then, auxiliary gate dielectric layer is formed in stacked structure side wall, assists the top of gate dielectric layer to be located at auxiliary
Grid is helped between grid of erasing, forms tunnel dielectric layer in the substrate between stacked structure.Then, in auxiliary gate dielectric layer
Upper to form gate dielectric layer of erasing, the side wall in the first side of stacked structure forms conductor clearance wall, the base between conductor clearance wall
Source area is formed in bottom.Then, patterned conductor clearance wall, to form floating grid, wherein the top of floating grid, which has, turns
Corner, the neighbouring grid of erasing of corner portion, and corner portion height is fallen between erasing gate height.Then, in the second of stacked structure
Drain region is formed in the substrate of side, the first side is opposite with second side.Then, the dielectric layer between forming grid on floating grid, and
Control grid is formed on dielectric layer between grid.
In one embodiment of this invention, the shape of above-mentioned auxiliary gate dielectric layer, erase gate dielectric layer and conductor clearance wall
Include: to form spacer material layer in stacked structure side wall at step, forms the first conductor layer, the first conductor layer in tunnel dielectric layer
Top between auxiliary grid and grid of erasing.Then, part spacer material layer is removed, to form auxiliary gate dielectric layer.
Then, it erases gate dielectric layer in being formed on auxiliary gate dielectric layer, in forming the second conductor layer in the first conductor layer.Then, it removes
The second conductor layer of part and the first conductor layer, to form conductor clearance wall.
In one embodiment of this invention, above-mentioned the second conductor layer of removal part and the first conductor layer, to be formed between conductor
The step of gap wall includes: to carry out anisotropic etching processing procedure to the second conductor layer and the first conductor layer.
The present invention provides a kind of manufacturing method of nonvolatile memory, includes the following steps.Firstly, substrate is provided, in
At least two auxiliary grid structures are formed in substrate, each auxiliary grid structure sequentially includes gate dielectric layer, auxiliary grid by substrate
And insulating layer.Then, it is formed in auxiliary grid structure side wall and assists gate dielectric layer, in the substrate between auxiliary grid structure
Tunnel dielectric layer is formed, in forming the first conductor layer in substrate.Then, the first conductor layer is patterned, at least exposure auxiliary is formed
The opening of tunnel dielectric layer between gate structure, and the first conductor gap is formed in the side wall of the first side of auxiliary grid structure
Wall.Then, the side wall formation of the first conductor layer exposed in the opening is erased gate dielectric layer, on the first conductor clearance wall with
It erases and forms the second conductor clearance wall by gate dielectric layer.Then, the first conductor layer of part is removed, is erased grid with being formed, in the
Source area is formed in substrate between one conductor clearance wall.Then, the first conductor clearance wall and the second conductor clearance wall are patterned
To form floating grid, wherein the top of floating grid has corner portion, the neighbouring grid of erasing of corner portion, and corner portion height is fallen
Between gate height of erasing.Then, drain region, the first side and second side are formed in the substrate of second side of auxiliary grid structure
Relatively, the dielectric layer between forming grid on floating grid, and control grid is formed on dielectric layer between grid.
In one embodiment of this invention, the width of the opening between above-mentioned first conductor layer be greater than auxiliary grid structure it
Between width.
In nonvolatile memory and its manufacturing method of the invention, in two adjacent storage units of X-direction (line direction)
Structure is identical and is, for example, to be mirrored into configuration, common source polar region or drain region, and share control grid.And (column side in the Y direction
To) adjacent two memory cell structures are identical, common source polar region, auxiliary grid (character line), erase grid and control grid.
Therefore the integrated level of element can be improved.
In nonvolatile memory and its manufacturing method of the invention, auxiliary grid is arranged in parallel with grid of erasing, therefore
The integrated level of element can be improved.
In nonvolatile memory of the invention, the thinner thickness of the gate dielectric layer below auxiliary grid is stored in operation
When unit, lesser voltage can be used and open/close channel region below auxiliary grid, low operating voltage can also be dropped.
In nonvolatile memory and its manufacturing method of the invention, control grid coats floating grid, can increase control
Folded area between grid and floating grid processed, and improve the coupling efficiency of memory component.
In nonvolatile memory and its manufacturing method of the invention, since floating grid is arranged between gate height of erasing
Angled portion, and the angle of this corner portion is less than or equal to 90 degree, concentrates electric field by corner portion, can reduce voltage of erasing,
It is efficient to pull out electronics from floating grid, improve the speed for data of erasing.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make
Carefully it is described as follows.
Detailed description of the invention
Figure 1A is a kind of top view of nonvolatile memory shown by the embodiment of the present invention；
Figure 1B is a kind of diagrammatic cross-section of nonvolatile memory shown by the embodiment of the present invention；
Fig. 1 C is a kind of diagrammatic cross-section of nonvolatile memory shown by another embodiment of the present invention；
Fig. 2A to Fig. 2 H is a kind of cuing open for production process of nonvolatile memory shown by one embodiment of the invention
Face schematic diagram；
Fig. 3 A to Fig. 3 H is a kind of cuing open for production process of nonvolatile memory shown by one embodiment of the invention
Face schematic diagram；
Fig. 4 A is the schematic diagram that an example of programming operations is carried out to storage unit；
Fig. 4 B be storage unit erase operation an example schematic diagram；
Fig. 4 C is the schematic diagram for the example being read to storage unit.
Description of symbols:
100,200,300: substrate；
102: isolation structure；
104: active region；
110,112,114,116, MC: storage unit；
120: stacked structure；
122: gate dielectric layer；
124,124a: auxiliary grid；
126: insulating layer；
128,128a, 352: grid of erasing；
130,234,314: auxiliary gate dielectric layer；
132,236,336: gate dielectric layer of erasing；
140,140a, 256,354: floating grid；
140b: first part；
140c: second part；
141,258,358: corner portion；
142,228,318: tunnel dielectric layer；
146,252,346: source area；
148,260,360: drain region；
150,264,364: control grid；
152,262,362: dielectric layer between grid；
160,268,368: interlayer insulating film；
162,270,370: plug；
164,274,374: bit line；
202,206,210,224,226,302,306,308322: dielectric layer；
204,208,230,240,304,320: conductor layer；
212,254,310,330,350: patterning photoresist layer；
220,356: stacked structure；
222: spacer material layer；
250: conductor clearance wall；
312: auxiliary grid structure；
332: opening；
334: the first conductor clearance walls；
340: the second conductor clearance walls.
Specific embodiment
Figure 1A is a kind of top view of nonvolatile memory shown by the embodiment of the present invention.Figure 1B is of the invention
A kind of diagrammatic cross-section of nonvolatile memory shown by embodiment.Figure 1B is shown to cut open along A-A' line in Figure 1A
Face figure.Fig. 1 C is a kind of diagrammatic cross-section of nonvolatile memory shown by another embodiment of the present invention.
Figure 1A and Figure 1B is please referred to, nonvolatile memory includes multiple storage unit MC.These storage units MC arrangement
It embarks on journey/column array.
Nonvolatile memory is set in substrate 100.Regularly arranged multiple isolation are for example provided in substrate 100
Structure 102, to define the active region 104 with trellis.Isolation structure 102 is, for example, shallow slot isolation structure.
Each storage unit MC includes stacked structure 120, auxiliary gate dielectric layer 130, erase gate dielectric layer 132, floating grid
140, dielectric layer 152 between tunnel dielectric layer 142, source area 146, drain region 148, control grid 150 and grid.In addition, substrate
With more interlayer insulating film 160, plug 162 and bit line 164 on 100.
Stacked structure 120 is from substrate 100 sequentially by gate dielectric layer 122, auxiliary grid (character line) 124, insulating layer 126
And the composition of grid 128 of erasing.Gate dielectric layer 122 is, for example, to be set between auxiliary grid 124 and substrate 100.Gate dielectric layer
122 material is, for example, silica.The thickness of the thickness of gate dielectric layer 122 e.g., less than or equal to tunnel dielectric layer 142.
Auxiliary grid 124 is, for example, to be set between gate dielectric layer 122 and insulating layer 126.Grid 128 of erasing is, for example, to set
It is placed on insulating layer 126.Auxiliary grid 124, grid 128 of erasing e.g. extend in the Y direction.Auxiliary grid 124, grid of erasing
128 material is, for example, the conductors material such as DOPOS doped polycrystalline silicon.Insulating layer 126 is, for example, to be set to auxiliary grid 124 and grid of erasing
Between pole 128.The material of insulating layer 126 is, for example, silica.
Auxiliary gate dielectric layer 130 is, for example, to be set between floating grid 140 and auxiliary grid 124.Assist gate dielectric layer
130 material is, for example, silicon oxide/silicon nitride/silicon oxide or nitridation silicon/oxidative silicon.Assist the thickness of gate dielectric layer 130 for example
More than or equal to the thickness for gate dielectric layer 132 of erasing.Gate dielectric layer 132 of erasing be, for example, be set to erase grid 128 with it is floating
Between grid 140.The material of gate dielectric layer 132 of erasing is, for example, silica.Erase gate dielectric layer 132 thickness for example between
Between 100 angstroms to 180 angstroms.
Floating grid 140 is e.g. set to the side wall of the first side of stacked structure 120, and the top of this floating grid 140
Portion has corner portion 141.The neighbouring grid 128 of erasing of this corner portion 141, and to fall within grid 128 of erasing high for this 141 height of corner portion
Between degree.This 141 angle of corner portion is less than or equal to 90 degree.The material of floating grid 140 is, for example, the conductors material such as DOPOS doped polycrystalline silicon
Material.Floating grid 140 can be made of one or more layers conductor layer.
Tunnel dielectric layer 142 is, for example, to be set between floating grid 140 and substrate 100.This tunnel dielectric layer 142 is for example
It is more to be set between control grid 150 and source area 146.The material of tunnel dielectric layer 142 is, for example, silica.Tunneling dielectric
The thickness of layer 142 is between 60 angstroms to 200 angstroms.
Source area 146 is, for example, to be set in the substrate 100 on 140 side of floating grid.Drain region 148 is, for example, to be set to heap
In the substrate 100 of 120 second side of stack structure, wherein the first side is opposite with second side.Source area 146, drain region 148 are, for example, to contain
There is the doped region of N-type or p-type admixture, holds depending on the design of element.
Control grid 150 is, for example, to be set on source area 146 and floating grid 140.Controlling grid 150 is, for example, in Y
Direction (column direction) extends.The material for controlling grid 150 is, for example, the conductors material such as DOPOS doped polycrystalline silicon.Dielectric layer 152 between grid
It is set between control grid 150 and floating grid 140 in this way.The material of dielectric layer 152 is, for example, silica/nitridation between grid
The material (k > 4) of silicon/oxidative silicon or nitridation silicon/oxidative silicon or other high dielectric constants.
Interlayer insulating film 160 is, for example, to be set in substrate 100, and cover the first storage unit 110 and the second storage
Unit 112.The material of interlayer insulating film 160 is, for example, silica, phosphorosilicate glass, boron-phosphorosilicate glass or other suitable dielectric materials
Material.Plug 162 is, for example, to be set in interlayer insulating film 160, and plug 162 and drain region 148 are electrically connected.The material of plug 162
Matter is, for example, the conductors material such as aluminium, tungsten.Bit line 164 is, for example, to be set on interlayer insulating film 160, and bit line 164 is by slotting
Plug 162 is electrically connected with drain region 148.The material of bit line 164 is, for example, the conductors material such as aluminium, tungsten, copper.
On X-direction (line direction), multiple storage unit MC are serially connected by source area 146 or drain region 148.It lifts
For example, the structure of storage unit 110 is identical with the structure of storage unit 112, and storage unit 110 and storage unit 112 at
Mirror configuration, common source polar region 146 or drain region 148；The structure of storage unit 114 is identical as the structure of storage unit 116, and
Storage unit 114 and storage unit 116 are mirrored into configuration, common source polar region 146 or drain region 148.Meanwhile storage unit 110
Control grid 150 is shared with storage unit 112, and controls grid 150 and fills up between storage unit 110 and storage unit 112；It deposits
Storage unit 114 and storage unit 116 share control grid 150, and control grid 150 and fill up storage unit 114 and storage unit
Between 116.
In the Y direction on (column direction), multiple storage unit MC by source area 146, auxiliary grid (character line) 124, erase
Grid 128 and control grid 150 are serially connected.That is, in a column direction, multiple storage unit MC share the same source area
146, auxiliary grid (character line) 124, erase grid 128 and control grid 150.For example, the structure of storage unit 110
Identical as the structure of storage unit 114, the structure of storage unit 112 is identical as the structure of storage unit 116, controls grid 150
It fills up between storage unit 110 and the structure and storage unit 116 of storage unit 114 and storage unit 112.Same row is deposited
Storage unit 114 and the first storage unit 110 share with source region 146, auxiliary grid (character line) 124, erase grid 128 with
And control grid 150.
Fig. 1 C is a kind of diagrammatic cross-section of nonvolatile memory shown by another embodiment of the present invention.In Fig. 1 C
In, component person identical as Figure 1B gives identical label, and the description thereof will be omitted.
As shown in Figure 1 C, the width of auxiliary grid 124a is greater than the width for the grid 128a that erases, and in stacked structure 120
First side forms stepped profile.Floating grid 140a includes being located at the first part 140b of auxiliary grid 124a side wall and being located at
Erase the second part 140c of grid 128a side wall.
In above-mentioned nonvolatile memory, it is identical in two adjacent storage unit MC structures of X-direction (line direction) and
It is e.g. mirrored into configuration, common source polar region 146 or drain region 148, and shares control grid 150.And (column side in the Y direction
To) adjacent two storage unit MC structures are identical, common source polar region 146, auxiliary grid (character line) 124 (124a), grid of erasing
Pole 128 (128a) and control grid 150.Therefore the integrated level of element can be improved.
In above-mentioned nonvolatile memory, auxiliary grid and gate configuration is erased into stacked structure, therefore can improve
The integrated level of element.
In above-mentioned nonvolatile memory, the thinner thickness of gate dielectric layer 122 can be with when operating storage unit
The channel region below auxiliary grid 124 (124a) is opened/closed using lesser voltage, it can drop low operating voltage.Control
Grid 150 coats floating grid 140 (140a), can increase folded by controlling between grid 150 and floating grid 140 (140a)
Area, and improve the coupling efficiency of memory component.Since floating grid 140 (140a) is in grid 128 (128a) height of erasing
Corner portion 141 is provided between degree, and the angle of this corner portion 141 is less than or equal to 90 degree, makes electric field collection by corner portion 141
In, it can reduce that voltage of erasing is efficient to pull out electronics from floating grid 140 (140a), improve the speed of data of erasing.
Fig. 2A to Fig. 2 H is the production process according to a kind of nonvolatile memory shown by one embodiment of the invention
Diagrammatic cross-section.
A referring to figure 2., first offer substrate 200.Then, in sequentially forming dielectric layer 202, conductor layer in substrate 200
204, dielectric layer 206, conductor layer 208 and dielectric layer 210.The material of dielectric layer 202 is, for example, silica, forming method example
Thermal oxidation method in this way.Conductor layer 204, the material of conductor layer 208 are, for example, DOPOS doped polycrystalline silicon or multi-crystal silicification metal etc..Work as conductor
When layer 204, the material of conductor layer 208 are DOPOS doped polycrystalline silicon, forming method is, for example, that chemical vapour deposition technique is utilized to form one
After layer undoped polysilicon layer, ion implantation step is carried out to be formed；Or it can also be used and be implanted into admixture when participating in the cintest (in-situ)
Method is formed using chemical vapour deposition technique.Dielectric layer 206, dielectric layer 210 material be, for example, silicon oxide or silicon nitride,
Forming method is, for example, chemical vapour deposition technique.
Then, in forming a pattern layers photoresist layer 212 in substrate 200, the forming method of photoresist layer 212 is patterned
E.g. prior to forming a layer photoresist material layer in entire substrate 200, then it is exposed, develops and formed.
B referring to figure 2. removes part dielectric layer 210, conductor layer 208, dielectric to pattern photoresist layer 212 as mask
Layer 206, conductor layer 204 and dielectric layer 202, to form at least two stacked structures 220.Wherein, dielectric layer 202 is used as grid dielectric
Layer.Conductor layer 204 is used as auxiliary grid (character line).Dielectric layer 206 is used as insulating layer.Conductor layer 208 is as grid of erasing.It is situated between
Electric layer 210 is used as curtain layer of hard hood.Then, patterning photoresist layer 212 is removed.Remove the method example of patterning photoresist layer 212
Wet type in this way goes photoresist method or dry type to go photoresist method.
Then, spacer material layer 222 is formed in the side wall of this stacked structure 220.The material of spacer material layer 222 is, for example,
Silicon oxide/silicon nitride/silicon oxide or nitridation silicon/oxidative silicon.The forming method of spacer material layer 222 is, for example, prior to substrate 200
On sequentially form the dielectric layer 224 and dielectric layer 226 for covering each stacked structure 220, then remove part of dielectric layer 224 and dielectric
Layer 226 and in the side wall of stacked structure 220 formed spacer material layer 222.The material of dielectric layer 224 is, for example, silicon nitride, dielectric
The material of layer 226 is, for example, silica.The forming method of dielectric layer 224 and dielectric layer 226 is, for example, chemical vapour deposition technique.It moves
Except the method for part of dielectric layer 224 and dielectric layer 226 is, for example, anisotropic etching method.
Then, tunnel dielectric layer 228 is formed in the substrate 200 between each stacked structure 220.Tunnel dielectric layer 228
Material is, for example, silica, and forming method is, for example, thermal oxidation method.
C referring to figure 2. forms conductor layer 230 in the tunnel dielectric layer 228 between each stacked structure 220.Conductor layer
230 material is, for example, DOPOS doped polycrystalline silicon or multi-crystal silicification metal etc..The forming method of conductor layer 230 is, for example, prior to substrate
Conductor material layer (not shown) is formed on 200, is then removed part conductor material layer and is formed conductor layer 230.Conductor material layer
Forming method be, for example, chemical vapour deposition technique.The method for removing part conductor material layer is, for example, to be etched back lithography or anisotropic
Property etching method.
Then, part spacer material layer 222 is removed, assists gate dielectric layer 234 to be formed.Remove part spacer material layer
222 method is, for example, wet etching.
D referring to figure 2. erases gate dielectric layer 236 in being formed on the side wall, auxiliary gate dielectric layer 234 of stacked structure 220.
The material of gate dielectric layer 236 of erasing is, for example, silica.Erase gate dielectric layer 236 forming method be, for example, prior to shape in substrate
At dielectric layer (not shown), then removes part of dielectric layer and form gate dielectric layer 236 of erasing.The forming method of dielectric layer is for example
It is chemical vapour deposition technique.The method for removing part of dielectric layer is, for example, to be etched back lithography or anisotropic etching method.
Then, conductor layer 240 is formed in the conductor layer 230 between each stacked structure 220.The material example of conductor layer 240
DOPOS doped polycrystalline silicon or multi-crystal silicification metal etc. in this way.The forming method of conductor layer 240 is, for example, chemical vapour deposition technique.
E referring to figure 2. removes part conductor layer 230 and conductor layer 240, to form conductor in the side wall of stacked structure 220
Clearance wall 250.The method for removing part conductor layer 230 and conductor layer 240 is, for example, anisotropic etching method or eatch-back method.
Then, source area 252 is formed in the substrate 200 between conductor clearance wall 250.That is, in stacked structure 220 first
Source area 252 is formed in the substrate 200 on 250 side of conductor clearance wall of side.The forming method of source area 252 is, for example, with the first side
Conductor clearance wall 250 be mask, carry out ion implantation manufacture process.The admixture of implantation can be N-type or p-type admixture, end view member
Depending on the design of part.
Then, in forming a pattern layers photoresist layer 254 in substrate 200.Pattern the forming method of photoresist layer 254
E.g. prior to forming a layer photoresist material layer in entire substrate 200, then it is exposed, develops and formed.
F referring to figure 2., to pattern photoresist layer 254 as mask, between the conductor for removing each 220 second side of stacked structure
Gap wall 250, wherein second side is opposite with the first side.The conductor clearance wall 250 of 220 first side of stacked structure is patterned simultaneously, and
Form floating grid 256.The top of this floating grid 256 has a corner portion 258, the neighbouring grid 208 of erasing of corner portion 258, and
258 height of corner portion is fallen within erase 208 height of grid between.
Then, patterning photoresist layer 254 is removed.The method for removing patterning photoresist layer 254 is, for example, that wet type is delustered
Photoresist method or dry type go photoresist method.
The dielectric layer 262 between forming grid in substrate 200, dielectric layer 262 covers floating grid 256 between this grid.Dielectric between grid
The material of layer 262 includes silicon oxide/silicon nitride/silicon oxide.The forming method of dielectric layer 262 is, for example, to utilize chemical gaseous phase between grid
Sedimentation sequentially forms silicon oxide layer, silicon nitride layer and another layer of silicon oxide layer.The material of dielectric layer 262 is also possible to nitrogen between grid
Change silicon/oxidative silicon or the material (k > 4) of other high dielectric constants.
Then G referring to figure 2. forms control grid 264 between grid on dielectric layer 262.Control the material example of grid 264
DOPOS doped polycrystalline silicon or multi-crystal silicification metal etc. in this way.The forming method for controlling grid 264 is, for example, prior to forming conductor in substrate
Material layer (not shown), then patterned conductor material layer and formed control grid 264.The forming method of conductor material layer is for example
It is chemical vapour deposition technique.
Then, drain region 260 is formed in the substrate 200 by 220 second side of stacked structure.The formation side of drain region 260
Rule carries out ion implantation manufacture process in this way.The admixture of implantation can be N-type or p-type admixture, and end is depending on the design of element.Source
The doping admixture and doping concentration of polar region 252 and drain region 260 may be the same or different.
H referring to figure 2., the insulating layer 268 between being formed from level to level in substrate 200.The material of interlayer insulating film 268 is, for example,
Silica, phosphorosilicate glass, boron-phosphorosilicate glass or other suitable dielectric materials, forming method are, for example, chemical vapor deposition
Method.Then, multiple plugs 270 that drain region 260 is electrically connected are formed in this interlayer insulating film 268.The material of plug 270
Matter is, for example, the conductors material such as aluminium, tungsten.
The step of plug 270 are formed in interlayer insulating film 268 is as follows.Remove part interlayer insulating film 268 first with shape
At the opening of exposure drain region 260.Then, the conductor material layer (not shown) of opening is filled up in one layer of formation in substrate 200.It
Afterwards, part conductor material layer is removed using chemical mechanical milling method or eatch-back lithography, until exposing interlayer insulating film 268.Its
The forming method of split shed is, for example, photolithography techniques.
Then, in formation bit line 274 on interlayer insulating film 268.Bit line 274 is by 260 electricity of plug 270 and drain region
Property connection.The material of bit line 274 is, for example, the conductors material such as aluminium, tungsten, copper.The forming method of bit line 274 is, for example, in base
On bottom 200 formed conductor material layer (not shown), then patterned conductor material layer and form bit line 274.Conductor material layer
Forming method be, for example, chemical vapour deposition technique.
Fig. 3 A to Fig. 3 H is the production stream according to a kind of nonvolatile memory shown by another embodiment of the present invention
The diagrammatic cross-section of journey.
A referring to figure 3., first offer substrate 300.Then, in sequentially forming dielectric layer 302, conductor layer in substrate 300
304, dielectric layer 306 and dielectric layer 308.The material of dielectric layer 302 is, for example, silica, and forming method is, for example, thermal oxide
Method.The material of conductor layer 304 is, for example, DOPOS doped polycrystalline silicon or multi-crystal silicification metal etc..When the material of conductor layer 304 is that doping is more
When crystal silicon, forming method is, for example, after utilizing chemical vapour deposition technique to form one layer of undoped polysilicon layer, to carry out ion plant
Enter step to be formed；Or the method that (in-situ) is implanted into admixture when participating in the cintest can also be used, it is formed using chemical vapour deposition technique.
The material of dielectric layer 306 is, for example, silica, and forming method is, for example, chemical vapour deposition technique.The material example of dielectric layer 308
Silicon nitride in this way, forming method are, for example, chemical vapour deposition technique.
Then, in forming a pattern layers photoresist layer 310 in substrate 300, the forming method of photoresist layer 310 is patterned
E.g. prior to forming a layer photoresist material layer in entire substrate 300, then it is exposed, develops and formed.
B referring to figure 3. removes part dielectric layer 308, dielectric layer 306, conductor to pattern photoresist layer 310 as mask
Layer 304 and dielectric layer 302, to form at least two auxiliary grid structures 312.Dielectric layer 302 is used as gate dielectric layer, conductor layer
304 are used as auxiliary grid (character line), and dielectric layer 306 is used as insulating layer.Then, patterning photoresist layer 310 is removed.Remove figure
The method of case photoresist layer 310 is, for example, that wet type goes photoresist method or dry type to go photoresist method.
Then, auxiliary gate dielectric layer 314 is formed in the side wall of auxiliary grid structure 312.Assist the material of gate dielectric layer 314
E.g. silicon oxide/silicon nitride/silicon oxide or nitridation silicon/oxidative silicon.Assist gate dielectric layer 314 forming method be, for example, prior to
The dielectric layer (not shown) for covering each auxiliary grid structure 312 is formed in substrate 300, is then removed part of dielectric layer and is formed auxiliary
Help gate dielectric layer 314.The forming method of dielectric layer is, for example, chemical vapour deposition technique.Remove part of dielectric layer method be, for example,
Anisotropic etching method.
C referring to figure 3. forms tunnel dielectric layer 318 in the substrate 300 between each auxiliary grid structure 312.Tunnelling is situated between
The material of electric layer 318 is, for example, silica, and forming method is, for example, thermal oxidation method.
Then, in formation conductor layer 320 in substrate 300.The material of conductor layer 320 is, for example, DOPOS doped polycrystalline silicon or polysilicon
Change metal etc..When the material of conductor layer 320 is DOPOS doped polycrystalline silicon, forming method is, for example, to utilize chemical vapour deposition technique shape
After one layer of undoped polysilicon layer, ion implantation step is carried out to be formed；Or (in-situ) implantation when participating in the cintest can also be used and mix
The method of matter, is formed using chemical vapour deposition technique.
Then, in formation dielectric layer 322 in substrate 300.The material of dielectric layer 322 is, for example, silica, forming method
E.g. chemical vapour deposition technique.Then, in forming a pattern layers photoresist layer 330 in substrate 300.Pattern photoresist layer
330 forming method be, for example, prior to forming a layer photoresist material layer in entire substrate 300, be then exposed, develop and
It is formed.
D referring to figure 3. removes part dielectric layer 322 and conductor layer 320 to pattern photoresist layer 330 as mask,
To form the opening 332 at least exposing the tunnel dielectric layer 318 between auxiliary grid structure 312.
Then, the side wall in the first side of auxiliary grid structure 312 forms the first conductor clearance wall 334.Between first conductor
The forming method of gap wall 334 is, for example, to remove part conductor layer 320 and form the first conductor clearance wall 334.Remove part conductor
The method of layer 320 is, for example, anisotropic etching method or eatch-back lithography.Then, patterning photoresist layer 330 is removed.Remove pattern
The method for changing photoresist layer 330 is, for example, that wet type goes photoresist method or dry type to go photoresist method.
Then, the side wall of the conductor layer 320 exposed in opening 332 forms gate dielectric layer 336 of erasing.It erases gate dielectric layer
336 material is, for example, silica, and forming method is, for example, the then removal portion prior to forming dielectric layer (not shown) in substrate
Divide dielectric layer and forms gate dielectric layer 336 of erasing.The forming method of dielectric layer is, for example, chemical vapour deposition technique.Part is removed to be situated between
The method of electric layer is, for example, anisotropic etching method.
E referring to figure 3., on the first conductor clearance wall 334 with form the second conductor by the gate dielectric layer 336 of erasing between
Gap wall 340.The material of second conductor clearance wall 340 is, for example, DOPOS doped polycrystalline silicon or multi-crystal silicification metal etc..Second conductor gap
The forming method of wall 340 is, for example, then to remove part conductor material layer prior to forming conductor material layer (not shown) in substrate
And form the second conductor clearance wall 340.The forming method of conductor material layer is, for example, chemical vapour deposition technique.Remove part conductor
The method of material layer is, for example, anisotropic etching method.
Then, source area 346 is formed in the substrate 300 between the first conductor clearance wall 334.The formation of source area 346
It is mask that method, which is, for example, with the first conductor clearance wall 334 and the second conductor clearance wall 340 of the first side, carries out ion implantation system
Journey.The admixture of implantation can be N-type or p-type admixture, and end is depending on the design of element.
Then, in forming a pattern layers photoresist layer 350 in substrate 300, the forming method of photoresist layer 350 is patterned
E.g. prior to forming a layer photoresist material layer in entire substrate 300, then it is exposed, develops and formed.
F referring to figure 3. removes the second of 312 second side of auxiliary grid structure to pattern photoresist layer 350 as mask
Conductor clearance wall 340, part dielectric layer 322 and conductor layer 320, to erase grid in being formed on auxiliary grid structure 312
352, and pattern the second conductor clearance wall 340 and the first conductor clearance wall 334 and in 312 first side shape of auxiliary grid structure
At floating grid 354.Wherein second side is opposite with the first side.The top of this floating grid 354 has corner portion 358, corner portion
358 neighbouring grids 352 of erasing, and 358 height of corner portion is fallen between erasing 352 height of grid.And it auxiliary grid structure 312, smears
Except grid 352 forms stacked structure 356.Then, patterning photoresist layer 350 is removed.Remove the side of patterning photoresist layer 350
Rule wet type in this way goes photoresist method or dry type to go photoresist method.
G referring to figure 3., the dielectric layer 362 between forming one layer of grid in substrate 300, dielectric layer 362 covers floating grid between this grid
Pole 354.The material of dielectric layer 362 includes silicon oxide/silicon nitride/silicon oxide between grid.The forming method of dielectric layer 362 is for example between grid
It is that silicon oxide layer, silicon nitride layer and another layer of silicon oxide layer are sequentially formed using chemical vapour deposition technique.Dielectric layer 362 between grid
Material is also possible to nitrogenize the material (k > 4) of silicon/oxidative silicon or other high dielectric constants.
Then, control grid 364 is formed on dielectric layer 362 between grid.The material for controlling grid 364 is, for example, doped polycrystalline
Silicon or multi-crystal silicification metal etc..The forming method for controlling grid 364 is, for example, prior to forming conductor material layer (not in substrate 300
Show), then, patterned conductor material layer and formed control grid 364.The forming method of conductor material layer is, for example, chemical gas
Phase sedimentation.
Then, in the substrate 300 of second side of this stacked structure 356, drain region 360 is formed.The formation of drain region 360
Method is, for example, to carry out ion implantation manufacture process.The admixture of implantation can be N-type or p-type admixture, and end is depending on the design of element.
Source area 346 and the doping admixture and doping concentration of drain region 360 may be the same or different.
H referring to figure 3., in formation interlayer insulating film 368 in substrate 300.The material of interlayer insulating film 368 is, for example, to aoxidize
Silicon, phosphorosilicate glass, boron-phosphorosilicate glass or other suitable dielectric materials, forming method are, for example, chemical vapour deposition technique.So
Afterwards, multiple plugs 370 that drain region 360 is electrically connected are formed in this interlayer insulating film 368.The material example of plug 370
The conductors materials such as aluminium, tungsten in this way.
The step of plug 370 are formed in interlayer insulating film 368 is as follows.Remove part interlayer insulating film 368 first with shape
At the multiple openings for exposing drain region 360 respectively.Then, the conductor material layer of opening is filled up (not in one layer of formation in substrate 300
It shows).Later, part conductor material layer is removed using chemical mechanical milling method or eatch-back lithography, until exposing layer insulation
Layer 368.The forming method of its split shed is, for example, photolithography techniques.
Then, in formation bit line 374 on interlayer insulating film 368.Bit line 374 is by 360 electricity of plug 370 and drain region
Property connection.The material of bit line 374 is, for example, the conductors material such as aluminium, tungsten, copper.The forming method of bit line 374 is, for example, in base
On bottom prior in substrate 300 formed conductor material layer (not shown), then patterned conductor material layer and form bit line 374.
The forming method of conductor material layer is, for example, chemical vapour deposition technique.
In the manufacturing method of nonvolatile memory of the invention, in two adjacent storage units of X-direction (line direction)
Structure is identical and is, for example, to be mirrored into configuration, common source polar region or drain region, and share control grid.And (column side in the Y direction
To) adjacent two memory cell structures are identical, common source polar region, auxiliary grid (character line), insulating layer, is erased at gate dielectric layer
Grid and control grid.Therefore the integrated level of element can be improved.
In the manufacturing method of nonvolatile memory of the invention, it is formed by auxiliary grid and grid of erasing is constituted and stacked
Structure, therefore the integrated level of element can be improved.
In the manufacturing method of above-mentioned nonvolatile memory, it is formed by the thickness of the gate dielectric layer under auxiliary grid
It is relatively thin, when operating storage unit, lesser voltage can be used and open/close channel region below auxiliary grid, it can
Low operating voltage drops.It is formed by control grid cladding floating grid, can be increased folded between control grid and floating grid
Area, and improve the coupling efficiency of memory component.Since floating grid is formed with corner portion between gate height of erasing,
And the angle of this corner portion is less than or equal to 90 degree, concentrates electric field by corner portion, can reduce the efficient general of voltage of erasing
Electronics is pulled out from floating grid, improves the speed for data of erasing.
Then, illustrate the operation mode of nonvolatile memory of the invention, including sequencing, erase with reading data etc.
Operation mode.Fig. 4 A is the schematic diagram that an example of programming operations is carried out to storage unit.Fig. 4 B is to carry out to storage unit
Erase operation an example schematic diagram.Fig. 4 C is the schematic diagram for the example being read to storage unit.
A referring to figure 4. applies voltage Vwl_ in the auxiliary grid WL0 of selected memory cell when carrying out programming operations
P, to form channel in the substrate below auxiliary grid, voltage Vwl_p is, for example, 0.6~1.2 volt.Non-selected storage unit
Auxiliary grid WL1 apply 0 volt of voltage.Apply voltage Vsrc_p in source area S；Apply voltage Vcg_ in control grid CG
p；The grid EP1 application voltage Vep_p that erases of erase grid EP0 and the non-selected storage unit of selected memory cell.Voltage
Vsrc_p is, for example, 3~7 volts；Voltage Vcg_p is, for example, 5~9 volts；Voltage Vep_p is, for example, 3~7 volts.Such inclined
Pressure keeps electronics mobile from drain electrode toward source electrode, with the mode that source side hot electron injects, injects the floating grid of selected memory cell
Pole FG0.Since the auxiliary grid WL1 of non-selected storage unit applies 0 volt of voltage, channel region can not be formed, electronics can not
The floating grid FG1 of non-selected storage unit is injected, therefore non-selected storage unit will not be programmed.
B referring to figure 4., erase operate when, in control grid CG apply voltage Vcg_e；In selected memory cell
Erase grid EP0 apply voltage Vep_e；Apply 0 volt of voltage in the grid EP1 that erases of non-selected storage unit.Voltage
Vep_e is, for example, 6~12 volts；Voltage Vcg_e is, for example, -8~0 volt.Utilize the electricity of control grid CG and the grid EP0 that erases
Pressure difference causes FN tunneling effect, the floating grid FG0 electronics for being stored in storage unit is pulled out and removed.
C referring to figure 4. applies voltage vcc in the auxiliary grid WL0 of selected memory cell when being read；In
It controls grid CG and applies 0~Vcc of voltage；Apply 0~Vcc of voltage in the grid EP0 that erases of selected memory cell；It is deposited in non-selected
The grid EP1 that erases of storage unit applies 0~Vcc of voltage.Wherein, voltage vcc is, for example, supply voltage.The above-mentioned bias the case where
Under, it can be by the channel current size of detecting storage unit, to judge the digital information being stored in storage unit.
In the operating method of nonvolatile memory of the invention, when carrying out programming operations, auxiliary grid is applied
Add low-voltage, channel can be formed in the substrate below auxiliary grid, with the mode that source side hot electron injects, electronics is write
Enter floating grid.Erase operate when, using grid of erasing come data of erasing, move electronics via gate dielectric layer of erasing
It removes, number of the electronics Jing Guo tunnel dielectric layer can be reduced, and then improve reliability.In addition, the corner portion of floating grid is set to
It erases between gate height, and the angle of this corner portion is less than or equal to 90 degree, concentrates electric field by corner portion, it can be efficient
Electronics is pulled out from floating grid, improves the speed for data of erasing.
Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to
So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into
Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (19)
1. a kind of nonvolatile memory characterized by comprising
First storage unit, is set in substrate, first storage unit, comprising:
Stacked structure, including gate dielectric layer, auxiliary grid, insulating layer and the grid of erasing being sequentially arranged in the substrate；
Floating grid is set to the side wall of the first side of the stacked structure, and the top of the floating grid has corner portion,
The corner portion grid of erasing, and corner portion height is fallen between the gate height of erasing；
Tunnel dielectric layer is set between the floating grid and the substrate, and the thickness of the gate dielectric layer is less than described
The thickness of tunnel dielectric layer；
It erases gate dielectric layer, is set to described erase between grid and the floating grid；
Gate dielectric layer is assisted, is set between the auxiliary grid and the floating grid, and the thickness of the auxiliary gate dielectric layer
Degree is greater than the thickness of the gate dielectric layer of erasing；
Source area and drain region are respectively arranged in the substrate of the stacked structure and the floating grid two sides, wherein
The adjacent floating grid of the source area, second side of the adjacent stacked structure in the drain region, first side and institute
It is opposite to state second side；
Grid is controlled, is set on the source area and the floating grid；And
Dielectric layer between grid is set between the control grid and the floating grid.
2. nonvolatile memory according to claim 1, which is characterized in that further include:
Second storage unit is set in the substrate, the structure of second storage unit and first storage unit
Structure is identical, and second storage unit and first storage unit are mirrored into configuration, share the source area or described
Drain region.
3. nonvolatile memory according to claim 2, which is characterized in that first storage unit and described second
Storage unit shares the control grid, and the control grid fills up first storage unit and second storage unit
Between opening.
4. nonvolatile memory according to claim 1, which is characterized in that further include:
Third storage unit is set in the substrate, the structure of the third storage unit and first storage unit
Structure is identical, shares the source area, the auxiliary grid, erase grid and the control grid, and the control
Grid fills up between first storage unit and the third storage unit.
5. nonvolatile memory according to claim 1, which is characterized in that the tunnel dielectric layer is more set to described
It controls between grid and the source area.
6. nonvolatile memory according to claim 1, which is characterized in that it is described auxiliary gate dielectric layer material include
Silica/silicon nitride, silicon oxide/silicon nitride/silicon oxide or silica.
7. nonvolatile memory according to claim 1, which is characterized in that the material of the insulating layer includes oxidation
Silicon.
8. nonvolatile memory according to claim 1, which is characterized in that the material of dielectric layer includes oxygen between the grid
The material (k > 4) of SiClx/silicon nitride/silicon oxide or silicon nitride/silica or other high dielectric constants.
9. nonvolatile memory according to claim 1, which is characterized in that the material of the tunnel dielectric layer includes oxygen
SiClx, the thickness of the tunnel dielectric layer is between 60 angstroms to 200 angstroms.
10. nonvolatile memory according to claim 1, which is characterized in that the material of the gate dielectric layer includes oxygen
SiClx.
11. nonvolatile memory according to claim 1, which is characterized in that the material packet of the gate dielectric layer of erasing
Silica is included, the thickness of the gate dielectric layer of erasing is between 100 angstroms to 180 angstroms.
12. nonvolatile memory according to claim 1, which is characterized in that the top of the floating grid, which has, to be turned
Corner, the corner portion angle are less than or equal to 90 degree.
13. nonvolatile memory according to claim 1, which is characterized in that the width of the auxiliary grid is greater than institute
The width for grid of erasing is stated, and forms stepped profile in first side of the stacked structure.
14. nonvolatile memory according to claim 13, which is characterized in that the floating grid includes positioned at described
The first part of auxiliary grid side wall and second part positioned at the gate lateral wall of erasing.
15. a kind of manufacturing method of nonvolatile memory characterized by comprising
Substrate is provided；
In forming at least two stacked structures in the substrate, each stacked structure sequentially includes grid dielectric by the substrate
Layer, auxiliary grid, insulating layer and grid of erasing；
Auxiliary gate dielectric layer is formed in the stacked structure side wall, the top of the auxiliary gate dielectric layer is located at the auxiliary grid
Between the grid of erasing；
Tunnel dielectric layer is formed in the substrate between the stacked structure；
It erases gate dielectric layer in being formed on the auxiliary gate dielectric layer；
Side wall in first side of stacked structure forms conductor clearance wall；
Source area is formed in substrate between the conductor clearance wall；
The conductor clearance wall is patterned, to form floating grid, wherein the top of the floating grid has corner portion, it is described
The corner portion grid of erasing, and corner portion height is fallen between the gate height of erasing；
Drain region is formed in the substrate of second side of the stacked structure, first side is opposite with described second side；
The dielectric layer between forming grid on the floating grid；And
Control grid is formed on dielectric layer between the grid.
16. the manufacturing method of nonvolatile memory according to claim 15, which is characterized in that the supplementary gate dielectric
Layer, erase gate dielectric layer and the conductor clearance wall forming step include:
Spacer material layer is formed in the stacked structure side wall；
In the tunnel dielectric layer formed the first conductor layer, the top of first conductor layer be located at the auxiliary grid with it is described
It erases between grid；
The part spacer material layer is removed, to form the auxiliary gate dielectric layer；
It erases gate dielectric layer described in formed on the auxiliary gate dielectric layer；
In forming the second conductor layer in first conductor layer；And
Part second conductor layer and first conductor layer are removed, to form the conductor clearance wall.
17. the manufacturing method of nonvolatile memory according to claim 16, which is characterized in that remove part described the
Two conductor layers and first conductor layer include: the step of the conductor clearance wall to be formed
Anisotropic etching processing procedure is carried out to second conductor layer and first conductor layer.
18. a kind of manufacturing method of nonvolatile memory characterized by comprising
Substrate is provided；
In forming at least two auxiliary grid structures in the substrate, each auxiliary grid structure sequentially includes by the substrate
Gate dielectric layer, auxiliary grid and insulating layer；
Auxiliary gate dielectric layer is formed in the auxiliary grid structure side wall；
Tunnel dielectric layer is formed in the substrate between the auxiliary grid structure；
In forming the first conductor layer in the substrate；
First conductor layer is patterned, is formed and at least exposes opening for the tunnel dielectric layer between the auxiliary grid structure
Mouthful, and the first conductor clearance wall is formed in the side wall of the first side of the auxiliary grid structure；
Gate dielectric layer of erasing is formed in the side wall for first conductor layer that the described opening is exposed；
In on the first conductor clearance wall with the side wall of the gate dielectric layer of erasing formed the second conductor clearance wall；
The first conductor layer of part is removed, to form grid of erasing；
Source area is formed in the substrate between the first conductor clearance wall；
The first conductor clearance wall and the second conductor clearance wall are patterned to form floating grid, wherein the floating grid
Top has corner portion, the neighbouring grid of erasing of the corner portion, and corner portion height falls within the grid height of erasing
Between degree；
Drain region, first side and second side phase are formed in the substrate of second side of the auxiliary grid structure
It is right；
The dielectric layer between forming grid on the floating grid；And
Control grid is formed on dielectric layer between the grid.
19. the manufacturing method of nonvolatile memory according to claim 18, which is characterized in that first conductor layer
Between the opening width be greater than the auxiliary grid structure between width.
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| CN108695332B (en) * | 2018-05-18 | 2021-05-07 | 上海华虹宏力半导体制造有限公司 | Split-gate flash memory and forming method and control method thereof |
| TWI696272B (en) * | 2018-11-30 | 2020-06-11 | 力晶積成電子製造股份有限公司 | Memory structure and manufacturing method thereof |
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| US5268319A (en) * | 1988-06-08 | 1993-12-07 | Eliyahou Harari | Highly compact EPROM and flash EEPROM devices |
| CN102044545A (en) * | 2009-10-20 | 2011-05-04 | 中芯国际集成电路制造(上海)有限公司 | Flash memory of discrete gate and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5268319A (en) * | 1988-06-08 | 1993-12-07 | Eliyahou Harari | Highly compact EPROM and flash EEPROM devices |
| CN102044545A (en) * | 2009-10-20 | 2011-05-04 | 中芯国际集成电路制造(上海)有限公司 | Flash memory of discrete gate and manufacturing method thereof |
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