CN100527423C - Self-alignment non-volatile memory and method for manufacturing same - Google Patents
Self-alignment non-volatile memory and method for manufacturing same Download PDFInfo
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- CN100527423C CN100527423C CNB2004100869691A CN200410086969A CN100527423C CN 100527423 C CN100527423 C CN 100527423C CN B2004100869691 A CNB2004100869691 A CN B2004100869691A CN 200410086969 A CN200410086969 A CN 200410086969A CN 100527423 C CN100527423 C CN 100527423C
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Abstract
The non-volatile memory comprises a base with stack layer. Wherein, covering a sacrificial layer with a first opening on said stack layer; forming a first gap wall on side wall of the first opening; with this gap as mask, etching the stack layer to form a second opening and a isolation layer to cover partly the openings; then covering a conductive layer to be used as second mask to etch the stack layer and form grid structure.
Description
Technical field
The present invention relates to a kind of semiconductor making method, particularly relate to the separate gate flash memory structure that this method of a kind of separate gate (split gate) flash memory making method and mat thereof forms.
Background technology
General alleged non-volatility memorizer, for example flash memory can continue to preserve data under power down state, and its reading and writing data then adjusts by the critical voltage (thresholdvoltage) of adjusting control gate (control gate).
Figure 1 shows that read-only memory (the electricallyerasable and programmable read only memory that existing a kind of electronics can be erased and programme; EEPROM) profile.In substrate 100, be to form gate dielectric 102 and a plurality of floating grids 104 on it wherein by the optical semiconductor carving technology.Insulating barrier 114 then compliance be covered in substrate 100 and floating gate 104 surfaces.Control grid layer 116 is covered on this insulating barrier 114 in regular turn with 118 of dielectric layers.Then generally carry out photoetching process again, on dielectric layer 118, form photoresist mask 120, use between two floating gates 104, defining the control grid, that is the defined zone of dotted line among Fig. 1.
In general, finish as the EEPROM flash memory structure as Fig. 1 and need Twi-lithography technology at least to form floating gate 104 and control gate 106 respectively.Also therefore, its technology is comparatively complicated and cost is higher.
In addition, when aligning (alignment) control of photoetching process is accurate inadequately, then cause the channel width difference of 104 of floating gates easily.That is as shown in Figure 1, the channel width 106A and the 106B of two floating gates 104 are inconsistent because of alignment error, also therefore influence this type of reliability of products.
Summary of the invention
One object of the present invention is to provide a kind of manufacture method, can define the channel width (channel width) of floating gate (floating gate) by self-aligned (self-aligned) mode, and can select the grid channel width, use generation and have the fixedly memory construction of floating gate channel width.
Another object of the present invention is to provide a kind of formation to have the method for the flash memory structure of separate gate.Its method is more simple and easy and low-cost.
An aspect of of the present present invention provides a kind of non-volatility memorizer of self-aligned, and the reservoir of two separation has identical width, is arranged in the substrate.Then be provided with a grid between two reservoir, the width of reservoir then defines by clearance wall (spacer).
In addition, another aspect of the present invention provides the manufacture method of the non-volatility memorizer of self-aligned.After forming a stack layer (stacked layer) in the substrate, form sacrifice layer (sacrificial layer) thereon, on this sacrifice layer, then form first opening.On the sidewall of first opening, form first clearance wall earlier.Be mask with this first clearance wall then, this stack layer of etching is to form second opening.Form a separator then and cover first and second opening with part.Then cover a conductive layer thereon, again with the conductive layer of this part as second mask, with this stack layer of etching.
For allow above-mentioned purpose of the present invention, feature, and advantage can become apparent, following conjunction with figs. and preferred embodiment are to illustrate in greater detail the present invention.
Description of drawings
Figure 1 shows that the profile of existing a kind of separate gate structure flash memory.
Fig. 2 A-2H is depicted as the method flow according to the formation one separate gate flash memory of first embodiment of the invention.
Fig. 2 I is depicted as the top view according to a kind of separate gate flash memory of the present invention.
Fig. 2 J is depicted as the profile according to the J-J ' tangent line of Fig. 2 I.
Fig. 3 A-3F is depicted as the method flow according to the formation one separate gate flash memory of second embodiment of the invention.
Fig. 4 A-4E is depicted as the method flow according to the formation one separate gate flash memory of third embodiment of the invention.
The simple symbol explanation
100: substrate, 102: gate dielectric, 104: floating gate, 106A, 106B: grid channel width, 114: insulating barrier, 116: control grid layer, 118: dielectric layer, 120: photoresist mask, 200: substrate, 202: tunneling dielectric layer, 204: electric charge capture layer, 204a, 204b: floating gate, 206,206a: an interlayer dielectric layer, 208,208a, 208b: control gate, 210,210a: stack layer, 212: sacrifice layer, 214: the first openings, 216,: first clearance wall, 218: the second openings, 220: the second clearance walls, 224: select gate dielectric layer, 226: conductive layer, 228: mask layer, 230: the third space wall, 232: interlayer dielectric layer, 234: contact plunger, 240: a pair of memory cell, 240a, 240b: a pair of reservoir, 242,244: control gate line, 246,248: gate line, 250: bit line, 260: a pair of memory cell, 262,264: contact point, 280: width, 300: substrate, 302: tunneling dielectric layer, 304: the floating gate layer, 306: sacrifice layer, 308: the first openings, 310: the first clearance walls, 312: the second openings, 314: separator, 316: conductive layer, 318: mask layer, 320,322: floating gate, 400: substrate, 402: the first oxide skin(coating)s, 404: nitride layer, 406: the second oxide skin(coating)s, 408: stack layer, 410: sacrifice layer, 412: the first openings, 414: the first clearance walls, 416: the second openings, 418: separator, 420: conductive layer.
Embodiment
Three preferred embodiments are below described.First embodiment is the flash memory structure that has a floating gate (being reservoir (storage block)), a control gate (control gate) and selection grid (select gate) in order to explanation.Second embodiment then has the flash memory of floating gate (reservoir) and control gate in order to explanation.The 3rd embodiment then illustrates a kind of stack architecture, comprises one first silicon oxide layer, a silicon nitride layer (reservoir) and one second silicon oxide layer.Among these a little embodiment, the reservoir width of channel all defines by clearance wall
First embodiment
Shown in Fig. 2 A, in a substrate 200, preferred person is a silicon base, is provided with tunneling dielectric layer (tunneling dielectric layer) 202, and preferred person is a silicon oxide layer.On this tunneling dielectric layer 202, then form a stack layer 210.In the present embodiment, stack layer 210 can be the stacking-type film, comprises an electric charge capture layer (charge trapping layer) 204, one an interlayer dielectric layer 206 and a control grid layer 208.Electric charge capture layer 204 and this control grid layer 208 can be made of polycrystalline silicon material, and interlayer dielectric layer 206 then is ONO film (that is a stacking-type film, have one first silicon oxide layer, a silicon nitride layer, one second silicon oxide layer).Moreover a SONOS structure also can adopt.For example: electric charge capture layer 204 is oxide skin(coating) for silicon nitride layer, this control grid layer 208 for polysilicon interlayer dielectric layer 206.Then on this stack layer 210, form a sacrifice layer 212, preferred this sacrifice layer 212 of person can comprise silicon nitride.
Shown in Fig. 2 B, this sacrifice layer 212 carries out patterning by general photoetching and engraving method, with in wherein forming first opening 214.Then form one first dielectric layer (not illustrating) on stack layer 210, then carry out etch-back again, on the sidewall of this first opening 214, to form two first clearance walls 216.Preferred person, this first dielectric layer is made of silica, and forms by anisotropic etch process (anisotropic etching).
Then referring to Fig. 2 C, this stack layer 210 further with first clearance wall 216 and this sacrifice layer 212 as first mask, form second opening 218 with this stack layer 210 of anisotropic etching.Then referring to Fig. 2 D, deposit second dielectric layer (not illustrating), preferred person is deposited on substrate 200 surfaces for silica, then again with this second dielectric layer of anisotropic etching etch-back, and forms second clearance wall 220 on the sidewall of this second opening 218.Then thermal oxidation is carried out in substrate 200, formed with the partial oxidation that will expose in second opening 218 and select gate dielectric layer 224.
According to Fig. 2 E, then on this sacrifice layer 212, form a conductive layer 226 to fill up this first and second opening, its preferable material is a polysilicon.Then remove the partially conductive layer 226 on the sacrifice layer 212, for example use chemical mechanical milling method or etch-back method.Then adopt the thermal oxidation mode to handle this conductive layer that exposes 226, use barrier enough when subsequent etch is provided to form a mask layer 228.
Shown in 2F, by mask layer 228 and first clearance wall 216 as second mask, with anisotropic etch process etch sacrificial layer 212 and this stack layer 210.Stack layer 210a after the etching comprises the conductive layer 226 of a floating gate 204a (the following reservoir that also is regarded as), an interlayer dielectric layer 206a, a control gate 208a and conduct selection grid.
Because reservoir 204a (floating gate) defines by first clearance wall 216 on it, therefore finish itself width of back with and floating gate channel width unanimity all.Moreover, because of a pair of (a pair) reservoir 204a and 204b are defined by first clearance wall 216, but not define, so more can guarantee the consistency of the two width with traditional photoetching process.Also therefore, reliability of products also improves relatively.In addition, owing to select grid between floating gate, its channel width also is easy to be consistent.Shown in Fig. 2 F,, and form by the self-aligned mode because its structure is to define with this mask layer 228 with this first clearance wall 216.Therefore, reduced photoetching process one, so can reduce production costs and simplify production procedure.
Shown in Fig. 2 G, a third space wall 230 forms on the sidewall of the stack layer 210a behind this patterning and first clearance wall 216.In Fig. 2 H, follow the comprehensive interlayer dielectric layer 232 that on the surface of substrate 200, forms.In this interlayer dielectric layer 232, form contact plunger 234 then, to be electrically connected the regions and source 236 in the substrate 200.
Fig. 2 I is depicted as the top view according to a kind of self-aligned flash memory structure of the present invention.And Fig. 2 H is the profile of Fig. 2 I along 2H-2H ' tangential direction.In Fig. 2 H, two reservoir 204a and 204b with same widths are arranged in the substrate 200, and one deck is worn and satisfied dielectric layer 202 then between reservoir 204a, 204b and substrate 200.All be isolated from each other between substrate 200 and two reservoir 204a and the 204b.Also be provided with selection grid in the substrate 200 and between two reservoir 204a and the 204b, that is conductive layer 226.This two reservoir 204a and 204b then define with two adjacent clearance walls 216 on it and form, and therefore have identical width 280.
Because select grid to be arranged in the substrate 200, and shared mutually with 204b by two floating gate 204a, therefore the memory cell structure shown in Fig. 2 H is more tight.Therefore, also reach the effect of dwindling memory cell size.
Fig. 2 J is the profile along 2J-2J ' tangential direction on Fig. 2 I.Interlayer dielectric layer 206a and control gate 208a are positioned on the shallow-channel isolation region 201 in the substrate 200, select grid (being conductive layer 226) then therebetween.216 of first clearance walls are positioned on each control gate 208a, and mask layer 228 is positioned on these selection grid 226.
With reference to Fig. 2 I, this self-aligned non-volatility memorizer comprises that how parallel gate line 248, multidigit line 250 are with many to memory cell 240.Each gate line 248 extends toward the Y direction, and two parallel control gate line 242 and 244 then are divided into the both sides of gate line 246.
Each comprises a gate electrode (gate electrode) to memory cell 240, and the gate line 246 corresponding with is of coupled connections.Two control gates then are coupled in the control gate line 242 and 244 of the correspondence of gate line 246 both sides.Two reservoir 240a and 240b (being floating gate) lay respectively at the two opposite sides of gate electrode.Reservoir 240a and 240b are as floating gate, and first and second contact point 262 and 264 is then respectively adjacent to two reservoir 240a and 240b.
First and second is adjacent one another are to memory cell 240 and 260, and controls by one of gate line 248.The first make contact (contact) 262 of 250 of bit lines and first pair of memory cell 240, and second contact point 264 of second pair of memory cell 260 is electrical connection.If bit line 250 intersects vertically with gate line 248, then do not have potential drop (potential drop) in the memory cell of same column.Therefore, shown in Fig. 2 I, most preferred bit lines 250 are to extend generally along directions X, and are provided with the Z word pattern, and are isolated from each other.In addition, bit line may be designed to when producing potential drop, can be electrically connected and separate each any spread pattern to memory cell.
Memory cell shown in Fig. 2 H has the interlayer dielectric layer of floating polysilicon moving grid and ONO film, the programming of its operation (programming), erase (erase) with read (read) voltage such as following table 1 is listed.Wherein FG1 and FG2 represent floating gate 204a and 204b respectively, and Vsg puts on the voltage of selecting grid 226, and Vs and Vd are respectively the voltage that puts on source electrode and drain electrode 236, and Vcg1 and Vcg2 represent the voltage that puts on control gate 208a and 208b respectively.By this, self-aligned flash memory of the present invention can be operated according to this.
Table 1: memory cell operation
Second embodiment
As shown in Figure 3A, substrate 300, preferred person can adopt silicon base, has a tunneling dielectric layer (tunneling dielectric layer) 302 on it, and the preferred person of this layer can be silica.And on tunneling dielectric layer 302, floating gate layer 304 being set then, preferred person can be polycrystalline silicon material and constitutes.Then on floating gate layer 304, cover a sacrifice layer 306 again, preferred person can adopt silicon nitride material.
Shown in Fig. 3 B, with general photoetching process patterning and this sacrifice layer 306 of etching, to form one first opening 308.Then form one first dielectric layer (not illustrating) thereon, carry out etch-back again, on the sidewall of this first opening 308, to form a pair of first clearance wall 310.Preferred person, this first dielectric layer is made of silica, and forms by anisotropic etch process (anisotropic etching).
Then referring to Fig. 3 C, this floating gate layer 304 further with first clearance wall 310 as first mask, with anisotropic etching floating gate layer 304 to form second opening 312.Then referring to Fig. 3 D, this first clearance wall 310 that early forms is removed, and substrate 300 of exposing in first and second opening 308 and 312 then and floating gate layer 304 further oxidation processes are with formation separator 314, that is silica.In another embodiment, then keep first clearance wall 310, the substrate 300 and the then oxidized formation separator of floating gate 304 that in second opening 312, expose.
Referring to 3D figure, on sacrifice layer 306, further fill a conductive layer 316 (preferred person is a polycrystalline silicon material), again to fill up first and second opening.Then, remove the conductive layer on the sacrifice layer 306, and keep the conductive layer 316 in first and second opening with cmp or etch-back mode.Shown in Fig. 3 E, this conductive layer 316 further by thermal oxidation to form a mask layer 318, the barrier that provides subsequent etch enough is provided.
Shown in Fig. 3 F, with this mask layer 318 as mask, with sacrifice layer 306 and floating gate layer 304 further with anisotropic etch process etching in regular turn.By this, etched floating gate layer 304 forms two floating gates 320 and 322, and etched conductive layer 316 is then as control gate and selection grid.
The stack layer of formed patterning comprises floating gate 320,322 and conductive layer 316, can further form third space wall (not illustrating) on its sidewall.Then can form interlayer dielectric layer (not illustrating), the comprehensive surface that is covered in substrate 300.Then form contact plunger (not illustrating) in this interlayer dielectric layer, with substrate 300 on source/drain be and be electrically connected.
Because reservoir (that is floating grid 320 and 322) is defined by aforesaid first clearance wall 310 and forms, so grid width and grid width of channel all can be consistent, and the minimizing error.Moreover a pair of reservoir 320 that is defined by first clearance wall 310 more can make the two form identical width with 322 comparable conventional lithography mode definiens.In addition, said method also can reduce photoetching process one time, and can reduce production costs.
According to the programming of above-mentioned formed memory cell, erase and operation such as read, be well known to those skilled in the art, repeat no more herein.
The 3rd embodiment
Shown in Fig. 4 A, a substrate 400 is provided, preferred person can adopt silicon base, has a stack layer (stacked layer) 408 on it.Stack layer 408 can be a storehouse film, comprising: one first oxide skin(coating) 402, mononitride layer 404 and one second oxide skin(coating) 406.Then on stack layer 408, cover a sacrifice layer 410 again, preferred person can adopt silicon nitride material.
Shown in Fig. 4 B, with general photoetching process patterning and this sacrifice layer 410 of etching, to form first opening 412.Then form first dielectric layer (not illustrating) thereon, then carry out etch-back again, on the sidewall of first opening 412, to form a pair of first clearance wall 414.Preferred person, first dielectric layer is made of silica, and forms by anisotropic etch process (anisotropic etching).
Then referring to Fig. 4 C, this stack layer 408 further with this to first clearance wall 414 as first mask, anisotropic etching stack layer 408 is to form second opening 416.And first clearance wall 414 in first and second opening 412 and 416 and second oxide skin(coating) 406 then remove with isotropic etching, for example soak with hydrogen fluoride solution (HF).Then, in first and second opening 412 and 416 and on the sacrifice layer 410, formation one separator 418 of compliance, preferred person is a silicon oxide layer.
Referring to Fig. 4 D, on this sacrifice layer 410, form conductive layer 420, preferred person is a polycrystalline silicon material, and fills up this first and second opening 412 and 416.Follow this conductive layer 420 of etching, for example with cmp (chemical mechanical polishing; CMP) or the etch-back method, this conductive layer is etched to only retains in first and second opening 412 and 416.
Shown in Fig. 4 E, with conductive layer 420 as second mask, previous sacrifice layer 410, separator 418, silicon nitride layer 404 and first silicon oxide layer 402 that forms of anisotropic etching in regular turn.By this, the silicon nitride layer 404 after this etching can be used as a reservoir, and conductive layer 420 can be used as a control gate and selects grid.
Then, can on the sidewall of stack layer behind the patterning (comprising first silicon oxide layer 402 and silicon nitride layer 404) and separator 418, form third space wall (not illustrating), cover an interlayer dielectric layer again in substrate 400.Then in interlayer dielectric layer, form contact plunger, become to be electrically connected with source/drain in the substrate 400.
As three embodiment of above exposure, reservoir all is to form by the definition of first clearance wall, and therefore every pair of reservoir can have identical width and identical channel width, and also can reach the effect that size is dwindled simultaneously.In addition, every pair by the defined reservoir of first clearance wall, can existing photoetching process definien have more conforming width, and reduce error.Also therefore, its product reliability also can promote.Moreover, reduce by a photoetching process and also can simplify manufacturing process and reduce production costs.
The programming of the formed memory cell structure of above method, erase and operation such as read and write, be the state of the art, repeat no more herein.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (24)
1, a kind of non-volatility memorizer of self-aligned comprises:
One substrate:
Two reservoir of separating are positioned in this substrate, and this two reservoir has identical width;
One first clearance wall is arranged on each storage part, and the width of this each reservoir is defined by this first clearance wall; And
One grid is in this substrate and between this two reservoir.
2, the non-volatility memorizer of self-aligned according to claim 1, wherein each reservoir is made of polysilicon or silicon nitride.
3, the non-volatility memorizer of self-aligned according to claim 1 also comprises a tunneling dielectric layer, between this substrate and this two reservoir.
4, the non-volatility memorizer of self-aligned according to claim 1 also comprises a gate dielectric, between this substrate and this grid.
5, the non-volatility memorizer of self-aligned according to claim 1 also comprises:
One interlayer dielectric layer is positioned on each reservoir; And
One control gate is positioned on this interlayer dielectric layer.
6, the non-volatility memorizer of self-aligned according to claim 5, wherein this grid is that the reservoir that should respectively separate is then as floating gate as selection grid.
7, the non-volatility memorizer of self-aligned according to claim 5, also comprise one second clearance wall, adjacent with the formed stack layer of this each reservoir, this interlayer dielectric layer and this control gate, wherein this stack layer and this grid are isolated with this second clearance wall.
8, the non-volatility memorizer of self-aligned according to claim 1, wherein this grid is positioned on those reservoir.
9, the non-volatility memorizer of self-aligned according to claim 8, wherein this grid is selected grid as a control gate and.
10, the non-volatility memorizer of self-aligned according to claim 8 also comprises a separator, is arranged between those reservoir and this grid.
11, a kind of method with self-aligned manufacturing non-volatility memorizer comprises:
One substrate that comprises a stack layer is provided;
Form a sacrifice layer on this stack layer;
This sacrifice layer of patterning is to form one first opening;
Form one first clearance wall on a sidewall of this first opening;
As one first mask, this stack layer of etching is to form one second opening with this first clearance wall and this sacrifice layer;
Form a conductive layer and be covered in this first opening and this second opening; And
With this conductive layer as one second mask, this stack layer of etching.
12, the method for making non-volatility memorizer with self-aligned according to claim 11, wherein this stack layer comprises a floating gate layer, an interlayer dielectric layer and a control grid layer, and this conductive layer is selected grid as one, and a dielectric layer is between this stack layer and this substrate.
13, the method with self-aligned manufacturing non-volatility memorizer according to claim 12 before forming this conductive layer, also comprises the steps:
In this first opening and this second opening, form a separator; And
This separator of etch-back is to form one second clearance wall on a sidewall of this second opening.
14, the method for making non-volatility memorizer with self-aligned according to claim 13, wherein when this separator of etch-back, can expose this substrate, and this method comprises that also this substrate oxidation of will expose in second opening is to form a selection gate dielectric layer.
15, the method with self-aligned manufacturing non-volatility memorizer according to claim 12, wherein this floating gate layer is polysilicon or silicon nitride.
16, according to claim 11ly make the method for non-volatility memorizer, also comprise this conductive layer oxidation forming a mask layer with self-aligned, and, utilize this mask layer and this conductive layer as another mask, with this conductive layer of etching.
17, the method with self-aligned manufacturing non-volatility memorizer according to claim 11, wherein this conductive layer comprises polysilicon.
18, the method with self-aligned manufacturing non-volatility memorizer according to claim 11, wherein this stack layer comprises the floating gate layer and a tunneling dielectric layer of polysilicon.
19, according to claim 18ly make the method for non-volatility memorizer with self-aligned, also be included in form this conductive layer before, formation one separator in this first opening and this second opening earlier.
20, according to claim 19ly make the method for non-volatility memorizer with self-aligned, also be included in form this separator before, remove this first clearance wall.
21, the method for making non-volatility memorizer with self-aligned according to claim 20, wherein after removing this first clearance wall, to expose this floating gate layer and this substrate, and in this first opening and this second opening, form this separator, then form by floating gate layer that this is exposed and substrate oxidation.
22, the method with self-aligned manufacturing non-volatility memorizer according to claim 11, wherein this stack layer comprises that first oxide layer, mononitride layer are positioned on this first oxide layer and one second oxide skin(coating) is positioned on this nitride layer.
23, the method with self-aligned manufacturing non-volatility memorizer according to claim 22 before forming this conductive layer, also comprises the following steps:
This first clearance wall and this second oxide skin(coating) of removal in this first opening; And
In this first opening and this second opening, form a separator.
24, the method with self-aligned manufacturing non-volatility memorizer according to claim 23, wherein the step of this separator of formation in this first opening and this second opening comprises that deposition monoxide layer is on this substrate and this sacrifice layer.
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| CNB2004100869691A CN100527423C (en) | 2004-10-20 | 2004-10-20 | Self-alignment non-volatile memory and method for manufacturing same |
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| CN101847606A (en) * | 2009-03-24 | 2010-09-29 | 华邦电子股份有限公司 | Nonvolatile memory and manufacture method thereof |
| US8450207B2 (en) * | 2011-06-21 | 2013-05-28 | Nanya Technology Corp. | Method of fabricating a cell contact and a digit line for a semiconductor device |
| CN105324707B (en) * | 2013-06-12 | 2020-06-12 | 唯景公司 | Pretreatment of Transparent Conductive Oxide (TCO) films for improved electrical contact |
| CN107039334B (en) * | 2016-02-03 | 2019-09-27 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
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