CN105990252B - Memory construction and its manufacturing method - Google Patents
Memory construction and its manufacturing method Download PDFInfo
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- CN105990252B CN105990252B CN201510098924.4A CN201510098924A CN105990252B CN 105990252 B CN105990252 B CN 105990252B CN 201510098924 A CN201510098924 A CN 201510098924A CN 105990252 B CN105990252 B CN 105990252B
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- 238000010276 construction Methods 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 238000003475 lamination Methods 0.000 claims abstract description 98
- 239000004020 conductor Substances 0.000 claims abstract description 69
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000009413 insulation Methods 0.000 claims abstract description 10
- 239000012774 insulation material Substances 0.000 claims 1
- 238000000034 method Methods 0.000 description 18
- 238000005520 cutting process Methods 0.000 description 8
- 239000011810 insulating material Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000002305 electric material Substances 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000010941 cobalt Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 1
- 229910019001 CoSi Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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Abstract
The invention discloses provide a kind of memory construction and its manufacturing method herein.This memory construction includes a substrate, multiple laminations, multiple memory layers, a conductive material and multiple conducting wires.Lamination is located on substrate.Lamination is separated from each other by multiple grooves.Multiple conductions that lamination respectively includes alternately storehouse are being got lines crossed and multiple insulation are being got lines crossed.Memory layer distinguishes conformal covering lamination.Conductive material is located in groove and on lamination.Conductive material in the trench forms one or more holes in these groove each.Conducting wire is located on conductive material.Conducting wire respectively includes a first part and a second part, and first part and second part are connected to each other, and first part extends along the direction of the extending direction perpendicular to lamination, and second part extends along the extending direction of lamination.
Description
Technical field
The present invention relates to a kind of semiconductor structure and its manufacturing methods, especially with regard to a kind of memory construction and its system
Make method.
Background technique
Memory generally comprises array area (array region) and peripheral region (periphery region).Position is in array
The storage unit in area is controlled by conducting wire (such as bit line and wordline).These conducting wires extend to peripheral region from array area, and
Peripheral region connects decoder.In the array region, conducting wire can be formed under the environment of rule.However, for example close to boundary
Region, conducting wire must be formed under complex environment.This complex environment may cause higher failure rate.Citing comes
It says, in typical three-dimensional perpendicular grid nand memory, the lamination for being fanned out to (fan-out) and being partially formed in bit line of wordline
Outside.That is, wordline is manufactured in a manner of across bit line boundary.Therefore, optics or quarter based on line boundary area in place
The not predictability of erosion behavior, bridge joint (bridge) may betide between wordline.
Summary of the invention
In the present invention, a kind of memory construction of improvement is provided.Conducting wire on lamination its to be fanned out to part be to build
It makes in a virtual array area, also that is, being built on virtual lamination.In this way, which conducting wire is whole all in relatively regular region
Middle formation, can reduce failure rate.
According to some embodiments, a kind of manufacturing method of memory construction is provided.This manufacturing method includes the following steps.
Firstly, forming multiple laminations on a substrate.These laminations are separated from each other by multiple grooves.Lamination respectively includes alternately storehouse
Multiple conductions get lines crossed and it is multiple insulation get lines crossed.Form the conformal multiple memory layers for covering these laminations respectively.In the trench
And a conductive material is formed on lamination.The conductive material has a top section.In the conductive material in these groove each
Form one or more holes.The multiple fates for being for respectively forming multiple conducting wires are defined in the top section of conductive material.In advance
Determine area and respectively include one first fate and one second fate, the first fate and the second fate are connected to each other, and first is pre-
Determine area to extend along a direction of the extending direction perpendicular to lamination, which prolongs along the extending direction of lamination
It stretches.Then, the part of the top section of removing conductive material being not formed in fate.In the conduction material stayed in fate
Conducting wire is formed on the top section of material.
According to some embodiments, a kind of memory construction is provided.This memory construction include a substrate, multiple laminations,
Multiple memory layers, a conductive material and multiple conducting wires.Lamination is located on substrate.Lamination is separated from each other by multiple grooves.It is folded
Multiple conductions that layer respectively includes alternately storehouse are being got lines crossed and multiple insulation are being got lines crossed.Memory layer distinguishes conformal these laminations of covering.
Conductive material is located in groove and on lamination.Conductive material in the trench forms one or more holes in these groove each
Hole.Conducting wire is located on conductive material.Conducting wire respectively includes a first part and a second part, first part and second part that
This connection, first part extend along a direction of the extending direction perpendicular to lamination, and second part prolongs along this of lamination
Stretch direction extension.
More preferably understand to have to above-mentioned and other aspect of the invention, preferred embodiment is cited below particularly, and cooperates institute
Accompanying drawings are described in detail below:
Detailed description of the invention
Figure 1A~Fig. 1 C is painted the concept of the memory construction manufacturing method according to an embodiment.
Fig. 2A~Fig. 2 B is painted the concept of the memory construction manufacturing method according to an embodiment.
Fig. 3 A~Fig. 3 C is painted the concept of the memory construction manufacturing method according to an embodiment.
Fig. 4 A~Fig. 4 C is painted the concept of the memory construction manufacturing method according to an embodiment.
Fig. 5 A~Figure 12 B is painted the memory construction manufacturing method according to an exemplary embodiment.
[symbol description]
104: lamination
114: conductive material
122: fate
1221: the first fates
1222: the second fates
204: lamination
214: conductive material
222: fate
2221: the first fates
2222: the second fates
304: lamination
314: conductive material
318: cutting channel
322: fate
3221: the first fates
3222: the second fates
322A: extension
404: lamination
414: conductive material
418: cutting channel
422: fate
4221: the first fates
4222: the second fates
422A: extension
422B: extension
500: substrate
502: buried layer
504: lamination
506: conduction is being got lines crossed
508: insulation is being got lines crossed
510: oxide skin(coating)
512: memory layer
514: conductive material
514A: top section
516: insulating materials
518: cutting channel
520: removing channel
522: fate
5221: the first fates
5222: the second fates
524: conducting wire
5241: first part
5242: second part
H: hole
T: groove
Specific embodiment
A kind of manufacturing method of memory construction provided below.Firstly, forming multiple laminations on a substrate.These are folded
Layer is separated from each other by multiple grooves.Multiple conductions that lamination respectively includes alternately storehouse are being got lines crossed and multiple insulation are being got lines crossed.Then,
Form the conformal multiple memory layers for covering these laminations respectively.Next, forming a conductive material in the trench and on lamination.
The top section that the conductive material has position higher than lamination.It is formed in the conductive material in these groove each one or more
A hole.One insulating materials can be inserted in one or more holes in these groove each.Figure 1A is please referred to, is shown in figure
Lamination 104, conductive material 114 and hole H.In this embodiment, one or more holes H in these groove each is arrangement
At rectangular.
Then, Figure 1B is please referred to, is defined in the top section of conductive material 114 and is for respectively forming the multiple of multiple conducting wires
Fate 122.Fate 122 respectively includes one first fate 1221 and one second fate 1222, the first fate 1221
And second fate 1222 be connected to each other.First fate 1221 extends along the direction of the extending direction perpendicular to lamination 104,
Second fate 1222 extends along the extending direction of lamination 104.In this embodiment, the first fate 1221 and second is pre-
The length for determining area 1222 is to gradually increase.
It later, can be with the part of the top section of removing conductive material being not formed in fate.Then, stay in it is pre-
Determine to form conducting wire on the top section of the conductive material in area.Conducting wire can be formed by silicide.Conduction in lamination, which is being got lines crossed, to be made
For bit line, and conducting wire can be used as wordline.Alternatively, the conduction in lamination, which is being got lines crossed, can be used as wordline, and conducting wire can be used as bit line.
Since technique limits, conducting wire is formed by by the method according to this embodiment, coupling part may be bending
Shape, as shown in Figure 1 C.As long as being fanned out to for conducting wire can partially work normally, this kenel is without departing from the scope of the present invention.
Technique described in cooperation Figure 1A~Fig. 1 C can be replaced by following process.A referring to figure 2. shows lamination in figure
204, conductive material 214 and hole H.In this embodiment, the step of definition is used to form the fate of conducting wire is to be formed
It was carried out before the step of one or more holes H.(such as only had in this way, which hole H can be only formed in conducting wire by a narrow spacing
About 30~40 nanometers) position that separates.Therefore in this embodiment, one or more holes H in these groove each
It is to be arranged in triangle.
Then, B referring to figure 2., defines in the top section of conductive material 214 and is for respectively forming the multiple of multiple conducting wires
Fate 222.Fate 222 respectively includes one first fate 2221 and one second fate 2222, the first fate 2221
And second fate 2222 be connected to each other.First fate 2221 extends along the direction of the extending direction perpendicular to lamination 204,
Second fate 2222 extends along the extending direction of lamination 204.In this embodiment, the first fate 2221 and second is pre-
The length for determining area 2222 is to gradually increase.
Due to hole and it is not formed at the position of corresponding second fate 2222, the conducting wire as manufactured by this embodiment
Intensity can than the intensity of conducting wire manufactured by the embodiment by Figure 1A~Fig. 1 C come it is high.
Alternatively, above-mentioned technique can be replaced by following process.A referring to figure 3. shows lamination 304, conductive material in figure
314 and hole H.In this embodiment, hole H is only formed in the position that conducting wire is separated by a narrow spacing, and arranges
At triangle.
Then, B referring to figure 3., defines in the top section of conductive material 314 and is for respectively forming the multiple of multiple conducting wires
Fate 322.Fate 322 respectively includes one first fate 3221, one second fate 3222 and an extension 322A.
First fate 3221 and the second fate 3222 are connected to each other.First fate 3221 is along the extension perpendicular to lamination 304
The direction in direction extends, and the second fate 3222 extends along the extending direction of lamination 304.Adjacent pairs in fate 322
First fate 3221 is the extension by the second fate 3222 of the one of them of the adjacent pairs in fate 322
322A is connected to each other.In this embodiment, the length of the first fate 3221 and the second fate 3222 is to gradually increase.
The step of part for being not formed at fate 322 of the top section of removing conductive material 314 includes an excision step
A rapid and removing step.As shown in Figure 3 C, excision step includes removing to lead along the direction of the extending direction perpendicular to lamination 304
A part of the top section of electric material 314 and a part of the memory layer on lamination 304.It is shown in figure by excision step institute
The cutting channel 318 of formation.The top section of conductive material 314 in the 322A of extension is moved by excision step
It removes.Removing step includes that other of the top section of removing conductive material 314 are not formed at the part in fate 322.
It is removed due to having used an additional excision step close to the conduction in the extension 322A of coupling part
Material 314 is formed by the shape that coupling part can have closer right angle.Therefore, compared to the reality by Fig. 2A~Fig. 2 B
Conducting wire manufactured by example is applied, the conducting wire as manufactured by this embodiment has higher intensity.
Or above-mentioned technique can be replaced by following process.A referring to figure 4. shows lamination 404, conduction material in figure
Expect 414 and hole H.In this embodiment, hole H is only formed in the position that conducting wire is separated by a narrow spacing, side by side
Arrange into triangle.
Then, B referring to figure 4., defines in the top section of conductive material 414 and is for respectively forming the multiple of multiple conducting wires
Fate 422.Fate 422 respectively includes one first fate 4221, one second fate 4222 and multiple extensions
422A,422B.First fate 4221 and the second fate 4222 are connected to each other.First fate 4221 is along perpendicular to lamination
The direction of 404 extending direction extends, and the second fate 4222 extends along the extending direction of lamination 404.Phase in fate 422
The first both adjacent fate 4221 is the second fate 4222 by the one of them of the adjacent pairs in fate 422
The extension 422B of second fate 4222 of another one is connected to each other in extension 422A and fate 422.At this
In embodiment, the length of the first fate 4221 and the second fate 4222 is to gradually increase.
The step of part for being not formed at fate 422 of the top section of removing conductive material 414 includes an excision step
A rapid and removing step.As shown in Figure 4 C, excision step includes removing to lead along the direction of the extending direction perpendicular to lamination 404
A part of the top section of electric material 414 and a part of the memory layer on lamination 404.It is shown in figure by excision step institute
The cutting channel 418 of formation.In this embodiment, cutting channel 418 is the area for substantially corresponding to the triangle of hole H
Domain is formed.The extension 422A of second fate 4222 of the one of them of the adjacent pairs and pre- in fate 422
It is logical for determining the top section of the conductive material 414 in the extension 422B of the second fate 4222 of the another one in area 422
Excision step is crossed to remove.Removing step includes that other of the top section of removing conductive material 414 are not formed at fate 422
In part.
Since fate 422 is more symmetrical design, the step of top section of removing conductive material 414, leads compared with removal
The step of top section of electric material 314, is more simple.Therefore, according to this embodiment, technique can yet further be expanded
Window (process window).
Other techniques can also be used to replace cooperation Figure 1A~Fig. 1 C, Fig. 2A~Fig. 2 B, Fig. 3 A~Fig. 3 C or Fig. 4 A~figure
Technique described in 4C.For example, in one embodiment, hole can be arranged as shown in the embodiment of Figure 1A~Fig. 1 C, and
Fate can be defined as shown in the embodiment of Fig. 3 A~Fig. 3 C.In another embodiment, hole can be such as Figure 1A~Fig. 1 C
Embodiment shown in as arrange, and fate can be defined as shown in the embodiment of Fig. 4 A~Fig. 4 C.
In order to further understand the manufacturing method of memory construction, Fig. 5 A~Figure 12 C is cooperated to give one below
A exemplary embodiment.1-1 ' the line and 2- being taken from respectively with figure indicated by " B " and " C " in the figure as indicated by " A "
The sectional view of 2 ' lines.This exemplary embodiment is about manufacture memory construction as shown in Fig. 4 A~Fig. 4 C.
A~Fig. 5 C referring to figure 5. forms multiple laminations 504 on a substrate 500.In one embodiment, in substrate 500
One buried layer 502 of upper formation, and lamination 504 is formed on buried layer 502.Buried layer 502 can be formed of oxide.Lamination 504 is logical
Multiple groove T are crossed to be separated from each other.Lamination 504 respectively include alternately storehouse multiple conductions get lines crossed 506 and it is multiple insulation get lines crossed
508.Conduction, which is being got lines crossed, 506 can be formed by polysilicon, and insulating to get lines crossed 508 can be formed of oxide.Lamination 504 may be used also respectively
Including monoxide layer 510, positioned at conduction get lines crossed 506 and insulation get lines crossed on 508.
Fig. 6 A~Fig. 6 C is please referred to, multiple memory layers 512 of conformal covering lamination 504 respectively are formed.Memory layer 512
It can be oxidenitride oxide (ONO) structure or similar structures.
Fig. 7 A~Fig. 7 C is please referred to, forms a conductive material 514 in groove T and on lamination 504.Conductive material 514 has
There is a top section 514A.Here, top section 514A, which is defined as position in conductive material 514, is higher than lamination 504 and lamination
The part of memory layer 512 on 504.Conductive material 514 can be polysilicon.
Fig. 8 A~Fig. 8 C is please referred to, forms one or more holes H in the conductive material 514 in groove T each.Definition is used
In formed conducting wire 524 (being shown in Figure 12 A) fate 522 (being shown in Figure 11 A) the step of can before forming one or more holes H,
It carries out afterwards or at any suitable time point.Alternatively, definition step for several times can be carried out.For example, it can be defined step at this time
Suddenly.In this way, which hole H can be only formed in the position that conducting wire 524 is separated by a narrow spacing.Hole H can pass through light
It carves and etching technics is formed.In the step of forming hole H, the memory on 504 side wall of lamination in hole H can be removed
Layer 512.
Fig. 9 A~Fig. 9 C is please referred to, an insulating materials 516 can be inserted in one or more holes H in groove T each.Absolutely
Edge material 516 can cover the top section 514A of conductive material 514, as shown in Fig. 9 B and Fig. 9 C.Insulating materials 516 can be oxidation
Object.
Then, the non-shape for being used to form the top section 514A of conductive material 514 of conducting wire 524 (being shown in Figure 12 A) is removed
At the part in fate 522 (being shown in Figure 11 A).Being not formed at for the top section 514A of removing conductive material 514 is predetermined
The step of part in area 522 includes an excision step and a removing step.
Figure 10 A~Figure 10 C is please referred to, excision step includes removing along the direction of the extending direction perpendicular to lamination 504
A part of the memory layer 512 of a part and lamination 504 of the top section 514A of conductive material 514.Cutting is shown in figure
Channel 518.In the case where insulating materials 516 covers the top section 514A of conductive material 514, cutting channel 518 is also removed
In insulating materials 516.Excision step can be carried out by photoetching and etching technics.In this embodiment, channel is cut
518 be substantially corresponding to hole H triangle region in along hole H-shaped at.
Figure 11 A~Figure 11 C is please referred to, step can be defined again.It is fixed in the top section 514A of conductive material 514
Adopted fate 522, to form conducting wire.Fate 522 respectively includes one first fate 5221 and one second fate 5222,
First fate 5221 and this connection of the second fate 5222, the first fate 5221 is along the extension side perpendicular to lamination 504
To direction extend, the second fate 5222 along lamination 504 extending direction extend.Removing step is such as Figure 11 A~Figure 11 C
It is shown to carry out.Removing step includes that other of the top section 514A of removing conductive material 514 are not formed in fate 522
Part.It is shown in figure and removes channel 520.Similar to excision step, removing step can by photoetching and etching technics come into
Row.
Figure 12 A~Figure 12 B is please referred to, is formed on the top section 514A of the conductive material 514 stayed in fate 522
Conducting wire 524.Conducting wire 524 can be formed by silicide.In one embodiment, conducting wire 524 is by staying in leading in fate 522
A tungsten silicide (WSi) layer is deposited on the top section 514A of electric material 514 to be formed.In another embodiment, the shape of conducting wire 524
At being by the deposited metal on the top section 514A of the conductive material 514 stayed in fate 522, such as cobalt (Co), nickel
(Ni) or titanium (Ti) etc. this metal is reacted, and with conductive material 514 (polysilicon) to form silicide such as silication
Cobalt (CoSi), nickle silicide (NiSi) or titanium silicide (TiSi) etc..As illustrated in fig. 12, conducting wire 524 respectively includes a first part
5241 and a second part 5242, first part 5241 and second part 5242 be connected to each other, first part 5241 is along vertical
Extend in the direction of the extending direction of lamination 504, second part 5242 extends along the extending direction of lamination 504.Conducting wire 524
The length of first part 5241 and second part 5242 is to gradually increase.
Above-mentioned method is compatible with the manufacture general technology of semiconductor structure (such as memory construction).For example, it adopts
With the concept for the technique for being formed in the conductive material on lamination including hole-line second order segmentation patterning.Therefore, structure can
It is formed in a manner of more regular.
In the example of three-dimensional perpendicular grid nand memory, the conduction in lamination 504, which is being got lines crossed, 506 can be used as bit line, lead
Line 524 can be used as wordline.And in the example of three-dimensional perpendicular channel nand memory, the conduction in lamination 504 is being got lines crossed and 506 can made
For wordline, conducting wire 524 can be used as bit line.
The memory construction as made by the above method includes a substrate 500, multiple laminations 504 (or 104/204/304/
404), multiple memory layers 512, a conductive material 514 (or 114/214/314/414) and multiple conducting wires 524.Lamination 504 (or
104/204/304/404) it is located on substrate 500.Lamination 504 (or 104/204/304/404) is divided each other by multiple groove T
From.Lamination 504 (or 104/204/304/404) respectively include alternately storehouse multiple conductions get lines crossed 506 and it is multiple insulation get lines crossed
508.Memory layer 512 distinguishes conformal covering lamination 504 (or 104/204/304/404).Conductive material 514 (or 114/214/
314/414) it is located in groove T and on lamination 504 (or 104/204/304/404).In groove T conductive material 514 (or
114/214/314/414) one or more holes H is formed in groove T each.In one embodiment, one in groove T each
Or multiple hole H be arranged in it is rectangular, as shown in Figure 1A.One or more holes in another embodiment, in groove T each
H is to be arranged in triangle, as shown in Fig. 2A, Fig. 3 A and Fig. 4 A.
Conducting wire 524 is located at conducting wire 524 on conductive material 514 (or 114/214/314/414) and respectively includes a first part
5241 and a second part 5242, first part 5241 and second part 5242 be connected to each other, first part 5241 is along vertical
In lamination 504 (or 104/204/304/404) extending direction direction extend, second part 5242 along lamination 504 (or
104/204/304/404) extending direction extends.The first part 5241 of conducting wire 524 and the length of second part 5242 be by
It is cumulative to add.Conducting wire 524 can be formed by silicide.In one embodiment, the conduction in lamination 504 (or 104/204/304/404)
Getting lines crossed 506 is being as bit line, and conducting wire 524 is as wordline.In another embodiment, lamination 504 (or 104/204/304/404)
In conduction to get lines crossed 506 be as wordline, conducting wire 524 is as bit line.
For the sake of clarity, other detailed construction features for having matched that composition manufacture method described just are omitted herein.
According to embodiment, conducting wire be fanned out to part (that is, the first part of conducting wire and second part be formed in it is virtual folded
On layer (also that is, position is in lamination in an extension area of array area).Therefore, the whole shape all in relatively regular region of conducting wire
At can reduce failure rate.
Although however, it is not to limit the invention in conclusion the present invention has been disclosed as a preferred embodiment.This hair
Bright those of ordinary skill in the art, without departing from the spirit and scope of the present invention, when various changes can be made
With retouching.Therefore, subject to protection scope of the present invention ought be defined depending on appended claims range.
Claims (7)
1. a kind of manufacturing method of memory construction, comprising:
Multiple laminations are formed on a substrate, and wherein these laminations are separated from each other by multiple grooves, and these laminations wrap respectively
The multiple conductions for including alternately storehouse are being got lines crossed and multiple insulation are being got lines crossed；
Form the conformal multiple memory layers for covering these laminations respectively；
A conductive material is formed in these grooves and on these laminations, which has a top section；
One or more holes are formed in the conductive material in these groove each；And
The multiple fates for being for respectively forming multiple conducting wires are defined in the top section of the conductive material, wherein these are predetermined
Area respectively includes one first fate and one second fate, and first fate and second fate are connected to each other, this
One fate extends along a direction of the extending direction perpendicular to these laminations, and second fate is along these laminations
The extending direction extends；
Remove the part of the top section of the conductive material being not formed in these fates；And
Multiple conducting wires are formed on the top section of the conductive material stayed in these fates.
2. the manufacturing method of memory construction according to claim 1, wherein this in these groove each is one or more
A hole is to be arranged in rectangular or triangle.
3. the manufacturing method of memory construction according to claim 1, wherein the step of defining these fates is in shape
At progress later the step of one or more holes.
4. the manufacturing method of memory construction according to claim 1, wherein these first fates and these are second pre-
The length for determining area is to gradually increase.
5. the manufacturing method of memory construction according to claim 1, further includes:
The step of removing the part of the top section being not formed in these fates of the conductive material before, by an insulation
Material is inserted in one or more holes in these groove each.
6. the manufacturing method of memory construction according to claim 5, wherein removing the top section of the conductive material
The part being not formed in these fates the step of include an excision step and a removing step, which includes edge
Perpendicular to the extending direction of these laminations the direction remove the conductive material the top section a part and these
A part of these memory layers on lamination, the removing step include remove the conductive material the top section other not
It is formed in the part in these fates.
7. a kind of memory construction, comprising:
One substrate；
Multiple laminations are located on the substrate, and wherein these laminations are separated from each other by multiple grooves, and these laminations respectively include
Alternately multiple conductions of storehouse are being got lines crossed and multiple insulation are being got lines crossed；
Multiple memory layers, conformal these laminations of covering of difference；
One conductive material is located in these grooves and on these laminations, wherein the conductive material in these grooves is at these
One or more holes are formed in groove each；And
Multiple conducting wires are located on the conductive material, and wherein these conducting wires respectively include a first part and a second part, this
A part and the second part are connected to each other, which prolongs along a direction of the extending direction perpendicular to these laminations
It stretches, which extends along the extending direction of these laminations.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510098924.4A CN105990252B (en) | 2015-03-06 | 2015-03-06 | Memory construction and its manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510098924.4A CN105990252B (en) | 2015-03-06 | 2015-03-06 | Memory construction and its manufacturing method |
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| Publication Number | Publication Date |
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| CN105990252A CN105990252A (en) | 2016-10-05 |
| CN105990252B true CN105990252B (en) | 2019-01-11 |
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Citations (2)
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| US20120206979A1 (en) * | 2011-02-16 | 2012-08-16 | Hack Seob Shin | 3-d structured non-volatile memory device and method of manufacturing the same |
| CN102867831A (en) * | 2011-07-08 | 2013-01-09 | 爱思开海力士有限公司 | Semiconductor device and method of manufacturing the same |
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| US20120206979A1 (en) * | 2011-02-16 | 2012-08-16 | Hack Seob Shin | 3-d structured non-volatile memory device and method of manufacturing the same |
| CN102867831A (en) * | 2011-07-08 | 2013-01-09 | 爱思开海力士有限公司 | Semiconductor device and method of manufacturing the same |
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