CN105280687B - Semiconductor structure and its manufacturing method - Google Patents
Semiconductor structure and its manufacturing method Download PDFInfo
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- CN105280687B CN105280687B CN201410280113.1A CN201410280113A CN105280687B CN 105280687 B CN105280687 B CN 105280687B CN 201410280113 A CN201410280113 A CN 201410280113A CN 105280687 B CN105280687 B CN 105280687B
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Abstract
The invention discloses a kind of semiconductor structure and its manufacturing methods.Semiconductor structure includes a conductive layer, an electricity conductive construction and a dielectric layer.Conductive layer defines adjacent multiple first openings.Part of the electricity conductive construction around conductive layer between the first opening.Dielectric layer separates conductive layer and electricity conductive construction.
Description
Technical field
The invention relates to a kind of semiconductor structure and its manufacturing methods, and in particular to a kind of memory and its
Manufacturing method.
Background technology
The structure of semiconductor element is constantly changing in recent years, and the memory storage capacity of element is also continuously increased.It deposits
Storage device is to be used in many products, such as in the storage element of MP3 player, digital camera, computer archives etc..
With the increase of application, smaller size, larger memory capacity are also tended to for the demand of storage device.In response to this need
It asks, is to need to manufacture high component density and the storage device with small size.
Therefore, designers are dedicated to developing a kind of three-dimensional memory devices invariably, not only have many lamination planes and reach
To higher memory storage capacity, there is more small size, be provided simultaneously with good characteristic and stability.
Invention content
According to an embodiment, a kind of semiconductor structure is disclosed comprising a conductive layer, an electricity conductive construction and a dielectric layer.
Conductive layer defines adjacent multiple first openings.Part of the electricity conductive construction around conductive layer between the first opening.Dielectric
Layer separates conductive layer and electricity conductive construction.
According to another embodiment, a kind of semiconductor structure is disclosed comprising multiple conductive stripes of lamination, a conductive structure
Make, with an electricity conductive construction.Electricity conductive construction is around conductive stripe.Dielectric layer separates conductive stripe and electricity conductive construction.
According to still another embodiment, a kind of manufacturing method of semiconductor structure is disclosed comprising following steps.Interaction lamination
Multiple insulating layers and multiple conductive layers.It forms multiple first openings and runs through insulating layer and conductive layer.Insulating layer is removed to be opened by first
The part that mouth exposes, to form multiple second openings of the size more than the first opening in a insulating layer.Form dielectric layer covering
The part that conductive layer is exposed by the first opening with the second opening.Multiple electricity conductive constructions are formed on dielectric layer.
Description of the drawings
Figure 1A to Fig. 5 C is painted the manufacturing method of the semiconductor structure according to an embodiment.
【Symbol description】
102:Insulating layer
104:Conductive layer
106:Semiconductor substrate
108:Hard mask
110:First opening
112:Second opening
114:First direction
116:Second direction
118:Partly
120:Insulated part
122:Dielectric layer
124:Electricity conductive construction
126:First current-carrying part
128:Second current-carrying part
130:Insulated plug
132:Third is open
134:Conductive stripe
136:Third direction
138:It is conductively connected
P1、P2:Spacing
Specific implementation mode
Figure 1A to Fig. 5 C is painted the manufacturing method of the semiconductor structure according to an embodiment.It is wherein partly to lead with A marks
The top view of body structure, it is the sectional view for being respectively semiconductor structure along BB lines and CC lines to be denoted as B and C.
Figure 1A to Fig. 1 C is please referred to, insulating layer 102 is formed on semiconductor substrate 106 with interacting lamination with conductive layer 104.
Semiconductor substrate 106 may include silicon substrate, silicon-on-insulator (SOI) or other suitable material structures.Insulating layer 102 can
Including oxide, nitride, nitrogen oxides, such as silica, silicon nitride, silicon oxynitride or other suitable dielectric materials.It can
Using etching technics, the conductive layer 104 that exposes in the hard mask 108 (such as silicon nitride) of top (such as undoped polycrystalline
Silicon) with insulating layer 102 (such as silica) defined in go out the first opening 110.Etching technics is carved including such as wet etching, dry method
Erosion or other suitable methods.
Fig. 2A to Fig. 2 C is please referred to, the part that insulating layer 102 is exposed by the first opening 110 is removed, in insulating layer 102
The second opening 112 is defined, size is more than the first opening 110 of conductive layer 104, and is connected to the first opening 110.Compared to leading
Electric layer 104, the etching technics used for insulating layer 102 have higher Etch selectivity (that is, this etching technics to insulation
The etch rate of layer 102 is higher than conductive layer 104, or substantially without etching conductive layer 104).For example, using hydrogen fluorine
Sour dilute solution (DHF), buffer-type oxide etching agent (buffered oxide etchant;BOE) or other are suitably carved
It loses agent and removes oxide insulating layer 102.In one embodiment, the first opening 110 spacing (pitch) P1 on 114 in a first direction
It is greater than the spacing P2 in second direction 116, and etching technics is that control (such as control etc. to the time of etching technics) moves
Except the material of 102 specific dimensions of insulating layer, thereby leave between the first opening 110 of the insulating layer 102 in a first direction on 114
Some 118 (Fig. 2A and Fig. 2 C), and the first opening (as shown in Fig. 2A and Fig. 2 B) being connected in second direction 116, to be formed
Be separated from each other on 114 (Fig. 2A and Fig. 2 C) in a first direction, and in being connected to the first openings of difference simultaneously in second direction 116
Second opening 112 of 110 (Fig. 2A and Fig. 2 B) forms.It is to leave insulating layer after forming the second opening 112 in embodiment
102 are located at insulated part 120 (Fig. 2A) of first opening 110 wherein between four, this insulated part 120, which can support, to be separated
The conductive layer 104 of upper and lower deforms short circuit or collapses and collapses to avoid conductive layer 104.
Fig. 3 A to Fig. 3 C are please referred to, form dielectric layer 122 to cover the institute that the first opening 110 and the second opening 112 are exposed
There are conductive layer 104 and insulating layer 102.With conductive material (such as P+ type polysilicon, N+ types polysilicon, TiN, TaN, W, Ti, Cu,
Or other conformal conductors (conformal conductors)) filling conductive layer 104 the first opening 110 and insulating layer 102
The second opening 112, to form electricity conductive construction 124 on dielectric layer 122, wherein electricity conductive construction 124 includes being filled in first and opening
First current-carrying part 126 of mouth 110, and be filled in the second opening 112 and connect the second conductive part of the first current-carrying part 126
Divide 128.Using chemical mechanical milling tech, the dielectric layer 122 of 108 top of hard mask is removed with conductive material.Second leads
Electric part 128 configures the upper and lower in conductive layer 104.In addition, dielectric layer 122 electrically isolates conductive layer 104 and electricity conductive construction
124, and electrically isolate the electricity conductive construction 124 of different location on first direction 114.
Please refer to Fig. 3 B, electricity conductive construction 124 be looped around upper and lower surface of the conductive layer 104 between the first opening 110 with
In opposing sidewalls.Single the second current-carrying part 128 is overlapped from the first current-carrying part 126 in different first openings 110.
Fig. 4 A to Fig. 4 C are please referred to, insulated plug 130 is formed, pass through conductive layer 104 and insulating layer 102, with electrically exhausted
Edge electricity conductive construction 124.The forming method of insulated plug 130, which is included in, goes out third opening defined in conductive layer 104 and insulating layer 102
132, and formed with dielectric material (such as oxide) filling third opening 132.It, will be hard using chemical mechanical milling tech
The dielectric material of 108 top of mask removes.In one embodiment, what insulated plug 130 was disposed on first direction 114 first leads
Between electric part 126, and at least adjacent first current-carrying part 126 (or in first opening 110) dielectric layer 122, with Jie
Electric layer 122 goes out the conductive stripe 134 that past first direction 114 extends defined in conductive layer 104, and (Fig. 4 D, are only painted conductive layer
Element configuration in 104 single stratum).In other embodiment, electricity conductive construction 124 is not being influenced in 136 (Vertical Square of third direction
To) under different estate electrically conducts premised on effect, insulated plug 130 can also further extend to the first current-carrying part 126 of contact.
The semiconductor structure of embodiment is 3-D stacks memory array, wherein the conductive bar extended toward first direction 114
Line 134 is used as bit line, and the electricity conductive construction 124 extended toward second direction 116, which is made, is used as wordline.For example, conductive stripe
Dielectric layer 122 between 134 and electricity conductive construction 124 can be ONO structure, ONONO structures, ONONONO structures or by tunnelling material
Expect (tunneling material)/capture material (trapping material)/barrier material (blocking
Material) the material layer constituted is applied to the storage material of NAND gate (NAND).For example, from the first of interior number outward
Layer oxide is tunneling material with the oxide (O1N1O2) of nitride and the second layer, and second layer nitride (N2) is to capture
Material, third layer oxide (O3) or third layer oxide/nitride or the 4th layer of oxide (O3/N3/O4) are blocking material
Material.In one embodiment, semiconductor structure uses titanium-aluminium-nitrogen-oxygen-silicon (tantalum-alumina-nitride-oxide-
silicon;TANOS) structure comprising Si substrates, oxide/silicon nitride/aluminium oxide (OX/SiN/Al2O3) dielectric medium and
TaN grids.
As shown in Figure 4 B, device has circulating type of the electricity conductive construction 124 (grid) around conductive stripe 134 (bit line channel)
Grid (Gate-all-around, GAA) structure.The gate control ability of such structure is good, and cell current is big, is better than double grid formula
(double gate) or single grating (single gate) device.Also, since (conductive stripe (134) is by grid ring for bit line
Around, use and be less susceptible to be influenced by other bit lines, therefore between bit line Z-direction coupled interference it is relatively low.
In some comparative examples, the formation of bit line is the lamination by patterned conductive layer and insulating layer, to form strip
The opening of shape and define.In other words, it can be open there is a situation where whole face side wall exposes in bit line forming process.However, high
The bit line of depth-to-width ratio (aspect ratio) in both sides is all opening and in the case of do not supported by other elements, be easy by
It is influenced (such as in immersion liquid cleaning step, stress caused by making full of liquid in the opening, or leaching, pulling) to other stress
And bend (bending) so that structural damage even forms undesirable short circuit, reduces product yield.
In an embodiment of the present invention, conductive stripe 134 is to utilize patterning opening (including the first opening 110 and third
The mode of opening 132) is formed, and the material part to form conductive stripe 134 is to be supported in the process, therefore (compared to
Comparative example) there is relatively stable structure feature, it is not easy to the problem of deforming upon, and product reliability is high.
Fig. 5 A to Fig. 5 C are please referred to, in some embodiments, can also be formed on electricity conductive construction 124 and 116 be prolonged in a second direction
Stretch and it is separated from each other it is multiple be conductively connected 138, e.g. wordline connects.
Also other suitable contact structures and interlayer dielectric layer (not being painted) can be formed.
The present invention is not limited to the embodiments utilized above illustrated, also can be according to actual demand or other designs
Suitably modulation.
For example, in embodiment, in conductive layer 104 single stratum the first current-carrying part 126 (the first opening 110)
4 (between define a conductive stripe 134 extended toward first direction 114) of 2x2 illustrated above are not limited to, and it can
Arbitrarily use other more quantity, such as 9x8 64 (between define 8 toward first directions 114 extend and pass through dielectric
The conductive stripes 134 that layer 122 is electrically isolated with insulated plug 130) or 128 etc. of 9x16, wherein prolonging toward second direction 116
It is Chong Die with 9 the first current-carrying parts 126 simultaneously to stretch single the second current-carrying part 128 (in 8 or 16), to be formed more
The array apparatus of storage unit.
In some embodiments, the spacing P1 that first 110 (Figure 1A) of opening may be designed in a first direction on 114 is equal to
Spacing P2 in second direction 116, and therefore after performing etching technique,
The second opening 112 formed not only interconnects (as shown in Figure 2 A) in second direction 116, also in a first direction
It is connected with each other (not being painted) on 114.Although this can cause electricity conductive construction 124 to connect simultaneously toward first direction 114 and second direction 116
Extension (not being painted) is connect, but after forming insulated plug 130, since to can pass through insulated plug 130 electric each other for electricity conductive construction 124
Property insulation, and define 116 wordline extended in a second direction, therefore can still form out the storage device of expected electrical property feature.
In this instance, the etching technics to form the second opening 112 is that control leaves insulating layer 102 positioned at the first opening 110 wherein
Insulated part 120 between four neighbouring, this insulated part 120 can support the conductive layer 104 for separating upper and lower, to avoid leading
Electric layer 104, which deforms short circuit or collapses, to collapse.
In addition to multilayered structure, the structure of simple layer can also be used in dielectric layer 122.The dielectric element of embodiment, material can
Including oxide, nitride, nitrogen oxides, such as silica, silicon nitride or silicon oxynitride or other suitable materials.It is conductive
Element may include that polysilicon, metal are suitable such as titanium nitride (TiN), titanium (Ti), tantalum nitride (TaN), tantalum (Ta), gold, tungsten
Material.
In conclusion although the present invention has been disclosed by way of example above, it is not intended to limit the present invention..Institute of the present invention
Belong in technical field and have usually intellectual, without departing from the spirit and scope of the present invention, when various changes and profit can be made
Decorations.Therefore, subject to protection scope of the present invention ought be defined depending on appended claims range.
Claims (8)
1. a kind of semiconductor structure, including:
One conductive layer defines adjacent multiple first openings;
One electricity conductive construction, around part of the conductive layer between these first openings;And
One dielectric layer separates the conductive layer and the electricity conductive construction;
Wherein, which includes:
Multiple first current-carrying parts fill these first openings of the conductive layer;And
One second current-carrying part connects these the first current-carrying parts, and configures the upper and lower in the conductive layer.
2. semiconductor structure according to claim 1, including:
Multiple electricity conductive constructions;And
Multiple insulated plugs, be electrically insulated these electricity conductive constructions.
3. semiconductor structure according to claim 1 further includes multiple insulated plugs, wherein the electricity conductive construction includes mutual
Separated multiple first current-carrying parts,
Between these first current-carrying parts on a first direction of these insulated plugs configuration, with the dielectric layer in the conduction
Go out the conductive stripe extended toward the first direction defined in layer.
4. semiconductor structure according to claim 1, the wherein electricity conductive construction be looped around the conductive layer between these first
On upper and lower surface and opposing sidewalls between opening.
5. a kind of semiconductor structure, including:
Multiple conductive stripes of lamination;
One electricity conductive construction, around these conductive stripes;And
One dielectric layer separates these conductive stripes and the electricity conductive construction;
Wherein, the extending direction of these conductive stripes is perpendicular to the extending direction of the electricity conductive construction, these conductive stripes are to use
Make bit line, which is used as wordline;
The electricity conductive construction includes:
Multiple first current-carrying parts, multiple first current-carrying part are separated from each other;And
One second current-carrying part connects these the first current-carrying parts.
6. semiconductor structure according to claim 5 further includes multiple insulated plugs, these conductive stripes are exhausted by these
Edge plug is defined with the dielectric layer.
7. according to the semiconductor structure described in any one of claim 1-6, for circulating type grid (Gate-all-
Around, GAA) structure 3-D stacks memory array.
8. a kind of manufacturing method of semiconductor structure, including:
The interaction multiple insulating layers of lamination and multiple conductive layers;
Multiple first openings are formed through these insulating layers and these conductive layers;
Remove the part that these insulating layers are exposed by these first openings, with formed in these insulating layers size be more than these the
Multiple second openings of one opening;
It forms a dielectric layer and covers the part that these conductive layers are exposed by these first openings with these second openings;And
Multiple electricity conductive constructions are formed on the dielectric layer, the plurality of electricity conductive construction is filled in the first opening and absolutely of dielectric layer
Second opening of edge layer.
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Citations (2)
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CN101414631A (en) * | 2007-10-18 | 2009-04-22 | 旺宏电子股份有限公司 | Semiconductor device and manufacture method thereof |
US7855457B2 (en) * | 2007-06-29 | 2010-12-21 | Kabushiki Kaisha Toshiba | Stacked multilayer structure and manufacturing method thereof |
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US7855457B2 (en) * | 2007-06-29 | 2010-12-21 | Kabushiki Kaisha Toshiba | Stacked multilayer structure and manufacturing method thereof |
CN101414631A (en) * | 2007-10-18 | 2009-04-22 | 旺宏电子股份有限公司 | Semiconductor device and manufacture method thereof |
Non-Patent Citations (3)
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A novel three-dimensional dual control-gate with surrounding floating-gate(DC-SF) NAND flash cell;Seiichi Aritome et al;《Solid-State Electronics》;20130131;第79卷;第166-171页 * |
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New Three-Dimensional High-Density Stacked-Surrounding Gate Transistor (S-SGT) Flash Memory Architecture Using Self-Aligned Interconnection Fabrication Technology without Photolithography Process for Tera-Bits and Beyond;Hiroshi SAKURABA et al;《Japanese Journal of Applied Physics》;20040427;第43卷(第4B期);第2217-2219页 * |
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