CN105990232A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN105990232A CN105990232A CN201610149691.0A CN201610149691A CN105990232A CN 105990232 A CN105990232 A CN 105990232A CN 201610149691 A CN201610149691 A CN 201610149691A CN 105990232 A CN105990232 A CN 105990232A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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- H01—ELECTRIC ELEMENTS
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/82385—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
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Abstract
The present invention provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes at least one first gate structure and at least one second gate structure on a semiconductor substrate. The at least one first gate structure has a flat upper surface extending in a first direction and a first width in a second direction perpendicular to the first direction. The at least one second gate structure has a convex upper surface extending in the first direction and a second width in the second direction, the second width being greater than the first width.
Description
Cross-Reference to Related Applications
This application claims in the Korea S that on March 17th, 2015 submits in Korean Intellectual Property Office
The rights and interests of patent application No.10-2015-0036761, the disclosure of this application is with way of reference also
Enter herein.
Technical field
The example embodiment of present inventive concept relates to a kind of semiconductor device, in particular it relates to
A kind of semiconductor device including grid structure and the method manufacturing this semiconductor device.
Background technology
Metal-oxide semiconductor (MOS) (MOS) transistor utilizing polysilicon is widely known as grid
The example of electrode.Polysilicon is more more robust than most metals at a relatively high temperature, thus polysilicon
And source electrode and drain region can anneal at a relatively high temperature.Polysilicon can complete gate patterning
It is used for afterwards forming self-aligned source and drain electrode structure.But, because polysilicon and most of gold
Genus material is compared has relatively high resistance, so the speed of operation of polygate electrodes compares metal
The speed of operation of gate electrode is slower.As the method for the relatively high resistance compensating polysilicon, can
Use the method that polygate electrodes is replaced with metal gate electrode.Available replacement metal gate
(RMG) technique performs this method.When polysilicon is present in Semiconductor substrate, can hold
The technique of row relatively-high temperature, then, by removing polysilicon and can be replaced with metal and carry out shape
Become metal gates.
Summary of the invention
The example embodiment of present inventive concept provides the half of a kind of operating characteristics with improvement
Conductor device and a kind of method manufacturing this semiconductor device.
According to the example embodiment of present inventive concept, a kind of semiconductor device includes: quasiconductor
At least one first grid structure on substrate, at least one first grid structure described has
The upwardly extending flat upper surfaces of first party, and have and be perpendicular to the second party of first direction
The first width upwards；And at least one the second grid structure in Semiconductor substrate, described
At least one second grid structure has the convex upper surface extended in a first direction, and has
The second width in a second direction, the second width is more than the first width.
According to the example embodiment of present inventive concept, a kind of semiconductor device includes: quasiconductor
Substrate, which defines the firstth district and the secondth district；At least the first fin and the second fin, it is from quasiconductor
Substrate highlights, and described at least the first fin and the second fin extend in a first direction；At least one is years old
One grid structure, it is positioned in the firstth district of Semiconductor substrate, and covers the upper table of the first fin
Face and side surface, at least one first grid structure described has and is being perpendicular to the of first direction
Two upwardly extending flat upper surfaces of side and there is the first width in a first direction；And
At least one second grid structure, it is positioned in the secondth district of Semiconductor substrate, and covers
The upper surface of two fins and side surface, at least one second grid structure described has and is being perpendicular to
The upwardly extending convex upper surface of second party in one direction and there is being more than in a first direction
Second width of the first width.
According to the example embodiment of present inventive concept, a kind of method manufacturing semiconductor device,
Described method includes step: form the multiple puppets extended in a first direction on a semiconductor substrate
Grid structure, each in the plurality of dummy gate structure includes dummy grid dielectric film and pseudo-grid
Electrode；The sidewall of the plurality of dummy gate structure is formed distance piece；Formed and cover quasiconductor
The interlayer dielectric of substrate；Interlayer dielectric is planarized, so that the plurality of dummy grid knot
The upper surface of structure comes out；Remove the plurality of dummy gate structure；On interlayer dielectric and
The part eliminating the plurality of dummy gate structure of Semiconductor substrate is formed the first insulation
Film and metal film；And by the first dielectric film and metal film are planarized exhausted to expose interlayer
The upper surface of velum forms multiple grid structure, each bag in the plurality of grid structure
Including gate insulating film and metal gate electrode, the plurality of grid structure includes: at least one is first years old
Grid structure, it has flat upper surfaces, and at least one first grid structure described has is hanging down
Straight the first width in the second direction of first direction, and at least one second grid structure,
It has convex upper surface, and it is big that at least one second grid structure described has in a second direction
The second width in the first width.
According to the example embodiment of present inventive concept, a kind of method manufacturing semiconductor device,
Described method includes step: a part for etching Semiconductor substrate is to form groove；Groove it
Between formed from the prominent raised structures of Semiconductor substrate, described raised structures prolongs in a first direction
Stretch；By a part of fill insulant of groove is formed device isolation film；Form correspondence
In at least one fin on the top of raised structures, at least one fin described highlights from device isolation film；
And form a part for covering Semiconductor substrate, device isolation film and at least one fin described
Multiple grid structures, the plurality of grid structure prolongs in a second direction perpendicular to the first direction
Stretch, and each in the plurality of grid structure include gate insulating film and metal gate electrode,
The plurality of grid structure includes: at least one first grid structure, and it has flat upper surfaces,
At least one first grid structure described has the first width in a first direction, and at least
One second grid structure, it has convex upper surface, at least one second grid structure described tool
There is the second width more than the first width in a first direction.
According to the example embodiment of present inventive concept, a kind of semiconductor device includes: quasiconductor
Substrate, it includes the firstth district and the secondth district；And at least two grid knot in Semiconductor substrate
Structure, described at least two grid structure includes: at least one the first grid structure in the firstth district,
At least one first grid structure described has the flat upper surfaces extended in a first direction, and
And there is the first width in a second direction perpendicular to the first direction, and in the secondth district
Second grid structure, this second grid structure has the convex upper surface extended in a first direction,
And there is the second width in a second direction, described second width be the first width at least
Twice.
Accompanying drawing explanation
By the detailed description carried out below in conjunction with accompanying drawing, the present invention be will be more clearly understood
The example embodiment of design, wherein:
Fig. 1 is the schematic plan view illustrating the semiconductor device according to example embodiment；
Fig. 2 is the sectional view of the line I-I' intercepting of the semiconductor device along Fig. 1；
Fig. 3 is the enlarged drawing of part M1 of the semiconductor device illustrating Fig. 2；
Fig. 4 to Fig. 8 is to illustrate the semiconductor device corresponding to Fig. 2 according to example embodiment
The sectional view of semiconductor device of sectional view；
Fig. 9 is the perspective view illustrating the semiconductor device according to example embodiment；
Figure 10 is the sectional view of the line II-II' intercepting of the semiconductor device along Fig. 9；
Figure 11 is that line III-III' and IV-IV' of the semiconductor device along Fig. 9 intercepts
Sectional view；
Figure 12 is the enlarged drawing of part M2 of the semiconductor device illustrating Figure 10；
Figure 13 is to illustrate cuing open of the semiconductor device corresponding to Figure 10 according to example embodiment
The sectional view of the semiconductor device of view；
Figure 14 and Figure 15 be shown respectively according to example embodiment corresponding to Figure 10 and Figure 11
The sectional view of semiconductor device of sectional view of semiconductor device；
Figure 16 and Figure 17 is namely for describing the semiconductor device according to example embodiment
Circuit diagram and layout；
Figure 18 and Figure 19 is to be shown respectively to include the semiconductor device according to example embodiment
The block diagram of electronic system；
Figure 20 and Figure 21 is to illustrate to can be applicable to the semiconductor device according to example embodiment
The schematic diagram of example electronic system；
Figure 22 A to Figure 22 F is for describing the manufacture Fig. 1 to Fig. 3 according to example embodiment
The sectional view of method of semiconductor device；
Figure 23 A and Figure 23 B is for describing partly leading of the manufacture Fig. 4 according to example embodiment
The sectional view of the method for body device；
Figure 24 A to Figure 24 D is for describing partly leading of the manufacture Fig. 8 according to example embodiment
The sectional view of the method for body device；
Figure 25 A to Figure 25 G is for describing the manufacture Fig. 9 to Figure 12 according to example embodiment
The sectional view of method of semiconductor device, it is corresponding to the line of the semiconductor device along Fig. 9
The sectional view that II-II' intercepts；And
Figure 26 A to Figure 26 G is for describing the manufacture Fig. 9 to Figure 12 according to example embodiment
The sectional view of method of semiconductor device, it is corresponding to the line of the semiconductor device along Fig. 9
The sectional view that III-III' and IV-IV' intercepts.
Detailed description of the invention
Now, the most more will add with reference to the accompanying drawing of the element showing present inventive concept
Present inventive concept is described entirely.
But, present inventive concept can realize in many different forms and should not be understood and be limited
In example embodiment set forth herein.On the contrary, it is provided that these embodiments will be so that the disclosure will be
Thorough and complete, and the scope of present inventive concept will be entirely delivered to the common skill in this area
One of art personnel.
It should be understood that when by an element be referred to as " being positioned at " another element " on " time, institute
State an element to can be directly on another element described, or also can exist between which
Between element.Similarly, it should be appreciated that, when an element is referred to as " being connected to " another element
Time, one element " can be connected directly to " another element described, or also can be at them
Between there is intermediary element.For the sake of describing and be clear, the element in accompanying drawing can be exaggerated
Structure or size, and eliminate the parts unrelated with detailed description of the invention in accompanying drawing.Phase
With reference refer to identical element all the time.Terms used herein is merely to describe and show
Example embodiment, and be not intended to limit example embodiment.As used herein, term "and/or"
One of listd or multiple any and all combination including relevant.When such as " in ... extremely
Few one " expression come across element list after time, the whole list of its modified elements and
Do not modify the single element in list.
Should be appreciated that, although term such as first, second, third, etc. can be used herein
Multiple element, assembly, district, floor and/or part described, but these elements, assembly, district,
Layer and/or part should not be limited by these terms.These terms are only used for element, a group
Part, district, floor and/or part distinguish with another element, assembly, district, floor and/or part.
Such as, the first element, the first assembly, the firstth district, ground floor and/or Part I can be claimed
Make the second element, the second assembly, the secondth district, the second layer and/or Part II, without deviating from
The teaching of exemplary embodiment.
For ease of describing, can use such as herein " ... lower section ", " ...
Under ", D score, " ... on ", " on " etc. space relative terms describe
Shown in accompanying drawing a assembly and/or feature and another (some) assembly and/or feature
Relation.It should be understood that described space relative terms is intended to the device in using or operating
Different orientation in addition to the orientation shown in figure.
Term used herein is merely to describe particular example embodiment, and is not intended to limit
Example embodiment processed.It is as used herein, unless it is not so that context clearly indicates, otherwise
Singulative " one ", " one " and " being somebody's turn to do " are also intended to include plural form.Also should manage
Solving, term " includes ", " include ... ", " comprising " and/or " comprising ... "
When used in this specification, existence listed feature, entirety, step, operation, element are indicated
And/or assembly, but do not preclude the presence or addition of one or more further feature, entirety, step,
Operation, element, assembly and/or their group.
Section view herein by reference to the schematic diagram as ideal example embodiment (and intermediate structure)
Figure describes example embodiment.So, as the result of such as manufacturing technology and/or tolerance, can
Change with the shape in prediction accompanying drawing.Therefore, example embodiment is not understood as limited to this
The concrete shape in the district shown in literary composition, but include the deviation of the shape such as caused by manufacturing process.
Such as, the injection region being shown as rectangle will be generally of circle or bending features and/or at its edge
There is the gradient of implantation concentration, rather than from injection region to the change of non-injection regions two-value.Similarly,
The buried regions formed by injection can be between buried regions and the surface that injection is occurred by it
District cause some inject.Therefore, the district shown in figure is the most schematic, and it
Shape be not intended to illustrate the true form in the district of device, and their shape is not intended to limit
The scope of example embodiment processed.
Unless otherwise defined, all terms the most used herein (include technology and science
Term) have and containing that one of example embodiment those of ordinary skill in the field are generally understood that
The implication that justice is identical.Be also to be understood that unless the most so definition herein, the most such as exist
The term of those defined in universaling dictionary should be interpreted as having with them in correlation technique
Context in the consistent implication of implication, and should be according to not ideally or the most formal
Implication explains them.
Fig. 1 is the schematic plan view illustrating the semiconductor device 100 according to example embodiment.
Fig. 2 is the sectional view of the line I-I' intercepting of the semiconductor device 100 along Fig. 1.Fig. 3 is
The enlarged drawing of part M1 of the semiconductor device 100 of Fig. 2 is shown.
Referring to figs. 1 through Fig. 3, the semiconductor device 100 of example embodiment can include that quasiconductor serves as a contrast
The end 101, grid structure 110a and 110b and interlayer dielectric 120a and 120b.
Semiconductor substrate 101 can include the first district A and the second district B.Semiconductor substrate can be passed through
Device isolation film 105a and 105b on 101 is limited to the upper extension of first direction (x direction)
Active area ACT.First grid structure 110a extended in a second direction (y-direction)
May be arranged in the first district A.The second grid structure extended in a second direction (y-direction)
110b may be arranged in the second district B.
Simultaneously, although active area ACT is arranged as and grid structure 110a and 110b in FIG
Vertically intersect, but active area ACT and grid structure 110a and 110b can be with off plumb
Angle is intersected with each other.Although in FIG, active area ACT and grid structure 110a and
110b intersects, but multiple active area ACT can intersect with grid structure 110a and 110b.
Additionally, the active area ACT (x in a first direction of the active area ACT of the first district A and the second district B
Direction) upper extension, but they can extend in different directions.The active area of the first district A
The active area ACT of ACT and the second district B has same widths in a second direction (y-direction),
But they can have different in width in a second direction (y-direction).
Semiconductor substrate 101 can be based on silicon body wafer or silicon-on-insulator (SOI) wafer.Half
The material of conductor substrate 101 is not limited to silicon.Such as, Semiconductor substrate 101 can include such as germanium
(Ge) IV race quasiconductor, such as SiGe (SiGe) or the IV-IV of carborundum (SiC)
Compound semiconductor or such as GaAs (GaAs), indium arsenide (InAs) or indium phosphide
(InP) Group III-V compound semiconductor.Semiconductor substrate 101 can based on SiGe wafer,
Epitaxial wafer, wafer polishing and/or annealing wafer.
Semiconductor substrate 101 can be p-substrate or n-type substrate.Such as, Semiconductor substrate
101 can be the p-substrate including n-type impurity ion, or includes the n of p-type impurity ion
Type substrate.Meanwhile, as it has been described above, Semiconductor substrate 101 can include by the example on its top
The active area ACT limited such as device isolation film 105a and 105b of shallow trench isolation (STI).
Active area ACT can include by being injected with relatively high concentration by foreign ion (i.e. alloy)
The impurity range formed to Semiconductor substrate 101.Such as, active area ACT can include by inciting somebody to action
More than 1E20/cm3Alloy be injected in Semiconductor substrate 101 formed source/drain regions
107a and 107b.
Device isolation film 105a and 105b may be formed to have the structure surrounding active area ACT,
As the district defining source region ACT.Device isolation film 105a and 105b may be arranged at each active
Between district ACT, and each active area ACT is electrically insulated.Device isolation film 105a and 105b
The the first device isolation film 105a being arranged in the first district A can be included and be arranged in the second district B
In the second device isolation film 105b.Such as, device isolation film 105a and 105b can include
At least one in silicon dioxide film, silicon nitride film, oxygen silicon nitride membrane and combinations thereof.
Grid structure 110a and 110b can be at second direction (y in Semiconductor substrate 101
Direction) upper extend across with active area ACT, and can by interlayer dielectric 120a with
120b is spaced apart from each other on (x direction) in a first direction.Grid structure 110a and 110b
First grid structure 110a being arranged in the first district A can be included and be arranged in the second district B
Second grid structure 110b.Interlayer dielectric 120a and 120b can include being arranged in first
The first interlayer dielectric 120a in district A and the second layer insulation being arranged in the second district B
Film 120b.Meanwhile, distance piece 130a and 130b may be arranged at grid structure 110a and 110b
And between interlayer dielectric 120a and 120b.Distance piece 130a and 130b can include being arranged in
The first distance piece 130a in first district A and the second distance piece being arranged in the second district B
130b.Distance piece 130a and 130b is included in interlayer dielectric 120a and 120b, and
Do not separate in FIG and illustrate.
Meanwhile, when element the most clearly divides into the first element and the second element, band
The element having reference number " a " can represent the structure being formed in the first district A, with reference
The element of label " b " can represent the structure being formed in the second district B.
Such as, interlayer dielectric 120a and 120b and distance piece 130a and 130b can shape
Become and include in silicon dioxide film, silicon nitride film, oxygen silicon nitride membrane and combinations thereof at least
One.Interlayer dielectric 120a and 120b and distance piece 130a and 130b can be by having not
The material of same etching selectivity is formed.Such as, formed as interlayer dielectric 120a and 120b
During for silicon dioxide film, distance piece 130a and 130b is formed as silicon nitride film.
Grid structure 110a and 110b can include gate insulating film 112a and 112b and gold
Belong to gate electrode 114a and 114b.Grid structure 110a and 110b can divide into and be arranged in first
First grid structure 110a in district A and the second grid structure being arranged in the second district B
110b。
Gate insulating film 112a and 112b may be arranged at metal gate electrode 114a and 114b with
Between active area ACT, and can by selected from silicon dioxide film, silicon nitride film, oxygen silicon nitride membrane,
Oxide/nitride/oxide (ONO) and dielectric constant are than the dielectric constant of silicon dioxide film
At least one in higher high-k dielectric films is formed.Such as, gate insulating film 112a and 112b
Dielectric constant can be in the range of about 10 to about 25.
For particular example, gate insulating film 112a and 112b can be by metal-oxide (example
As, hafnium oxide (HfO2), zirconium dioxide (ZrO2), titanium dioxide (TiO2) and three
Al 2 O (Al2O3)), their silicate or their aluminate formed.Gate insulator
Film 112a and 112b can be by metal oxynitrides (such as, aluminium oxynitride (AlON), oxygen nitrogen
Change zirconium (ZrON), oxynitriding hafnium (HfON), oxynitriding lanthanum (LaON) and oxynitriding yttrium (YON)),
Their silicate or their aluminate are formed.Additionally, gate insulating film 112a and 112b
Can be by perofskite type oxide, niobates or tantalite based material, tungsten bronze based material or bilayer
Perovskite series material is formed.
Available various deposition process form gate insulating film 112a and 112b, described method example
As chemical gaseous phase deposition (CVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure CVD (APCVD),
Low temperature CVD (LTCVD), the CVD (PECVD) of plasma enhancing, atomic layer CVD (ALCVD),
Ald (ALD) or physical vapour deposition (PVD) (PVD).Meanwhile, gate insulating film 112a
With 112b not only may be formed between metal gate electrode 114a and 114b and active area ACT,
And may be formed between distance piece 130a and 130b and metal gate electrode 114a and 114b,
As shown in the figure.
Metal gate electrode 114a and 114b is formed as a metal film or at least two metal
Film.Such as, metal gate electrode 114a and 114b can include potential barrier metal film and electrode metal film.
About this point, potential barrier metal film can include selected from W, WN, WC, Ti, TiN, Ta, TaN,
At least one material in Ru, Co, Mn, WN, Ni and NiB, and it is formed as monolayer
Or multilamellar.Electrode metal film can include at least one in Al, Cu and W.Such as, electrode
Metal film can include Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe,
CuW, W or W alloy, but it is not limited to this.Electrode metal film may also include selected from Al, Au,
Be、Bi、Co、Cu、Hf、In、Mn、Mo、Ni、Pb、Pd、Pt、Rh、Re、Ru、
One or more in Ta, Te, Ti, W, Zn and Zr, and can have one or two
Or more stacked structure.Potential barrier metal film and electrode metal film can be formed by PVD or CVD,
But it is not limited to this.
Meanwhile, grid structure 110a and 110b can include gate insulating film 112a and 112b
And the work function between metal gate electrode 114a and 114b adjusts film.Such as, work function adjusts
Film can include at least one in TiN, TaC, TaN and TaCN.In more detail, grid
Dielectric film 112a and 112b can include p-type metal according to the channel type of transistor to be formed
Gate electrode or N-shaped metal gate electrode.Such as, when limiting to each other in Semiconductor substrate 101
When the first active area separated and the second active area, PMOS is formed in the first active area, and
NMOS is formed in the second active area, and the grid structure 110a constituting PMOS can include p-type
Metal gate electrode, and the grid structure 110b constituting NMOS can include N-shaped metal gate electrode.
Meanwhile, work function adjusts film can be made only in the bottom of p-type metal gate electrode, and can not shape
Become in the bottom of N-shaped metal gate electrode.
Meanwhile, in first grid structure 110a of the first district A (x direction) in a first direction
Width can be the first width W1, and second grid structure 110b of the second district B is first
Width on direction (x direction) can be the second width W2.Such as, first grid structure 110a
The first width W1 be smaller than 80nm, the second width W2 of second grid structure 110b can
More than 80nm.By the first width W1 of first grid structure 110a and second grid structure
When the second width W2 of 110b compares, the second width W2 of second grid structure 110b
Can be more than 2 times of the first width W1 of first grid structure 110a.But, first grid is tied
The first width W1 of structure 110a and the second width W2 of second grid structure 110b is not limited to this.
In the semiconductor device 100 of example embodiment, it is assumed that gate insulating film 112a and
The thickness of 112b is relatively small, and the first width W1 and second of first grid structure 110a
The second width W2 of grid structure 110b is defined to include first grid dielectric film 112a respectively
Thickness with second grid dielectric film 112b.But, can be by the of first grid structure 110a
Second width W2 of one width W1 and second grid structure 110b is defined to get rid of gate insulator
Only first metal gate electrode 114a of the thickness of film 112a and 112b and the second metal gate electrode
The width of 114b.First width W1 of first grid structure 110a may correspond to by first
The channel length of the upper transistor formed of grid structure 110a (x direction) in a first direction.
Second width W2 of second grid structure 110b may correspond to by second grid structure 110b
The channel length of (x direction) upper transistor formed in a first direction.This point can be applicable to
Herein below.
Multiple first grid structures 110a with the first width W1 can be arranged in the first district A.
About this point, between the plurality of first grid structure 110a in a first direction (x direction)
On gap can be similar to the first width W1.In other words, first grid structure 110a it is arranged in
Between the first interlayer dielectric 120a (x direction) in a first direction on width can be with
One width W1 is similar.About this point, the similarity of width can refer to width in comparison object
About 1/2 again in the range of about 2 times.Meanwhile, a tool can only be arranged in the second district B
There is second grid structure 110b of the second width W2.(x direction) is upper in a first direction surrounds
Second interlayer dielectric 120b (x side in a first direction of the both sides of second grid structure 110b
To) on width can be similar to the second width W2 or more than 2 times of the second width W2.But,
The quantity of first grid structure 110a in the first district A or the first interlayer dielectric 120a
Width on (x direction) and second grid structure 110b in the second district B in a first direction
Quantity or the second interlayer dielectric 120b (x direction) in a first direction on width not
It is limited to this.Such as, two second grid structures 110b can be formed in the second district B, and
Second interlayer dielectric 120b (x in a first direction between two second grid structures 110b
Direction) on width can be similar to the second width W2.
Meanwhile, in the first district A, the upper surface of first grid structure 110a can be smooth.
In the first district A, the first interlayer dielectric 120a's between first grid structure 110a is upper
Surface is alternatively smooth.The height of the upper surface of the first interlayer dielectric 120a can be with neighbouring
The height of first grid structure 110a identical, and may make up a plane, this is because
First grid structure 110a and the first interlayer dielectric 120a between them are according to the first district A
In design rule can have the width of opposite, narrow, and therefore in first grid structure 110a
The upper surface of first grid structure 110a during the chemically mechanical polishing (CMP) of upper execution
Can be smooth with the upper surface of the first interlayer dielectric 120a.It addition, distance piece 130a
May be arranged between first grid structure 110a and the first interlayer dielectric 120a, can have it
Height is identical with the height of neighbouring first grid structure 110a and the first interlayer dielectric 120a
Upper surface, and the upper surface of distance piece 130a, the upper surface of first grid structure 110a
Also a plane is may make up with the upper surface of the first interlayer dielectric 120a.
In the second district B, the upper surface of second grid structure 110b can have convex core.
In other words, second grid structure 110b can have relative to Semiconductor substrate at core
Centre-height Hgc of the upper surface Fs of 101, and can have relative to partly leading in marginal portion
The brim height Hge of the upper surface Fs of body substrate 101.Centre-height Hgc is at second grid
Structure 110b can be the highest.Brim height Hge can be in second grid structure 110b
Minimum.About this point, second grid structure 110b includes gate insulating film 112b and gold
Belonging to gate electrode 114b, therefore to may correspond to grid exhausted in the marginal portion of second grid structure 110b
The marginal portion of velum 112b.The upper surface of second grid structure 110b can be from core court
Marginal portion to be gradually reduced.Such as, the upper surface of second grid structure 110b can with partly lead
The upper surface of body substrate 101 forms the first gradient θ 1.
Meanwhile, the height of the second interlayer dielectric 120b is along with away from second grid structure 110b
Can be gradually lowered relative to the upper surface of Semiconductor substrate 101.Such as, when the outermost of Fig. 2
Part is the central part of distance farthest the second interlayer dielectric 120b of second grid structure 110b
Timesharing, the core of the second interlayer dielectric 120b can have relative to Semiconductor substrate 101
Centre-height Hic of upper surface Fs, and be adjacent to the edge part of second grid structure 110b
Divide the brim height Hie can with the upper surface Fs relative to Semiconductor substrate 101.Center
Highly Hic can be minimum in the second interlayer dielectric 120b.Brim height Hie is second
Interlayer dielectric 120b can be the highest.About this point, the second interlayer dielectric 120b
A side surface can be adjacent to second grid structure 110b on (x direction) in a first direction,
And its opposite side surface can be adjacent to another second grid structure 110b or except second grid is tied
Semiconductor structure beyond structure 110b.The upper surface of the second interlayer dielectric 120b is from edge part
Divide and can be gradually reduced towards core.Such as, the upper surface of the second interlayer dielectric 120b
The second gradient θ 2 can be formed with the upper surface of Semiconductor substrate 101.Meanwhile, the first gradient θ 1
May be the same or different with the second gradient θ 2.
It addition, as it can be seen, distance piece 130b may be arranged at second grid structure 110b with
Between second interlayer dielectric 120b, and its upper surface is relative to Semiconductor substrate 101
Upper surface can have gradual slope.Such as, the gradient of the upper surface of distance piece 130b can smooth
Ground connects the marginal portion of second grid structure 110b and the edge of the second interlayer dielectric 120b
Part.
In the second district B, due to during the CPM performed in second grid structure 110b
Between the second metal gate electrode 114b and nonmetallic second interlayer dielectric 120b of metal
The difference of etching speed, the upper surface of second grid structure 110b and the second interlayer dielectric
The upper surface of 120b is formed as having gradual slope relative to the upper surface of Semiconductor substrate 101.
Such as, when by selecting suitable polishing agent to perform CPM, due to the second interlayer dielectric
The etching speed of the 120b etching speed than the second metal gate electrode 114b faster, therefore with
Two metal gate electrode 114b compare, and the second interlayer dielectric 120b can be etched quickly.So
And, the upper surface of the second metal gate electrode 114b and the upper surface of the second interlayer dielectric 120b
Step can not be had in marginal portion.Therefore, as it can be seen, the second metal gate electrode 114b
The upper surface upper surface than the second interlayer dielectric 120b higher, the most between which
There is gradual slope and continuous print coupling part.The upper surface of distance piece 130b is also dependent on phase
Same principle is formed, and second grid structure 110b and the second interlayer dielectric 120b is connected,
And relative to the upper surface of Semiconductor substrate 101, there is gradual slope.
The grid structure 110a of the first district A generally may make up the most intensive according to design rule
The transistor of cellular zone.The grid structure 110b of the second district B generally may make up more than cellular zone
The logic area of transistor or the transistor of surrounding zone.But, the grid structure of the first district A
The district of the grid structure 110b of 110a and the second district B is not limited to this.Such as, the first district A
Grid structure 110a can be applicable to the transistor of logic area.
Meanwhile, in the marginal portion of the first district A and the second district B of Fig. 2, due to described
Marginal portion corresponding to the core of the second interlayer dielectric 120b, therefore the second district B
The height of the first interlayer dielectric 120a of aspect ratio the firstth district A of the second interlayer dielectric 120b
Spend shorter.Correspondingly, if described marginal portion is corresponding to the second interlayer dielectric 120b's
Marginal portion, the then height of the second interlayer dielectric 120b and the first interlayer dielectric 120a
Height can be almost identical.The grid structure 110a of the first district A generally may make up cellular zone
Transistor.This point can be applicable to following other embodiments.
In the semiconductor device 100 of example embodiment, there is narrow width and flat upper surfaces
First grid structure 110a may be arranged in the first district A, there is wide degree and convex upper surface
Second grid structure 110b may be arranged in the second district B.Multiple first grid structures 110a
May be arranged in the first district A.One second grid structure 110b may be arranged in the second district B.
As it has been described above, the grid structure with different configuration and varying number is arranged in the first district A and
In two district B, thus improve global reliability and the operating characteristics of semiconductor device 100.Example
As, first grid structure 110a with same configuration is formed in the first district A, therefore,
Can realize the transistor with uniform characteristics, thus be favorably improved semiconductor device 100 can
By property.Second grid structure 110b of the marginal portion with gradual slope is formed at the secondth district
In B, therefore the defect in marginal portion reduces, it is achieved that the transistor that operating characteristics is improved,
Thus contribute to improving reliability and the operating characteristics of semiconductor device 100.
Fig. 4 to Fig. 8 is to illustrate the semiconductor device corresponding to Fig. 2 according to example embodiment
The sectional view of the semiconductor device 100a to 100e of the sectional view of 100.Describe for convenience,
To briefly provide or omit the description made with reference to Fig. 1 to Fig. 3.
With reference to Fig. 4, in terms of the structure of grid structure 110a1 and 110b1, example embodiment
Semiconductor device 100a can be different from the semiconductor device 100 of Fig. 1 to Fig. 3.Such as,
Each included grid in first grid structure 110a1 and second grid structure 110b1 is exhausted
Velum 112a1 and 112b1, lower metal gate electrode 114a1 and 114b1 and upper metal gate electricity
Pole 116a1 and 116b1.
Gate insulating film 112a1 and 112b1 can be arranged only at lower metal gate electrode 114a1 and
Between 114b1 and Semiconductor substrate 101.It is to say, gate insulating film 112a1 and 112b1
Can be not formed on the side surface of lower metal gate electrode 114a1 and 114b1.Form gate insulator
The material of film 112a1 and 112b1 or method and those phases described above by reference to Fig. 1 to Fig. 3
With.
Such as, lower metal gate electrode 114a1 and 114b1 can include TiN, TaN, TaC, TaCN,
At least one in TiAl and TiAlC.Lower metal gate electrode 114a1 and 114b1 can be used as
Work function adjusts film and/or potential barrier metal film.Therefore, lower metal gate electrode 114a1 and 114b1
Potential barrier metal film can be included, or can be formed separately with potential barrier metal film.
Upper metal gate electrode 116a1 and 116b1 may correspond to the semiconductor device of Fig. 1 to Fig. 3
Metal gate electrode 114a and 114b of part 100.Correspondingly, metal gate electrode 116a1 in formation
Identical with those described above by reference to Fig. 1 to Fig. 3 with the material of 116b1 or method.
Although it is not shown, first grid structure 110a1 and second grid structure 110b1
Can include that work function adjusts film.Work function adjusts film and may be formed at lower metal gate electrode 114a1
And between 114b1 and upper metal gate electrode 116a1 and 116b1, or may be formed at lower metal
On the bottom of gate electrode 114a1 and 114b1.
In the semiconductor device 100a of example embodiment, it is arranged in first in the first district A
Grid structure 110a1 can have narrow width and flat upper surfaces on (x direction) in a first direction,
Being arranged in can in second grid structure 110b1 in the second district B (x direction) in a first direction
There is wide degree and convex upper surface.First grid structure 110a1, second grid structure 110b1,
Interlayer dielectric 120a and 120b and the width of distance piece 130a and 130b and structure detailed
Thin description is identical with those described above by reference to Fig. 1 to Fig. 3.
Although in the semiconductor device 100 of Fig. 1 to Fig. 3, first grid structure 110a
Second width W2 of the first width W1 and second grid structure 110b includes metal gate electrode
The thickness of gate insulating film 112a and 112b of the side surface of 114a and 114b, but due to
In the semiconductor device 100a of example embodiment, gate insulating film 112a1 and 112b1 is not
It is formed in the side surface of metal gate electrode 114a and 114b, therefore first grid structure 110a
The first width W1 and the second width W2 of second grid structure 110b can only include lower metal
Gate electrode 114a1 and 114b1 and upper metal gate electrode 116a1 and 116b1 (x in a first direction
Direction) on width.
With reference to Fig. 5, in terms of the structure of grid structure 110a2 and 110b2, example embodiment
Semiconductor device 100b can be different from the semiconductor device 100 of Fig. 1 to Fig. 3.Such as,
Each included grid in first grid structure 110a2 and second grid structure 110b2 is exhausted
Velum 112a2 and 112b2, lower metal gate electrode 114a2 and 114b2 and upper metal gate electricity
Pole 116a2 and 116b2.
The structure of gate insulating film 112a2 and 112b2 can be with partly the leading of figure 1 above to Fig. 3
The structure of grid structure 112a with 112b of body device 100 is similar.It is to say, grid is exhausted
Velum 112a2 and 112b2 not only may be formed under lower metal gate electrode 114a2 and 114b2
On surface, and may be formed on its side surface.Gate insulating film 112a2 and 112b2
Material with reference to figure 1 above to Fig. 3 semiconductor device 100 describe material identical.
Lower metal gate electrode 114a2 and 114b2 and upper metal gate electrode 116a2 and 116b2
Structure and material and the lower metal gate electrode of semiconductor device 100a with reference to figure 4 above
The structure of 114a1 and 114b1 and upper metal gate electrode 116a1 and 116b1 description and material
Identical.
With reference to Fig. 6, in terms of the structure of grid structure 110a3 and 110b3, example embodiment
Semiconductor device 100c can be different from the semiconductor device 100 of Fig. 1 to Fig. 3.Such as,
Each included grid in first grid structure 110a3 and second grid structure 110b3 is exhausted
Velum 112a3 and 112b3 and metal gate electrode 114a3 and 114b3.
Gate insulating film 112a3 and 112b3 can be as in the semiconductor device 100a of Fig. 4
It is arranged only between metal gate electrode 114a3 and 114b3 and Semiconductor substrate 101, and can
It is not formed on the side surface of metal gate electrode 114a3 and 114b3.
Metal gate electrode 114a3 and 114b3 may be formed at gate insulating film 112a3 and 112b3
On, and the potential barrier metal film on outside it can be included.Formed metal gate electrode 114a3 and
The material of 114b3 or method and the semiconductor device 100 with reference to figure 1 above to Fig. 3 describe
Those are identical.
With reference to Fig. 7, in terms of the structure of grid structure 110a4 and 110b4, example embodiment
Semiconductor device 100d can be different from the semiconductor device 100 of Fig. 1 to Fig. 3.Such as,
Each included grid in first grid structure 110a4 and second grid structure 110b4 is exhausted
Velum 112a4 and 112b4, lower metal gate electrode 114a4 and 114b4 and upper metal gate electricity
Pole 116a4 and 116b4.
Gate insulating film 112a4 and 112b4 can be as in the semiconductor device 100a of Fig. 4
It is arranged only between lower metal gate electrode 114a4 and 114b4 and Semiconductor substrate 101.Lower gold
Belong to gate electrode 114a4 and 114b4 and can be made only in metal gate electrode 116a4 and 116b4
And between gate insulating film 112a4 and 112b4.It is to say, with the semiconductor device of Fig. 4
Unlike 100a, lower metal gate electrode 114a4 and 114b4 can be not formed in metal gate
On the side surface of electrode 116a4 and 116b4.
Form gate insulating film 112a4 and 112b4, lower metal gate electrode 114a4 and 114b4
With the material of upper metal gate electrode 116a4 and 116b4 or method and partly leading with reference to figure 4 above
Those of body device 100a description are identical.
In semiconductor device 100b, 100c and 100d of Fig. 5 to Fig. 7, it is arranged in
First grid structure 110a2 in one district A, 110a3 and 110a4 (x side in a first direction
To) on can have narrow width and flat upper surfaces, the second grid that is arranged in the second district B knot
Can have on structure 110b2,110b3 and 110b4 (x direction) in a first direction wide degree and
Convex upper surface.As described above with Fig. 1 to Fig. 3 semiconductor device 100 describe as,
In first district A, first grid structure 110a2,110a3 and 110a4, distance piece 130a with
And the upper surface of interlayer dielectric 120a can have identical height, and constitute a plane,
Second grid structure 110b2,110b3 and 110b4, distance piece 130b and interlayer dielectric
The upper surface of 120b can have from second grid structure 110b2, the center of 110b3 and 110b4
The gradual slope reduced partially towards the core of interlayer dielectric 120b.
With reference to Fig. 8, in terms of the structure of grid structure 110a5,110a5-1 and 110b5-1,
The semiconductor device 100e of example embodiment can with semiconductor device 100,100a, 100b,
100c with 100d is different.Such as, N-shaped first grid structure 110a5 and p-type first grid
Structure 110a5-1 may be formed in the first district A, and second grid structure 110b5-1 can shape
Become in the second district B.
N-shaped first grid structure 110a5 can include gate insulating film 112a5, lower metal gate electricity
Pole 114a5, potential barrier metal film 116a5 and upper metal gate electrode 118a5.Gate insulating film
112a5 is formed as surrounding lower surface and the side surface of lower metal gate electrode 114a5.Form grid
The material of pole dielectric film 112a5 or method and the semiconductor device with reference to figure 1 above to Fig. 3
100 those described are identical.
Lower metal gate electrode 114a5 may be formed on gate insulating film 112a5, to surround gesture
Build lower surface and the side surface of metal film 116a5.Such as, lower metal gate electrode 114a5 can wrap
Include at least one in TiN, TaN, TaC, TaCN, TiAl and TiAlC, and can be used as
Work function adjusts film.In the semiconductor device 100e of example embodiment, lower metal gate electrode
114a5 can be formed by TiAlC.Although it is not shown, lower metal gate electrode 114a5 can wrap
Include the capping film relatively thinly formed on gate insulating film 112a5.Capping film can be used as potential barrier gold
Belong to film, and can be formed by such as TiN.
Potential barrier metal film 116a5 can be formed as surrounding gold on lower metal gate electrode 114a5
Belong to lower surface and the side surface of gate electrode 118a5.Potential barrier metal film 116a5 can include selected from W,
In WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni and NiB at least
A kind of material, and it is formed as single or multiple lift.Semiconductor device in example embodiment
In 100e, potential barrier metal film 116a5 can be formed by TiN.
Upper metal gate electrode 118a5 may be formed on potential barrier metal film 116a5.Upper metal gate
Electrode 118a5 may correspond to the metal gate electrode 114a of the semiconductor device 100 of Fig. 1 to Fig. 3
And 114b.Correspondingly, in formation the material of metal gate electrode 118a5 or method with reference to
Figure 1 above to the semiconductor device 100 of Fig. 3 describe those are identical.In example embodiment half
In conductor device 100e, upper metal gate electrode 118a5 can be formed by such as W.
P-type first grid structure 110a5-1 can include gate insulating film 112a5, lower metal gate
Electrode 114a5-1 and potential barrier metal film 116a5.Formed gate insulating film 112a5 structure,
Material and method and the gate insulating film 112a5 with reference to above N-shaped first grid structure 110a5
Those described are identical.
Lower metal gate electrode 114a5-1 may be formed on gate insulating film 112a5, to surround
The lower surface of potential barrier metal film 116a5 and side surface.Lower metal gate electrode 114a5-1 is than n
The lower metal gate electrode 114a5 of type first grid structure 110a5 is thicker.Such as, lower metal gate
Electrode 114a5-1 may also include p-type work function and adjusts film.In other words, lower metal gate electrode
114a5-1 can include that p-type work function adjusts film and corresponding to N-shaped first grid structure 110a5
Lower metal gate electrode 114a5 common work function adjust film.P-type work function adjusts film can be by
Such as TiN is formed.Common work function adjusts film and can be formed by TiAlC.Meanwhile, lower metal gate
Electrode 114a5-1 may also include p-type work function and adjusts between film and common work function adjustment film
Capping film.Adjusting film with p-type work function identical, capping film can be formed by TiN.
Potential barrier metal film 116a5 may be formed on lower metal gate electrode 114a5-1.Potential barrier gold
Belonging to film 116a5 can be by the material with the potential barrier metal film 116a5 of N-shaped first grid structure 110a5
Expect that identical material is formed.Such as, potential barrier metal film 116a5 can be formed by TiN.Under due to
Metal gate electrode 114a5-1 is formed thicker, results in the sky of metal gate electrode 118a5
Between not enough, therefore go up metal gate electrode 118a5 and can be not formed in p-type first grid structure
In 110a5-1.This point will be more fully described with reference to Figure 24 A to Figure 24 D.But, on
Metal gate electrode 118a5 may be formed in p-type first grid structure 110a5-1.Such as, when
Lower metal gate electrode 114a5-1 is formed relatively thin or p-type first grid structure 110a5-1
In a first direction during the wider width on (x direction), upper metal gate electrode 118a5 can be formed
In p-type first grid structure 110a5-1.
Second grid structure 110b5-1 can include gate insulating film 112b5, lower metal gate electrode
114b5-1, potential barrier metal film 116b5 and upper metal gate electrode 118b5.In terms of Rotating fields,
Second grid structure 110b5-1 can be similar to N-shaped first grid structure 110a5, and second gate
Electrode structure 110b5-1 may differ in N-shaped first grid structure 110a5: is formed
The material of lower metal gate electrode 114b5-1 and structure and formation p-type first grid structure
The material of the lower metal gate electrode 114a5-1 of 110a5-1 is identical with structure.
In other words, the gate insulating film 112b5 of second grid structure 110b5-1, potential barrier gold
Belong to film 116b5 and upper metal gate electrode 118b5 respectively with N-shaped first grid structure 110a5
Gate insulating film 112a5, potential barrier metal film 116a5 identical with upper metal gate electrode 118a5.
The lower metal gate electrode 114b5-1 of second grid structure 110b5-1 can include that p-type work function is adjusted
Whole film, capping film, common work function adjust film, and than N-shaped first grid structure 110a5
Lower metal gate electrode 114a5 thicker.
Meanwhile, the width in second grid structure 110b5-1 (x direction) in a first direction can
More than the width in p-type first grid structure 110a5-1 in a first direction (x direction), because of
On this, metal gate electrode 118b5 may be formed on potential barrier metal film 116b5.
In the semiconductor device 100e of example embodiment, the second grid structure of the second district B
The formation structure of the lower metal gate electrode 114b5-1 of 110b5-1 and material and p-type first grid
The formation structure of the lower metal gate electrode 114a5-1 of structure 110a5-1 is identical with material, but
According to function, the lower metal gate electrode of second grid structure 110b5-1 of the second district B
The structure that formed of 114b5-1 can be with the lower metal gate of N-shaped first grid structure 110a5 with material
The formation structure of electrode 114a5 is identical with material.Although only forming a p in the first district A
Type first grid structure 110a5-1, but N-shaped first grid structure 110a5 and p-type first
The quantity of grid structure 110a5-1 is unrestricted, and can adjust in various manners.Additionally,
In the first district A, do not mix N-shaped first grid structure 110a5 and p-type first grid structure
110a5-1, but can only arrange the first grid structure of a kind of channel type.
In the semiconductor device 100e of example embodiment, it is arranged in the N-shaped in the first district A
First grid structure 110a5 and p-type first grid structure 110a5-1 (x side in a first direction
To) on can have narrow width and flat upper surfaces, and be arranged in the second gate in the second district B
Electrode structure 110b5-1 can have wide degree and convex upper surface on (x direction) in a first direction.
Meanwhile, in the first district A, N-shaped first grid structure 110a5 and p-type first grid structure
Width on 110a5-1 (x direction) in a first direction can be identical.But, according to environment, n
One of width of type first grid structure 110a5 and p-type first grid structure 110a5-1 can be more
Greatly.
As described above with as semiconductor device 100 description of Fig. 1 to Fig. 3, first
In district A, N-shaped first grid structure 110a5 of the semiconductor device 100e of example embodiment,
The upper table of p-type first grid structure 110a5-1, distance piece 130a and interlayer dielectric 120a
Face can have identical height and constitute a plane, in the second district B, and second grid structure
The upper surface of 110b5-1, distance piece 130b and interlayer dielectric 120b can have from second gate
The core of electrode structure 110b5-1 towards interlayer dielectric 120b core reduce
Gradual slope.
Described above is the semiconductor device 100 of the grid structure including various structure, 100a,
100b, 100c, 100d and 100e.But, present inventive concept be not limited to semiconductor device 100,
100a, 100b, 100c, 100d and 100e.Such as, when grid structure tool in a district
There are the narrow width corresponding to channel length and flat upper surfaces, and another grid in another district
When structure has the wide degree corresponding to channel length and convex upper surface, semiconductor device can belong to
Present inventive concept, regardless of grid structure structure how.
Fig. 9 is the perspective view illustrating the semiconductor device 200 according to example embodiment.Figure 10
It it is the sectional view of the line II-II' intercepting of the semiconductor device 200 along Fig. 9.Figure 11 is edge
The sectional view that line III-III' and IV-IV' of the semiconductor device 200 Fig. 9 intercepts.Figure
12 is the enlarged drawing of part M2 of the semiconductor device 200 illustrating Figure 10.
With reference to Fig. 9 to Figure 12, the semiconductor device 200 of example embodiment may be included in partly leads
There is on body substrate 201 active region of the structure of fin 240a and 240b.First district A and
Two district B can correspond respectively to the first district A and second of the semiconductor device 100 of Fig. 1 to Fig. 3
District B.
In more detail, the semiconductor device 200 of example embodiment can include Semiconductor substrate
201, fin 240a and 240b, device isolation film 250a and 250b, grid structure 210a and
210b and interlayer dielectric 220a and 220b.
Semiconductor substrate 201 may correspond to partly leading of the semiconductor device 100 of Fig. 1 to Fig. 3
Body substrate 101, therefore omits detailed description.
Fin 240a and 240b may have a structure such that, wherein fin 240a and 240b is from half
Conductor substrate 201 is prominent and (x direction) is upper in a first direction extends.Multiple fin 240a
Can be formed in a second direction (y-direction) in Semiconductor substrate 201 with 240b.Fin 240a
The second fin 240b of the first fin 240a and the second district B of the first district A can be included with 240b.
First fin 240a and the second fin 240b can be electrically insulated from each other by device isolation film.But, the
One fin 240a and the second fin 240b can be connected to each other.Although the first fin in the exemplary embodiment
240a and the second fin 240b extends in the same direction, but the first fin 240a and the second fin
240b can extend in different directions.
Each in first fin 240a and the second fin 240b can include lower fin 240a-1 and
240b-1 and upper fin 240a-2 and 240b-2.Lower fin 240a-1 and 240b-1 can be based on half
Conductor substrate 101 is formed.Upper fin 240a-2 and 240b-2 is formed as from lower fin 240a-1
Epitaxial film with 240b-1 growth.As shown in Figure 10, relative to grid structure 210a and 210b,
Upper fin 240a-2 and 240b-2 may make up source/drain regions, and lower fin 240a-1 and
240b-1 may make up the channel region in the bottom of grid structure 210a and 210b.
When the first fin 240a and the second fin 240b includes the upper fin 240a-2 that is formed as epitaxial film
During with 240b-2, the first fin 240a and the second fin 240b can include as semiconductor element
Silicon or germanium.First fin 240a and the second fin 240b can include compound semiconductor, such as IV-IV
Compound semiconductor or Group III-V compound semiconductor.Such as, the first fin 240a and
Two fin 240b can include the binary compound as IV-IV compound semiconductor or ternary
Compound, it includes at least two in carbon (C), silicon (Si), germanium (Ge) and stannum (Sn)
Individual or more elements, or the IV that includes adulterating described binary compound or ternary compound
The compound of race's element.First fin 240a and the second fin 240b can include as iii-v
One of the binary compound of compound quasiconductor, ternary compound and quaternary compound, it passes through will
As at least one in aluminum (Al), gallium (Ga) and the indium (In) of group-III element and phosphorus
(P), the combination of one of arsenic (As) and antimony (Sb) is formed.Will be with reference to Figure 25 A to Figure 26 G
It is more fully described formation the first fin 240a and the structures and methods of the second fin 240b.
Meanwhile, upper fin 240a-2 and 240b-2 of fin 240a and 240b can be at lower fin 240a-1
Be formed at the both sides of grid structure 210a and 210b on 240b-1, and can be according to required
The channel type of transistor include compressive stress material or tensile stress material.Such as, when forming p
During transistor npn npn, it is formed at fin 240a and 240b of the both sides of grid structure 210a and 210b
Upper fin 240a-2 and 240b-2 can include compressive stress material.In more detail, fin instantly
When 240a-1 and 240b-1 is formed by silicon, upper fin 240a-2 and 240b-2 can be answered by as pressure
The material (such as, SiGe (SiGe)) that the lattice paprmeter of dead-wood material is bigger than the lattice paprmeter of silicon
Formed.When forming n-type transistor, it is formed at the both sides of grid structure 210a and 210b
Upper fin 240a-2 and 240b-2 of fin 240a and 240b can include tensile stress material.In more detail
Ground is said, when fin 240a-1 and 240b-1 is formed by silicon instantly, and upper fin 240a-2 and 240b-2
Can be by the material less than the lattice paprmeter of silicon as the silicon of tensile stress material or lattice paprmeter
(such as, carborundum (SiC)) is formed.
It addition, upper fin 240a-2 and 240b-2 is at the semiconductor device 200 of example embodiment
In can have variously-shaped.Such as, upper fin 240a-2 and 240b-2 is being perpendicular to first direction
Can have variously-shaped on the cross section in (x direction), such as, rhombus, circle, ellipse
And polygonal shape.Fig. 9 shows example pentagon diamond-shaped.
Device isolation film 250a and 250b may be formed in Semiconductor substrate 201, and can
The first device isolation film 250a and second device isolation film of the second district B including the first district A
250b.First device isolation film 250a is formed as surrounding the lower fin 240a-1 of the first fin 240a
Two side surfaces.Second device isolation film 250b is formed as surrounding under the second fin 240b
Two side surfaces of fin 240b-1.
Device isolation film 250a and 250b may correspond to the semiconductor device 100 of Fig. 1 to Fig. 3
Device isolation film 105a and 105b, and can be used in a second direction (y-direction)
The fin electric isolution of arrangement.Such as, device isolation film 250a and 250b can include silicon dioxide film,
At least one in silicon nitride film, oxygen silicon nitride membrane and combinations thereof.Device isolation film 250a
First fin 240a and the second fin 240b can be electrically insulated with a part of 250b.
Meanwhile, upper fin 240a-2 and 240b-2 of fin 240a and 240b can highlight and not by
Device isolation film 250a and 250b surrounds.As shown in figure 11, grid structure 210a it is arranged in
Can be from device with lower fin 240a-1 and 240b-1 of fin 240a and 240b in the bottom of 210b
Part isolating membrane 250a and 250b highlights.
Grid structure 210a and 210b can be second on device isolation film 250a and 250b
Direction (y direction) is upper intersects extension with fin 240a and 240b, and may be arranged at first party
On (x direction).Grid structure 210a and 210b can include the first grid of the first district A
Structure 210a and second grid structure 210b of the second district B.
Grid structure 210a and 210b can correspond respectively to the semiconductor device of Fig. 1 to Fig. 3
Grid structure 110a and 110b of 100.But, it is similar to the semiconductor device 100b of Fig. 5,
In the semiconductor device 200 of example embodiment, grid structure 210a and 210b can include grid
Pole dielectric film 212a and 212b, lower metal gate electrode 214a and 214b and upper metal gate electricity
Pole 216a and 216b.
First grid structure 210a is formed as surrounding the first fin 240a.Second grid structure
210b is formed as surrounding the second fin 240b.In more detail, first grid structure 210a
It is formed as surrounding upper surface and a part for side surface of the lower fin 240a-1 of the first fin 240a,
Second grid structure 210b is formed as surrounding the upper table of the lower fin 240b-1 of the second fin 240b
Face and a part for side surface.With reference to Figure 25 A to Figure 26 G, grid structure will more clearly be described
The structure of 210a and 210b.In addition to structure, form grid structure 210a's and 210b
The semiconductor device of material or method and the semiconductor device 100 and Fig. 5 referring to figs. 1 through Fig. 3
Those of 100b description are identical.
Interlayer dielectric 220a and 220b may be formed on device isolation film 250a and 250b
To cover fin 240a and 240b.Interlayer dielectric 220a and 220b can include the first district A's
The second interlayer dielectric 220b of the first interlayer dielectric 220a and the second district B.First interlayer
Dielectric film 220a can cover the first fin 240a on the first device isolation film 250a, and can
It is formed between each first grid structure 210a.Second interlayer dielectric 220b can be at the second device
Cover the second fin 240b on part isolating membrane 250b, and may be formed at second grid structure 210b
Two side surfaces on.
Interlayer dielectric 220a and 220b may have a structure such that, it is according to as active
Prominent fin 240a and 240b in district surrounds the upper surface of fin 240a and 240b and side surface
A part.In more detail, interlayer dielectric 220a and 220b is formed as surrounding fin 240a
Structure with upper fin 240a-2 and 240b-2 of 240b.Interlayer dielectric 220a and 220b
Can correspond respectively to Fig. 1 to Fig. 3 semiconductor device 100 interlayer dielectric 120a and
120b.Correspondingly, the material or the method that form interlayer dielectric 220a and 220b are schemed with reference
Those of semiconductor device 100 description of 1 to Fig. 3 are identical.
Distance piece 230a and 230b may be formed at interlayer dielectric 220a and 220b and grid
Between structure 210a and 210b.Distance piece 230a and 230b can surround grid structure 210a
With two side surfaces of 210b, extend in a second direction (y-direction), and can be with grid
Electrode structure 210a and 210b similarly surround across with fin 240a and 240b fin 240a and
The upper surface of 240b and side surface.Distance piece 230a and 230b can correspond respectively to Fig. 1 extremely
Distance piece 130a and 130b of the semiconductor device 100 of Fig. 3.Correspondingly, distance piece is formed
Material or the method for 230a and 230b describe with the semiconductor device 100 referring to figs. 1 through Fig. 3
Those are identical.
With the semiconductor device 100 of Fig. 1 to Fig. 8 described above, 100a, 100b, 100c,
100d with 100e is similar, and in the semiconductor device 200 of example embodiment, first grid is tied
Width on structure 210a (x direction) in a first direction can be less, second grid structure 210b
Width on (x direction) can be wider in a first direction.Such as, first grid structure 210a
Width on (x direction) is smaller than 80nm, second grid structure 210b in a first direction
Width on (x direction) can be more than 80nm in a first direction.In first grid structure 210a
When comparing with second grid structure 210b, second grid structure 210b (x in a first direction
Direction) on width can be more than in first grid structure 210a (x direction) in a first direction
The twice of width.First grid structure 210a and second grid structure 210b are in a first direction
Width on (x direction) is not limited to above numerical value.
As shown in Figure 10, first grid structure 210a, the first interlayer dielectric 220a and
The upper surface of spacing body 230a can be smooth, and the upper surface of distance Semiconductor substrate 201
Fs' can have identical height.Therefore, first grid structure 210a, the first interlayer dielectric 220a
A flat upper surfaces can be had with distance piece 230a.Meanwhile, second grid structure 210b
Upper surface can cardiac prominence go out wherein, and can reduce towards outside.In more detail, second
Grid structure 210b can under core has distance the center of the upper surface of fin 240b-1 high
Degree Hgc and under marginal portion has distance the brim height of upper surface of fin 240b-1
Hge.Centre-height Hgc can be the highest in second grid structure 210b.Brim height Hge
Second grid structure 210b can be minimum.Second interlayer dielectric 220b can be at central part
Divide and there is centre-height Hic of the upper surface apart from upper fin 240b-2 and be adjacent to second
The marginal portion of grid structure 210b has the brim height of the upper surface apart from upper fin 240b-2
Hie.Centre-height Hic can be minimum in the second interlayer dielectric 220b.Brim height
Hie can be the highest in the second interlayer dielectric 220b.It is arranged in second grid structure 210b
And the upper surface of the distance piece 230b between the second interlayer dielectric 220b can have relative to half
The gradual slope of the upper surface Fs' of conductor substrate 201.The upper surface of distance piece 230b oblique
Degree can be by the edge of the marginal portion of second grid structure 210b Yu the second interlayer dielectric 220b
Part smoothly connects.
Above by reference to the line II-II'(along Fig. 9 i.e., fin 240a and 240b is in second party
Core on (y direction)) description of profile that intercepts second grid structure 210b
Upper surface and the height of upper surface of the second interlayer dielectric 220b.If using other to cut open
Face rather than include the part of fin 240a and 240b, then can refer to the upper table of Semiconductor substrate 201
The upper surface of face Fs' or device isolation film 250a and 250b describes second grid structure
The upper surface of 210b and the height of the upper surface of the second interlayer dielectric 220b.Although employing
The upper surface Fs' of Semiconductor substrate 201 or the upper surface of device isolation film 250a and 250b,
But the upper surface of the upper surface of second grid structure 210b and the second interlayer dielectric 220b
Height can be almost identical with described above.
In the semiconductor device 200 of example embodiment, the first grid structure of the first district A
210a can have little width and flat upper surfaces, the secondth district on (x direction) in a first direction
Wide width and convex can be had in second grid structure 210b of B (x direction) in a first direction
Upper surface.In the first district A, first grid structure 210a, the first interlayer dielectric 220a
Identical height and a flat upper surfaces can be had with distance piece 230a.In the second district B,
Second grid structure 210b, the second interlayer dielectric 220b and distance piece 230b can have from
The core of second grid structure 210b reduces towards the core of interlayer dielectric 220b
Gradual slope.
Figure 13 is to illustrate cuing open of the semiconductor device corresponding to Figure 10 according to example embodiment
The sectional view of the semiconductor device 200a of view.Describe for convenience, will briefly provide or save
The description slightly made with reference to Fig. 9 to Figure 12.
With reference to Figure 13, in terms of the structure of grid structure 210a1 and 210b1, example is implemented
The semiconductor device 200a of example can be different from the semiconductor device 200 of Fig. 9 to Figure 12.Such as,
Each included grid in first grid structure 210a1 and second grid structure 210b1 is exhausted
Velum 212a1 and 212b1, lower metal gate electrode 214a1 and 214b1 and upper metal gate electricity
Pole 216a1 and 216b1.
Similar to the semiconductor device 100a of Fig. 4, gate insulating film 212a1 and 212b1 can
It is arranged only between lower metal gate electrode 214a1 and 214b1 and lower fin 240a-1 and 240b-1.
It is to say, gate insulating film 212a1 and 212b1 can be not formed in lower metal gate electrode
In the side surface of 214a1 and 214b1.Correspondingly, gate insulating film 212a1 and 212b1 is formed
Material or method describe with the semiconductor device 100a with reference to Fig. 4 those are identical.
Formed lower metal gate electrode 214a1 and 214b1 and upper metal gate electrode 216a1 and
The material of 216b1 or method describe with the semiconductor device 100a with reference to Fig. 4 those are identical.
But, grid structure 210a1 and 210b1 is formed as surrounding the upper surface of fin 240a and 240b
With a part for side surface, therefore gate insulating film 212a1 and 212b1, lower metal gate electrode
214a1 and 214b1 and upper metal gate electrode 216a1 and 216b1 is formed as surrounding fin
The upper surface of 240a and 240b and a part for side surface.
It addition, first grid structure 210a1 and second grid structure 210b1 can include work content
Number adjusts film.Work function adjusts film and may be formed at lower metal gate electrode 214a1 and 214b1 with upper
Between metal gate electrode 216a1 and 216b1, or may be formed at lower metal gate electrode 214a1
With in the lower surface of 214b1.
In the semiconductor device 200a of example embodiment, it is arranged in first in the first district A
Also can have on grid structure 210a1 (x direction) in a first direction little width and smooth on
Surface, is arranged in second grid structure 210b1 in the second district B (x direction) in a first direction
On also can have wide width and convex upper surface.First grid structure 210a1, second grid are tied
Structure 210b1, interlayer dielectric 220a and 220b and the width of distance piece 230a and 230b and
Construct identical with describe with reference to Fig. 9 to Figure 12.
Figure 14 and Figure 15 be shown respectively according to example embodiment corresponding to Figure 10 and Figure 11
The sectional view of semiconductor device 200b of sectional view of semiconductor device.Describe for convenience,
To briefly provide or omit the description made with reference to Fig. 9 to Figure 12.
With reference to Figure 14 and Figure 15, at grid structure 210a2,210a2-1 and 210b2-1
Structure aspect, the semiconductor device 200b of example embodiment can be with the quasiconductor of Fig. 9 to Figure 12
The semiconductor device 200a of device 200 or Figure 13 is different.Such as, with the quasiconductor of Fig. 8
Device 100e is similar, and the semiconductor device 200b of example embodiment can include in the first district A
N-shaped first grid structure 210a2 and p-type first grid structure 210a2-1, and the secondth district
Second grid structure 210b2-1 in B.
N-shaped first grid structure 210a2 can include gate insulating film 212a2, lower metal gate electricity
Pole 214a2, potential barrier metal film 216a2 and upper metal gate electrode 218a2.Form gate insulator
The material of film 212a2 or method and the semiconductor device 200 with reference to Fig. 9 to Figure 12 describe
Those are identical.
Lower metal gate electrode 214a2 may be formed on gate insulating film 212a2, to surround gesture
Build lower surface and the side surface of metal film 216a2.The material of lower metal gate electrode 214a2, merit
The lower metal gate electrode 114a5 with the semiconductor device 100e with reference to Fig. 8 and can be constructed describe
Those are identical.But, N-shaped first grid structure 210a2 is formed as surrounding fin 240a's
Upper surface and a part for side surface, therefore descend metal gate electrode 214a2 to may be alternatively formed to surround
The upper surface of fin 240a and a part for side surface.
Potential barrier metal film 216a2 may be formed on lower metal gate electrode 214a2, on surrounding
The lower surface of metal gate electrode 218a2 and side surface.Due to N-shaped first grid structure 210a2
Overall structure, potential barrier metal film 216a2 is formed as surrounding the upper surface of fin 240a and side
The part on surface.The material of potential barrier metal film 216a2 and the semiconductor device with reference to Fig. 8
Those of the potential barrier metal film 116a5 description of 100e are identical.
Upper metal gate electrode 218a2 may be formed on potential barrier metal film 216a2.Upper metal gate
Electrode 218a2 may correspond to the upper metal gate electrode 118a5 of the semiconductor device 100e of Fig. 8.
Therefore, it is formed as surrounding upper surface and the side table of fin 240a except upper metal gate electrode 218a2
Beyond the part in face, the semiconductor device 100e's of upper metal gate electrode 218a2 Yu Fig. 8
Upper metal gate electrode 118a5 is identical.
P-type first grid structure 210a2-1 can include gate insulating film 212a2, lower metal gate
Electrode 214a2-1 and potential barrier metal film 216a2.P-type first grid structure 210a2-1 can be with
P-type first grid structure 110a5-1 of the semiconductor device 100e of Fig. 8 is essentially identical.So
And, p-type first grid structure 210a2-1 can be with the p-type of the semiconductor device 100e of Fig. 8
First grid structure 110a5-1 is different, and difference is, p-type first grid structure
210a2-1 is again formed as surrounding upper surface and a part for side surface of fin 240a.
Second grid structure 210b2-1 can include gate insulating film 212b2, lower metal gate electrode
214b2-1, potential barrier metal film 216b2 and upper metal gate electrode 218b2.Second grid structure
210b2-1 can be basic with second grid structure 110b5-1 of the semiconductor device 100e of Fig. 8
Identical.But, second grid structure 210b2-1 also can be with the semiconductor device 100e of Fig. 8
Second grid structure 110b5-1 different, difference is, second grid structure 210b2-1
It is again formed as surrounding upper surface and a part for side surface of fin 240a.
In the semiconductor device 200b of example embodiment, although the second grid of the second district B
The material of the lower metal gate electrode 214b2-1 of structure 210b2-1 and structure and p-type first grid
Those of the lower metal gate electrode 214a2-1 of structure 210a2-1 are identical, but according to function,
The material of the lower metal gate electrode 214b2-1 of second grid structure 210b2-1 of the second district B and
Structure can be identical with those of the lower metal gate electrode 214a2 of N-shaped first grid structure 210a2.
P-type first grid structure 210a2-1 is only arranged in the first district A, but N-shaped first
The quantity of grid structure 210a2 and p-type first grid structure 210a2-1 is not limited to this, but
Can adjust in various manners.Additionally, N-shaped first grid knot can not be mixed in the first district A
Structure 210a2 and p-type first grid structure 210a2-1, but only can arrange in the first district A
A kind of first grid structure of channel type.
In the semiconductor device 200b of example embodiment, it is arranged in the N-shaped in the first district A
First grid structure 210a2 and p-type first grid structure 210a2-1 (x side in a first direction
To) on can have narrow width and flat upper surfaces, and be arranged in the second gate in the second district B
Electrode structure 210b2-1 can have wide degree and convex upper surface on (x direction) in a first direction.
Meanwhile, in the first district A, N-shaped first grid structure 210a2 and p-type first grid structure
Width on 210a2-1 (x direction) in a first direction can be identical.But, according to environment, n
One of width of type first grid structure 210a2 and p-type first grid structure 210a2-1 can be more
Greatly.
As describing as described above with Fig. 9 to Figure 12, in the first district A, N-shaped first
Grid structure 210a2, p-type first grid structure 210a2-1, distance piece 230a and interlayer are exhausted
The upper surface of velum 220a can have identical height and constitute a plane, at the second district B
In, the upper table of second grid structure 210b2-1, distance piece 230b and interlayer dielectric 220b
Face can have from the core of second grid structure 210b2-1 towards interlayer dielectric 220b
Core reduce gradual slope.
The semiconductor device with Fig. 4 and Fig. 8 is described above in association with the semiconductor device including fin
The similar structure of structure of the grid structure of part 100a with 100e, but include the quasiconductor of fin
Device is not limited to this.The grid of semiconductor device 100b, 100c and 100d of Fig. 5 to Fig. 7
The structure of structure also apply be applicable to include the semiconductor device of fin.If additionally, grid structure exists
One district has narrow width and flat upper surfaces, and another grid structure has in another district
Wide degree and convex upper surface, then the structure of the grid structure in addition to above-mentioned grid structure also can be answered
For including the semiconductor device of fin.
Figure 16 and Figure 17 is namely for describing the semiconductor device 300 according to example embodiment
Circuit diagram and layout.
With reference to Figure 16 and Figure 17, the semiconductor device 300 of example embodiment may be included in power
Between node Vcc and ground node Vss a pair changer INV1 and INV2 being connected in parallel to each other and
It is respectively connecting to the first conducting transistor PS1 of the output node of changer INV1 and INV2
With the second conducting transistor PS2.First conducting transistor PS1 and the second conducting transistor PS2
Bit line BL and paratope line BL/ can be respectively connecting to.First conducting transistor PS1 and second
The grid of conducting transistor PS2 is connectable to wordline WL.
First changer INV1 can include that be one another in series first pulls up transistor PU1 and first
Pull-down transistor PD1.Second changer INV2 can include being one another in series second on crystal pulling
Pipe PU2 and the second pull-down transistor PU2.First pulls up transistor crystal pulling on PU1 and second
Pipe PU2 can be PMOS transistor.First pull-down transistor PD1 and the second pull-down transistor PU2
It can be nmos pass transistor.
In order to constitute latch cicuit, the input node of the first changer INV1 is connectable to second
The output node of changer INV2, and the input node of the second changer INV2 is connectable to
The output node of the first changer INV1.
The first active area being spaced apart from each other is to the 4th active area (310,320,330 and 340)
Can extend on (x direction) in a first direction longlyer.Second active area 320 and the 3rd is active
The extension that the development length in district 330 is smaller than the first active area 310 and the 4th active area 340 is long
Degree.
First gate electrode can be in second party to the 4th gate electrode (351,352,353 and 354)
Extend on (y direction) longlyer, and can be with the first active area 310 and the 4th active area
340 intersect.In more detail, first gate electrode 351 can be with the first active area 310 and second
Active area 320 intersects, and can partly overlap with the longitudinal end of the 3rd active area 330.The
Three gate electrodes 353 can intersect with the 3rd active area 330 and the 4th active area 340, and can be with
The longitudinal end of the second active area 320 partly overlaps.Second gate electrode 352 and the 4th gate electrode
354 can intersect with the first active area 310 and the 4th active area 340 respectively.
As shown in Figure 16 and Figure 17, first pull up transistor PU1 can be limited to the first grid electricity
In the district that pole 351 is intersected with each other with the second active area 320, the first pull-down transistor PD1 can limit
It is scheduled in the district that first gate electrode 351 is intersected with each other with the first active area 310, the first conducting crystalline substance
Body pipe PS1 can be limited in the district that second gate electrode 352 is intersected with each other with the first active area 310.
Second PU2 that pulls up transistor can be limited to the 3rd gate electrode 353 and the 3rd active area 330 each other
In the district intersected, the second pull-down transistor PD2 can be limited to the 3rd gate electrode 353 to be had with the 4th
In the district that source region 340 is intersected with each other, the second conducting transistor PS2 can be limited to the 4th gate electrode
In 354 districts intersected with each other with the 4th active area 340.
Although being not expressly shown in Figure 16 and Figure 17, but source/drain may be formed at
Wherein first to fourth gate electrode (351,352,353 and 354) is active with first to fourth
The both sides in the district that district (310,320,330 and 340) is intersected with each other.It addition, share contact
Part 361 can be simultaneously connected with the second active area the 320, the 3rd gate electrode 353 and wiring 371.Altogether
Enjoy contact 362 and can be simultaneously connected with the 3rd active area 330, first gate electrode 351 and wiring 372.
Such as, the semiconductor device 300 of example embodiment may correspond to SRAM.About this
Point, first gate electrode may correspond to shape to the 4th gate electrode (351,352,353 and 354)
Become the semiconductor device 100 of Fig. 1 to Figure 15,100a, 100b, 100c, 100d, 100e,
200, one of grid structure in the first district A in 200a and 200b.First active area is extremely
4th active area (310,320,330 and 340) may correspond to be formed at Fig. 1 to Figure 15
Semiconductor device 100,100a, 100b, 100c, 100d, 100e, 200,200a and
Active area in the Semiconductor substrate of the first district A in 200b or fin.Although it is not shown, but
Be when transistor layout in the surrounding zone of SRAM to apply power or during ground connection, transistor
Gate electrode and active area may correspond to the semiconductor device 100 of Fig. 1 to Figure 15,100a, 100b,
100c, 100d, 100e, 200, grid being formed in the second district B in 200a and 200b
Active area in the Semiconductor substrate of electrode structure and formation the first district A or fin.
Figure 18 and Figure 19 is to be shown respectively to include the semiconductor device according to example embodiment
The block diagram of electronic system 1100 and 1200.
With reference to Figure 18, according to the electronic system 1100 of example embodiment can include controller 1110,
I/O device 1120, memorizer 1130, interface 1140 and bus 1150.Controller 1110,
I/O device 1120, memorizer 1130 and/or interface 1140 can be connected to each other through bus 1150.
Bus 1150 can be that data are by its path sent between elements.
Controller 1110 can include microprocessor, digital signal processor, microcontroller and use
In performing and at least one in the logic device of their intimate function.I/O device
1120 can include keypad, keyboard and display device.Memorizer 1130 can store data and/or
Order.Interface 1140 can send data to communication network or receive data from communication network.
Interface 1140 can be wireline interface or wave point.Such as, interface 1140 can include antenna
Or wire/wireless transceiver.
Although it is not shown, electronic system 1100 may also include as improving controller
Relatively high speed DRAM and/or SRAM of the operation memorizer of the operation of 1110.Example is implemented
The semiconductor device 100 of example, 100a, 100b, 100c, 100d, 100e, 200,200a
May be provided in a memorizer 1130 with at least one in 200b, or as controller
A part for 1110 and/or I/O devices 1120.
Electronic system 1100 can be applicable to personal digital assistant (PDA), portable computer,
Web-tablet, radio telephone, mobile phone, digital music player, storage card or for nothing
Line ground sends and/or any electronic product of the information of reception.
With reference to Figure 19, can be storage card according to the electronic system 1200 of example embodiment.Electronics
System 1200 can include memorizer 1210 and Memory Controller 1220.Memory Controller
1220 can control the data exchange between main frame 2000 and memorizer 1210.Memorizer 1210
With Memory Controller 1220 can include the semiconductor device 100 of example embodiment, 100a,
100b, 100c, 100d, 100e, 200, at least one in 200a and 200b.
Memory Controller 1220 can include SRAM 1221, CPU (CPU) 1222,
HPI 1223, error correcting code (ECC) 1224 and memory interface 1225.SRAM 1221
Can be used as the operation memorizer of CPU 1222.HPI 1223 can include allowing main frame 2000
It is connected to electronic system 1200 and exchanges the agreement of data.ECC 1224 can detect and correct
From the mistake of the data that memorizer 1210 reads.Memory interface 1225 can be with memorizer 1210
Couple, with input and output data.CPU 1222 can perform about Memory Controller 1220
The overall of data exchange control operation.
Figure 20 and Figure 21 is to illustrate to can be applicable to the semiconductor device according to example embodiment
The schematic diagram of example electronic system.
Figure 20 and Figure 21 respectively illustrates flat board PC and notebook.Partly leading of example embodiment
Body device 100,100a, 100b, 100c, 100d, 100e, 200,200a and 200b
In at least one can be used in flat board PC and/or notebook.The semiconductor device of example embodiment
Part 100,100a, 100b, 100c, 100d, 100e, 200, in 200a and 200b extremely
Few one can be applicable to other electronic system unshowned.
Figure 22 A to Figure 22 F is for describing the manufacture Fig. 1 to Fig. 3 according to example embodiment
The sectional view of method of semiconductor device.Describe for convenience, will briefly provide or omit
The description made referring to figs. 1 through Fig. 3.
With reference to Figure 22 A, can be formed in Semiconductor substrate 101 dummy gate structure 110d with
110d1 and distance piece 130a1 and 130b1.
In more detail, sacrifice dielectric film and sacrificial gate can be formed in Semiconductor substrate 101
Pole film, can be patterned with sacrifice gate electrode film sacrificing dielectric film by photoetching process, first
Dummy gate structure 110d may be formed in the first district A, and the second dummy gate structure 110d1 can shape
Become in the second district B.Sacrificing dielectric film can be by the amorphous with relatively great amount of carbon or C-SOH
Carbon-coating (ACL) is formed.Sacrifice gate electrode film to be formed by polysilicon.But, sacrifice dielectric film
It is not limited to these materials with the material sacrificing gate electrode film.
First dummy gate structure 110d and the second dummy gate structure 110d1 can be in second directions
(being perpendicular to the direction of paper) is upper to be extended.First dummy gate structure 110d can include that first is pseudo-
The pseudo-gate electrode 114d of gate insulating film 112d and first.Second dummy gate structure 110d1 can be wrapped
Include the pseudo-gate electrode 114d1 of the second dummy grid dielectric film 112d1 and second.
First dummy gate structure 110d or the first pseudo-gate electrode 114d (x in a first direction
Direction) on can have the first width W1.Second dummy gate structure 110d1 or the second pseudo-grid
Electrode 114d1 can have the second width W2 on (x direction) in a first direction.Such as, first
Width W1 is smaller than 80nm, and the second width W2 can be more than 80nm.Wide by first
When degree W1 and the second width W2 relatively compares, the second width W2 can be more than the first width W1
2 times.
After forming the first dummy gate structure 110d and the second dummy gate structure 110d1,
Spacing body 130a1 and 130b1 may be formed at the first dummy gate structure 110d and the second dummy grid knot
On each two sidewalls in structure 110d1.Distance piece can be formed by following steps
130a1 and 130b1: form the gains covered in Semiconductor substrate 101 equably and (do not show
Go out) dielectric film；By dry etching and/or eat-back from pseudo-gate electrode 114d and 114d1
Dielectric film is removed with the upper surface of Semiconductor substrate 101；And it is retained in pseudo-gate electrode 114d
With the dielectric film on two sidewalls of 114d1.Such as, distance piece 130a1 and 130b1 can shape
Become silicon dioxide film, silicon nitride film or oxygen silicon nitride membrane.
After forming distance piece 130a1 and 130b1, can be by utilizing dummy gate structure 110d
Ion implantation technology is performed as mask with 110d1 and distance piece 130a1 and 130b1, from
And in Semiconductor substrate 101, form impurity range, and such as, source/drain regions 107a and 107b.
Before forming distance piece 130a1 and 130b1, ion implantation technology can be performed slight to be formed
Drain electrode (LDD) district of doping.
With reference to Figure 22 B, can be by forming the insulation of the gains covered in Semiconductor substrate 101
Film and planarize described dielectric film to form interlayer dielectric 120a1 and 120b1.Can pass through
CMP planarization dielectric film.Dummy gate structure 110d can be exposed by planarizing described dielectric film
Upper surface with 110d1.Interlayer dielectric 120a1 and 120b1 can include silicon dioxide film,
At least one in silicon nitride film, oxygen silicon nitride membrane and combinations thereof, and can by have with
The material of the etching selectivity that the etching selectivity of distance piece 130a1 with 130b1 is different is formed.
With reference to Figure 22 C, after forming interlayer dielectric 120a1 and 120b1, removable puppet
Grid structure 110d and 110d1.Can expose by removing dummy gate structure 110d and 110d1
Go out the upper surface Fs of Semiconductor substrate 101.Distance piece 130a1 and 130b1 and interlayer are exhausted
Velum 120a1 and 120b1 can have etching choosing relative to dummy gate structure 110d and 110d1
Selecting property.Therefore, can by such as wet etching be readily removable dummy gate structure 110d and
110d1.Can be by sequentially removing pseudo-gate electrode 114d and 114d1 and dummy grid dielectric film
112d and 112d1 removes dummy gate structure 110d and 110d1.
With reference to Figure 22 D, after removing dummy gate structure 110d and 110d1, can partly lead
Dielectric film 112a' and 112b' for gate insulating film is formed on the gains of body substrate 101
With metal film 114a' and 114b'.The available semiconductor device 100 forming Fig. 1 to Fig. 3
The material of gate insulating film 112a and 112b and method formed for gate insulating film exhausted
Velum 112a' and 112b'.Such as, can be by selected from silicon dioxide film, silicon nitride film, oxygen nitrogen
SiClx film, ONO and dielectric constant are higher than in the high-k dielectric films of the dielectric constant of silicon dioxide film
At least one formed for dielectric film 112a' and 112b' of gate insulating film.
The metal gate electrode 114a of the available semiconductor device 100 forming Fig. 1 to Fig. 3 and
The material of 114b and method form metal film 114a' and 114b'.Metal film 114a' and
114b' is formed as a metal film, but may also comprise at least two metal film.Such as,
Metal film 114a' and 114b' can include potential barrier metal film and electrode metal film.Metal film 114a'
Can include that work function adjusts film with 114b'.
With reference to Figure 22 E, after forming metal film 114a' and 114b', first can be performed flat
Face metallization processes.The first planarization technology can be performed by a CMP CMP1.In the first plane
Metal film 114a' and 114b' can be only removed during metallization processes.Therefore, at the first plane chemical industry
The polishing agent being only used for etching metal film 114a' and 114b' can be used during skill.In this feelings
Under condition, during the first planarization technology, it is anti-that dielectric film 112a' and 112b' can be used as etching
Only film.
In the first planarization technology, remove only metal film 114a' and 114b', therefore may be used
Whole district is etched equably with same etch speed.Therefore, after the first planarization technology,
The upper surface of the gains retained can have almost identical height.Although it is the most sudden and the most violent in Figure 22 E
Expose dielectric film 112a' and 112b', but can expose after the first planarization technology absolutely
Velum 112a' and 112b'.
With reference to Figure 22 F, after the first planarization technology, the second planarization technology can be performed.
The second planarization technology can be performed by the 2nd CMP CMP2.The second planarization technology can be performed
Till exposing the upper surface of interlayer dielectric 120a and 120b.At the second plane chemical industry
During skill, the most etchable metal film 114a' and 114b' the most etchable dielectric film 112a' and
112b' and the top of interlayer dielectric 120a and 120b.Therefore, at the second plane chemical industry
During skill, can use and etch metal film 114a' and 114b', dielectric film 112a' for jointly
With 112b' and the polishing agent of interlayer dielectric 120a and 120b.
Meanwhile, use the second planarization technology, with by dielectric film 112a' and 112b' from interlayer
Dielectric film 120a and 120b removes, the most generally can use relative to dielectric film 112a' and
The etching speed ratio of 112b' and interlayer dielectric 120a and 120b is relative to metal film
The faster polishing agent of etching speed of 114a' and 114b'.Therefore, at the second planarization technology
Period, the etching speed relative to metal film 114a' and 114b' is than relative to dielectric film
The etching speed of 112a' and 112b' and interlayer dielectric 120a and 120b is slower.
In the second planarization technology, due to the etching relative to metal film 114a' and 114b'
Speed with relative to dielectric film 112a' and 112b' and the erosion of interlayer dielectric 120a and 120b
Carving the difference between speed, the structure of the grid structure 110a of the first district A can be with the second district B
The structure of grid structure 110b different.It is to say, in the first district A, grid structure
110a has narrow width and has little space between which on (x direction) in a first direction,
Although therefore etching speed is different, grid structure 110a and interlayer dielectric 120a also can have
Flat upper surfaces.
Meanwhile, in the second district B, on grid structure 110b (x direction) in a first direction
There is wide degree, and be formed at the interlayer dielectric 120b of the both sides of grid structure 110b
Also having wide degree on (x direction) in a first direction, therefore the difference in terms of etching speed can
It is reflected on grid structure 110b and interlayer dielectric 120b.Therefore, grid structure 110b
Less it is etched than interlayer dielectric 120b.Grid structure 110b and interlayer dielectric
The upper space of 120b smoothly can link together with the upper surface of distance piece 130b.Therefore,
As it can be seen, the upper surface of the grid structure 110b in the second district B can be at core
Height, and can reduce towards marginal portion, the interlayer dielectric 120b's in the second district B is upper
Surface can be the highest in the marginal portion being adjacent to grid structure 110b and can be towards central part
Divide and reduce.
Meanwhile, the first planarization technology and the second planarization technology can use identical polishing agent.
In this case, can jointly use there is the feature described about the second planarization technology
Polishing agent.Therefore, after the second planarization technology, the grid structure 110a of the first district A
Structure and the structure of grid structure 110b of the second district B can be different.
Figure 23 A and Figure 23 B is for describing partly leading of the manufacture Fig. 4 according to example embodiment
The sectional view of the method for body device.Figure 23 A may correspond to Figure 22 C.Figure 23 B may correspond to figure
22D.Describe for convenience, will briefly provide or omit with reference to Fig. 4 and Figure 22 A to Figure 22 F
The description made.
With reference to Figure 23 A, can be as with reference to the formation interlayer dielectric 120a1 described in Figure 22 B
Gate electrode pseudo-with removal after 120b1.But, different from describe with reference to Figure 22 C, can not
Remove dielectric film 112a and 112b in the bottom being formed at pseudo-gate electrode, but retained.
The most removed dielectric film 112a and 112b can later serve as gate insulating film.
In more detail, when forming dummy gate structure 110d and 110d1 in Figure 22 A,
The dielectric film for gate insulating film can be formed and sacrifice dielectric film with replacement.Correspondingly, for grid
The dielectric film of pole dielectric film can be by the gate insulating film with the semiconductor device 100 of Fig. 1 to Fig. 3
The material that the material of 120a with 120b is identical is formed.Forming the insulation for gate insulating film
After film, dummy grid film can be formed, and dummy gate structure 110d can be formed by patterning
And 110d1.As describe with reference to Figure 22 A, dummy grid film can be formed by polysilicon.
With reference to Figure 23 B, after removing pseudo-gate electrode, lower metal film 114a1' and 114b1'
With the gained that upper metal film 116a1' and 116b1' can be sequentially formed at Semiconductor substrate 101
On thing.Form material or the method and the half of formation Fig. 4 of lower metal film 114a1' and 114b1'
Material or the method for lower metal gate electrode 114a1 with 114b1 of conductor device 100a are identical.
The semiconductor device of the material of metal film 116a1' and 116b1' or method and formation Fig. 4 in formation
Material or the method for upper metal gate electrode 116a1 with 116b1 of part 100a are identical.
Then, as describe with reference to Figure 22 E and 22F, can be by performing the first plane
Metallization processes and the second planarization technology manufacture the semiconductor device 100a of Fig. 4.
Figure 24 A to Figure 24 D is for describing partly leading of the manufacture Fig. 8 according to example embodiment
The sectional view of the method for body device.Describe for convenience, will briefly provide or omit with reference to figure
The description that 8 and Figure 22 A to Figure 22 F make.
With reference to Figure 24 A, removing dummy gate structure 110d by the process of Figure 22 A to Figure 22 C
After 110d1, can be sequentially formed for gate insulating film dielectric film 112a5' and
112b5' and first time metal film 113a and 113b.Dielectric film for gate insulating film
112a5' and 112b5' may correspond to the gate insulating film of the semiconductor device 100e of Fig. 8
112a5 and 112b5, correspondingly, formed for gate insulating film dielectric film 112a5' and
The gate insulating film of the semiconductor device 100e of the material of 112b5' or method and formation Fig. 8
Material or the method for 112a5 with 112b5 are identical.Meanwhile, first time metal film 113a and 113b
Under p-type first grid structure 110a5-1 of the semiconductor device 100e that may correspond to Fig. 8
A part of metal gate electrode 114a5-1.Such as, first time metal film 113a and 113b
Can be used as p-type work function and adjust film.
After forming first time metal film 113a and 113b, covering the second district B can be formed
Mask layer 210 with the part by forming p-type first grid structure in the first district A.If
The second grid structure of the second district B is formed as N-shaped, then mask layer 210 can be not formed in second
On district B.Mask layer 210 can by photoresist (PR) patterning is formed by PR or
Person is formed by layers of additional materials.
With reference to Figure 24 B, first time gold can be removed by utilizing mask layer 210 as etching mask
Belong to the part that film 113a exposes in the first district A.In more detail, removable first time gold
Belong to the part corresponding with the part that will form N-shaped first grid structure of film 113a.Removing
After a part of first time metal film 113a of the first district A, removable mask layer 210.
By removing mask layer 210, it can be seen that remain in the second district B and the first district A and formed
First time metal film 113a' and 113b' in the part of p-type first grid structure.
With reference to Figure 24 C, after removing a part of first time metal film 113a, second time
Metal film 114a5' and 114b5' may be formed on the gains of Semiconductor substrate 101.With
Second time metal film 114a5' of the part that the N-shaped first grid structure of one district A is corresponding can structure
Become the lower metal gate electrode 114a5 of the semiconductor device 100e of Fig. 8.P with the first district A
The of second time metal film 114a5' and the second district B of the part that type first grid structure is corresponding
Two times metal film 114b5' can together with first time metal film 113a' and 113b' pie graph 8
Lower metal gate electrode 114a5-1 and 114b5-1 of semiconductor device 100e.Correspondingly, shape
The material or the method that become second time metal film 114a5' and 114b5' can be with the semiconductor devices of Fig. 8
The material of lower metal gate electrode 114a5,114a5-1 and 114b5-1 of part 100e or method phase
With.Second time metal film 114a5' can be used as common work function in the first district A and adjust film.
First time metal film 113a' of the first district A and the portion corresponding with p-type first grid structure
The second time metal film 114a5' divided and first time metal film 113b' and second of the second district B
Lower metal film 114b5' will be indicated as a monomer film, and is referred to as below combining second time
Metal film 114a5-1' and 114b5-1'.
With reference to Figure 24 D.After forming second time metal film 114a5' and 114b5', it is used for
Metal film 116a5' and 116b5' and upper metal film 118a5' and 118b5' of potential barrier metal film
Can be sequentially formed on the gains of Semiconductor substrate 101.Metal for potential barrier metal film
Film 116a5' and 116b5' may correspond to the potential barrier metal film of the semiconductor device 100e of Fig. 8
116a5 and 116b5.Upper metal film 118a5' and 118b5' may correspond to the semiconductor device of Fig. 8
Upper metal gate electrode 118a5 and 118b5 of part 100e.Correspondingly, formed for potential barrier gold
Belong to metal film 116a5' and 116b5' and the material of upper metal film 118a5' and 118b5' of film
Or potential barrier metal film 116a5 and 116b5 of the semiconductor device 100e of method and formation Fig. 8
And the material of upper metal film 118a5 with 118b5 or method identical.
Meanwhile, second time metal film 114a5-1' of associating may be formed at and the p-type of the first district A
In the part that first grid structure is corresponding and thicker than second time metal film 114a5'.
Therefore, in the groove in the part corresponding with the p-type first grid structure of the first district A, can
Second time metal film 114a5-1' of associating is only formed the metal film for potential barrier metal film
116a5'.In other words, metal film 118a5' can be formed without in the trench.
Then, as describe with reference to Figure 22 E and 22F, can be by performing the first plane
Metallization processes and the second planarization technology manufacture the semiconductor device 100e of Fig. 8.
Figure 25 A to Figure 25 G and Figure 26 A to Figure 26 G is for describing according to example embodiment
The sectional view of method of semiconductor device of manufacture Fig. 9 to Figure 12.Figure 25 A to Figure 25 G
Correspond to the sectional view of the sectional view of the line II-II' intercepting of the semiconductor device along Fig. 9.
Figure 26 A to Figure 26 G correspond to the semiconductor device along Fig. 9 line III-III' and
The sectional view of the sectional view that IV-IV' intercepts.Describe for convenience, will briefly provide or omit
The description made with reference to Fig. 9 to Figure 12 and Figure 22 A to Figure 22 F.
With reference to Figure 26 A, by etching the top of Semiconductor substrate 201, can be at the first district A
First time fin 240a-1 of middle formation, and second time fin 240b-1 can be formed in the second district B.
First time fin 240a-1 and second time fin 240b-1 can be in first party in Semiconductor substrate 201
To (being perpendicular to the direction of paper) upper extension.To Semiconductor substrate 201 and first time fin
The description of 240a-1 and second time fin 240b-1 and the semiconductor device 200 of Fig. 9 to Figure 12
Those are identical.
With reference to Figure 26 B, after forming first time fin 240a-1 and second time fin 240b-1,
The first device isolation film of the bottom of two side surfaces covering first time fin 240a-1 can be formed
Second device isolation film of the bottom of two side surfaces of 250a and second time fin 240b-1 of covering
250b.It is formed as described above the first device isolation film 250a and the second device isolation film 250b,
Therefore the top of first time fin 240a-1 and second time fin 240b-1 can be from the first device isolation film
250a and the second device isolation film 250b highlights.
The first device isolation film 250a and the second device isolation film can be formed by following steps
250b: form the dielectric film of the gains covering Semiconductor substrate 201 and planarized；With
And remove the top of the first device isolation film 250a and the second device isolation film 250b so that the
Once the top of fin 240a-1 and second time fin 240b-1 can highlight.To the first device isolation film
The description of the material of 250a and the second device isolation film 250b and the quasiconductor of Fig. 9 to Figure 12
Those of device 200 are identical.
With reference to Figure 25 A and Figure 26 C, forming the first device isolation film 250a and the second device
After isolating membrane 250b, dummy gate structure 210d and 210d1 can be formed, and can be at pseudo-grid
Two side surfaces of electrode structure 210d and 210d1 formed the first interlayer dielectric 220a0 and
220b0.Formed dummy gate structure 210d and 210d1 and the first interlayer dielectric 220a0 and
Processing of 220b0 is identical with describe with reference to Figure 22 A and Figure 22 B.But, owing to defining
Surround two side surfaces of first time fin 240a-1 and second time fin 240b-1 bottom first
Device isolation film 250a and the second device isolation film 250b, therefore dummy gate structure 210d and
210d1 and the first interlayer dielectric 220a0 and 220b0 can be at the first device isolation film 250a
With encirclement first time fin 240a-1 and second time fin 240b-1 on the second device isolation film 250b
Upper surface and side surface.
Meanwhile, dummy gate structure 210d and 210d1 such as can be in second direction (y directions)
Upper extension.Distance piece 230a1 and 230b1 may be formed at dummy gate structure 210d and 210d1
And between the first interlayer dielectric 220a0 and 220b0.
With reference to Figure 25 B, can be by utilizing dummy gate structure 210d and 210d1 and distance piece
230a1 and 230b1 removes the first interlayer dielectric 220a0 and 220b0 as mask.Also may be used
Remove the first time fin 240a-1 exposed by the first interlayer dielectric 220a0 and 220b0 and
The top of second time fin 240b-1.Can be by first time fin 240a-1 and second time fin 240b-1
Corresponding to the first device isolation film 250a and the position of the upper surface of the second device isolation film 250b
Put those above parts to remove.
Then, can be by raw from remaining first fin 240a-1 and second time fin 240b-1
Long epitaxial layer forms on first fin 240b-2 on fin 240a-2 and second.First time fin
The first fin 240a during fin 240a-2 may make up the first district A on 240a-1 and first.Second time
The second fin 240b during fin 240b-2 may make up the second district B on fin 240b-1 and second.
As it can be seen, on fin 240a-2 and second, the upper surface of fin 240b-2 is comparable on first
First time fin 240a-1 of the bottom of dummy gate structure 210d and 210d1 and second time fin
The upper surface of 240b-1 is higher.On first, on fin 240a-2 and second, fin 240b-2 can cover
A part for the bottom of distance piece 230a1 and 230b1.
With reference to Figure 25 C, in formation first on fin 240a-2 and second after fin 240b-2,
The second interlayer dielectric 220a1 and 220b1 can be formed: formed to cover and partly lead by following steps
The dielectric film of the gains of body substrate 201 is also planarized.Second interlayer dielectric 220a1
The second interlayer dielectric of the semiconductor device 200 of Fig. 9 to Figure 12 is may correspond to 220b1
220a and 220b.Correspondingly, the material of the second interlayer dielectric 220a1 and 220b1 can be with
That of second interlayer dielectric 220a and 220b of the semiconductor device 200 of Fig. 9 to Figure 12
The most identical.
With reference to Figure 25 D and Figure 26 D, forming the second interlayer dielectric 220a1 and 220b1
Afterwards, as describe with reference to Figure 22 C, removable dummy gate structure 210d and 210d1.
As shown in fig. 26d, first time can be exposed by removing dummy gate structure 210d and 210d1
Fin 240a-1 and the upper surface of second time fin 240b-1 and a part for side surface.
Though it addition, not shown in Figure 26 D, remove dummy gate structure 210d and
After 210d1, distance piece 230a1 and 230b1 can be regarded as first time fin 240a-1 and
The upper surface of second time fin 240b-1 and the outside of side surface.
With reference to Figure 25 E and Figure 26 E, after removing dummy gate structure 210d and 210d1,
Dielectric film 212a' and 212b', lower metal film 214a' and 214b' for gate insulating film
And upper metal film 216a' and 216b' can be sequentially formed at the gained of Semiconductor substrate 201
On thing.For dielectric film 212a' and 212b' of gate insulating film, lower metal film 214a' and
214b' and upper metal film 216a' and 216b' can correspond respectively to partly leading of Fig. 9 to Figure 12
Gate insulating film 212a and 212b of body device 200, lower metal gate electrode 214a and 214b
With upper metal gate electrode 216a and 216b.Correspondingly, for the dielectric film of gate insulating film
212a' and 212b', lower metal film 214a' and 214b' and upper metal film 216a' and 216b'
Material or function with reference to Fig. 9 semiconductor device 200 describe identical.
With reference to Figure 25 F and Figure 26 F, formed for gate insulating film dielectric film 212a' and
After 212b', lower metal film 214a' and 214b' and upper metal film 216a' and 216b',
The first planarization technology can be performed.The first planarization technology can be performed by a CMP CMP1.
First planarization technology can be similar to the first planarization technology described with reference to Figure 22 E.In more detail
Ground is said, during the first planarization technology, can use be only used for etching lower metal film 214a' with
214b' and the polishing agent of upper metal film 216a' and 216b'.Insulation for gate insulating film
Film 212a' and 212b' can be used as etching in the first planarization technology and prevent film.
In the first planarization technology, can only etch lower metal film 214a' and 214b' and on
Metal film 216a' and 216b', therefore can etch whole district according to same etch speed equably.
Therefore, after the first planarization technology, the upper surface of remaining gains can have almost identical
Height.
With reference to Figure 25 G and Figure 26 G, after the first planarization technology, the second plane can be performed
Metallization processes.The second planarization technology can be performed by the 2nd CMP CMP2.Second can be performed flat
Face metallization processes is till exposing the upper surface of the second interlayer dielectric 220a and 220b.The
Two planarization technologies can be similar to the second planarization technology described with reference to Figure 22 F.
In more detail, during the second planarization technology, the most etchable lower metal film
214a' and 214b' and upper metal film 216a' and 216b', the most etchable for gate insulator
Dielectric film 212a' and 212b' and interlayer dielectric 220a and 220b of film.Therefore, exist
During second planarization technology, can use for jointly etch lower metal film 214a' and
214b', upper metal film 216a' and 216b', for gate insulating film dielectric film 212a' and
212b' and the polishing agent of interlayer dielectric 220a and 220b.
Meanwhile, as described in second planarization technology of Figure 22 F, in the second plane
After metallization processes, the structure of the grid structure 210a of the first district A can be with the grid of the second district B
The structure of structure 210b is different.It is to say, in the first district A, grid structure 210a
Identical height and smooth can be had with the upper surface of interlayer dielectric 220a.Second district B's
The upper surface of grid structure 210b can be the highest at core, and can drop towards marginal portion
Low, the upper surface of the interlayer dielectric 220b in the second district B can be adjacent to grid structure
The marginal portion of 210b is the highest, and can reduce towards core.
Although the example embodiment with reference to present inventive concept specifically illustrates and describes this
Bright design, it should be appreciated that, in the case of without departing from spirit and scope by the claims,
Can various changes in form and detail may be made therein.Therefore, the real technology scope of present inventive concept
Even if being limited by the spirit of claim.
Claims (25)
1. a semiconductor device, including:
At least one first grid structure in Semiconductor substrate, at least one first grid described
Electrode structure has a flat upper surfaces extended in a first direction, and has and be perpendicular to first
The first width in the second direction in direction；And
At least one second grid structure in Semiconductor substrate, at least one second gate described
Electrode structure has the convex upper surface extended in a first direction, and has in a second direction
Second width, described second width is more than described first width.
Semiconductor device the most according to claim 1, wherein, described at least one
The upper surface of two grid structures height on third direction in central part office than described extremely
Few second grid structure edge part office in a second direction is higher.
Semiconductor device the most according to claim 1, also includes:
Interlayer dielectric in Semiconductor substrate, described interlayer dielectric is the most adjacent
It is bordering on the side surface of at least one second grid structure described,
Wherein, the upper surface of described interlayer dielectric height on third direction is along with
Subtract with the increase of the distance of the side surface of at least one second grid structure described on two directions
Little.
Semiconductor device the most according to claim 1, also includes:
Distance piece, the side surface of its encirclement at least one second grid structure described,
Wherein, the upper surface of at least one second grid structure described height on third direction
Spend more neighbouring than at least one second grid structure described in central part office
At the side surface of described distance piece higher, and
Wherein, the upper surface of described distance piece height on third direction is along with in second party
Upwards persistently subtract with the increase of the distance of the side surface of at least one second grid structure described
Little.
Semiconductor device the most according to claim 1, wherein, described at least one
Second width of two grid structures is the first width of at least one first grid structure described
At least twice.
Semiconductor device the most according to claim 1, wherein, described at least one
One grid structure is multiple first grid structures located adjacent one another, and described semiconductor device also includes:
Interlayer dielectric, it is positioned at located adjacent one another in the plurality of first grid structure two
Between first grid structure, the flat upper surfaces of described interlayer dielectric and the said two first grid
The upper surface of electrode structure is in the same plane.
Semiconductor device the most according to claim 1, also includes:
Interlayer dielectric in Semiconductor substrate, at least one first grid structure described and institute
State the groove in interlayer dielectric described at least one second grid structure filling,
Wherein, at least one first grid structure described include first grid dielectric film and
The first metal gate electrode film on described first grid dielectric film, and described at least one second
Grid structure include second grid dielectric film and on described second grid dielectric film second
Metal gate electrode film, and
Wherein, the upper surface of described first metal gate electrode film is smooth, described second gold medal
The upper surface belonging to gate electrode film is convex.
Semiconductor device the most according to claim 1, also includes:
At least one fin, it is prominent from Semiconductor substrate, and at least one fin described is being perpendicular to
The second party of first direction upwardly extends,
Wherein, at least one first grid structure described and at least one second grid described knot
Structure extends to cover a part at least one fin described.
Semiconductor device the most according to claim 8, also includes:
Interlayer dielectric, it is adjacent to the side surface of at least one second grid structure described, and
And cover the portion not covered by least one second grid structure described of at least one fin described
Point,
Wherein, the upper surface of at least one second grid structure described height on third direction
Spend more neighbouring than at least one second grid structure described in central part office
At the side surface of described interlayer dielectric higher, and
Wherein, the upper surface of described interlayer dielectric along with in a second direction with described at least
The increase of the distance of the side surface of one second grid structure and reduce.
Semiconductor device the most according to claim 8, wherein, described at least one
First grid structure is multiple first grid structures located adjacent one another, and described semiconductor device also wraps
Include:
Interlayer dielectric, it is adjacent to the side surface of the plurality of first grid structure, and covers
The part not covered by the plurality of first grid structure of lid at least one fin described,
The flat upper surfaces of described interlayer dielectric and two in the plurality of first grid structure
The upper surface of individual neighbouring first grid structure is in the same plane.
11. semiconductor device according to claim 8, wherein, described at least one
The transistor in first grid constituent unit district, at least one second grid structure described is constituted
The transistor of one of logic area and surrounding zone.
12. 1 kinds of semiconductor device, including:
Semiconductor substrate, which defines the firstth district and the secondth district；
At least the first fin and the second fin, it highlights from described Semiconductor substrate, and described at least the
One fin and the second fin extend in a first direction；
At least one first grid structure, it is positioned in the firstth district of described Semiconductor substrate,
And cover upper surface and the side surface of described first fin, at least one first grid structure described
There is the flat upper surfaces extended in a second direction perpendicular to the first direction and have
The first width on first direction；And
At least one second grid structure, it is positioned in the secondth district of described Semiconductor substrate,
And cover upper surface and the side surface of described second fin, at least one second grid structure described
There is the convex upper surface extended in a second direction perpendicular to the first direction and have
The second width more than described first width on one direction.
13. semiconductor device according to claim 12, wherein, described at least one
The upper surface of second grid structure height on third direction at central part office ratio described
At least one second grid structure edge part office in a first direction is higher.
14. semiconductor device according to claim 12, also include:
Interlayer dielectric, it is adjacent to the side surface of at least one second grid structure described, institute
State interlayer dielectric and cover described Semiconductor substrate and described second fin,
Wherein, the upper surface of at least one second grid structure described height on third direction
Degree in central part office than at least one second grid structure described in a first direction towards
Described interlayer dielectric is higher at the side surface with neighbouring described interlayer dielectric, and
Wherein, the upper surface of described interlayer dielectric height on third direction is along with
Subtract with the increase of the distance of the side surface of at least one second grid structure described on one direction
Little.
15. semiconductor device according to claim 12, wherein, described at least one
First grid structure is multiple first grid structures located adjacent one another, and described semiconductor device also wraps
Include:
Interlayer dielectric, it is adjacent to the side surface of the plurality of first grid structure, and covers
Cover the part not covered by the plurality of first grid structure of described first fin,
The flat upper surfaces of described interlayer dielectric and two in the plurality of first grid structure
The upper surface of individual neighbouring first grid structure is in the same plane.
16. 1 kinds of methods manufacturing semiconductor device, described method includes step:
Form the multiple dummy gate structure extended in a first direction, institute on a semiconductor substrate
State each in multiple dummy gate structure and include dummy grid dielectric film and pseudo-gate electrode；
The sidewall of the plurality of dummy gate structure is formed distance piece；
Form the interlayer dielectric covering described Semiconductor substrate；
Described interlayer dielectric is planarized, so that the upper table of the plurality of dummy gate structure
Come out in face；
Remove the plurality of dummy gate structure；
First is formed on described interlayer dielectric and in a part for described Semiconductor substrate
Dielectric film and metal film；And
By described first dielectric film and described metal film are planarized to expose described interlayer
The upper surface of dielectric film forms multiple grid structure, each in the plurality of grid structure
Including gate insulating film and metal gate electrode, the plurality of grid structure includes:
At least one first grid structure, it has a flat upper surfaces, described at least one
First grid structure has the first width in a second direction perpendicular to the first direction, and
At least one second grid structure, it has a convex upper surface, described at least one
Two grid structures have the second width more than described first width in a second direction.
17. methods according to claim 16, wherein,
Form the step of multiple grid structure by the first planarization technology and the second plane chemical industry
Described first dielectric film and described metal film are planarized by skill,
Wherein, in the first planarization technology, described metal film is planarized, and
Wherein, exhausted by etching described metal film and described interlayer in the second planarization technology
The metal film of at least one second grid structure described is planarized to protrude by velum.
18. methods according to claim 16, wherein, form multiple first grid knot
The step of structure defines the flat upper surfaces of described interlayer dielectric, and this flat upper surfaces is with described
The upper surface of two neighbouring first grid structures in multiple first grid structures is same flat
In face.
19. 1 kinds of methods manufacturing semiconductor device, described method includes step:
A part for etching Semiconductor substrate is to form groove；
The raised structures highlighted from described Semiconductor substrate, described projection is formed between groove
Structure extends in a first direction；
By a part of fill insulant of groove is formed device isolation film；
Form at least one fin on top corresponding to raised structures, at least one fin described from
Described device isolation film highlights；And
Formed and cover described Semiconductor substrate, described device isolation film and at least one fin described
Multiple grid structures of a part, the plurality of grid structure is being perpendicular to the of first direction
Two sides upwardly extend, and each in the plurality of grid structure include gate insulating film and
Metal gate electrode, the plurality of grid structure includes:
At least one first grid structure, it has a flat upper surfaces, and described at least one
Individual first grid structure has the first width in a first direction, and
At least one second grid structure, it has a convex upper surface, described at least one
Second grid structure has the second width more than the first width in a first direction.
20. methods according to claim 19, wherein, form multiple grid structure
Step includes:
Formed extend in a second direction and cover described Semiconductor substrate, described device every
From multiple dummy gate structure of a part for film and at least one fin described, the plurality of dummy grid
Each in structure includes dummy grid dielectric film and pseudo-gate electrode；
The side surface of the plurality of dummy gate structure is formed distance piece；
Form the interlayer dielectric covering described Semiconductor substrate；
Described interlayer dielectric is planarized, so that the upper table of the plurality of dummy gate structure
Come out in face；
Remove the plurality of dummy gate structure；
The part eliminating the plurality of dummy gate structure of described Semiconductor substrate is formed
First dielectric film and metal film；And
Described first dielectric film and described metal film are planarized, so that described layer insulation
The upper surface of film comes out.
21. 1 kinds of semiconductor device, including:
Semiconductor substrate, it includes the firstth district and the secondth district；And
At least two grid structure in described Semiconductor substrate, described at least two grid is tied
Structure includes:
At least one first grid structure in described firstth district, described at least one
One grid structure has a flat upper surfaces extended in a first direction, and has and be perpendicular to
The first width in the second direction of first direction, and
Second grid structure in described secondth district, described second grid structure has
The upwardly extending convex upper surface of first party, and there is the second width in a second direction, institute
State at least twice that the second width is described first width.
22. semiconductor device according to claim 21, wherein, described second grid
The upper surface of structure height on third direction at central part office ratio at described second grid
Structure edge part office in a second direction is higher.
23. semiconductor device according to claim 21, wherein,
Second width of described second grid structure is at least 80nm, and
First width of at least one first grid structure described is less than 80nm.
24. semiconductor device according to claim 21, also include:
Interlayer dielectric in described Semiconductor substrate, described interlayer dielectric is in second direction
On be adjacent to the side surface of described second grid structure,
Wherein, the upper surface of described interlayer dielectric height on third direction is along with
Reduce with the increase of the distance of the side surface of described second grid structure on two directions.
25. semiconductor device according to claim 21, also include:
Distance piece, the side surface of its described second grid structure of encirclement,
Wherein, the upper surface of described second grid structure height on third direction is at center
Than in described second grid structure in a second direction adjacent to the side table of described distance piece at Bu Fen
At face higher, and
Wherein, the upper surface of described distance piece height on third direction is along with in second party
Upwards persistently reduce with the increase of the distance of the side surface of described second grid structure.
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| KR10-2015-0036761 | 2015-03-17 | ||
| KR1020150036761A KR102306674B1 (en) | 2015-03-17 | 2015-03-17 | Semiconductor device and method for manufacturing the same |
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Also Published As
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| US10177144B2 (en) | 2019-01-08 |
| US20160276485A1 (en) | 2016-09-22 |
| CN105990232B (en) | 2021-04-23 |
| US9614090B2 (en) | 2017-04-04 |
| KR102306674B1 (en) | 2021-09-29 |
| KR20160111725A (en) | 2016-09-27 |
| US20170179124A1 (en) | 2017-06-22 |
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