CN105988079A - System and method for testing power consumption of integrated circuit - Google Patents
System and method for testing power consumption of integrated circuit Download PDFInfo
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- CN105988079A CN105988079A CN201510091782.9A CN201510091782A CN105988079A CN 105988079 A CN105988079 A CN 105988079A CN 201510091782 A CN201510091782 A CN 201510091782A CN 105988079 A CN105988079 A CN 105988079A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
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Abstract
The invention discloses a system for testing power consumption of an integrated circuit. The system comprises: an upper computer, a power consumption test board and an integrated circuit test board, wherein the upper computer is used for setting voltage data of the tested integrated circuit and data of a plurality of working scenarios; the power consumption test board is used for outputting voltage to the integrated circuit test board according to the voltage data and outputting the data of the plurality of working scenarios to the integrated circuit test board, and is further used for synchronously acquiring current data of the tested integrated circuit under each of the working scenarios and calculating power consumption data of the tested integrated circuit under each of the working scenarios; and the integrated circuit test board is used for successively testing each working scenario according to the data of the plurality of working scenarios, and outputting data of each of the working scenarios to the power consumption test board at a moment when each of the working scenarios starts. The invention further discloses a method for testing power consumption of the integrated circuit.
Description
Technical field
The present invention relates to ic test technique, particularly relate to a kind of IC power consumption test system and side
Method.
Background technology
In existing IC power consumption measuring technology, a kind of power consumption test method includes: use milliohm level
Resistant series, on power path, uses circuit tester test both end voltage to carry out electric current and power consumption calculation subsequently；
The defect of this method is: the work using the method for manual measurement to cause is numerous and diverse, is readily incorporated people simultaneously
For error.Another kind of power consumption test method is: uses digital voltage source and ammeter to coordinate and builds test automatically
System；This method is used for system test, and the method has a problem in that: due to the power supply electricity of integrated circuit
Pressure kind is more, so needing to use a lot of voltmeter, ammeter and numerous and complicated mixed and disorderly wiring, thus leads
Cause the raising of testing cost.Additionally, a kind of power consumption test method is: in use prior art only
One a DC source analyser, to realize supply and the current detecting of four-way power supply；But, this method
There is also that passage is limited, function is fixed, expensive and interface does not mate the problems such as the connection caused is mixed and disorderly；
Further, the number mutual with equipment under test (DUT, Device Under Test) is lacked due to this method
According to passage, it is thus impossible to integrated circuit operation scene is connected with power consumption, and then can not be automatically performed
Power consumption test under various integrated circuit operation scenes.
In consideration of it, the power consumption test how integrated circuit carries out under multiple operative scenario automatization has become
For the technical problem that association area is urgently to be resolved hurrily.
Summary of the invention
In view of this, embodiment of the present invention expectation provides a kind of IC power consumption test system and method, energy
The problem enough solving, under multiple operative scenario, integrated circuit is carried out automatization's power consumption test.
For reaching above-mentioned purpose, the technical scheme of the embodiment of the present invention is achieved in that
Embodiments provide a kind of IC power consumption test system, including: host computer, power consumption are surveyed
Test plate (panel) and integrated circuit testing plate；Wherein,
Described host computer, for arranging the voltage data of tested integrated circuit and multiple operative scenario data, and
Export described voltage data and the plurality of operative scenario data to described power consumption test plate；
Described power consumption test plate, is used for receiving described voltage data and the plurality of operative scenario data, according to
Described voltage data output voltage is to described integrated circuit testing plate, and exports the plurality of operative scenario data
To described integrated circuit testing plate；It is additionally operable to receive each operative scenario from described integrated circuit testing plate
The current data of tested integrated circuit under data, and each operative scenario described in synchronous acquisition, according to described electricity
Pressure data and described current data calculate the power consumption data of tested integrated circuit under described each operative scenario；
Described integrated circuit testing plate, is used for receiving described voltage and the plurality of operative scenario data, according to
Each operative scenario is tested by the plurality of operative scenario data successively, and in described each operative scenario
The moment started exports described each operative scenario data to described power consumption test plate.
In such scheme, described power consumption test plate includes:
Central processing unit, is used for receiving described voltage data and the plurality of operative scenario data, and output
Under described each operative scenario data and described each operative scenario, the power consumption data of tested integrated circuit is to described
Host computer；
Field programmable gate array, is used for exporting the plurality of operative scenario data to described integrated circuit testing
Plate, receives the described each operative scenario data from described integrated circuit testing plate, and according to described electricity
Pressure data and described current data calculate the power consumption data of tested integrated circuit under described each operative scenario；
Programmable power supply chip, surveys to described integrated circuit for exporting described voltage according to described voltage data
Test plate (panel)；
Current sampling circuit, the electric current number of tested integrated circuit under operative scenario each described in synchronous acquisition
According to.
In such scheme, described power consumption test plate be additionally operable to storage and show described each operative scenario data and
The power consumption data of tested integrated circuit under described each operative scenario, and export described each operative scenario data
With the power consumption data of tested integrated circuit under described each operative scenario to described host computer.
In such scheme, described power consumption test plate also includes:
Memorizer, is used for storing under described each operative scenario data and described each operative scenario tested integrated
The power consumption data of circuit；
Liquid crystal display, is used for showing under described each operative scenario data and described each operative scenario tested
The power consumption data of integrated circuit.
In such scheme, described integrated circuit testing plate includes:
Electric source line interface, for receiving the described voltage from described power consumption test plate；
Tested integrated circuit, for receiving the plurality of operative scenario data from described power consumption test plate,
Successively each operative scenario is tested according to the plurality of operative scenario data, and in described each work
The moment that scene starts exports described each operative scenario data to described power consumption test plate.
In such scheme, described host computer is additionally operable to receive the described each work from described power consumption test plate
Under contextual data and described each operative scenario, the power consumption data of tested integrated circuit, generates described each work
The power consumption situation report of scene and change of power consumption curve.
The embodiment of the present invention additionally provides a kind of IC power consumption method of testing, including: arrange tested integrated
The voltage data of circuit and multiple operative scenario data；Described method also includes:
Power consumption test plate receives according to described voltage data output voltage to integrated circuit testing plate, and exports institute
State multiple operative scenario data to described integrated circuit testing plate；
Each operative scenario is carried out successively by described integrated circuit testing buttress according to the plurality of operative scenario data
Test, and export described each operative scenario data to described merit in the moment that described each operative scenario starts
Consumption test board；
The current data of tested integrated circuit under each operative scenario described in described power consumption test plate synchronous acquisition,
The merit of tested integrated circuit under described each operative scenario is calculated according to described voltage data and described current data
Consumption data.
In such scheme, also include:
Described power consumption test plate stores and shows under described each operative scenario data and described each operative scenario
The power consumption data of tested integrated circuit, and export described each operative scenario data and described each operative scenario
Under the power consumption data of tested integrated circuit to host computer.
In such scheme, also include:
Described host computer receives from described each operative scenario data of described power consumption test plate and described each
The power consumption data of tested integrated circuit under operative scenario, generates the power consumption situation report of described each operative scenario
With change of power consumption curve.
The IC power consumption test system and method that the embodiment of the present invention is provided, arranges tested integrated circuit
Voltage data and multiple operative scenario data；Power consumption test buttress is according to described voltage data output voltage extremely collection
Become circuit test plate, and export the plurality of operative scenario data to described integrated circuit testing plate；Described collection
Circuit test buttress is become successively each operative scenario to be tested according to the plurality of operative scenario data, and
The moment that described each operative scenario starts exports described each operative scenario data to described power consumption test plate；
The current data of tested integrated circuit under each operative scenario described in described power consumption test plate synchronous acquisition, and count
Calculate the power consumption data of tested integrated circuit under described each operative scenario.
So, the embodiment of the present invention makes IC power consumption test break away from the miscellaneous work amount of manual measurement,
Thus reduce the error of hand dipping.Simultaneously as need not use multiple stage instrument to build complication system,
Also without the wiring of mixed and disorderly complexity, so, the passage that can overcome current DC source analyser is limited,
Function fixes, the expensive problem such as do not mate with interface.Additionally, the embodiment of the present invention can also be the completeest
Become the power consumption test under multiple operative scenario.
Accompanying drawing explanation
The IC power consumption test system composition structural representation that Fig. 1 provides for the embodiment of the present invention；
The IC power consumption method of testing that Fig. 2 provides for the embodiment of the present invention realizes schematic flow sheet.
Detailed description of the invention
In embodiments of the present invention, the voltage data of tested integrated circuit and multiple operative scenario data are first set；
Power consumption test buttress to integrated circuit testing plate, and exports the plurality of work according to described voltage data output voltage
Make contextual data to described integrated circuit testing plate；Described integrated circuit testing buttress is according to the plurality of yard
Each operative scenario is tested by scape data successively, and in the moment output that described each operative scenario starts
Described each operative scenario data are to described power consumption test plate；Described in described power consumption test plate synchronous acquisition each
The current data of tested integrated circuit under operative scenario, and calculate tested integrated electricity under described each operative scenario
The power consumption data on road.
Here, the described voltage data arranging tested integrated circuit and multiple operative scenario data can be by host computers
Complete, and, after being provided with, host computer can be by described voltage data and the plurality of operative scenario data
Output is to power consumption test plate.
Further, after described power consumption test plate calculates power consumption data, can store and show described each
The power consumption data of tested integrated circuit under operative scenario data and described each operative scenario；And can be to described
Host computer exports the power consumption of tested integrated circuit under described each operative scenario data and described each operative scenario
Data.
Below in conjunction with the accompanying drawings and the present invention is further described in detail by specific embodiment again.
Embodiment one
The IC power consumption test system composition structural representation that Fig. 1 provides for the embodiment of the present invention, such as figure
Shown in 1, described IC power consumption test system includes: host computer 110, power consumption test plate 120 and integrated
Circuit test plate 130.
Wherein, described host computer 110, for arranging the voltage data of tested integrated circuit and multiple yard
Scape data, and export described voltage data and the plurality of operative scenario data to power consumption test plate 120.
Specifically, each circuit institute during described host computer 110 uses upper software design patterns integrated circuit testing plate
Voltage data, dynamic voltage regulation data and the electric sequence needed.Described voltage data includes described integrated electricity
The voltage of tested integrated circuit and the voltage of other circuit in drive test test plate (panel) 130.Meanwhile, described host computer 110
Use multiple operative scenario data of the tested integrated circuit of upper software design patterns.Described operative scenario data are permissible
Including: the call contextual data of mobile phone and standby contextual data.
Secondly, described host computer 110 also uses testing time and the merit of power consumption under each scene of upper software design patterns
The sample frequency of consumption data.
After accomplishing the setting up, described host computer 110 arranges data and power consumption test by described to start order the most defeated
Go out to described power consumption test plate 120.
Additionally, during power consumption test, described host computer 110 is additionally operable to receive from described power consumption test
The power consumption figure of tested integrated circuit under described each operative scenario data of plate 120 and described each operative scenario
According to rear, generate power consumption situation report and the change of power consumption curve of described each operative scenario.
It should be noted that described each operative scenario can carry out the test of a period of time, period will produce
A large amount of described power consumption data.
Here, described host computer 110 can be personal computer (PC, Personal Computer).
Described power consumption test plate 120, for receiving the described voltage data from described host computer 110 and institute
After stating multiple operative scenario data, according to described voltage data output voltage to described integrated circuit testing plate
130, and export the plurality of operative scenario data to described integrated circuit testing plate 130；It is additionally operable to receive
From described each operative scenario data of described integrated circuit testing plate 130, and each work described in synchronous acquisition
Make the current data of tested integrated circuit under scene, calculate institute according to described voltage data and described current data
State the power consumption data of tested integrated circuit under each operative scenario.
Further, described power consumption test plate 120 is additionally operable to storage and shows described each operative scenario data
With the power consumption data of tested integrated circuit under described each operative scenario, and export described each operative scenario number
According to the power consumption data of tested integrated circuit under described each operative scenario to described host computer 110.
Specifically, described power consumption test plate 120 includes:
Central processing unit (CPU, Central Processing Unit) 121, for receiving from described upper
The described voltage data of machine 110 and the plurality of operative scenario data, and export described each operative scenario number
According to the power consumption data of tested integrated circuit under described each operative scenario to described host computer 110.
First, described CPU121 receives the institute from described host computer 110 by the RS-232 interface of peripheral hardware
State voltage data, the plurality of operative scenario data and described power consumption test and start order.Described CPU121
After resolving described power consumption test startup order, generation control signal output to field programmable gate array (FPGA,
Field Programmable Gate Array)122.Meanwhile, described CPU121 export described voltage data and
The plurality of operative scenario data extremely described FPGA122.
During described power consumption test, described CPU121 receives the marking signal from described FPGA122
After, start quilt under the described each operative scenario data and described each operative scenario read in memorizer 125
Survey the power consumption data of integrated circuit, and export described power consumption data on the most described by the Ethernet interface of peripheral hardware
Position machine 110, and export described each operative scenario data to described host computer 110 by described RS-232 interface.
Here, described CPU121 can be processor MPC8360, and described RS-232 interface can be DB9
Socket, described Ethernet interface can be RJ45 socket.
Described FPGA122, is used for exporting the plurality of operative scenario data to described integrated circuit testing plate
130, receive the described each operative scenario data from described integrated circuit testing plate 130, and according to described
Voltage data and described current data calculate the power consumption data of tested integrated circuit under described each operative scenario.
First, described FPGA122 receives from the described control signal of described CPU121, described voltage
Data and the plurality of operative scenario data.
Subsequently, the plurality of operative scenario data are sequentially output to described by described FPGA122 by data wire
Tested integrated circuit 132 in integrated circuit testing plate 130.Meanwhile, described FPGA122 exports described electricity
Pressure data are to programmable power supply chip 123, to realize controlling described programmable power supply chip 123 by setting
Each road voltage that integrated circuit testing plate 130 described in electricity Sequential output needs, described voltage includes described tested
The voltage of integrated circuit.When described each operative scenario starts, described integrated circuit testing plate 130
In described tested integrated circuit 132 export described each operative scenario data to described FPGA122.Subsequently,
Described FPGA122 receives from the described each operative scenario data in described tested integrated circuit 132.As
The situations such as the most described FPGA122 detects the described each operative scenario data exception received, such as deadlock,
The most described FPGA122 controls described surface-mounted integrated circuit 130 and re-powers, and continues the yard being not fully complete
Scape is tested.In described each operative scenario running, described FPGA122 will receive from electric current
The current data of the tested integrated circuit of a large amount of synchronous acquisition of sample circuit 124, and according to described voltage number
Each power consumption of tested integrated circuit under described each operative scenario is calculated according to current data each described
Data.Concrete power consumption calculation formula is: power consumption=voltage * electric current.It should be noted that due to described each
Operative scenario running will produce the current data of substantial amounts of described tested integrated circuit, generated
The power consumption data of described tested integrated circuit is also substantial amounts of.
Subsequently, quilt under described FPGA122 exports described each operative scenario data and described each operative scenario
Survey the power consumption data of integrated circuit to memorizer 125 and liquid crystal display (LCD, Liquid Crystal Display)
126.Meanwhile, during described FPGA122 can also receive described LCD126, the manual power consumption test received sets
Put data.When a district of described memorizer 125 or 2nd district pile data, described FPGA122 produces mark
Signal also exports to described CPU121 so that described CPU121 reads the data of described memorizer 125.
Here, described data wire can be Ethernet interface, generic reception output port, universal asynchronous receiving-transmitting biography
Defeated device.
Programmable power supply chip 123, for exporting described voltage to described integrated electricity according to described voltage data
Drive test test plate (panel) 130.
Specifically, described programmable power supply chip 123 exports described voltage to described integrated electricity by power line
Electric source line interface 131 in drive test test plate (panel) 130.
Further, described programmable power supply chip 123 can be additionally used in the described integrated circuit testing plate 130 of monitoring
In the voltage of tested integrated circuit 132 and export to described FPGA122, in order to described FPGA122 root
The voltage of described tested integrated circuit 132 is dynamically regulated according to monitoring voltage.
Current sampling circuit 124, the electricity of tested integrated circuit under operative scenario each described in synchronous acquisition
Flow data.
Further, described current sampling circuit 124 is by the most described for described current data synchronism output
FPGA122。
Further, described power consumption test plate 120 also includes:
Memorizer 125, is used for storing under described each operative scenario data and described each operative scenario tested
The power consumption data of integrated circuit.
Specifically, the memory block of described memorizer 125 can be divided into a district and 2nd district.When a described district or two
When district's data are piled, described FPGA122 will produce marking signal and receive to described CPU121, in order to institute
State CPU121 start, according to described marking signal, the data read in a district or 2nd district and receive to described upper
Machine 110.
Here, the interface of described memorizer 125 can be 184 core DDR DIMM sockets.Meanwhile, may be used
With as desired to select the memory bar of described memorizer 125.
LCD126, is used for showing under described each operative scenario data and described each operative scenario tested integrated
The power consumption data of circuit.
Specifically, described LCD126 receive from described FPGA122 described each operative scenario data and
The power consumption data of tested integrated circuit under described each operative scenario, and according to quilt under described each operative scenario
Survey power consumption data change of power consumption curve of each operative scenario described in Dynamic Announce on screen of integrated circuit.
Described integrated circuit testing plate 130, for receiving the described voltage from described power consumption test plate 120
After the plurality of operative scenario data, according to the plurality of operative scenario data successively to each operative scenario
Carry out testing and exporting described each operative scenario data to described in the moment that described each operative scenario starts
Power consumption test plate 120.
Specifically, described integrated circuit testing plate 130 includes:
Electric source line interface 131, for receiving the described voltage from described power consumption test plate.
Specifically, described electric source line interface 131 is received from described power consumption test plate 120 by described power line
In described each road voltage of described programmable power supply chip 123.
Ic power voltage (IC_VCC, Integrated on described electric source line interface 131
Circuit_Volt Current Condenser) 1 to IC_VCCn output voltage extremely tested integrated circuit 132.Institute
State the supply voltage on electric source line interface 131 and receive (VCC_IN, Volt Current Condenser_Input)
Output voltage is to direct current inversion of direct current transducer (DCDC, Direct Current-Direct Current), subsequently, institute
State the voltage after DCDC will change to export to other circuit.
Here, described electric source line interface 131 can be DB25 interface.
Tested integrated circuit 132, for receiving the plurality of operative scenario number from described power consumption test plate
According to rear, successively each operative scenario is tested and described each according to the plurality of operative scenario data
The moment that operative scenario starts exports described each operative scenario data to described power consumption test plate.
Specifically, described tested integrated circuit 132 is received from described power consumption test plate by described data wire
The plurality of operative scenario data of the described FPGA122 in 120.According to the plurality of operative scenario data,
Each operative scenario is tested by described tested integrated circuit 132 successively, and in described each operative scenario
The moment started exports described in described power consumption test plate 120 of described each operative scenario data
FPGA122。
Embodiment two
The IC power consumption method of testing that Fig. 2 provides for the embodiment of the present invention realizes schematic flow sheet, such as figure
Shown in 2, in conjunction with above-described embodiment one and Fig. 1, described IC power consumption method of testing includes:
Step 210: the voltage data of tested integrated circuit and multiple operative scenario data are set.
In this step, described setting can be completed by host computer, and after setting, host computer can export described electricity
Pressure data and the plurality of operative scenario data are to power consumption test plate.
Step 220: power consumption test plate receives according to described voltage data output voltage to integrated circuit testing plate,
And export the plurality of operative scenario data to described integrated circuit testing plate.
Step 230: described integrated circuit testing buttress according to the plurality of operative scenario data successively to each work
Test as scene, and export described each operative scenario number in the moment that described each operative scenario starts
According to described power consumption test plate.
Step 240: tested integrated circuit under each operative scenario described in described power consumption test plate synchronous acquisition
Current data, calculates tested collection under described each operative scenario according to described voltage data and described current data
Become the power consumption data of circuit.
After step 240, the IC power consumption method of testing of the embodiment of the present invention can also include:
Step 250: described power consumption test plate stores and show described each operative scenario data and described each
The power consumption data of tested integrated circuit under operative scenario.
Step 260: described power consumption test plate exports described each operative scenario data and described each yard
Under scape, the power consumption data of tested integrated circuit is to described host computer.
Further, described IC power consumption method of testing also includes:
Described host computer receives from described each operative scenario data of described power consumption test plate and described each
The power consumption data of tested integrated circuit under operative scenario, generates the power consumption situation report of described each operative scenario
With change of power consumption curve.
Detailed description of the invention in embodiment two sees the description in embodiment one.
As can be seen from the above-described embodiment, the embodiment of the present invention makes IC power consumption test break away from manually
The miscellaneous work amount measured, thus reduce the error of hand dipping.Simultaneously as need not use multiple stage
Instrument builds complication system, it is not required that the wiring of mixed and disorderly complexity, it is possible to, overcome current DC source
The passage of analyser is limited, function is fixed, the expensive problem such as do not mate with interface.Additionally, the present invention
Embodiment can also be automatically performed the power consumption test under multiple operative scenario.
The above, only presently preferred embodiments of the present invention, it is not intended to limit the protection model of the present invention
Enclose.
Claims (9)
1. an IC power consumption test system, it is characterised in that described system includes: host computer, merit
Consumption test board and integrated circuit testing plate；Wherein,
Described host computer, for arranging the voltage data of tested integrated circuit and multiple operative scenario data, and
Export described voltage data and the plurality of operative scenario data to described power consumption test plate；
Described power consumption test plate, is used for receiving described voltage data and the plurality of operative scenario data, according to
Described voltage data output voltage is to described integrated circuit testing plate, and exports the plurality of operative scenario data
To described integrated circuit testing plate；It is additionally operable to receive each operative scenario from described integrated circuit testing plate
The current data of tested integrated circuit under data, and each operative scenario described in synchronous acquisition, according to described electricity
Pressure data and described current data calculate the power consumption data of tested integrated circuit under described each operative scenario；
Described integrated circuit testing plate, is used for receiving described voltage and the plurality of operative scenario data, according to
Each operative scenario is tested by the plurality of operative scenario data successively, and in described each operative scenario
The moment started exports described each operative scenario data to described power consumption test plate.
System the most according to claim 1, it is characterised in that described power consumption test plate includes:
Central processing unit, is used for receiving described voltage data and the plurality of operative scenario data, and output
Under described each operative scenario data and described each operative scenario, the power consumption data of tested integrated circuit is to described
Host computer；
Field programmable gate array, is used for exporting the plurality of operative scenario data to described integrated circuit testing
Plate, receives the described each operative scenario data from described integrated circuit testing plate, and according to described electricity
Pressure data and described current data calculate the power consumption data of tested integrated circuit under described each operative scenario；
Programmable power supply chip, surveys to described integrated circuit for exporting described voltage according to described voltage data
Test plate (panel)；
Current sampling circuit, the electric current number of tested integrated circuit under operative scenario each described in synchronous acquisition
According to.
System the most according to claim 1 and 2, it is characterised in that described power consumption test plate is additionally operable to
Store and show the power consumption of tested integrated circuit under described each operative scenario data and described each operative scenario
Data, and export the merit of tested integrated circuit under described each operative scenario data and described each operative scenario
Consumption data are to described host computer.
System the most according to claim 3, it is characterised in that described power consumption test plate also includes:
Memorizer, is used for storing under described each operative scenario data and described each operative scenario tested integrated
The power consumption data of circuit；
Liquid crystal display, is used for showing under described each operative scenario data and described each operative scenario tested
The power consumption data of integrated circuit.
System the most according to claim 1 and 2, it is characterised in that described integrated circuit testing plate bag
Include:
Electric source line interface, for receiving the described voltage from described power consumption test plate；
Tested integrated circuit, for receiving the plurality of operative scenario data from described power consumption test plate,
Successively each operative scenario is tested according to the plurality of operative scenario data, and in described each work
The moment that scene starts exports described each operative scenario data to described power consumption test plate.
System the most according to claim 3, it is characterised in that described host computer be additionally operable to receive from
Tested integrated circuit under described each operative scenario data of described power consumption test plate and described each operative scenario
Power consumption data, generate described each operative scenario power consumption situation report and change of power consumption curve.
7. an IC power consumption method of testing, it is characterised in that the voltage number of tested integrated circuit is set
According to multiple operative scenario data；Described method also includes:
Power consumption test plate receives according to described voltage data output voltage to integrated circuit testing plate, and exports institute
State multiple operative scenario data to described integrated circuit testing plate；
Each operative scenario is carried out successively by described integrated circuit testing buttress according to the plurality of operative scenario data
Test, and export described each operative scenario data to described merit in the moment that described each operative scenario starts
Consumption test board；
The current data of tested integrated circuit under each operative scenario described in described power consumption test plate synchronous acquisition,
The merit of tested integrated circuit under described each operative scenario is calculated according to described voltage data and described current data
Consumption data.
Method the most according to claim 7, it is characterised in that described method also includes:
Described power consumption test plate stores and shows under described each operative scenario data and described each operative scenario
The power consumption data of tested integrated circuit, and export described each operative scenario data and described each operative scenario
Under the power consumption data of tested integrated circuit to host computer.
Method the most according to claim 8, it is characterised in that described method also includes:
Described host computer receives from described each operative scenario data of described power consumption test plate and described each
The power consumption data of tested integrated circuit under operative scenario, generates the power consumption situation report of described each operative scenario
With change of power consumption curve.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510091782.9A CN105988079A (en) | 2015-02-28 | 2015-02-28 | System and method for testing power consumption of integrated circuit |
| PCT/CN2015/083364 WO2016134573A1 (en) | 2015-02-28 | 2015-07-06 | System and method for testing power consumption of integrated circuit |
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| CN201510091782.9A CN105988079A (en) | 2015-02-28 | 2015-02-28 | System and method for testing power consumption of integrated circuit |
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| CN108828310A (en) * | 2018-07-16 | 2018-11-16 | 中国电力科学研究院有限公司 | A kind of test method of low power consuming devices service life |
| CN109061502A (en) * | 2018-08-21 | 2018-12-21 | 厦门盈趣科技股份有限公司 | Low power consuming devices battery life test macro and test method |
| CN109085493A (en) * | 2018-09-11 | 2018-12-25 | 山东鲁能智能技术有限公司 | embedded module test system and method |
| CN109765481A (en) * | 2018-12-29 | 2019-05-17 | 西安智多晶微电子有限公司 | A kind of test board of the CPLD chip based on FPGA/MCU |
| CN110441672A (en) * | 2019-08-06 | 2019-11-12 | 西安太乙电子有限公司 | A kind of SoC type integrated circuit dynamic device and method |
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