CN105981182A - Solar cell with trench-free emitter regions - Google Patents

Solar cell with trench-free emitter regions Download PDF

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Publication number
CN105981182A
CN105981182A CN201580005976.0A CN201580005976A CN105981182A CN 105981182 A CN105981182 A CN 105981182A CN 201580005976 A CN201580005976 A CN 201580005976A CN 105981182 A CN105981182 A CN 105981182A
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Prior art keywords
impurity
polysilicon emitter
type
emitter region
region
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CN201580005976.0A
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CN105981182B (en
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大卫·D·史密斯
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Maikesheng Solar Energy Co ltd
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SunPower Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0368—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including polycrystalline semiconductors
    • H—ELECTRICITY
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • H—ELECTRICITY
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • H01L31/182—Special manufacturing methods for polycrystalline Si, e.g. Si ribbon, poly Si ingots, thin films of polycrystalline Si
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/546—Polycrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

Methods of fabricating solar cells having trench-free emitter regions are described. In an example, a solar cell includes a substrate. A thin dielectric layer is disposed on a portion of the back surface of the substrate. A first polycrystalline silicon emitter region is disposed on a first portion of the thin dielectric layer and doped with an impurity of a first conductivity type. A second polycrystalline silicon emitter region is disposed on a second portion of the thin dielectric layer proximate to the first polycrystalline silicon emitter region disposed on the first portion of the thin dielectric layer. The second polycrystalline silicon emitter region is doped with an impurity of a second, opposite, conductivity type. A total concentration of the impurity of the first conductivity type is at least an order of magnitude greater than a total concentration of the impurity of the second conductivity type.

Description

There is the solaode without raceway groove emitter region
Technical field
Embodiment of the disclosure and belong to field of renewable energy, and specifically, relate to manufacturing tool With or without the method for the solaode of raceway groove emitter region, and gained solaode.
Background technology
Photovoltaic cell (being commonly referred to as solaode) be known to for solar radiation is directly turned It is changed to the device of electric energy.In general, semiconductor processing technology is used to be formed at the near surface of substrate P-n junction and on semiconductor wafer or substrate manufacture solaode.Irradiate on the surface of the substrate and enter Solar radiation in substrate forms electronics and hole pair in substrate block.Electronics and hole are to migrating to P doped region in substrate and n doped region, so that generating voltage difference between doped region.Will Doped region is connected to the conduction region on solaode, to be guided to being coupled with it from battery by electric current External circuit.
Efficiency is the key property of solaode, because it directly has with solar cell power generation ability Close.Equally, the direct cost benefit with this type of solaode of efficiency preparing solaode has Close.Therefore, improve the technology of solar battery efficiency or improve the technology manufacturing solar battery efficiency It is universal required.Some embodiments of the disclosure allow by providing manufacture solar battery structure New technology and improve the manufacture efficiency of solaode.Some embodiments of the disclosure allow by providing Novel solar battery structure improves solar battery efficiency.
Accompanying drawing explanation
Figure 1A-1E shows each rank in manufacturing according to the solaode that embodiment of the disclosure The sectional view of section, wherein:
Figure 1A shows the thin electrolyte formed in a part for solar cell substrate back surface Layer；
Figure 1B shows the structure of the Figure 1A being formed with boracic silicon layer on it；
Fig. 1 C shows that the first area of the boracic silicon layer of Figure 1B rather than second area are injected into phosphorus The structure of ion；
Fig. 1 D shows the structure of Fig. 1 C, its be heated to provide N-type polycrystalline silicon emitter stage and P-type polysilicon emitter stage；And
Fig. 1 E shows the N-type polycrystalline silicon emitter stage into Fig. 1 D and p-type polysilicon emitter stage shape Become the structure after multiple conductive contact structures.
The flow chart that embodiment of the disclosure according to Fig. 2, described flow chart list with Figure 1A- Operation in the method manufacturing solaode that 1E is corresponding.
Fig. 3 A schematically shows and patterns the embedded of injection according to embodiment of the disclosure The sectional view of platform, this patterning injects and relates to mobile wafer and fixed form mask.
Fig. 3 B shows and covers through graphite is close according in Fig. 3 A device that embodiment of the disclosure The injection sequence of mould.
The flow chart that embodiment of the disclosure according to Fig. 4, described flow chart lists manufacture solar energy Operation in the other method of battery.
Detailed description of the invention
Detailed description below is the most illustrative, is not intended to limit described theme Embodiment or the application of this type of embodiment and purposes.As used herein, word " exemplary " means " to be used as Example, example or illustration ".It is not necessarily to be construed as comparing it described herein as exemplary any enforcement He implements preferred or favourable.Additionally, be not intended by aforementioned technical field, background technology, send out The constraint of any theory expressed or imply perhaps proposed in detailed description below in bright.
This specification includes mentioning " embodiment " or " embodiment ".Phrase is " an enforcement In example " or the appearance of " in an embodiment " be not necessarily referring to same embodiment.Specific feature, structure or Characteristic can be combined by any suitable method consistent with the disclosure.
Term.Paragraphs below provides and is present in the art in the disclosure (including appended claims) The definition of language and/or linguistic context:
" comprise/include ".This term is open.As used by the dependent claims, This term is not precluded from other structure or step.
" it is configured to ".Various unit or parts can be described or advocate into " being configured to " and perform one Item or the multi-task.Under such linguistic context, " being configured to " is for by indicating this units/components bag Include and perform the structure of those tasks one or more during operation and imply structure.Therefore, even if referring to Fixed units/components is not at duty (such as, do not open/activate) at present, it is possible to by this unit / parts are said to be and are configured to execution task.A certain unit/circuit/component is described in detail in detail " be configured to " perform one Item or the multi-task are intended to for this units/components not quote 35U.S.C. § 112 the 6th clearly Section.
The mark of the noun after these terms such as " first ", " second " are used as it as used herein Note, and do not imply that any kind of order (such as, space, time and logic etc.).Such as, Mention " first " solaode do not necessarily imply that this solaode be first in a certain sequence too Sun can battery；On the contrary, term " first " is used for distinguishing this solaode and another solaode (such as, " second " solaode).
" couple "-be described below finger element or node or architectural feature " is coupled " together.Such as this Literary composition is used, unless otherwise explicitly indicated, otherwise " couples " and means that an element/node/architectural feature is direct Or it is indirectly connected to another element/node/architectural feature (or directly or indirectly communicating therewith), and It is not necessarily machinery to couple.
Additionally, following describe in also employ some term only for the purpose of reference, therefore this A little terms are not intended to limit.Such as, such as " top ", " bottom ", " top " or " lower section " etc Term refer to accompanying drawing provides the direction of reference.Such as " front ", " back side ", " below ", " side ", " outside " and some part of the term description parts of " inner side " etc are in consistent but arbitrary reference frame Orientation and/or position, can be clearly by word and the relevant accompanying drawing with reference to the discussed parts of description Understand described orientation and/or position.Such term can include word that mask body mentions, they Derivative word and the word of similar meaning.
This document describes the method with the solaode without raceway groove emitter region that manufactures, and Gained solaode.In the following description, many details, the most concrete work are given Process flow operates, in order to provide the thorough understanding of embodiment of this disclosure.To those skilled in the art Member it is evident that and can implement embodiment of the disclosure in the case of not having these details. In other cases, do not describe in detail known to manufacturing technology, such as lithographic printing and patterning Technology, to avoid unnecessarily making to embodiment of the disclosure indigestion.It is further understood that at figure Shown in various embodiments be exemplary displaying and be not necessarily drawn to scale.
The method manufacturing solaode is disclosed herein.In one embodiment, solar energy is manufactured The method of battery relates to being formed thin dielectric layer in a part for substrate back surface, this substrate have with The optical receiving surface that back surface is relative.The method further relates to be formed on the Part I of thin dielectric layer First polysilicon emitter region also mixes the impurity of the first conduction type.The method further relates at thin electricity Second polysilicon emitter in the first polysilicon emitter region it is formed close on the Part II of dielectric layer Region, this second polysilicon emitter region is mixed with the impurity of the second films of opposite conductivity.First polycrystalline In silicon emitter region, the total concentration ratio of the impurity of the first conduction type is in the second polysilicon emitter region The total concentration of the impurity of the second conduction type at least one order of magnitude big.
In another embodiment, the alternately arranged N-type and the p-type that manufacture solaode are launched The method in territory, polar region relates to being formed above a part for substrate containing borosilicate by in-situ deposition technique Layer.The method further relates to the first area of boracic silicon layer but does not injects phosphonium ion to second area, with The phosphorus injection zone of boracic silicon layer is provided.The method further relates to heating to provide N-type in the first region Polysilicon emitter and in the second area offer p-type polysilicon emitter stage.The method further relates to be formed Multiple conductive contact structures, each N-type polycrystalline silicon emitter stage is electrically connected to p-type polysilicon emitter stage In the plurality of conductive contact structures one.
There is disclosed herein solaode.In one embodiment, solaode includes having Optical receiving surface and the substrate of back surface.Thin dielectric layer is arranged on a part for substrate back surface On.First polysilicon emitter region be arranged on the Part I of described thin dielectric layer and mixed with The impurity of the first conduction type.Second polysilicon emitter region is arranged on described thin dielectric layer On Part II, near being arranged on described first on the described Part I of described thin dielectric layer Polysilicon emitter region.Described second polysilicon emitter region is mixed with the second films of opposite conductivity Impurity.In first polysilicon emitter region, the total concentration of the impurity of the first conduction type is than the second polycrystalline The total concentration of the impurity of the second conduction type at least one order of magnitude big in silicon emitter region.
One or more embodiment as herein described relates to having formation above solar cell substrate The solaode of emitter region, more particularly, relates to having emitter region and arranges without raceway groove This type of solaode.As reference, state-of-the-art solaode is at back contact solar electricity Being formed with emitter region in polysilicon layer on the back surface of pond, this solaode usually has to be made The gap that N-type emitter region separates with p-type emitter region.Additionally, this gap is usually extended The raceway groove in substrate below is extended into be formed.Therefore, this type of solaode is referred to alternatively as ditch Road contact solar battery.In contrast, one or more embodiment as herein described relates to passing through Ion implanting is used to provide the solar battery process flow process arranged without raceway groove in a simplified manner.
According to the general embodiment of the present invention, the foundation describing technique is to find at p-type polysilicon " finger piece " inner boron that is lightly doped is possibly for eliminating without the space charge in raceway groove back contact solar battery Compound essential.In one embodiment, due to the possible corresponding N-type polycrystalline silicon of unnecessary reduction Doping content, is therefore respectively formed low-level doped boron region in p-type and N-type finger region, makes The boron concentration of p-type finger region is of about 1e19cm-3.Meanwhile, in N-type region territory by concentration about 1e20cm-3Phosphorus to described low-level boron doping carry out contra-doping, to provide N-type finger piece district Territory.Combined as described in figure 1 below A-1E, an enforcement can relate to originally form and produced by plasma P+ doped silicon layer, then template mask inject phosphorus, making P+ doped silicon layer regioinvertions is that N-type refers to Shape thing or point.Adulterant is similar with activating, and thermally processable operation makes emitter region tie Crystalline substance, and the front surface of solaode may be made to be passivated.
According to exemplary embodiment, disclosing the method manufacturing solaode, the method relates to system Make alternately arranged N-type and the p-type emitter region of solaode.Figure 1A-1E shows basis The sectional view in each stage in the solaode manufacture that embodiment of the disclosure.According to Fig. 2 originally Flow process Figure 200 of disclosed embodiment, described flow chart lists the manufacture corresponding with Figure 1A-1E too Operation in the method for sun energy battery.
See the respective operations 202 of Figure 1A and flow process Figure 200, at solar cell substrate 100 Thin dielectric layer 102 is formed in a part for back surface.
In one embodiment, substrate 100 is monocrystalline silicon substrate, such as bulk single crystal n-type doping Silicon substrate.It will be appreciated, however, that substrate 100 can be provided on whole solar cell substrate Layer, such as polysilicon layer.In one embodiment, thin dielectric layer 102 be thickness about 2 nanometer or Less tunnel silicon oxide.
See the respective operations 204 of Figure 1B and flow process Figure 200, on thin dielectric layer 102 Form boracic silicon layer 104.
In one embodiment, boracic silicon layer 104 passes through in-situ deposition technique in a substrate part Top forms boracic silicon layer, in position in depositing operation, mixes bora in silicon layer when silicon layer is formed Matter.In one suchembodiment, form boracic silicon layer 104 to relate to forming boracic amorphous silicon layer. In another such embodiment, form boracic silicon layer 104 and relate to forming B-doped Polycrystalline Silicon layer.? In previous embodiment, boracic amorphous silicon layer is for using plasma enhanced chemical vapor deposition (PECVD) The boracic layer of hydrogenated formed, is represented by boron-doping a-Si:H, comprises S-H covalent bond in whole layer. Also the CVD (chemical gaseous phase deposition) of other forms, such as atmospheric pressure cvd or low pressure can be applied CVD.In later embodiment, pecvd process is used to form B-doped Polycrystalline Silicon layer.Should manage Solve, in other embodiments, after silicon layer is formed, boron impurity can be mixed silicon layer, such as by whole Body injection technology mixes.
See the respective operations 206 of Fig. 1 C and flow process Figure 200, to the of boracic silicon layer 104 One region 106 rather than second area 108 inject phosphonium ion.
In one embodiment, inject to first area 106 to provide the phosphorus of boracic silicon layer 104 to note Entering region 106, wherein the concentration of the phosphorus impurities of phosphorus injection zone 106 is than the boron impurity in region 106 Concentration is big at least 10 times (i.e. at least one order of magnitude), and therefore, ratio is in unimplanted phosphorus region 108 The concentration of boron impurity at least one order of magnitude big.In one embodiment, inject to boracic silicon layer 104 Phosphonium ion relates to injecting through template mask, describes this process below in conjunction with Fig. 3 A and Fig. 3 B Illustrative processes frock.In this type of concrete embodiment, through being disposed in boracic silicon layer 104 Outside but its immediate graphite template mask inject.In another specific embodiment, wear Cross the silicon template mask being disposed on boracic silicon layer 104 to inject.In one embodiment, logical Cross use ion beam mutation or plasma immersion is injected.Should be appreciated that actually It may happen that some residual doping, such as, by dispersion or not exclusively adulterate in two regions.But, appoint What this type of residual doping is not enough to second area 108 contra-doping.
Seeing the respective operations 208 of Fig. 1 D and flow process Figure 200, the structure of Fig. 1 C is heated 110 to provide N-type polycrystalline silicon emitter stage 112 and p-type polysilicon emitter stage 114.
In one embodiment, it is heated to be annealing process, such as rapid thermal anneal process, this technique For activating the impurity in first area 106 and second area 108 respectively of boracic silicon layer 104. In one embodiment, carry out annealing and make annealing to hold at a temperature in the range of about 850-1100 DEG C The continuous time is in the range of about 1 100 minutes.In one embodiment, boracic silicon layer 104 is to contain Boron amorphous silicon layer, and heat 110 and relate to making this boracic amorphous silicon layer with beyond activator impurity Also form B-doped Polycrystalline Silicon.In another embodiment, boracic silicon layer 104 is B-doped Polycrystalline Silicon layer, And heat 110 and relate to the phosphorus impurities at least activating phosphorus injection zone to form p-doped region.At one In embodiment, during heating or annealing, carry out a small amount of phosphorus dopant driving.
Therefore, the Part I of thin dielectric layer 102 forms the first polysilicon emitter region 112 and mix N-type impurity.The Part II of thin dielectric layer 102 forms the second polysilicon send out Emitter region 114, it is near the first polysilicon emitter region 112.Second polysilicon emitter region 114 mixed with p type impurity.In one suchembodiment, in the first polysilicon emitter region 112 The total concentration of the N-type impurity being activated is than the p-type being activated in the second polysilicon emitter region 114 The total concentration of impurity at least one order of magnitude big, therefore, ratio is in the first polysilicon emitter region 112 The total concentration of the p type impurity being activated at least one order of magnitude big.Refer again to Fig. 1 D, heat 110 Relate to being formed between adjacent N-type polycrystalline silicon emitter stage 112 and p-type polysilicon emitter stage 114 P/N knot 116.
See the respective operations 210 of Fig. 1 E and flow process Figure 200, form multiple conductive contact structures The structure of 120/122 is many for N-type polycrystalline silicon emitter stage (corresponding to contact structure 120) and p-type Crystal silicon emitter stage (corresponding to contact structure 122).
In one embodiment, conductive contact structures 120/122 manufactures in the following manner: first Deposition and patterned insulation layer 118 are to have opening, and are formed one or more the most in the opening Conductive layer.In one suchembodiment, opening is formed by laser ablation.An embodiment In, conductive contact structures 120/122 is comprised metal and is formed by deposition, photoetching and engraving method, or Formed alternatively by typography or electroplating technology, then or alternatively select Select and formed by paper tinsel adhesion technique.
Refer again to Fig. 1 E, optical receiving surface 124, i.e. with its on be formed with conductive contact structures The surface that surface is relative, is the optical receiving surface of veining.In one embodiment, use based on hydrogen The Wet-etching agent of oxide makes the front surface texture of substrate 102.Should be appreciated that light-receiving The arrangement of time of surface texturizing can change.For example, it is possible to before thin dielectric layer 102 is formed Or it is textured after being Xing Chenged, but in one embodiment, before boracic silicon layer 104 is formed It is textured.In one embodiment, texturizing surfaces can be have regular or erose Surface, this surface is used for scatter incident light, thus reduces and reflect from the optical receiving surface of solaode The light quantity left.Referring again to Fig. 1 E, additional embodiment may be included in and formed on optical receiving surface 124 Passivation and/or ARC (ARC) layer (being collectively shown as layer 126), such as silicon nitride layer, silicon layer, Silicon oxide layer or silicon oxynitride layer.Should be appreciated that the arrangement of time forming passivation and/or ARC layer is permissible Change.
Referring again to Fig. 1 E, subsequently, in one embodiment, solaode includes having light The substrate 100 of receiving surface 124 and the back surface relative with optical receiving surface.Thin dielectric layer 102 quilt In a part for the back surface being arranged on substrate 100.First polysilicon emitter region 112 is set On the Part I of thin dielectric layer 102 and mixed with the impurity of the first conduction type.Second polysilicon Emitter region 114 is arranged on the Part II of thin dielectric layer 102, thin near being arranged on The first polysilicon emitter region 112 on dielectric layer 102 Part I.Second polysilicon emitter Region 114 is mixed with the impurity of the second films of opposite conductivity.In first polysilicon emitter region 112 The total concentration of the impurity of one conduction type is than the second conduction type in the second polysilicon emitter region 114 Total concentration at least one order of magnitude big of impurity.First conductive contact structures 120 is electrically connected to first Polysilicon emitter region 112.Second conductive contact structures 122 is electrically connected to the second polysilicon emitter Region 114.In one embodiment, solaode is back contact solar battery.
In one embodiment, solaode also includes the first polysilicon emitter region 112 He P/N knot 116 between second polysilicon emitter region 114.In one embodiment, the first polycrystalline The impurity of the first conduction type in silicon emitter region 112 is N-type impurity, the second polysilicon emitter The impurity of the second conduction type in territory, polar region 114 is p type impurity.This type of concrete enforcement In example, N-type impurity is phosphorus, and the first conduction type in the first polysilicon emitter region 112 The total concentration of impurity be about 1E20 atom/cm3.In this embodiment, p type impurity is boron, and And the total concentration of the impurity of the second conduction type that second in polysilicon emitter region 114 is about 1E18 Individual atom/cm3。
According to the character of fabrication scheme, in one embodiment, the first polysilicon emitter region 112 impurity also including the second conduction type.In this type of concrete embodiment, the first polysilicon The total concentration of the impurity of the first conduction type in emitter region 112 is than the second polysilicon emitter polar region The total concentration of the impurity of the second conduction type in territory 114 and the first polysilicon emitter region 112 Exceed about two orders of magnitude.In one embodiment, contra-doping region is in doping content the biggest one The individual order of magnitude, in order to fully overwhelm the adulterant that (contra-doping) is comprised at first, thus determine doping Characteristic.But, in this embodiment, contra-doping region no longer exceeds about two numbers in doping content Magnitude so that contra-doping region does not interferes with solaode with the electrical conductivity difference in non-contra-doping region Final performance and efficiency.
On the other hand, as briefly described above, template mask is used for guiding and combines Fig. 1 C and retouch The phosphorus stated injects.In one suchembodiment, fixing graphite template mask is used to inject. Such as, Fig. 3 A schematically show according to embodiment of the disclosure for patterning the embedded of injection The sectional view of formula platform, this patterning injects and relates to mobile wafer and fixed form mask.Fig. 3 B illustrates According in Fig. 3 A device that embodiment of the disclosure through graphite close to the injection sequence of mask.See Fig. 3 A, embedded platform 300 includes wafer input area 302, injection source 304 (such as, ion note Enter or plasma immersion) and output area 306.By fixed form mask 308, such as fix graphite and cover Mould, remains neighbouring but does not contact substrate 310 and inject substrate 312 to provide.In another embodiment In, the silicon template mask that can contact substrate 312 can be used to inject.
In a word, although some material is specifically described above, but for still in the embodiment of the present invention Spirit and scope in other these type of embodiments, some materials can be easy to be replaced by other materials.Example As, in an embodiment, the substrate of different materials, the substrate of such as III-V material can be used, be used for Replace silicon substrate.Moreover, it will be appreciated that in the case of specifically describing N+ type and P+ type doping, Other embodiments of imagination include contrary conduction type, are respectively the doping of such as P+ type and N+ type. Although arranging it addition, refer primarily to back contact solar cell, it is to be understood that, side as herein described Method contacts electrode solaode before also apply be applicable to.In other embodiments, above-mentioned institute can be implemented Meaning finally produces raceway groove contact solar battery without raceway groove technique.Such as, can first implement as above Described technological process, can form raceway groove subsequently between emitter region.
Therefore, it has been disclosed that manufacture the method with the solaode without raceway groove emitter region, And gained solaode.As general exemplary process, Fig. 4 is the enforcement according to the disclosure The flow chart 400 of example, this flow chart lists the operation in the other method manufacturing solaode.See The flow chart 400 of Fig. 4, manufactures alternately arranged N-type and the p-type emitter region of solaode Method relate to being formed in a part for substrate back surface in operation 402 thin dielectric layer.The party Method further relates to be formed on the Part I of thin dielectric layer in operation 404 the first polysilicon emitter Region.The method further relates to be formed close in action 406 on the Part II of thin dielectric layer The second polysilicon emitter region in one polysilicon emitter region.In one embodiment, more than first In crystal silicon emitter region, the total concentration of the impurity of the first conduction type is than the second polysilicon emitter region In total concentration at least one order of magnitude big of impurity of the second films of opposite conductivity.
Although being described above specific embodiment, even if only describing relative to specific feature Single embodiment, these embodiments are also not intended to limit the scope of the present disclosure.Institute in the disclosure The example of the feature provided is unless otherwise indicated, it is intended that illustrative and not restrictive.Above The beneficial effect with the disclosure that is intended to will be apparent to those skilled in the science is described Those alternative forms, modification and equivalents.
The scope of the present disclosure includes that any feature disclosed herein or feature combination (are expressed or secretly Show), or its any summary, no matter whether it alleviates any or all of problem solved herein.Cause This, can during the checking process of the application (or application that it is claimed priority) to any this Category feature combination proposes new claim.Specifically, with reference to appended claims, since The feature belonging to claim can combine with those features of independent claims, and from accordingly The feature of independent claims can combine in any appropriate manner, and is not only with appended right The specific combination enumerated in requirement.
In one embodiment, solaode includes the base with optical receiving surface and back surface Plate.Thin dielectric layer is arranged in a part for substrate back surface.First polysilicon emitter region It is arranged on the Part I of described thin dielectric layer and mixed with the impurity of the first conduction type.Second Polysilicon emitter region is arranged on the Part II of described thin dielectric layer, near being arranged on Described first polysilicon emitter region on the described Part I of described thin dielectric layer.Described Two polysilicon emitter regions are mixed with the impurity of the second films of opposite conductivity.First polysilicon emitter polar region In territory, the total concentration of the impurity of the first conduction type is than the second conductive-type in the second polysilicon emitter region The total concentration of the impurity of type at least one order of magnitude big.
In one embodiment, solaode also includes the first polysilicon emitter region and second P/N knot between polysilicon emitter region.
In one embodiment, the impurity of the first conduction type in the first polysilicon emitter region For N-type impurity, the impurity of the second conduction type in the second polysilicon emitter region is that p-type is miscellaneous Matter.
In one embodiment, N-type impurity is phosphorus, and in the first polysilicon emitter region The total concentration of the impurity of the first conduction type is about 1E20 atom/cm3, and p type impurity is boron, and And the total concentration of the impurity of the second conduction type that second in polysilicon emitter region be about 1E18 former Son/cm3。
In one embodiment, the first polysilicon emitter region also includes the miscellaneous of the second conduction type Matter.
In one embodiment, the impurity of the first conduction type in the first polysilicon emitter region Total concentration lead than second in the second polysilicon emitter region and the first polysilicon emitter region The total concentration of the impurity of electricity type exceeds about two orders of magnitude.
In one embodiment, solaode also includes being electrically connected to the first polysilicon emitter polar region First conductive contact structures in territory, and it is electrically connected to second conduction in the second polysilicon emitter region Contact structure.
In one embodiment, the method manufacturing solaode is included in of substrate back surface Dividing upper formation thin dielectric layer, this substrate has the optical receiving surface relative with back surface.The method is also It is included on the Part I of thin dielectric layer to form the first polysilicon emitter region and mix first and leads The impurity of electricity type.The method is additionally included on the Part II of thin dielectric layer and is formed close to more than first Second polysilicon emitter region of crystal silicon emitter region, the second polysilicon emitter region is mixed with The impurity of two films of opposite conductivity, wherein the first conduction type in the first polysilicon emitter region The total concentration of impurity is than the total concentration of the impurity of the second conduction type in the second polysilicon emitter region At least one order of magnitude big.
In one embodiment, alternately arranged N-type and the p-type emitter stage of solaode are manufactured The method in region includes forming boracic silicon layer above a part for substrate by in-situ deposition technique. The method also includes to the first area of boracic silicon layer but does not injects phosphonium ion to second area, to provide The phosphorus injection zone of boracic silicon layer.The method also includes that heating is to provide N-type polycrystalline in the first region Silicon emitter and in the second area offer p-type polysilicon emitter stage.The method also includes being formed multiple Conductive contact structures, each N-type polycrystalline silicon emitter stage and p-type polysilicon emitter stage are electrically connected to described In multiple conductive contact structures one.
In one embodiment, form boracic silicon layer and include forming boracic amorphous silicon layer, and heat Including making boracic amorphous silicon layer.
In one embodiment, form boracic silicon layer and include forming B-doped Polycrystalline Silicon layer, and heat Including activating the phosphonium ion of phosphorus injection zone to form p-doped region.
In one embodiment, form B-doped Polycrystalline Silicon layer to include using plasma enhanced chemical gas Deposition (PECVD) technique mutually.
In one embodiment, phosphonium ion injects boracic silicon layer to include noting through template mask Enter.
In one embodiment, carry out injection through template mask to include through being placed on containing borosilicate Outside Ceng but be close to the graphite template mask of this boracic silicon layer and inject.
In one embodiment, carry out injection through template mask to include through being placed on containing borosilicate Silicon template mask on layer injects.
In one embodiment, heating is included in adjacent N-type polycrystalline silicon emitter stage and p-type polycrystalline P/N knot is formed between silicon emitter.
In one embodiment, heating provides N-type polycrystalline silicon emitter stage, its total phosphorus dopant Boron dope agent concentration at least one order of magnitude big that concentration than p-type polysilicon emitter stage is total.
In one embodiment, form boracic silicon layer and be included in the thin oxide layer being formed on substrate A part on formed.

Claims (20)

1. a solaode, including:
Substrate, described substrate has optical receiving surface and back surface；
Thin dielectric layer, described thin dielectric layer is arranged on the described back surface of described substrate A part on；
First polysilicon emitter region, described first polysilicon emitter region is arranged on Miscellaneous on the Part I of described thin dielectric layer and mixed with the first conduction type Matter；And
Second polysilicon emitter region, described second polysilicon emitter region is arranged on On the Part II of described thin dielectric layer, it is situated between near being arranged on described thin electricity Described first polysilicon emitter region on the described Part I of matter layer, institute State the second polysilicon emitter region impurity mixed with the second films of opposite conductivity, Described first conduction type in wherein said first polysilicon emitter region The total concentration of impurity is than described second in described second polysilicon emitter region The total concentration of the impurity of conduction type at least one order of magnitude big.
Solaode the most according to claim 1, also includes:
Between described first polysilicon emitter region and described second polysilicon emitter region P/N knot.
Solaode the most according to claim 1, wherein said first polysilicon emitter polar region The impurity of described first conduction type in territory is N-type impurity, described second polysilicon emitter The impurity of described second conduction type in territory, polar region is p type impurity.
Solaode the most according to claim 3, wherein said N-type impurity is phosphorus, and The total concentration of the impurity of described first conduction type in described first polysilicon emitter region It is about 1E20 atom/cm3, and wherein said p type impurity is boron, and described second The total concentration of the impurity of described second conduction type in polysilicon emitter region is about 1E18 Individual atom/cm3。
Solaode the most according to claim 1, wherein said first polysilicon emitter polar region Territory also comprises the impurity of described second conduction type.
Solaode the most according to claim 5, wherein said first polysilicon emitter polar region The total concentration of the impurity of described first conduction type in territory is than described second polysilicon emitter The impurity of described second conduction type in region and described first polysilicon emitter region Total concentration exceed about two orders of magnitude.
Solaode the most according to claim 1, also includes:
It is electrically connected to first conductive contact structures in described first polysilicon emitter region；With And
It is electrically connected to second conductive contact structures in described second polysilicon emitter region.
8. the method manufacturing solaode, described method includes:
A part for the back surface of substrate is formed thin dielectric layer, described substrate have with Described back surface back to optical receiving surface；
The Part I of described thin dielectric layer forms the first polysilicon emitter region also Mix the impurity of the first conduction type；And
The Part II of described thin dielectric layer is formed close to described first polysilicon emitter The second polysilicon emitter region in territory, polar region, described second polysilicon emitter Region is mixed with the impurity of the second films of opposite conductivity, wherein said first polysilicon The total concentration ratio of the impurity of described first conduction type in emitter region is described The impurity of described second conduction type in the second polysilicon emitter region total Concentration at least one order of magnitude big.
9. the solaode that a method according to claim 8 manufactures.
10. manufacture N-type alternately and the method for p-type emitter region of solaode, described Method includes:
Above a part for substrate, boracic silicon layer is formed by in-situ deposition technique；
To the first area of described boracic silicon layer but not to second area injection phosphonium ion, to carry Phosphorus injection zone for described boracic silicon layer；
Heat in described first area, to provide N-type polycrystalline silicon emitter stage and described second Region provides p-type polysilicon emitter stage；And
Forming multiple conductive contact structures, described N-type polycrystalline silicon emitter stage and described p-type are many Each in crystal silicon emitter stage is electrically connected to the plurality of conductive contact structures In one.
11. methods according to claim 10, wherein form described boracic silicon layer and include forming boracic Amorphous silicon layer, and wherein said heating includes making described boracic amorphous silicon layer.
12. methods according to claim 10, wherein form described boracic silicon layer and include forming boron-doping Polysilicon layer, and wherein said heating include the described phosphorus activating described phosphorus injection zone from Son is to form p-doped region.
13. methods according to claim 12, wherein form described B-doped Polycrystalline Silicon layer and include using Plasma enhanced chemical vapor deposition (PECVD) technique.
14. methods according to claim 10, wherein inject phosphonium ion to described boracic silicon layer and include Inject through template mask.
15. methods according to claim 14, wherein carry out injection through described template mask and include Through outside being placed on described boracic silicon layer but be close to the graphite template of described boracic silicon layer and cover Mould injects.
16. methods according to claim 14, wherein carry out injection through described template mask and include Inject through the silicon template mask being placed on described boracic silicon layer.
17. methods according to claim 10, wherein said heating is included in adjacent described N-type P/N knot is formed between polysilicon emitter and described p-type polysilicon emitter stage.
18. methods according to claim 10, wherein said heating provides total phosphorus concentration of dopant ratio Total boron dope agent concentration of described p-type polysilicon emitter stage at least one order of magnitude big described N-type polycrystalline silicon emitter stage.
19. methods according to claim 10, wherein form described boracic silicon layer and are included in and are formed at Formed in a part for thin oxide layer on described substrate.
The solaode that 20. 1 kinds of methods according to claim 10 manufacture.
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