CN105981157B

CN105981157B - Grounding dummy gate in scaled layout design

Info

Publication number: CN105981157B
Application number: CN201580008258.9A
Authority: CN
Inventors: S·S·宋; Z·王; O·翁; K·利姆; J·J·朱; X·陈; F·万; R·G·斯特凡尼; C·F·耶普
Original assignee: Qualcomm Inc
Current assignee: Qualcomm Inc
Priority date: 2014-02-14
Filing date: 2015-01-08
Publication date: 2020-12-08
Anticipated expiration: 2035-01-08
Also published as: US9379058B2; US20150235948A1; EP3105782B1; WO2015122974A1; CN105981157A; JP2017506430A; EP3105782A1

Abstract

A semiconductor device includes a gate (210) and a first active contact (220) adjacent to the gate. Such devices further include a first stacked contact (1310) electrically coupled to the first active contact, the first stacked contact including a first isolation layer (1200) on the sidewalls electrically isolating the first stacked contact from the gate. The device also includes a first via (2000) electrically coupled to the gate and landing on the first stacked contact. The first via couples the first stacked contact and the first active contact to the gate to ground the gate.

Description

Grounding dummy gate in scaled layout design

Cross Reference to Related Applications

This application claims the benefit of U.S. provisional patent application No. 61/940,011, filed on 14/2/2014 in the name of Stanley setchul Song et al, the disclosure of which is expressly incorporated herein by reference in its entirety.

Background

FIELD

Aspects of the present disclosure relate to semiconductor devices, and more particularly, to electrically grounding a gate in a scaled layout design within an integrated circuit.

Background

Interconnect layers are commonly used to connect different devices together on an integrated circuit. As integrated circuits become more complex, more interconnect layers are required to provide electrical connections between devices. Furthermore, as device geometries become smaller, connection to the devices themselves becomes more difficult.

SUMMARY

A semiconductor device according to an aspect of the present disclosure includes a gate and a first active contact adjacent to the gate. Such a device further includes a first stacked contact electrically coupled to the first active contact, the first stacked contact including a first isolation layer on sidewalls electrically isolating the first stacked contact from the gate. The device also includes a first via electrically coupled to the gate and landing on the first stacked contact. The first via electrically couples the first stacked contact and the first active contact to the gate to ground the gate.

A semiconductor device according to another aspect of the present disclosure includes a gate and a first active contact adjacent to the gate. The device also includes extended stacked contacts electrically coupled to and partially overlapping the gate and the first active contact. The extended stacked contact is self-aligned with an adjacent stacked contact to electrically isolate the extended stacked contact from the adjacent stacked contact.

A semiconductor device according to another aspect of the present disclosure includes a gate and a first active contact adjacent to the gate. The device further includes means for electrically coupling to the first active contact, the means including means for isolating the electrically coupling means from the gate. The device also includes a first via electrically coupled to the gate and landing on the electrical coupling means. The first via electrically couples the electrical coupling device and the first active contact to the gate to ground the gate.

A semiconductor device according to another aspect of the present disclosure includes a gate and a first active contact adjacent to the gate. The device also includes means for electrically coupling to and partially overlapping the gate and the first active contact. The coupling device is self-aligned with adjacent stacked contacts to electrically isolate the coupling device from adjacent stacked contacts.

This has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter. It should be appreciated by those skilled in the art that the present disclosure may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the teachings of the disclosure as set forth in the appended claims. The novel features which are believed to be characteristic of the disclosure, both as to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present disclosure.

Brief Description of Drawings

For a more complete understanding of this disclosure, reference is now made to the following descriptions taken in conjunction with the accompanying drawing.

Fig. 1 illustrates a side view of an integrated circuit device including a mid-process interconnect layer.

Fig. 2 illustrates a top view of a semiconductor device including a first gate tie-off scheme within a mid-process interconnect layer.

Fig. 3 illustrates a top view of a semiconductor device including a second gate tie-off scheme within a middle-of-line interconnect layer.

Fig. 4 illustrates a side view of a semiconductor device in order to show the formation of a gate contact to provide a gate tie-down scheme within a middle-of-line interconnect layer, according to one aspect of the present disclosure.

Fig. 5 illustrates a side view of the semiconductor device of fig. 4 to show the formation of a gate contact to provide a gate tie-down scheme within a middle-of-line interconnect layer, according to one aspect of the present disclosure.

Fig. 6 illustrates a side view of the semiconductor device of fig. 5 to show the formation of a gate contact to provide a gate tie-down scheme within a middle-of-line interconnect layer, according to one aspect of the present disclosure.

Fig. 7 illustrates a side view of the semiconductor device of fig. 6 to show the formation of a gate contact to provide a gate tie-down scheme within a middle-of-line interconnect layer, in accordance with an aspect of the present disclosure.

Fig. 8 illustrates a side view of the semiconductor device of fig. 7 in order to show the formation of a gate contact to provide a gate tie-down scheme within a middle-of-line interconnect layer, according to one aspect of the present disclosure.

Fig. 9 illustrates a side view of the semiconductor device of fig. 8 including a gate contact to provide a gate tie-off scheme within a mid-process interconnect layer, according to one aspect of the present disclosure.

Fig. 10 illustrates a side view of the semiconductor device of fig. 9 in order to show the formation of stacked contacts to provide a gate tie-down scheme within a middle-of-line interconnect layer, according to one aspect of the present disclosure.

Fig. 11 illustrates a side view of the semiconductor device of fig. 10 in order to show the formation of stacked contacts to provide a gate tie-off scheme within a middle-of-line interconnect layer, according to one aspect of the present disclosure.

Fig. 12 illustrates a side view of the semiconductor device of fig. 11 in order to show the formation of stacked contacts to provide a gate tie-off scheme within a middle-of-line interconnect layer, according to one aspect of the present disclosure.

Fig. 13 illustrates a side view of the semiconductor device of fig. 12 in order to show the formation of stacked contacts to provide a gate tie-off scheme within a middle-of-line interconnect layer, according to one aspect of the present disclosure.

Fig. 14 illustrates a side view of the semiconductor device of fig. 13 in order to show the formation of stacked contacts for a gate tie-down scheme within a mid-process interconnect layer, according to one aspect of the present disclosure.

Fig. 15 illustrates a side view of the semiconductor device of fig. 14 to show the formation of stacked contacts for a gate tie-down scheme within a mid-process interconnect layer, according to one aspect of the present disclosure.

Fig. 16 illustrates a side view of the semiconductor device of fig. 15 to show the formation of stacked contacts for a gate tie-down scheme within a mid-process interconnect layer, according to one aspect of the present disclosure.

Fig. 17 illustrates a side view of the semiconductor device of fig. 16 to provide stacked contacts of a gate tie down scheme within a mid-process interconnect layer, according to one aspect of the present disclosure.

Fig. 18 illustrates a side view of the semiconductor device of fig. 17 to show the formation of vias to provide a gate tie down scheme within a middle-of-line interconnect layer, in accordance with an aspect of the present disclosure.

Fig. 19 illustrates a side view of the semiconductor device of fig. 18 to show the formation of vias to provide a gate tie down scheme within a middle-of-line interconnect layer, in accordance with an aspect of the present disclosure.

Fig. 20 illustrates a side view of the semiconductor device of fig. 19 in order to show the formation of vias to provide a gate tie down scheme within a middle-of-line interconnect layer, in accordance with an aspect of the present disclosure.

Fig. 21 illustrates a side view of the semiconductor device of fig. 20 in order to show vias to provide a gate tie down scheme within a mid-process interconnect layer, in accordance with an aspect of the present disclosure.

Fig. 22A-22B illustrate cross-sectional and top views of a semiconductor device including a gate tie-down scheme within a middle-of-line interconnect layer to electrically ground a dummy gate, according to one aspect of the present disclosure.

Fig. 23A-23B illustrate cross-sectional and top views of a semiconductor device including a gate tie-down scheme within a mid-process interconnect layer to electrically ground a dummy gate, according to another aspect of the present disclosure.

Fig. 24 is a process flow diagram illustrating electrical grounding of a dummy gate according to one aspect of the present disclosure.

Fig. 25 is a block diagram illustrating an example wireless communication system in which configurations of the present disclosure may be advantageously employed.

Fig. 26 is a block diagram illustrating a design workstation for circuit, layout, and logic design of semiconductor components according to one configuration.

Detailed Description

The detailed description set forth below in connection with the appended drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details in order to provide a thorough understanding of the various concepts. It will be apparent, however, to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts. As used herein, the use of the term "and/or" is intended to mean "facultative or" and the use of the term "or" is intended to mean "exclusive or".

Semiconductor manufacturing processes are generally divided into three parts: front-end-of-line (FEOL), middle-of-line (MOL), and back-end-of-line (BEOL). Front end of line processes include wafer preparation, isolation, well formation, gate patterning, spacers, and dopant implantation. The middle process includes gate and terminal contact formation. However, the middle of line gate and terminal contact formation is an increasingly challenging part of the fabrication flow, especially for lithographic patterning. The back-end-of-line process includes forming interconnects and dielectric layers for coupling to FEOL devices. These interconnects may be fabricated with a dual damascene process using an interlayer dielectric (ILD) material deposited using Plasma Enhanced Chemical Vapor Deposition (PECVD).

More recently, the number of interconnect stages for circuitry has increased dramatically due to the large number of transistors that are interconnected today in modern microprocessors. The increased number of interconnect levels used to support the increased number of transistors involves more intricate middle of line processes to perform gate and terminal contact formation.

As described herein, a middle-of-line interconnect layer may refer to an Oxide Diffusion (OD) layer used to connect a first conductive layer (e.g., metal 1(M1)) to an integrated circuit and a conductive interconnect used to connect M1 to an active device of the integrated circuit. The middle of the line interconnect layers used to connect M1 to the OD layer of the integrated circuit may be referred to as "MD 1" and "MD 2". The middle of line interconnect layer used to connect M1 to the polysilicon (conductive) gate of the integrated circuit may be referred to as "MP".

In some circuits, such as electrostatic discharge (ESD) or high speed devices, an additional gate, called a "dummy gate," is used to control the device. To prevent any floating bias voltage from activating the device, the dummy gate may be electrically coupled (tied) to ground. The dummy gate may be tied to the source of the adjacent FET device, which is referred to as a "dummy gate tie scheme".

Another way to couple the dummy gate to ground is to terminate the side of the source region where the dummy gate is located, which prevents the dummy gate from forming a drain contact. This is called "diffusion break (break) method". The diffusion break method typically uses two dummy gates, one on each side of the broken active region.

One aspect of the present disclosure allows for a small and scalable design rule spacing between active and dummy gates by merging a gate contact (e.g., metal to poly-silicon (MP)) to a first stacked contact (e.g., metal to diffusion (MD) contact) that contacts a source contact in an adjacent device. By combining these two contacts, other adjacent MD1 active contacts are not affected when the design rules scale down. However, in related art schemes, the overlap of the gate and dummy gate contacts overlaps with narrow spacing to other adjacent MD1 active contacts and results in difficulty in manufacturing or using larger layout areas to provide spacing between gates.

Fig. 1 shows a cross-sectional view illustrating an Integrated Circuit (IC) device 100 in which conductive layer routing is performed within a middle of line (MOL) interconnect layer 110, according to one aspect of the present disclosure. The IC device 100 includes a semiconductor substrate (e.g., a silicon wafer) 102 having Shallow Trench Isolation (STI) regions (e.g., an isolation layer 104). Within the STI regions and substrate 102 are active regions in which active devices having source, drain, and gate regions (e.g., conductive gate 106) are formed.

In fig. 1, the first MOL interconnect layer 110 includes a set of active (oxide diffusion (OD)) contacts, shown as MD 1112-1, 112-2, 112,3, 112-4, and 112-5 (collectively or generically referred to as MD 1112), commonly referred to as metal diffusion (MD1) contacts. MD1 active contact 112 is fabricated using substrate 102 technology. The active contacts 112 may be coupled to active devices (e.g., source and drain regions). In this configuration, routing of the conductive layer may be performed to ground the dummy gate to one of the active contacts 112. The first MOL conductive layer may be comprised of tungsten or other similar conductive material.

Fig. 2 illustrates a top view of a semiconductor circuit including a first gate tie-off scheme within a mid-process interconnect layer. Representatively, the conductive grid 106 is interwoven with, for example, MD1 active contacts 112-2 and MD1 active contacts 112-3. The configuration in fig. 2 is sometimes referred to as a continuous od (cnod) scheme. In some circuits, one of the conductive gates 106 is connected as a gate that may be referred to herein as a dummy gate 210 using a gate contact 200 (e.g., metal to poly-silicon (MP)). In small geometry circuitry, the distance 202 is designed to be at or near the limits of the design geometry constraints. In this arrangement, the distance 204 between gate contact 200 and MD1 active contact 112-3 may not be sufficient to prevent a short circuit. In particular, as the spacing between gates becomes smaller, there is an increased risk that gate contact 200 will electrically connect to more than MD1 active contacts 112. For example, when distance 204 is too small, gate contact 200 may connect to both MD1 active contact 112-2 and MD 1112-3 active contact.

Fig. 3 illustrates a top view of a semiconductor circuit including a second gate tie scheme within a middle-of-line interconnect layer. In this arrangement, a diffusion break (discontinuous OD) scheme is provided in which the OD is broken or disconnected between adjacent devices. This allows for some misalignment between gate contact 200 and MD1 active contact 112. However, the method shown in fig. 3 uses an additional gate 300 added to the device, which increases the distance 302 due to the additional spacing 304 between the devices. Distance 302 limits the number of devices per unit area, which may be undesirable or infeasible for certain applications.

Fig. 4-21 illustrate cross-sectional views of an exemplary process that provides a gate tie down scheme within a middle-of-line interconnect layer in order to electrically ground a dummy gate, according to aspects of the present disclosure. Although a dummy gate is described, a functional gate may be substituted.

Fig. 4 illustrates a side view of a semiconductor device in accordance with an aspect of the present disclosure to show the formation of a gate contact 810 (fig. 9) to provide a gate tie-down scheme within a mid-process interconnect layer. Representatively, a first active contact 220 (e.g., MD 1112) is shown with a dummy gate 210 as a neighbor. A hard mask 400 is formed on the surface of isolation layer 104. In addition, a photoresist layer 402 is formed on the hard mask 400. The photoresist layer 402 is then patterned according to pattern 404.

Fig. 5 illustrates a side view of the semiconductor device of fig. 4 in order to illustrate the formation of a gate contact 810 (fig. 9) to provide a gate tie-off scheme within a mid-process interconnect layer in accordance with an aspect of the present disclosure. Representatively, an etch 500 of the hard mask 400 is shown. This etch exposes the dummy gate 210 and a portion of the first active contact 220. An etch of the hard mask 400 is performed to enable the formation of a gate contact 810, as shown in fig. 9. In another aspect of the present disclosure, the via may fall directly on the dummy gate 210 without the gate contact 810.

Fig. 6 illustrates a side view of the semiconductor device of fig. 5 in order to show the formation of a gate contact 810 (fig. 9) to provide a gate tie-off scheme within a mid-process interconnect layer, according to one aspect of the present disclosure. This arrangement illustrates the removal of the photoresist layer 402. Once removed, liner material is deposited on the hard mask 400 to form the liner 600, the liner 600 may be a self-aligned liner. In this configuration, the liner 600 is disposed on the hard mask 400 and within the opening exposing the dummy gate 210. The liner 600 may ensure that there is no electrical contact to the first active contact 220 adjacent to the dummy gate 210.

Fig. 7 illustrates a side view of the semiconductor device of fig. 6 to show the formation of a gate contact 810 (fig. 9) to provide a gate tie-off scheme within a mid-process interconnect layer, in accordance with an aspect of the present disclosure. Representatively, the etch 700 removes the liner 600 from the hard mask 400. The etch 700 may be an isotropic etch in that the liner 600 remains within the opening exposing the dummy gate 210 to provide a spacer for the opening exposing the dummy gate 210. In this arrangement, the liner 600 provides spacers to enable the dummy gate 210 to be grounded to the first active contact 220 at the mid-line interconnect level.

Fig. 8 illustrates a side view of the semiconductor device of fig. 7 in order to show the formation of a gate contact 810 (fig. 9) to provide a gate tie-off scheme within a mid-process interconnect layer, according to one aspect of the present disclosure. In this arrangement, a conductive material is deposited on the hard mask 400 and within the opening exposing the dummy gate 210 to form the conductive layer 800. The conductive layer 800, which may be tungsten, copper, or another conductive material, is coupled to the hard mask 400, the liner 600, and the dummy gate 210.

Fig. 9 illustrates a side view of the semiconductor device of fig. 8 including a gate contact 810 to provide a gate tie-off scheme within a mid-process interconnect layer, according to one aspect of the present disclosure. Representatively, an etch 900 is performed to remove the conductive layer 800. In addition, the etch 900 may planarize the surface 902 of the isolation layer 104 with the conductive layer 800. In this configuration, the etching forms a gate contact 810 that is self-aligned to the first active contact 220. In this configuration, liner 600 is on opposing sidewalls of gate contact 810. The etching may be performed by using Chemical Mechanical Planarization (CMP).

Figure 10 illustrates a side view of the semiconductor device of figure 9 to illustrate the formation of the first stacked contact 1310 (figure 14) to provide a gate tie down scheme within a middle-of-line interconnect layer, according to one aspect of the present disclosure. In this arrangement, a hard mask 1000 is formed on a surface 902 of isolation layer 104. Additionally, a dielectric layer 1002 is deposited on the hard mask 1000.

Figure 11 illustrates a side view of the semiconductor device of figure 10 to illustrate the formation of the first stacked contact 1310 (figure 14) to provide a gate tie down scheme within a middle-of-line interconnect layer, according to one aspect of the present disclosure. Representatively, the dielectric layer 1002 is patterned to define a first stacked contact 1310 (FIG. 14). Specifically, an etch is then performed to selectively remove dielectric layer 1002 and hard mask 1000, thereby forming opening 1100. The opening 1100 exposes the first active contact 220 at the surface 902 of the isolation layer 104. In this configuration, the opening 1100 is offset from the first active contact 220. The liner 600 provides some flexibility and some misalignment in processing so that electrical coupling between the dummy gate 210 and the first active contact 220 can be avoided, if desired.

Figure 12 illustrates a side view of the semiconductor device of figure 11 to illustrate the formation of the first stacked contact 1310 (figure 14) to provide a gate tie down scheme within a middle-of-line interconnect layer, according to one aspect of the present disclosure. In this arrangement, liner 1200 is deposited on the dielectric layer and within opening 1100 to provide stacked contact opening 1202. Liner 1200 may be a self-aligned liner with respect to dielectric layer 1002. In this arrangement, the liner 1200 of the first stacked contact 1310 may be self-aligned to the liner 600 and/or the gate contact 810. In another aspect of the present disclosure, the gate contact 810 is removed to allow for vias that fall over the dummy gate 210 and the active contact 220.

Figure 13 illustrates a side view of the semiconductor device of figure 12 to illustrate the formation of the first stacked contact 1310 (figure 14) to provide a gate tie down scheme within a middle-of-line interconnect layer, according to one aspect of the present disclosure. Representatively, an etch of liner 1200 on dielectric layer 1002 is performed. Once completed, conductive material 1300 is deposited on dielectric layer 1002 and within stacked contact openings 1202. In this configuration, the liner 1200 is self-aligned to at least one side of the gate contact 810. As a result, the liner 1200 provides additional electrical insulation between the first active contact 220 and the dummy gate 210, if desired.

Figure 14 illustrates a side view of the semiconductor device of figure 13 to show the formation of a first stacked contact 1310 of a gate tie down scheme within a mid-process interconnect layer, according to one aspect of the present disclosure. In this arrangement, an etch 1400 is performed to selectively remove the conductive material 1300 from the surface 1402 of the dielectric layer 1002. The etch 1400 may be a Chemical Mechanical Planarization (CMP). The etch 1400 may also planarize the surface 1402 with the surface of the conductive material 1300 to form the first stacked contact 1310. In this configuration, the liner 1200 is on the sidewalls of the first stacked contact 1310 and is self-aligned to at least one edge of the liner of the gate contact 810.

Figure 15 illustrates a side view of the semiconductor device of figure 14 to show the formation of a first stacked contact 1310 of a gate tie down scheme within a mid-process interconnect layer, according to one aspect of the present disclosure. Representatively, an etch 1500 of the first stacked contact is performed. In this configuration, the etch 1500 recesses the conductive material 1300 and the level of the liner 1200 of the first stacked contact 1310 away from the surface 1402 of the dielectric layer 1002.

Figure 16 illustrates a side view of the semiconductor device of figure 15 to show the formation of a first stacked contact 1310 of a gate tie down scheme within a mid-process interconnect layer, according to one aspect of the present disclosure. Representatively, a liner 1600 is formed on a surface 1402 of dielectric layer 1002. Liner 1600 is also formed on the recessed portions of conductive material 1300 and liner 1200. In this arrangement, the liner 1600 provides a recessed spacer layer on the first stacked contact 1310.

Figure 17 illustrates a side view of the semiconductor device of figure 16 to provide a first stacked contact 1310 of a gate tie down scheme within a mid-process interconnect layer, according to one aspect of the present disclosure. In this arrangement, an etch 1700 of the liner 1600 is performed to expose the surface 1702. Surface 1702 may be at the same level as surface 1402 of dielectric layer 1002, but may be at a different level within dielectric layer 1002 if desired. In this configuration, the first stacked contact 1310 includes a liner 1600 to provide a cap layer or other similar protective layer.

Fig. 18 illustrates a side view of the semiconductor device of fig. 17 in order to show the formation of a via 2000 (fig. 20) to provide a gate tie-off scheme within a mid-process interconnect layer, according to an aspect of the present disclosure. Representatively, additional growth of dielectric layer 1002 is shown. Etching of dielectric layer 1002 is also performed. The pattern used in etching the dielectric layer 1002 may be self-aligned to the etch used to form the opening 1100, including the liner 1200 (as a spacer) and the conductive material 1300. The etch of dielectric layer 1002 and hard mask 1000 to form first opening 1800 exposes gate contact 810 and, if desired, a portion of liner 1600. In another configuration, when the gate contact is removed, the etch may expose the dummy gate 210 to allow the via 2000 to fall directly on the dummy gate 210.

Fig. 19 illustrates a side view of the semiconductor device of fig. 18 to show the formation of a via 2000 to provide a gate tie-off scheme within a middle-of-line interconnect layer, in accordance with an aspect of the present disclosure. In this arrangement, the etch removes an additional portion of the dielectric layer 1002 and a portion of the liner 1600 to form a first opening 1800. Subsequent etching forms a second opening 1900 exposing the first stacked contact 1310. As noted, this subsequent etch may be performed to directly expose the dummy gate 210.

Fig. 20 illustrates a side view of the semiconductor device of fig. 19 in order to show the formation of a via 2000 to provide a gate tie-off scheme within a middle-of-line interconnect layer, according to an aspect of the present disclosure. In this arrangement, the via 2000 is formed by filling the first opening 1800 and the second opening 1900 with a conductive material. A conductive material is deposited over the first stacked contact 1310 and the gate contact 810 to form the via 2000. This electrically couples the first active contact 220 and the dummy gate 210 by bonding the first stacked contact 1310 and the gate contact 810 together with the via 2000. In another configuration, the via 2000 electrically couples the first active contact 220 and the dummy gate 210 by landing on both the first stacked contact 1310 and the dummy gate 210 without the gate contact 810 (i.e., without providing a gate contact).

Fig. 21 illustrates a side view of the semiconductor device of fig. 20 in order to show a via 2000 to provide a gate tie-off scheme within a middle-of-line interconnect layer, in accordance with an aspect of the present disclosure. Representatively, deposition of capping layer 2100 on the surfaces of via 2000 and dielectric layer 1002 is performed. If desired, the etch may stop before the liner 1600 is removed, which will electrically isolate the first active contact 220 from the dummy gate 210.

One aspect of the present disclosure allows for a small and scalable design rule spacing between MD1 active contacts 112 and dummy gates 210 by merging gate contacts 810 (e.g., metal to poly-silicon (MP)) to first stacked contacts 1310 (e.g., metal to diffusion (MD) contacts) that contact neighboring devices. By combining these two contacts, other adjacent MD1 active contacts 112 are not affected when the design rules scale down. However, in related art schemes, the overlap of the gate and dummy gate contacts overlaps with narrow spacing to other adjacent MD1 active contacts 112 and results in difficulty in manufacturing or using larger layout area to provide spacing between gates.

Fig. 22A-23B illustrate cross-sectional views of a semiconductor device providing a gate tie-down scheme within a mid-process interconnect layer to electrically ground a virtual gate, according to aspects of the present disclosure.

Fig. 22A-23B illustrate cross-sectional and top views of a semiconductor device including a gate tie scheme to electrically ground the dummy gate 210. As shown in fig. 22A, the via 2200 couples to the conductive gate 106 and allows for external or interconnect coupling to the via 2200, the via 2200 is electrically isolated from the second stacked contact 1320 due to the liner 1600 on the surface of the second stacked contact 1320. Since the vias 2200 are self-aligned to the liner 1600 and the second stacked contact 1320, the vias 2200 are also isolated from the MD1 active contacts 112-4. The liner 1200 on the sidewalls of the second stacked contacts 1320 also electrically isolates the vias 2200 from the second stacked contacts 1320, as shown in the top view of fig. 22B.

Referring again to fig. 22A, another via 2202 is coupled to MD1 active contact 112-3 via third stacked contact 1330. Since via 2202 is self-aligned to third stacked contact 1330, via 2202 is electrically isolated from other connections. The vias 2000 couple the first active contact 220 to the dummy gate 210 by coupling a portion of the first stacked contact 1310 to the gate contact 810 of the dummy gate 210, as described in figures 4-21.

In another aspect of the present disclosure, the via 2000 can be formed prior to etching of the liner 1600. The liner 1600 may also electrically isolate the first active contact 220 from the gate contact 810 of the dummy gate 210. Since another MD 1112 active contact may be placed as another neighbor of the dummy gate 210, it is possible to connect the dummy gate 210 to a first active contact 220 while isolating the dummy gate 210 from another adjacent active contact 220. In this arrangement, the vias 2000 are self-aligned with adjacent active contacts 220.

Fig. 23A-23B illustrate cross-sectional and top views of a semiconductor device including a gate tie-down scheme within a mid-process interconnect layer to electrically ground the dummy gate 210, according to another aspect of the present disclosure. As shown in fig. 23A,

vias

2200 and 2202 are similar to those depicted in fig. 22A and 22B. However, an extended stacked contact 2300 may couple the first active contact 220 to the gate contact 810 to electrically ground the dummy gate 210. Because the extended stacked contact 2300 is formed using the same mask as the adjacent stacked contact 2302, the extended stacked contact 2300 is electrically isolated from the adjacent stacked contact 2302. This allows connection of the first active contact 220 and the dummy gate 210 at different levels of interconnect within the device. Furthermore, because the extended stacked contact 2300 and the adjacent stacked contact 2302 are self-isolating, strict design rules may be used to form the extended stacked contact 2300. In a conventional process window, the extended stacked contact 2300 would not connect to the gate contact 810 of the dummy gate 210.

Fig. 24 is a process flow diagram illustrating a method 2400 for grounding a gate in an active region of a device. In block 2402, a first active contact is formed adjacent to the gate. For example, as shown in fig. 4-6, a first active contact 220 is adjacent to the dummy gate 210. In block 2404, a first stacked contact electrically coupled to the first active contact is formed. For example, as shown in figures 13-15, the first stacked contact 1310 is coupled to the first active contact 220. In block 2406, a first isolation layer is deposited on sidewalls of the first stacked contact and self-aligned to the gate to at least partially overlap the first active contact. The electrical isolation may be provided by the liner 1200 located on the sidewalls of the first stacked contact 1310.

According to a further aspect of the present disclosure, a semiconductor device is described. The device includes a gate and a first active contact adjacent to the gate. The device further comprises means for electrically coupling to the first active contact, the means comprising means for isolating the electrically coupling means from the gate, the coupling means may be a via 2000 as shown in fig. 21. The device also includes a first via electrically coupled to the gate and landing on the electrical coupling means to electrically couple the electrical coupling means and the first active contact to the gate to ground the gate. In another aspect, the aforementioned means may be any module or any device configured to perform the functions recited by the aforementioned means.

According to a further aspect of the disclosure, a device is described having a gate coupled to an adjacent contact in an active region of the device. The device includes a gate and a first active contact adjacent to the gate. The device also includes means for electrically coupling to and at least partially overlapping the gate and the first active contact. The coupling device is self-aligned with an adjacent stacked contact to electrically isolate the coupling device from the adjacent stacked contact. The device may be an extended stacked contact 2300 as shown in figure 23. In another aspect, the aforementioned means may be any module or any device configured to perform the functions recited by the aforementioned means.

In a further aspect of the disclosure, a device having a gate electrically grounded in a device active region is described. In one configuration, the device includes means for electrically coupling a portion of the first stacked contact and the first gate contact while remaining electrically isolated from other portions of the first stacked contact. The device may be the through hole 2000 shown in fig. 21. In another aspect, the aforementioned means may be any module or any device configured to perform the functions recited by the aforementioned means.

According to a further aspect of the disclosure, a device is described having a gate coupled to an adjacent contact in an active region of the device. The device includes means for at least partially overlapping a selected portion of the second contact and a selected portion of the first contact, the means being self-aligned to the first contact and self-isolated in the means. The device may be an extended stacked contact 2300 as shown in figure 23. In another aspect, the aforementioned means may be any module or any device configured to perform the functions recited by the aforementioned means.

Fig. 25 is a block diagram illustrating an example wireless communication system 2500 in which an aspect of the present disclosure may be advantageously employed. For purposes of illustration, fig. 25 shows three

remote units

2520, 2530, and 2550 and two base stations 2540. It will be appreciated that a wireless communication system may have many more remote units and base stations than there are.

Remote units

2520, 2530 and 2550 include

IC devices

2525A, 2525C and 2525B, including the disclosed devices. It will be appreciated that other devices may also include the disclosed devices, such as base stations, switching devices, and network equipment. Figure 25 shows forward link signals 2580 from the base stations 2540 to the

remote units

2520, 2530 and 2550 and reverse link signals 2590 from the

remote units

2520, 2530 and 2550 to the base stations 2540.

In FIG. 25, the remote unit 2520 is illustrated as a mobile telephone, the remote unit 2530 is illustrated as a portable computer, and the remote unit 2550 is illustrated as a fixed location remote unit in a wireless local loop system. For example, the remote units may be mobile phones, hand-held Personal Communication Systems (PCS) units, portable data units such as personal data assistants, GPS enabled devices, navigation devices, set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, or other devices that store or retrieve data or computer instructions, or a combination thereof. Although fig. 25 illustrates remote units according to aspects of the disclosure, the disclosure is not limited to these exemplary illustrated units. Aspects of the disclosure may be suitably employed in a number of devices that include the disclosed apparatus.

Fig. 26 is a block diagram illustrating a design workstation for circuit, layout, and logic design of a semiconductor component, such as the device disclosed above. Design workstation 2600 includes a hard disk 2601, the hard disk 2601 containing operating system software, support files, and design software (such as Cadence or OrCAD). The design workstation 2600 also includes a display 2602 that facilitates the design of the pair of circuits 2610 or semiconductor assemblies 2612 (such as devices according to an aspect of the present disclosure). A storage medium 2604 is provided for tangibly storing a design of the circuit 2610 or the semiconductor assembly 2612. The design of circuit 2610 or semiconductor component 2612 may be stored on storage medium 2604 in a file format, such as GDSII or GERBER. The storage medium 2604 may be a CD-ROM, DVD, hard disk, flash memory, or other suitable device. In addition, design workstation 2600 includes a drive 2603 for accepting input from storage medium 2604 or writing output to storage medium 2604.

The data recorded on the storage medium 2604 may specify a logic circuit configuration, pattern data for a lithography mask, or mask pattern data for a serial writing tool (such as e-beam lithography). The data may further include logic verification data associated with the logic simulation, such as timing diagrams or net circuits. Providing data on storage medium 2604 facilitates the design of circuit 2610 or semiconductor assembly 2612 by reducing the number of processes used to design semiconductor wafers.

For a firmware and/or software implementation, the methodologies may be implemented with modules (e.g., procedures, functions, and so on) that perform the functions described herein. A machine-readable medium tangibly embodying instructions may be used to implement the methodologies described herein. For example, software codes may be stored in a memory and executed by a processor unit. The memory may be implemented within the processor unit or external to the processor unit. As used herein, the term "memory" refers to long term, short term, volatile, nonvolatile, or other types of memory and is not to be limited to a particular type of memory or number of memories, or type of media upon which memory is stored.

If implemented in firmware and/or software, the functions may be stored as one or more instructions or code on a computer-readable medium. Examples include computer-readable media encoded with a data structure and computer-readable media encoded with a computer program. Computer-readable media includes physical computer storage media. A storage media may be a available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer; disk (disk) and disc (disc), as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

In addition to being stored on a computer-readable medium, the instructions and/or data may also be provided as signals on a transmission medium included in the communication device. For example, the communication device may include a transceiver having signals indicative of instructions and data. The instructions and data are configured to cause one or more processors to implement the functions recited in the claims.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the technology of the disclosure as defined by the appended claims. For example, relational terms such as "above" and "below" are used with respect to a substrate or an electronic device. Of course, if the substrate or electronic device is turned upside down, the upper side becomes the lower side, and vice versa. Further, if laterally oriented, above and below may refer to the sides of a substrate or electronic device. Moreover, the scope of the present application is not intended to be limited to the particular configurations of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding configurations described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

The steps of a method or algorithm described in connection with the disclosure may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM, flash memory, ROM, EPROM, EEPROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.

In one or more exemplary designs, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media, including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to carry or store specified program code means in the form of instructions or data structures and which can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a web site, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk (disk) and disc (disc), as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk and blu-ray disc where disks (disks) usually reproduce data magnetically, while discs (discs) reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A semiconductor device, comprising:

a dummy gate in an active region of the semiconductor device;

a first active contact adjacent to the dummy gate;

a dielectric layer on the dummy gate and the first active contact, the dielectric layer having an opening formed therein;

a first isolation layer deposited on sidewalls of the opening;

a first stacked contact formed in the opening, the first stacked contact being electrically coupled to the first active contact;

a capping layer deposited on a surface of the first stacked contact opposite the first active contact, the first isolation layer on sidewalls electrically isolating the first stacked contact from the dummy gate; and

a first via through the dielectric layer, the first via landing on the dummy gate and directly landing on the surface of the first stacked contact through a portion of the capping layer to electrically couple the first stacked contact and the first active contact to the dummy gate to ground the dummy gate.

2. The semiconductor device of claim 1, further comprising:

a gate contact directly coupled between the dummy gate and the first via, the gate contact having a second isolation layer on sidewalls, the gate contact being self-aligned to the first active contact and to the first stacked contact.

3. The semiconductor device of claim 1, further comprising:

a second active contact adjacent to the dummy gate; and

an adjacent stacked contact electrically coupled to and aligned with the second active contact and self-aligned with the first via to electrically isolate the adjacent stacked contact from the first via.

4. The semiconductor device of claim 2, in which the first via and the gate contact are self-aligned, and the first isolation layer on the sidewall of the first stacked contact is arranged to at least partially overlap the first active contact, an overlapping portion of the first isolation layer electrically isolating a portion of the first stacked contact from a portion of the first via.

5. The semiconductor device of claim 1, further comprising:

an active gate electrode;

a second active contact adjacent to the active gate;

a second stacked contact electrically coupled to the second active contact and including a second isolation layer on a sidewall electrically isolating the second stacked contact from the active gate; and

a second via electrically coupled to the active gate and self-aligned with the second stacked contact.

6. The semiconductor device of claim 1, integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held Personal Communication Systems (PCS) unit, a portable data unit, and/or a fixed location data unit.

7. A semiconductor device, comprising:

a dummy gate in an active region of the semiconductor device;

first and second active contacts on each side of and adjacent to the dummy gate; and

a dielectric layer over the dummy gate and the first and second active contacts, the dielectric layer having a first opening and a second opening formed therein;

a first isolation layer deposited on sidewalls of the first and second openings;

an extended stacked contact formed in the first opening through the dielectric layer and electrically coupled directly to a gate contact of the dummy gate and the first active contact, the extended stacked contact arranged to ground the dummy gate by at least partially overlapping both the dummy gate and the first active contact; and

an adjacent stacked contact formed in the second opening through the dielectric layer and directly electrically coupled to a second active contact, wherein the extended stacked contact is electrically isolated from the adjacent stacked contact.

8. The semiconductor device of claim 7, further comprising:

an active gate electrode;

a third active contact adjacent to the active gate;

a first stacked contact through the dielectric layer and electrically coupled to the third active contact, the first stacked contact including an isolation layer on sidewalls electrically isolating the first stacked contact from the active gate; and

a via electrically coupled to the active gate and electrically isolated from the first stacked contact by the isolation layer, through the dielectric layer.

9. The semiconductor device of claim 7, integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held Personal Communication Systems (PCS) unit, a portable data unit, and/or a fixed location data unit.

10. A method for electrically grounding a dummy gate in an active area of a semiconductor device, comprising:

forming a first active contact adjacent to the dummy gate in the active region of the semiconductor device;

forming a dielectric layer on the dummy gate and the first active contact;

forming an opening on the dielectric layer;

depositing a first isolation layer on the side wall of the opening;

forming a first stacked contact in the opening, the first stacked contact electrically coupled to the first active contact;

depositing a capping layer on a surface of the first stacked contact; and

forming a first via through the dielectric layer, the first via landing on the dummy gate and directly landing on the surface of the first stacked contact through a portion of the capping layer to electrically couple the first stacked contact and the first active contact to the dummy gate to ground the dummy gate.

11. The method of claim 10, in which a portion of the first isolation layer is arranged to electrically isolate the first stacked contact from the dummy gate.

12. The method of claim 11, further comprising:

forming a grid contact on the virtual grid; and

depositing the first isolation layer on sidewalls of the gate contact, the gate contact being self-aligned to the first active contact and self-aligned to the first stacked contact, wherein the first stacked contact is electrically isolated from the gate contact by the first isolation layer, and wherein the first via lands on the gate contact.

13. The method of claim 10, in which a portion of the first stacked contact is electrically coupled to a portion of the dummy gate, the first stacked contact and an adjacent stacked contact being self-aligned to electrically isolate the adjacent stacked contact from the first stacked contact.

14. The method of claim 13, further comprising:

forming a grid contact on the virtual grid; and

depositing the first isolation layer on sidewalls of the gate contact, the gate contact self-aligned to the first active contact.

15. The method of claim 10, in which the semiconductor device is integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held Personal Communication Systems (PCS) unit, a portable data unit, and/or a fixed location data unit.