CN105978551A - Chaotic circuit - Google Patents
Chaotic circuit Download PDFInfo
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- CN105978551A CN105978551A CN201610273971.2A CN201610273971A CN105978551A CN 105978551 A CN105978551 A CN 105978551A CN 201610273971 A CN201610273971 A CN 201610273971A CN 105978551 A CN105978551 A CN 105978551A
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- Prior art keywords
- circuit
- pmos
- nmos tube
- drain electrode
- grid
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
Abstract
The invention discloses a 7-pipe MOS chaotic circuit of ultra-Low voltage power supply. In the invention, the chaotic circuit constructed based on two single frequency generation modules and one non-linear module is simplified. A core circuit is a 3-pipe active inductance circuit. A 4-pipe frequency generation circuit is used to output one path of basic frequency signal. Compared to the prior art, by using the circuit of the invention, a chaotic circuit structure realized through a known MOS pipe is greatly simplified; a design principle fully uses a 3-pipe MOS to realize an active inductor; simultaneously, an appropriate feed-in point of a feedback line is found so that one independent frequency generation circuit can be saved and a purpose of gradually simplifying the circuit structure to be a 7 pipe is reached; and simultaneously time domain complexity and a continuous bandwidth frequency spectrum characteristic realizing chaos simulation respectively are reserved.
Description
Technical field
The application relates to electronic circuit design field, more particularly, it relates to a kind of chaos circuit.
Background technology
In recent years, along with encoding and decoding and the continuation of the journey demand of miniature monitoring probe, new chaotic signal produces
Circuit enjoys favor.
Current chaos circuit is based primarily upon amplifier structure and realizes, and on the one hand needs multiple operational amplifier,
The multiple inductance of the requisite needs of another aspect or diode, components and parts required in its circuit structure
Number more, the especially number of metal-oxide-semiconductor is more, and this will cause the structure ratio of traditional chaos circuit
More complicated.
Summary of the invention
In view of this, the application provides a kind of chaos circuit, based on 7 metal-oxide-semiconductors, 1 resistance and 1
Individual electric capacity builds chaos circuit, simplifies the circuit structure of chaos circuit.
To achieve these goals, it is proposed that scheme as follows:
A kind of chaos circuit, including: frequency generating circuit and Active inductor circuit；
Wherein, described frequency generating circuit includes: the first PMOS, the first NMOS tube, the 2nd NMOS
Pipe, the 3rd NMOS tube, electric capacity and resistance；
The grid of described first PMOS, the grid of described first NMOS tube, described second NMOS tube
Grid be connected with described electric capacity, and ground connection；
The source electrode of described first PMOS is connected with the substrate of self, and is connected with power supply, and described first
The drain electrode of PMOS is connected with the drain electrode of described first NMOS tube；
The source electrode of described first NMOS tube is connected with the substrate of self, and with the leakage of described second NMOS tube
The most connected；
The source electrode of described second NMOS tube is connected with the substrate of self, and ground connection；
One end of described resistance is connected with the grid of described first PMOS, the other end and described first
The drain electrode of PMOS is connected；
The drain electrode of described 3rd NMOS tube is connected with power supply, the drain electrode phase of source electrode and described second NMOS tube
Even, grid is connected with the drain electrode of described first PMOS, and the grid of described 3rd NMOS tube is described mixed
First signal output part of ignorant circuit；
Described Active inductor circuit includes: the second PMOS, the 3rd PMOS and the 4th NMOS tube；
The grid of described second PMOS, the grid of described 3rd PMOS and described 4th NMOS
The grid of pipe is connected；
The source electrode of described second PMOS is connected with the substrate of self, and is connected with power supply, and described second
The drain electrode of PMOS is connected with the source electrode of described 3rd PMOS, and the drain electrode of described second PMOS is
The secondary signal outfan of described chaos circuit；
The source electrode of described 3rd PMOS is connected with the substrate of self, the drain electrode of described 3rd PMOS with
The drain electrode of described 4th NMOS tube is connected；
The source electrode of described 4th NMOS is connected with the substrate of self, and ground connection, described 4th NMOS tube
Drain electrode is the 3rd signal output part of described chaos circuit；
Wherein, described frequency generating circuit with the circuit connecting relation of described Active inductor circuit is:
In the grid of described 3rd NMOS tube in described frequency generating circuit and described Active inductor circuit
Described second PMOS grid be connected；
In the substrate of described 3rd NMOS tube in described frequency generating circuit and described Active inductor circuit
Described 4th NMOS tube drain electrode be connected.
Preferably, the supply voltage of described power supply is 300mV～500mV.
Preferably, the breadth length ratio of described first PMOS is 2.5mm/200nm；
The breadth length ratio of described first NMOS tube is 1.5mm/500nm；
The breadth length ratio of described second NMOS tube is 2.2mm/500nm；
The breadth length ratio of described 3rd NMOS tube is 2mm/500nm；
The breadth length ratio of described second PMOS is 100 μm/500nm；
The breadth length ratio of described 3rd PMOS is 1.5mm/500nm；
The breadth length ratio of described 4th NMOS tube is 500 μm/500nm.
Preferably, the Standard resistance range of described resistance is 7M Ω～10M Ω.
Preferably, the capacitance value range of described electric capacity is 23pF～33pF.
Through as shown from the above technical solution, this application discloses the 7 pipe MOS chaos electricity that extra low voltage is powered
Road.This invention simplifies the chaos constructed based on two unifrequency generation modules and a nonlinear block
Circuit, described core circuit is 3 pipe Active inductor circuit, utilizes 4 pipe frequency generating circuits to export a roadbed
Plinth frequency signal.Compared with prior art, the present invention simplifies the mixed of known metal-oxide-semiconductor realization significantly
Ignorant circuit structure, design principle takes full advantage of 3 pipe MOS and realizes active inductance, simultaneously as have found anti-
The suitable load point of feeder line, can save an independent frequency generating circuit, just can reach progressively to change
Letter circuit structure is the purpose of 7 pipes, remains the time domain complexity realizing simulation chaos respectively with continuous simultaneously
Bandwidth spectrum characteristic.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to reality
Execute the required accompanying drawing used in example or description of the prior art to be briefly described, it should be apparent that below,
Accompanying drawing in description is only embodiments of the invention, for those of ordinary skill in the art, not
On the premise of paying creative work, it is also possible to obtain other accompanying drawing according to the accompanying drawing provided.
Fig. 1 shows the electrical block diagram of a kind of chaos circuit of the present invention；
Fig. 2 shows that the first signal output part of a kind of chaos circuit of the present invention and secondary signal outfan are defeated
The signal time-domain diagram of the chaotic signal gone out；
Fig. 3 shows the frequency of the chaotic signal of the first signal output part output of a kind of chaos circuit of the present invention
Territory figure；
Fig. 4 shows the frequency of the chaotic signal of the secondary signal outfan output of a kind of chaos circuit of the present invention
Territory figure；
Fig. 5 shows the frequency of the chaotic signal of the 3rd signal output part output of a kind of chaos circuit of the present invention
Territory figure.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out
Clearly and completely describe, it is clear that described embodiment is only a part of embodiment of the present invention, and
It is not all, of embodiment.Based on the embodiment in the present invention, those of ordinary skill in the art are not doing
Go out the every other embodiment obtained under creative work premise, broadly fall into the scope of protection of the invention.
In chaos produces circuit, single tube Colpitts chaos circuit structure is the most succinct, however it is necessary that inductance,
Technique is difficult to integrated, and other metal-oxide-semiconductor chaos circuit is based primarily upon amplifier structure, it appears the most complicated,
And it is generally required to diode or inductance, this all will cause the structure of conventional MOS pipe chaos circuit to seem
Still complicated.
To sum up, in order to promote the development simplifying most structure of metal-oxide-semiconductor Generation of Chaotic Signals, meet main
The urgent demand that new chaotic signal in the sport technique segments such as dynamic measurement produces, directs the integrated water of metal-oxide-semiconductor concretely
Flat simulation chaotic signal produces the innovative design reference of special IC, has just possessed far-reaching reality
Engineering significance.
See Fig. 1 and show the circuit structure signal of a kind of chaos circuit disclosed in one embodiment of the invention
Figure.
This chaos circuit includes 2 circuit modules, i.e. frequency generating circuit and Active inductor circuit.
Wherein, described frequency generating circuit includes: the first PMOS PM1, the first NMOS tube NM1,
Second NMOS tube NM2, the 3rd NMOS tube NM3, electric capacity C and resistance R.
Active inductor circuit includes: the second PMOS PM2, the 3rd PMOS PM3 and the 4th NMOS
Pipe NM4.
Electricity between circuit connecting relation and each circuit module of components and parts in circuit module in detail below
Road annexation.
In described frequency generating circuit, the circuit connecting relation of each components and parts is:
The grid PM1 of described first PMOS, the grid of described first NMOS tube NM1, described second
The grid of NMOS tube NM2 is connected with described electric capacity C, and ground connection.
The source electrode of described first PMOS PM1 is connected with the substrate of self, and is connected with power supply, and described
The drain electrode of one PMOS PM1 is connected with the drain electrode of described first NMOS tube NM1.
The source electrode of described first NMOS tube NM1 is connected with the substrate of self, and with described 2nd NMOS
The drain electrode of pipe NM2 is connected.
The source electrode of described second NMOS tube NM2 is connected with the substrate of self, and ground connection.
One end of described resistance R is connected with the grid of described first PMOS PM1, the other end and described the
The drain electrode of one PMOS PM1 is connected.
The drain electrode of described 3rd NMOSNM3 pipe is connected with power supply, source electrode and described second NMOS tube
The drain electrode of NM2 is connected, and grid is connected with the drain electrode of described first PMOS PM1, described 3rd NMOS
The grid of pipe NM3 is the first signal output part V1 of described chaos circuit.
In described Active inductor circuit, the circuit connecting relation of each components and parts is:
The grid of described second PMOS PM2, the grid of described 3rd PMOS PM3 and described
The grid of four NMOS tube NM4 is connected.
The source electrode of described second PMOS PM2 is connected with the substrate of self, and is connected with power supply, and described
The drain electrode of two PMOS PM2 is connected with the source electrode of described 3rd PMOS PM3, described 2nd PMOS
The secondary signal outfan V2 that drain electrode is described chaos circuit of pipe PM2.
The source electrode of described 3rd PMOS PM3 is connected with the substrate of self, described 3rd PMOS PM3
Drain electrode be connected with the drain electrode of described 4th NMOS tube NM4.
The source electrode of described 4th NMOS tube NM4 is connected with the substrate of self, and ground connection, and the described 4th
The 3rd signal output part V3 that drain electrode is described chaos circuit of NMOS tube NM4.
Wherein, described frequency generating circuit with the circuit connecting relation of described Active inductor circuit is:
The grid of described 3rd NMOS tube NM3 in described frequency generating circuit and described active electrical electrification
The grid of described second PMOS PM2 in road is connected.
The substrate of described 3rd NMOS tube NM3 in described frequency generating circuit and described active electrical electrification
The drain electrode of described 4th NMOS tube NM4 in road is connected.
Optionally, in order to preferably realize the output of chaotic signal, in other embodiments disclosed by the invention
Always the parameter of each components and parts in this chaos circuit is defined.
Concrete, the supply voltage of described power supply is 300mV～500mV；
The breadth length ratio of described first PMOS is 2.5mm/200nm；
The breadth length ratio of described first NMOS tube is 1.5mm/500nm；
The breadth length ratio of described second NMOS tube is 2.2mm/500nm；
The breadth length ratio of described 3rd NMOS tube is 2mm/500nm；
The breadth length ratio of described second PMOS is 100 μm/500nm；
The breadth length ratio of described 3rd PMOS is 1.5mm/500nm；
The breadth length ratio of described 4th NMOS tube is 500 μm/500nm；
The Standard resistance range of described resistance is 7M Ω～10M Ω；
The capacitance value range of described electric capacity is 23pF～33pF.
In order to illustrate to use the exportable chaotic signal of chaos circuit disclosed by the invention, and the chaos letter of output
Number remain time domain complexity and the bandwidth spectrum characteristic realizing analogue signal chaos.See Fig. 2～Fig. 5.Figure
2 show the first signal output part of a kind of chaos circuit of the present invention, secondary signal outfan and the 3rd letter
The signal time-domain diagram of the chaotic signal of number outfan output；Fig. 3 shows the of a kind of chaos circuit of the present invention
The frequency domain figure of the chaotic signal of one signal output part output；Fig. 4 shows the of a kind of chaos circuit of the present invention
The frequency domain figure of the chaotic signal of binary signal outfan output；Fig. 5 shows the of a kind of chaos circuit of the present invention
The frequency domain figure of the chaotic signal of three signal output part outputs.Wherein, upper part image is the second letter in fig. 2
The time-domain diagram of the chaotic signal of number outfan V2 output, middle parts of images is the 3rd signal output part V3 output
The time-domain diagram of chaotic signal, lower part image be the chaotic signal of the first signal output part V1 output time
Territory figure.
Finally, in addition it is also necessary to explanation, in this article, the relational terms of such as first and second or the like
It is used merely to separate an entity or operation with another entity or operating space, and not necessarily requires
Or imply relation or the order that there is any this reality between these entities or operation.And, art
Language " includes ", " comprising " or its any other variant are intended to comprising of nonexcludability, thus
Make to include that the process of a series of key element, method, article or equipment not only include those key elements, and
Also include other key elements being not expressly set out, or also include for this process, method, article or
The key element that person's equipment is intrinsic.In the case of there is no more restriction, by statement " including ... "
The key element limited, it is not excluded that also deposit in including the process of described key element, method, article or equipment
In other identical element.
In this specification, each embodiment uses the mode gone forward one by one to describe, and each embodiment stresses
Being the difference with other embodiments, between each embodiment, identical similar portion sees mutually.
Described above to the disclosed embodiments, makes professional and technical personnel in the field be capable of or uses
The present invention.Multiple amendment to these embodiments will be aobvious and easy for those skilled in the art
See, generic principles defined herein can without departing from the spirit or scope of the present invention,
Realize in other embodiments.Therefore, the present invention is not intended to be limited to the embodiments shown herein,
And it is to fit to the widest scope consistent with principles disclosed herein and features of novelty.
Claims (5)
1. a chaos circuit, it is characterised in that including: frequency generating circuit and Active inductor circuit；
Wherein, described frequency generating circuit includes: the first PMOS, the first NMOS tube, the 2nd NMOS
Pipe, the 3rd NMOS tube, electric capacity and resistance；
The grid of described first PMOS, the grid of described first NMOS tube, described second NMOS tube
Grid be connected with described electric capacity, and ground connection；
The source electrode of described first PMOS is connected with the substrate of self, and is connected with power supply, and described first
The drain electrode of PMOS is connected with the drain electrode of described first NMOS tube；
The source electrode of described first NMOS tube is connected with the substrate of self, and with the leakage of described second NMOS tube
The most connected；
The source electrode of described second NMOS tube is connected with the substrate of self, and ground connection；
One end of described resistance is connected with the grid of described first PMOS, the other end and described first
The drain electrode of PMOS is connected；
The drain electrode of described 3rd NMOS tube is connected with power supply, the drain electrode phase of source electrode and described second NMOS tube
Even, grid is connected with the drain electrode of described first PMOS, and the grid of described 3rd NMOS tube is described mixed
First signal output part of ignorant circuit；
Described Active inductor circuit includes: the second PMOS, the 3rd PMOS and the 4th NMOS tube；
The grid of described second PMOS, the grid of described 3rd PMOS and described 4th NMOS
The grid of pipe is connected；
The source electrode of described second PMOS is connected with the substrate of self, and is connected with power supply, and described second
The drain electrode of PMOS is connected with the source electrode of described 3rd PMOS, and the drain electrode of described second PMOS is
The secondary signal outfan of described chaos circuit；
The source electrode of described 3rd PMOS is connected with the substrate of self, the drain electrode of described 3rd PMOS with
The drain electrode of described 4th NMOS tube is connected；
The source electrode of described 4th NMOS is connected with the substrate of self, and ground connection, described 4th NMOS tube
Drain electrode is the 3rd signal output part of described chaos circuit；
Wherein, described frequency generating circuit with the circuit connecting relation of described Active inductor circuit is:
In the grid of described 3rd NMOS tube in described frequency generating circuit and described Active inductor circuit
Described second PMOS grid be connected；
In the substrate of described 3rd NMOS tube in described frequency generating circuit and described Active inductor circuit
Described 4th NMOS tube drain electrode be connected.
Circuit the most according to claim 1, it is characterised in that the supply voltage of described power supply is
300mV～500mV.
Circuit the most according to claim 1, it is characterised in that the breadth length ratio of described first PMOS
For 2.5mm/200nm；
The breadth length ratio of described first NMOS tube is 1.5mm/500nm；
The breadth length ratio of described second NMOS tube is 2.2mm/500nm；
The breadth length ratio of described 3rd NMOS tube is 2mm/500nm；
The breadth length ratio of described second PMOS is 100 μm/500nm；
The breadth length ratio of described 3rd PMOS is 1.5mm/500nm；
The breadth length ratio of described 4th NMOS tube is 500 μm/500nm.
Circuit the most according to claim 1, it is characterised in that the Standard resistance range of described resistance is 7M
Ω～10M Ω.
Circuit the most according to claim 1, it is characterised in that the capacitance value range of described electric capacity is
23pF～33pF.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610273971.2A CN105978551B (en) | 2016-04-28 | 2016-04-28 | A kind of chaos circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610273971.2A CN105978551B (en) | 2016-04-28 | 2016-04-28 | A kind of chaos circuit |
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| Publication Number | Publication Date |
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| CN105978551A true CN105978551A (en) | 2016-09-28 |
| CN105978551B CN105978551B (en) | 2018-12-21 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11075541B2 (en) | 2017-08-22 | 2021-07-27 | Hangzhou Hikvision Digital Technology Co., Ltd. | Signal transmission system and signal transmission method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012156126A2 (en) * | 2011-05-19 | 2012-11-22 | Robert Bosch Gmbh | Sensor element having a piezoelectric transducer |
| CN202998051U (en) * | 2012-12-27 | 2013-06-12 | 西南大学 | Memristor-based hyperchaotic-system realization circuit |
| CN103744288A (en) * | 2013-12-20 | 2014-04-23 | 广西大学 | Memristor-based self-adaptive PD controller circuit |
-
2016
- 2016-04-28 CN CN201610273971.2A patent/CN105978551B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012156126A2 (en) * | 2011-05-19 | 2012-11-22 | Robert Bosch Gmbh | Sensor element having a piezoelectric transducer |
| CN202998051U (en) * | 2012-12-27 | 2013-06-12 | 西南大学 | Memristor-based hyperchaotic-system realization circuit |
| CN103744288A (en) * | 2013-12-20 | 2014-04-23 | 广西大学 | Memristor-based self-adaptive PD controller circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11075541B2 (en) | 2017-08-22 | 2021-07-27 | Hangzhou Hikvision Digital Technology Co., Ltd. | Signal transmission system and signal transmission method |
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| CN105978551B (en) | 2018-12-21 |
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