CN105978551B - A kind of chaos circuit - Google Patents
A kind of chaos circuit Download PDFInfo
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- CN105978551B CN105978551B CN201610273971.2A CN201610273971A CN105978551B CN 105978551 B CN105978551 B CN 105978551B CN 201610273971 A CN201610273971 A CN 201610273971A CN 105978551 B CN105978551 B CN 105978551B
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- circuit
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- nmos tube
- pmos tube
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
Abstract
This application discloses 7 pipe MOS chaos circuits of ultra low voltage power supply.This invention simplifies the chaos circuit constructed based on two unifrequency generation modules and a nonlinear block, the core circuit is 3 pipe Active inductor circuits, exports base frequency signal all the way using 4 pipe frequency generating circuits.Compared with prior art, the present invention significantly simplifies the chaos circuit structure that known metal-oxide-semiconductor is realized, design principle takes full advantage of 3 pipe MOS and realizes active inductance, simultaneously as having found the suitable load point of feedback line, an independent frequency generating circuit can be saved, it can achieve the purpose that gradually abbreviation circuit structure is 7 pipes, while remain the time domain complexity and continuous bandwidth spectral characteristic for realizing simulation chaos respectively.
Description
Technical field
This application involves electronic circuit design fields, more specifically to a kind of chaos circuit.
Background technique
In recent years, with the encoding and decoding of miniature monitoring probe and continuation of the journey demand, new chaotic signal generating circuit by
Favor.
Current chaos circuit is based primarily upon the realization of amplifier structure, on the one hand needs multiple operational amplifiers, another side
Face is essential to need multiple inductance or diode, and the number of component needed for circuit structure is more, especially MOS
The number of pipe is more, and the structure that this will lead to traditional chaos circuit is more complicated.
Summary of the invention
In view of this, the application provides a kind of chaos circuit, chaos is constructed based on 7 metal-oxide-semiconductors, 1 resistance and 1 capacitor
Circuit simplifies the circuit structure of chaos circuit.
To achieve the goals above, it is proposed that scheme it is as follows:
A kind of chaos circuit, comprising: frequency generating circuit and Active inductor circuit；
Wherein, the frequency generating circuit includes: the first PMOS tube, the first NMOS tube, the second NMOS tube, the 3rd NMOS
Pipe, capacitor and resistance；
The grid of first PMOS tube, the grid of first NMOS tube, the grid of second NMOS tube and described
Capacitor is connected, and is grounded；
The source electrode of first PMOS tube is connected with the substrate of itself, and is connected with power supply, the leakage of first PMOS tube
Pole is connected with the drain electrode of first NMOS tube；
The source electrode of first NMOS tube is connected with the substrate of itself, and is connected with the drain electrode of second NMOS tube；
The source electrode of second NMOS tube is connected with the substrate of itself, and is grounded；
One end of the resistance is connected with the grid of first PMOS tube, the drain electrode of the other end and first PMOS tube
It is connected；
The drain electrode of the third NMOS tube is connected with power supply, and source electrode is connected with the drain electrode of second NMOS tube, grid with
The drain electrode of first PMOS tube is connected, and the grid of the third NMOS tube is the first signal output end of the chaos circuit；
The Active inductor circuit includes: the second PMOS tube, third PMOS tube and the 4th NMOS tube；
The grid phase of the grid of second PMOS tube, the grid of the third PMOS tube and the 4th NMOS tube
Even；
The source electrode of second PMOS tube is connected with the substrate of itself, and is connected with power supply, the leakage of second PMOS tube
Pole is connected with the source electrode of the third PMOS tube, and the drain electrode of second PMOS tube is that the second signal of the chaos circuit exports
End；
The source electrode of the third PMOS tube is connected with the substrate of itself, the drain electrode of the third PMOS tube and the described 4th
The drain electrode of NMOS tube is connected；
The source electrode of 4th NMOS is connected with the substrate of itself, and is grounded, and the drain electrode of the 4th NMOS tube is described
The third signal output end of chaos circuit；
Wherein, the circuit connecting relation of the frequency generating circuit and the Active inductor circuit are as follows:
Described the in the grid of the third NMOS tube in the frequency generating circuit and the Active inductor circuit
The grid of two PMOS tube is connected；
Described the in the substrate of the third NMOS tube in the frequency generating circuit and the Active inductor circuit
The drain electrode of four NMOS tubes is connected.
Preferably, the supply voltage of the power supply is 300mV~500mV.
Preferably, the breadth length ratio of first PMOS tube is 2.5mm/200nm；
The breadth length ratio of first NMOS tube is 1.5mm/500nm；
The breadth length ratio of second NMOS tube is 2.2mm/500nm；
The breadth length ratio of the third NMOS tube is 2mm/500nm；
The breadth length ratio of second PMOS tube is 100 μm/500nm；
The breadth length ratio of the third PMOS tube is 1.5mm/500nm；
The breadth length ratio of 4th NMOS tube is 500 μm/500nm.
Preferably, the Standard resistance range of the resistance is 7M Ω~10M Ω.
Preferably, the capacitance value range of the capacitor is 23pF~33pF.
As can be seen from the above technical solutions, this application discloses 7 pipe MOS chaos circuits of ultra low voltage power supply.The present invention
The chaos circuit constructed based on two unifrequency generation modules and a nonlinear block is simplified, the core circuit is 3
Pipe Active inductor circuit exports base frequency signal all the way using 4 pipe frequency generating circuits.Compared with prior art, of the invention
The chaos circuit structure that known metal-oxide-semiconductor is realized significantly is simplified, design principle takes full advantage of 3 pipe MOS and realizes active electricity
Sense, simultaneously as having found the suitable load point of feedback line, as soon as an independent frequency generating circuit can be saved, can reach
Gradually abbreviation circuit structure is the purpose of 7 pipes, while remaining the time domain complexity and continuous bandwidth for realizing simulation chaos respectively
Spectral characteristic.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 shows a kind of electrical block diagram of chaos circuit of the present invention；
Fig. 2 shows the chaos of a kind of the first signal output end of chaos circuit of the invention and the output of second signal output end
The signal time-domain diagram of signal；
Fig. 3 shows a kind of frequency domain figure of the chaotic signal of the first signal output end output of chaos circuit of the present invention；
Fig. 4 shows a kind of frequency domain figure of the chaotic signal of the second signal output end output of chaos circuit of the present invention；
Fig. 5 shows a kind of frequency domain figure of the chaotic signal of the third signal output end output of chaos circuit of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
In chaos generation circuit, single tube Colpitts chaos circuit structure is the most succinct, but needs inductance, and technique is difficult
In integrated, other metal-oxide-semiconductor chaos circuits are based primarily upon amplifier structure, it appears it is excessively complicated, and generally require diode or
Inductance, this will all cause the structure of conventional MOS pipe chaos circuit to seem still complicated.
To sum up, in order to push metal-oxide-semiconductor Generation of Chaotic Signals most simplified structure development, meet actively measurement etc. skills
The urgent demand that new chaotic signal in art link generates, the simulation chaotic signal for directing metal-oxide-semiconductor integrated horizontal concretely generate specially
It is referred to the innovative design of integrated circuit, just has the engineering significance of far-reaching reality.
A kind of electrical block diagram of chaos circuit disclosed in one embodiment of the invention is shown referring to Fig. 1.
The chaos circuit includes 2 circuit modules, i.e. frequency generating circuit and Active inductor circuit.
Wherein, the frequency generating circuit include: the first PMOS tube PM1, the first NMOS tube NM1, the second NMOS tube NM2,
Third NMOS tube NM3, capacitor C and resistance R.
Active inductor circuit includes: the second PMOS tube PM2, third PMOS tube PM3 and the 4th NMOS tube NM4.
Circuit connection in physical circuit module between the circuit connecting relation and each circuit module of component below
Relationship.
The circuit connecting relation of each component in the frequency generating circuit are as follows:
The grid PM1 of first PMOS tube, the grid of the first NMOS tube NM1, the second NMOS tube NM2 grid
Pole is connected with the capacitor C, and is grounded.
The source electrode of the first PMOS tube PM1 is connected with the substrate of itself, and is connected with power supply, first PMOS tube
The drain electrode of PM1 is connected with the drain electrode of the first NMOS tube NM1.
The source electrode of the first NMOS tube NM1 is connected with the substrate of itself, and the drain electrode phase with the second NMOS tube NM2
Even.
The source electrode of the second NMOS tube NM2 is connected with the substrate of itself, and is grounded.
One end of the resistance R is connected with the grid of the first PMOS tube PM1, the other end and first PMOS tube
The drain electrode of PM1 is connected.
The drain electrode of the 3rd NMOSNM3 pipe is connected with power supply, and source electrode is connected with the drain electrode of the second NMOS tube NM2,
Grid is connected with the drain electrode of the first PMOS tube PM1, and the grid of the third NMOS tube NM3 is the first of the chaos circuit
Signal output end V1.
The circuit connecting relation of each component in the Active inductor circuit are as follows:
The grid and the 4th NMOS tube NM4 of the grid of the second PMOS tube PM2, the third PMOS tube PM3
Grid be connected.
The source electrode of the second PMOS tube PM2 is connected with the substrate of itself, and is connected with power supply, second PMOS tube
The drain electrode of PM2 is connected with the source electrode of the third PMOS tube PM3, and the drain electrode of the second PMOS tube PM2 is the chaos circuit
Second signal output end V2.
The source electrode of the third PMOS tube PM3 is connected with the substrate of itself, the drain electrode of the third PMOS tube PM3 with it is described
The drain electrode of 4th NMOS tube NM4 is connected.
The source electrode of the 4th NMOS tube NM4 is connected with the substrate of itself, and is grounded, the leakage of the 4th NMOS tube NM4
The third signal output end V3 of the extremely described chaos circuit.
Wherein, the circuit connecting relation of the frequency generating circuit and the Active inductor circuit are as follows:
The grid of the third NMOS tube NM3 in the frequency generating circuit with it is described in the Active inductor circuit
The grid of second PMOS tube PM2 is connected.
The substrate of the third NMOS tube NM3 in the frequency generating circuit with it is described in the Active inductor circuit
The drain electrode of 4th NMOS tube NM4 is connected.
Optionally, always mixed to this in other embodiments disclosed by the invention in order to preferably realize the output of chaotic signal
The parameter of each component is defined in ignorant circuit.
Specifically, the supply voltage of the power supply is 300mV~500mV；
The breadth length ratio of first PMOS tube is 2.5mm/200nm；
The breadth length ratio of first NMOS tube is 1.5mm/500nm；
The breadth length ratio of second NMOS tube is 2.2mm/500nm；
The breadth length ratio of the third NMOS tube is 2mm/500nm；
The breadth length ratio of second PMOS tube is 100 μm/500nm；
The breadth length ratio of the third PMOS tube is 1.5mm/500nm；
The breadth length ratio of 4th NMOS tube is 500 μm/500nm；
The Standard resistance range of the resistance is 7M Ω~10M Ω；
The capacitance value range of the capacitor is 23pF~33pF.
In order to illustrate the use exportable chaotic signal of chaos circuit disclosed by the invention, and the chaotic signal exported remains
Realize the time domain complexity and bandwidth spectrum characteristic of analog signal chaos.Referring to fig. 2~Fig. 5.Fig. 2 shows of the invention a kind of mixed
When the signal for the chaotic signal that the first signal output end, second signal output end and the third signal output end of ignorant circuit export
Domain figure；Fig. 3 shows a kind of frequency domain figure of the chaotic signal of the first signal output end output of chaos circuit of the present invention；Fig. 4 shows
A kind of frequency domain figure of the chaotic signal of the second signal output end output of chaos circuit of the invention is gone out；Fig. 5 shows the present invention
A kind of frequency domain figure of the chaotic signal of the third signal output end output of chaos circuit.It wherein, is the in the middle and upper part Fig. 2 partial image
The time-domain diagram of the chaotic signal of binary signal output end V2 output, middle parts of images are the chaos letter of third signal output end V3 output
Number time-domain diagram, lower parts of images be the first signal output end V1 output chaotic signal time-domain diagram.
Finally, it is to be noted that, herein, relational terms such as first and second and the like be used merely to by
One entity or operation are distinguished with another entity or operation, without necessarily requiring or implying these entities or operation
Between there are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant meaning
Covering non-exclusive inclusion, so that the process, method, article or equipment for including a series of elements not only includes that
A little elements, but also including other elements that are not explicitly listed, or further include for this process, method, article or
The intrinsic element of equipment.In the absence of more restrictions, the element limited by sentence "including a ...", is not arranged
Except there is also other identical elements in the process, method, article or apparatus that includes the element.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment may refer to each other.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (5)
1. a kind of chaos circuit characterized by comprising frequency generating circuit and Active inductor circuit；
Wherein, the frequency generating circuit includes: the first PMOS tube, the first NMOS tube, the second NMOS tube, third NMOS tube, electricity
Appearance and resistance；
The grid of first PMOS tube, the grid of first NMOS tube, second NMOS tube grid pass through the electricity
Hold ground connection；
The source electrode of first PMOS tube is connected with the substrate of itself, and is connected with power supply, the drain electrode of first PMOS tube with
The drain electrode of first NMOS tube is connected；
The source electrode of first NMOS tube is connected with the substrate of itself, and is connected with the drain electrode of second NMOS tube；
The source electrode of second NMOS tube is connected with the substrate of itself, and is grounded；
One end of the resistance is connected with the grid of first PMOS tube, the drain electrode phase of the other end and first PMOS tube
Even；
The drain electrode of the third NMOS tube is connected with power supply, and source electrode is connected with the drain electrode of second NMOS tube, grid with it is described
The drain electrode of first PMOS tube is connected, and the grid of the third NMOS tube is the first signal output end of the chaos circuit；
The Active inductor circuit includes: the second PMOS tube, third PMOS tube and the 4th NMOS tube；
The grid of the grid of second PMOS tube, the grid of the third PMOS tube and the 4th NMOS tube is connected；
The source electrode of second PMOS tube is connected with the substrate of itself, and is connected with power supply, the drain electrode of second PMOS tube with
The source electrode of the third PMOS tube is connected, and the drain electrode of second PMOS tube is the second signal output end of the chaos circuit；
The source electrode of the third PMOS tube is connected with the substrate of itself, the drain electrode of the third PMOS tube and the 4th NMOS tube
Drain electrode be connected；
The source electrode of 4th NMOS is connected with the substrate of itself, and is grounded, and the drain electrode of the 4th NMOS tube is the chaos
The third signal output end of circuit；
Wherein, the circuit connecting relation of the frequency generating circuit and the Active inductor circuit are as follows:
The grid of the third NMOS tube in the frequency generating circuit and described second in the Active inductor circuit
The grid of PMOS tube is connected；
The substrate of the third NMOS tube in the frequency generating circuit and the described 4th in the Active inductor circuit
The drain electrode of NMOS tube is connected.
2. circuit according to claim 1, which is characterized in that the supply voltage of the power supply is 300mV~500mV.
3. circuit according to claim 1, which is characterized in that the breadth length ratio of first PMOS tube is 2.5mm/200nm；
The breadth length ratio of first NMOS tube is 1.5mm/500nm；
The breadth length ratio of second NMOS tube is 2.2mm/500nm；
The breadth length ratio of the third NMOS tube is 2mm/500nm；
The breadth length ratio of second PMOS tube is 100 μm/500nm；
The breadth length ratio of the third PMOS tube is 1.5mm/500nm；
The breadth length ratio of 4th NMOS tube is 500 μm/500nm.
4. circuit according to claim 1, which is characterized in that the Standard resistance range of the resistance is 7M Ω~10M Ω.
5. circuit according to claim 1, which is characterized in that the capacitance value range of the capacitor is 23pF~33pF.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610273971.2A CN105978551B (en) | 2016-04-28 | 2016-04-28 | A kind of chaos circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610273971.2A CN105978551B (en) | 2016-04-28 | 2016-04-28 | A kind of chaos circuit |
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| Publication Number | Publication Date |
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| CN105978551A CN105978551A (en) | 2016-09-28 |
| CN105978551B true CN105978551B (en) | 2018-12-21 |
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| CN109428396B (en) | 2017-08-22 | 2021-01-12 | 杭州海康威视数字技术股份有限公司 | Signal transmission system and signal transmission method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012156126A2 (en) * | 2011-05-19 | 2012-11-22 | Robert Bosch Gmbh | Sensor element having a piezoelectric transducer |
| CN202998051U (en) * | 2012-12-27 | 2013-06-12 | 西南大学 | Memristor-based hyperchaotic-system realization circuit |
| CN103744288A (en) * | 2013-12-20 | 2014-04-23 | 广西大学 | Memristor-based self-adaptive PD controller circuit |
-
2016
- 2016-04-28 CN CN201610273971.2A patent/CN105978551B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012156126A2 (en) * | 2011-05-19 | 2012-11-22 | Robert Bosch Gmbh | Sensor element having a piezoelectric transducer |
| CN202998051U (en) * | 2012-12-27 | 2013-06-12 | 西南大学 | Memristor-based hyperchaotic-system realization circuit |
| CN103744288A (en) * | 2013-12-20 | 2014-04-23 | 广西大学 | Memristor-based self-adaptive PD controller circuit |
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| Publication number | Publication date |
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| CN105978551A (en) | 2016-09-28 |
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