CN104221348A - Current loop voltage modulator for communication interface - Google Patents
Current loop voltage modulator for communication interface Download PDFInfo
- Publication number
- CN104221348A CN104221348A CN201380019336.6A CN201380019336A CN104221348A CN 104221348 A CN104221348 A CN 104221348A CN 201380019336 A CN201380019336 A CN 201380019336A CN 104221348 A CN104221348 A CN 104221348A
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- China
- Prior art keywords
- circuit
- voltage
- signal
- integrated circuit
- current loop
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Classifications
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
- G05B19/056—Programming the PLC
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/50—Systems for transmission between fixed stations via two-conductor transmission lines
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25232—DCS, distributed control system, decentralised control unit
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Automation & Control Theory (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Arrangements For Transmission Of Measured Signals (AREA)
- Dc Digital Transmission (AREA)
Abstract
Systems for communicating over a communication interface are provided. An integrated circuit includes circuitry for monitoring a current flowing between two terminals of the integrated circuit. The integrated circuit also includes a voltage driver circuit for modulating a voltage between two terminals of the integrated circuit. The voltage driver modulates the voltage across the two terminals of the integrated circuit to encode data according to the Highway Addressable Remote Transducer protocol.
Description
Background technology
Theme disclosed herein relates to communicating by voltage modulated and current sense.
Programmable logic controller (PLC) (PLC), dcs (DCS) and auxiliary facility (BOP) usually use high-speed channel addressable remote transducer (HART) agreement to communicate.Therefore, HART agreement is usually in asset management.Such as, HART is used for continuous scanning means and acquisition operations data in power plant.The acceptor device carrying out communicating based on HART agreement modulates the ability of the terminal voltage between two terminals while requiring the loop current flowed between monitoring terminal.In general, HART communicator uses transformer to apply voltage, and does not change electric current.But, use transformer to be unpractical to the solid-state design such as realized in integrated circuit (such as application-specific integrated circuit (ASIC) (ASIC)).The dependence of this kind of larger discrete assembly is hindered HART protocol realization on the switch block of asic chip.
Summary of the invention
Summarize some embodiment that scope matches with the present invention claimed at first below.These embodiments are not be intended to limit claimed scope of the present invention, these embodiments but only estimate provide of the present invention may the general introduction of form.In fact, the present invention can comprise various ways that can be similar or different from the embodiment proposed below.
In a first embodiment, integrated circuit comprises the circuit being configured to monitor the electric current flowed between two terminals of integrated circuit.In addition, integrated circuit comprises voltage driver (voltage driver), its be configured to modulate across integrated circuit two terminals between voltage, remain on the electric current flowed between two terminals of integrated circuit simultaneously.Voltage driver modulates the voltage across two terminals according to high-speed channel addressable remote transducer (HART) agreement.
One additional embodiment comprises a kind of system, the reflector be electrically coupled together comprising the wire by forming current loop and receiver.Receiver comprises a kind of ASIC, and it comprises: be designed to the circuit of monitoring stream through current loop; And voltage driver, be designed to modulate the voltage across two terminals of current loop, keep the electric current flowing through current loop simultaneously.Reflector flows through the electric current of current loop to receiver transmission of information by modulation, and receiver passes through the voltage of modulation across two terminals of current loop to reflector transmission of information.
In an additional embodiment, electronic circuit comprises resistor, and it is designed to form voltage across its terminal about the electric current flowing through current loop.Current loop is formed between electronic circuit and radiating circuit.Electronic circuit also comprises differential amplifier, and its voltage being designed to be formed about resistor is to generate signal.This signal transmission is supplied process to modulator-demodulator (modulator-demodulator) and analog to digital converter (ADC).In addition, electronic circuit comprises Voltag driving circuit, and it is from modulator-demodulator Received signal strength, and modulates the voltage of the terminal across current loop based on the signal received from modulator-demodulator.
Accompanying drawing explanation
Read following detailed description in detail by referring to accompanying drawing, will understand these and other feature of the present invention, aspect and advantage better, in accompanying drawing, similar label represents similar parts in the whole text in the accompanying drawings, and accompanying drawing comprises:
Fig. 1 illustrate according to an embodiment, with the HART reflector of current loop electric coupling and HART receiver;
Fig. 2 illustrates according to an embodiment, the chart flowing through the electric current of current loop and the voltage across the terminal of current loop;
Fig. 3 illustrates according to an embodiment, example as the HART acceptor circuit of the voltage driver of connecting with current-sense resistor;
Fig. 4 illustrates the circuit-level sketch of the acceptor circuit of HART shown in Fig. 3; And
Fig. 5 illustrates according to an embodiment, the example using the HART acceptor circuit of the voltage driver in parallel with current-sense resistor.
Embodiment
One or more specific embodiment of the present invention will be described below.In the process of concise and to the point description that these embodiments are provided, all features of actual realization may not described in this specification.Be to be understood that, in the exploitation that any this reality realizes, as in any engineering or design object, many realizations must be carried out and specifically judge to realize the specific objective of developer, such as meet the relevant restriction relevant with business of system, these restrictions can change each realization.In addition, should be appreciated that this development may be complicated and time-consuming, but still be the routine matter benefiting from design that technical staff of the present disclosure carries out, making and manufacture.
When introducing the element of each embodiment of the present invention, determiner " ", " one ", " being somebody's turn to do " and " described " estimate to represent to there are the one or more of element.Term " comprises ", " comprising " and " having " expectation is included, and represents the add ons that can exist except listed elements.
As discussed more in detail below, the present embodiment relates to and is designed by the circuit that high-speed channel addressable remote transducer (HART) agreement carries out the receiver communicated.In order to communicate, the terminal voltage of voltage driver circuits modulation HART receiver, current sensing circuit monitors the loop current flowed between terminal simultaneously.Like this, the current value that voltage driver circuits keeps HART reflector to provide, changes the magnitude of voltage of signal simultaneously as required.The circuit with these characteristics can be called current follower again.In certain embodiments, the circuit of HART receiver is made up of discrete assembly, and in other embodiments, this circuit is the part of integrated circuit (such as application-specific integrated circuit (ASIC) (ASIC)).
In view of the above, the embodiment describing the HART acceptor circuit such as shown in Fig. 1 can be useful.In the embodiment shown, HART reflector 10 is electrically coupled to the current loop wire 12 formed with the current loop of HART receiver 14.In order to send information to HART receiver 14, HART reflector 10 can utilize HART communication protocol.HART agreement can use Bell 202 frequency shift keying (FSK) standard, thus changes the frequency of current signal, digit order number to be regulated in signal.Current signal can be that cycle in 4 mA to 20 mA scopes and sinusoidal low bandwidth direct current (DC) are to 25Hz signal.Because HART agreement is semiduplex, so only HART reflector 10 can modulate the electric current through current loop wire 12, or HART receiver 14 can at the voltage of modulation preset time across current loop terminal 13.
The electric current modulated by HART reflector 10 can flow through current loop wire 12 and flow through the current-sense resistor R1 of HART receiver 14.In certain embodiments, current-sense resistor R1 can have the value of 250 Ω, and in other embodiments, current-sense resistor can have other suitable resistance value.When electric current flows through current-sense resistor R1, voltage bias can be formed at the either side of current-sense resistor R1.Differential amplifier 16 can have two inputs of the either side being electrically coupled to current-sense resistor R1, and can be designed to about the voltage bias across two inputs to generate current signal.When more big current flows through current-sense resistor R1, larger voltage bias is formed across either side, and differential amplifier generates larger current signal.The current signal generated by differential amplifier 16 can pass to analog to digital converter (ADC) 18 and HART modulator-demodulator (modulator-demodulator) 20.The analog current signal that differential amplifier 16 produces can be converted to digital signal by ADC 18, and it can be explained by communication logic circuit 22.Similarly, HART modulator-demodulator 20 can carry out demodulation to the information entrained by current signal, and information is passed to communication logic circuit 22.In the embodiment shown, capacitor C1 can filter DC component before current signal is delivered to HART modulator-demodulator 20 from current signal.As shown in the spacing block 24 in HART receiver 14, the circuit of HART receiver 14 provides the electric isolution between HART acceptor circuit and communication logic circuit 22.
Except carrying out except demodulation to the electric current flowing through current loop, HART receiver 14 also can modulate the terminal voltage of current loop, to transmit information to HART reflector 10.Communication logic circuit 22 can send information to HART modulator-demodulator 20, to be converted to voltage signal.Summing circuit 26 can receiver voltage signal, and is added the electric current flowing through current loop, with the terminal voltage of modulated current loop.It should be noted that summing circuit can add voltage signal, with the terminal voltage of modulated current loop, but the electric current flowing through current loop can not changed by HART receiver 14 circuit.Summing circuit 26 can be called voltage driver 27 again.
As mentioned above, in order to use HART agreement to communicate, HART reflector 10 can modulate the electric current flowing through current loop, and HART receiver 14 can modulate the voltage of the terminal 13 across current loop.Fig. 2 is the chart that current signal and the voltage signal that can exist in the communication between HART reflector 10 and HART receiver 14 is shown.First waveform 40 can represent current modulated, and the second waveform 42 can represent voltage modulation signal.As described in and shown, the first waveform 40 can be low bandwidth DC to the 25 Hz signal in 4 mA to 20 mA scopes.By changing the frequency of signal, information bit is encoded to current modulated 40.Such as, in order to encode to numeral " 1 ", the set of frequency of current modulated 40 can be 23 Hz by HART reflector 10, and in order to encode to digital " 0 ", the set of frequency of signal can be 10 Hz by HART reflector 10.As described in, frequency shift keying (FSK) is called to this method that information bit is encoded.
In the same way, HART receiver 14 can use FSK to encode to information on voltage modulation signal.In the embodiment shown, voltage modulation signal adopts the 10 Hz cycle sinusoidal wanting much higher periodicity pitch (500-1000 Hz) to modulate.If see, the modulating frequency of signal changes, so that digit order number is encoded to signal.During the time period 44, the frequency of voltage modulation signal can higher (1000 Hz), thus encodes to numeral " 1 ".In a rear time period 46, frequency can lower (500 Hz), thus encodes to digital " 0 ".It should be noted that other frequency can be used to encode to digit order number, as long as their are fully different and be enough to be distinguished by the circuit of HART reflector 10 or HART receiver 14.HART reflector 10, by device and demodulator AC coupled end voltage after filtering, senses the tone of encoding to digital information.
Fig. 3 illustrates an alternative of the circuit of the reflector of HART shown in Fig. 1 14.As previously described, the electric current modulated by HART reflector 10 can flow through current loop wire 12 and flow through current-sense resistor R1.Differential amplifier 16 can have two inputs of the either side being electrically coupled to current-sense resistor R1, to carry out generating output signal about the voltage bias across current-sense resistor R1.In the embodiments of figure 3, the signal generated by differential amplifier 16 can through low pass filter 60 before being delivered to ADC 18.Low pass filter 60 can remove interchange (AC) component of signal, makes ADC 18 receive direct current (DC) signal.
As shown in Figure 1, HART receiver 14 can comprise HART modulator-demodulator 20, to carry out demodulation for the signal received from HART reflector 10, and the terminal voltage of modulated current loop terminals 13.But the voltage driver 27 of the embodiment of Fig. 3 can comprise transistor 62, to form common collector buffer.Shown transistor 62 is PNP bipolar junction transistor (BJT), but other embodiment can comprise NPN BJT, p-type metal-oxide semiconductor (MOS) (PMOS) transistor or n-type metal oxide semiconductor (NMOS) transistor.Reflux line 64 can allow the bias voltage from transistor 62, and wherein summing circuit 26 can be provided for the output voltage of the modulation of terminal voltage.Like this, the voltage driver 27 of the embodiment of Fig. 3 can modulate the terminal voltage of current loop, to encode to the information estimated for HART reflector 10.
The circuit diagram of Fig. 4 illustrates the circuit of the embodiment of the HART receiver 14 described in Fig. 3 with additional detail.As previously described, this circuit comprises differential amplifier 16, and it is designed to about flowing through the electric current of current-sense resistor R1 to generate signal.This signal propagates into ADC 18 as shown in Figure 3 and HART modulator-demodulator 20 at outlet line 67.Resistor R2, R3, R4 and R5 can be electrically coupled to the input and output of differential amplifier 16, to arrange the operating parameter of amplifier.In certain embodiments, resistor R2 and R4 can have the value of 100 k Ω, and resistor R3 and R5 can have the value of 400 k Ω.In other embodiments, other resistance can be suitable for resistor R2, R3, R4 and R5.In addition, in the embodiment shown, the electric current flowing out HART reflector 10 carrys out modeling by current source 66, because the electric current flowing through current loop is constant when the terminal voltage of HART receiver 14 positively-modulated current loop.
In the fig. 4 embodiment, it should be noted that, the transistor 62 of voltage driver 27 is PMOS transistor, but also can be PNP BJT transistor or other suitable transistor any, such as BJT (NPN or PNP), complementary metal oxide semiconductors (CMOS) (CMOS) transistor or nmos pass transistor.The summing circuit 26 of voltage driver can comprise differential amplifier 68, and it receives the bias voltage from transistor 62 on reflux line 64, to provide differential output voltage to the grid of transistor 62.That in some embodiment of PNP JBT transistor, differential amplifier can provide differential output voltage to the base stage of transistor 62 at transistor 62.When the voltage being applied to the base stage of transistor 62 or grid changes, the impedance of transistor also can change, thus the voltage bias between the terminal 13 of modulated current loop effectively.
In addition, the differential amplifier 68 of summing circuit 26 can export 70 from HART modulator-demodulator (its determine to be applied to the base stage of transistor 62 or the differential output voltage of grid and therefore also have in the modulation of terminal voltage work) receives modulation signal.In certain embodiments, voltage source can offset the modulation signal from HART modulator-demodulator output 70, to remain the correct bias on transistor.Correct bias can be guaranteed to be enough to keep the electric current through transistor 62 across the grid of transistor 62 and the voltage of source electrode.Resistor R6, R7, R8, R9 and R10 can be electrically coupled to differential amplifier 68, to arrange the operating parameter of amplifier.In certain embodiments, resistor R6, R8, R9 and R10 can have the value of 100 k Ω, and resistor R7 can have the value of 1000 k Ω.In other embodiments, can be resistor R6, R7, R8, R9 and R10 and select other resistance, to permit the communication using HART receiver 14.Resistor R11 can represent the resistance of the current loop wire of the return path of HART reflector 10.In the embodiment shown, resistor R11 can have the value of 50 Ω, and in other embodiments, resistor R11 can have other proper resistor any of the resistance representing current loop wire 12.In addition, some embodiment can be included in the grid of transistor 62 or the ground capacitor C2 of base stage be supplied to so that stable in the grid of transistor 62 or the signal of base stage compared with small oscillation or the voltage across differential amplifier 68.Capacitor C2 can have the electric capacity of 80 pF or other suitable electric capacity any.
Another embodiment of the circuit of HART receiver 14 is shown in Figure 5.The present embodiment comprises the circuit for monitor loop current identical with embodiment described in Fig. 4 with Fig. 1, Fig. 3.But although Fig. 1, Fig. 3 and Fig. 4 demonstration has the embodiment of the voltage driver 27 of connecting with current-sense resistor R1, the embodiment of Fig. 5 illustrates according to parallel connection configuration, the voltage driver 27 comprising coupling capacitor C3.In general, coupling capacitor is used for the DC component of block signal, allows AC component to pass through simultaneously.Like this, when summing circuit 26 is from reflux line 64 and HART modulator-demodulator 20 Received signal strength and to coupling capacitor C3 output modulation signal, the terminal voltage of coupling capacitor C3 modulated current loop, and do not change the electric current flowing through loop.
It should be noted that the comparable size of coupling capacitor C3 is practicable many greatly to integrated circuit.Bulky capacitor can be used to the comparatively Low ESR of drive current loop.When the capacity ratio of coupling capacitor C3 is wanted large to integrated circuit is practicable, coupling capacitor C3 can be the outside of the remainder of integrated circuit, and can consume two additional encapsulation pins, is connected to larger circuit for by integrated circuit.
The technique effect of embodiment comprises HART acceptor circuit, and it is designed to monitor the electric current flowed in current loop, simultaneously the terminal voltage of modulated current loop.In certain embodiments, voltage driver circuits is connected with current-sense resistor.Differential amplifier can amplify the voltage difference across current-sense resistor, and by signal transmission to HART modulator-demodulator and analog to digital converter, decodes with the information sent HART reflector.HART modulator-demodulator and being sued for peace by summing circuit from the feedback signal of transistor, and be applied to grid or the base stage of transistor, with the voltage between the terminal of modulated current loop, thus effectively transmit information to HART reflector.Voltage driver circuits is arranged in parallel with current-sense resistor by other embodiment of HART acceptor circuit.Coupling capacitor and feedback drives summing circuit and HART modulator-demodulator with the use of, with the terminal voltage of modulated current loop, to HART reflector transmission information.In embodiments, this circuit can realize when not using transformer, thus HART circuit is placed on the integrated.
This written description uses the open the present invention of example, comprising optimal mode, and also enables those skilled in the art to implement the present invention, comprises and makes and use any device or system and the method performing any combination.The scope of the claims of the present invention is defined by claims, and can comprise other example that those skilled in the art expects.If other example this kind of has construction unit identical with the word language of claim, if or they comprise the equivalent structure unit had with the insubstantial difference of the word language of claim, then estimate within the scope that they fall into claim.
Claims (20)
1. an integrated circuit, comprising:
Circuit, is configured to monitor the electric current flowed between two terminals of described integrated circuit; And
Voltage driver, be configured to modulate across described integrated circuit described two terminals between voltage, remain on the described electric current flowed between described two terminals of described integrated circuit simultaneously;
Wherein said voltage driver modulates the described voltage of described two terminals across described integrated circuit, to encode to data according to high-speed channel addressable remote transducer (HART) agreement.
2. integrated circuit as claimed in claim 1, wherein, the described circuit being configured to monitor the electric current flowed between described two terminals of described integrated circuit comprises the resistor being configured to generate the voltage across its terminal about the electric current flowed between described two terminals of described integrated circuit.
3. integrated circuit as claimed in claim 2, wherein, described voltage driver is arranged to and described resistor in series.
4. integrated circuit as claimed in claim 2, wherein, described voltage driver is arranged to and described capacitor in parallel.
5. a system, comprising:
Reflector; And
Receiver, comprises integrated circuit, and is electrically coupled to described reflector by the wire forming current circuit, and described integrated circuit comprises:
Circuit, is configured to the electric current of monitoring stream through described current loop; And
Voltage driver, is configured to modulate the voltage across two terminals of described current loop, keeps the described electric current flowing through described current loop simultaneously;
Wherein said transmitter configuration one-tenth flows through the described electric current of described current loop to described receiver transmission of information by modulation, and described receiver passes through the described voltage of modulation across described two terminals of described current loop to described reflector transmission of information.
6. system as claimed in claim 5, wherein, described integrated circuit comprise be configured to demodulation is carried out for the electric current of the described modulation from described reflector and modulation across the modulator-demodulator (modulator-demodulator) of the described voltage of described two terminals of described current loop.
7. system as claimed in claim 6, comprises communication logic circuit, and it is configured to send information with modulated to described modulator-demodulator, and from described modulator-demodulator receiving demodulation information.
8. system as claimed in claim 5, wherein, the circuit of described integrated circuit provides the electric isolution between the circuit of described integrated circuit and external circuit.
9. an electronic circuit, comprising:
Resistor, is configured to form voltage across its terminal for the electric current flowing through the current loop formed between described electronic circuit and radiating circuit;
Differential amplifier, described signal transmission, to generate signal, is wherein supplied process to modulator-demodulator (modulator-demodulator) and analog to digital converter by the described voltage being configured to be formed for described resistor; And
Voltag driving circuit, is configured to from described modulator-demodulator Received signal strength, and modulates the voltage of the terminal across described current loop based on the described signal received from described modulator-demodulator.
10. electronic circuit as claimed in claim 9, wherein, described electronic circuit is formed as the part of integrated circuit completely.
11. electronic circuits as claimed in claim 9, wherein, described electronic circuit comprises at least one discrete assembly.
12. electronic circuits as claimed in claim 9, wherein, described Voltag driving circuit is arranged to and described resistor in series.
13. electronic circuits as claimed in claim 12, wherein, described Voltag driving circuit comprises:
Transistor, is configured to the described voltage modulating the described terminal across described current loop based on the signal of the grid being applied to described transistor; And
Summing circuit, is configured to the signal from described modulator-demodulator to add the signal flowing through described transistor, and produced signal is applied to the described grid of described transistor.
14. electronic circuits as claimed in claim 13, wherein, described transistor comprises bipolar junction transistor (BJT).
15. electronic circuits as claimed in claim 13, wherein, described transistor comprises metal oxide semiconductor transistor (MOSFET).
16. electronic circuits as claimed in claim 12, wherein, described Voltag driving circuit comprises summing circuit, and it is configured to the signal from described modulator-demodulator to add the signal flowing through described current loop, to modulate the described voltage of the described terminal across described current loop.
17. electronic circuits as claimed in claim 9, wherein, described Voltag driving circuit is arranged to and described capacitor in parallel.
18. electronic circuits as claimed in claim 17, wherein, described Voltag driving circuit comprises:
Summing circuit, is configured to the signal from described modulator-demodulator to add the electric current flowing through described current loop, with generate generation signal; And
Coupling capacitor, is configured to interchange (AC) component from described the produced signal of described summing circuit be passed through, to modulate the described voltage of the described terminal across described current loop.
19. electronic circuits as claimed in claim 9, comprise low pass filter, its be configured to by described signal transmission to the high fdrequency component leaching the described signal that described differential amplifier generates before described ADC.
20. electronic circuits as claimed in claim 9, wherein, described electronic circuit does not comprise transformer.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2013/072847 WO2014146243A1 (en) | 2013-03-19 | 2013-03-19 | Current loop voltage modulator for communication interface |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104221348A true CN104221348A (en) | 2014-12-17 |
| CN104221348B CN104221348B (en) | 2017-07-18 |
Family
ID=51579267
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201380019336.6A Expired - Fee Related CN104221348B (en) | 2013-03-19 | 2013-03-19 | Integrated circuit, electronic circuit and system for communication interface |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP2832071A4 (en) |
| CN (1) | CN104221348B (en) |
| WO (1) | WO2014146243A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2019219876A (en) * | 2018-06-19 | 2019-12-26 | 三菱日立パワーシステムズ株式会社 | Signal processing device and signal processing module |
| CN111200445A (en) * | 2018-11-16 | 2020-05-26 | 亚德诺半导体无限责任公司 | Communication transmitter interface for current loop circuit |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016082840A1 (en) * | 2014-11-28 | 2016-06-02 | Pr Electronics A/S | Low-power hart transmitter |
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| US20050097194A1 (en) * | 1999-09-29 | 2005-05-05 | Fisher Controls International Llc | Downloadable code in a distributed process control system |
| CN1969238A (en) * | 2004-06-28 | 2007-05-23 | 罗斯蒙德公司 | Process field device with radio frequency communication |
| CN101147181A (en) * | 2005-03-31 | 2008-03-19 | 罗斯蒙德公司 | Process control loop current verification |
| WO2011119892A1 (en) * | 2010-03-24 | 2011-09-29 | Mark Sinreich | Power management circuit for a wireless communication device and process control system using same |
| CN102279595A (en) * | 2010-05-11 | 2011-12-14 | 罗斯蒙德公司 | Two-wire industrial process field device with power scavenging |
| CN102736513A (en) * | 2011-03-29 | 2012-10-17 | 通用电气公司 | Hart channel interface component including redundancy |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102538904A (en) * | 2010-12-08 | 2012-07-04 | 上海自动化仪表股份有限公司 | HART (Highway Addressable Remote Transducer)-communication-based capacitive level transmitter and working method thereof |
-
2013
- 2013-03-19 CN CN201380019336.6A patent/CN104221348B/en not_active Expired - Fee Related
- 2013-03-19 WO PCT/CN2013/072847 patent/WO2014146243A1/en active Application Filing
- 2013-03-19 EP EP13878673.6A patent/EP2832071A4/en not_active Withdrawn
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050097194A1 (en) * | 1999-09-29 | 2005-05-05 | Fisher Controls International Llc | Downloadable code in a distributed process control system |
| CN1969238A (en) * | 2004-06-28 | 2007-05-23 | 罗斯蒙德公司 | Process field device with radio frequency communication |
| CN101147181A (en) * | 2005-03-31 | 2008-03-19 | 罗斯蒙德公司 | Process control loop current verification |
| WO2011119892A1 (en) * | 2010-03-24 | 2011-09-29 | Mark Sinreich | Power management circuit for a wireless communication device and process control system using same |
| CN102279595A (en) * | 2010-05-11 | 2011-12-14 | 罗斯蒙德公司 | Two-wire industrial process field device with power scavenging |
| CN102736513A (en) * | 2011-03-29 | 2012-10-17 | 通用电气公司 | Hart channel interface component including redundancy |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2019219876A (en) * | 2018-06-19 | 2019-12-26 | 三菱日立パワーシステムズ株式会社 | Signal processing device and signal processing module |
| JP7113677B2 (en) | 2018-06-19 | 2022-08-05 | 三菱重工業株式会社 | Signal processor and signal processing module |
| CN111200445A (en) * | 2018-11-16 | 2020-05-26 | 亚德诺半导体无限责任公司 | Communication transmitter interface for current loop circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| EP2832071A1 (en) | 2015-02-04 |
| WO2014146243A1 (en) | 2014-09-25 |
| CN104221348B (en) | 2017-07-18 |
| EP2832071A4 (en) | 2015-11-18 |
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