CN105976780B - A kind of panel drive circuit and display device - Google Patents
A kind of panel drive circuit and display device Download PDFInfo
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- CN105976780B CN105976780B CN201610544304.3A CN201610544304A CN105976780B CN 105976780 B CN105976780 B CN 105976780B CN 201610544304 A CN201610544304 A CN 201610544304A CN 105976780 B CN105976780 B CN 105976780B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The present invention provides a kind of panel drive circuit, including control circuit, first memory, second memory, selection circuit and sequence controller, the output end of the first memory is connect with the first input end of the selection circuit, the output end of the second memory is connect with the second input terminal of the selection circuit, the control terminal of the selection circuit is connect with the control circuit, and the output end of the selection circuit connects the sequence controller；The control circuit outputs level signals control the selection circuit to the selection circuit and the parameter information corresponding to different panels stored in the first memory or the second memory are sent to the sequence controller, and the sequence controller drives corresponding panel according to the parameter information.The same printed circuit board can be made to be compatible with two different panels through the invention, reach the suitability for enhancing printed circuit board, reduce the purpose of panel production cost.
Description
Technical field
The present invention relates to technical field of display panel more particularly to a kind of panel drive circuit and display devices.
Background technology
With the progress of electronics technology, especially portable electronic product in daily life is universal, for it is light and short,
The demand of the low display device of power consumption is growing day by day.Liquid crystal display panel (Liquid Crystal Display, LCD)
Device suitable for such electronic product, or even gradually takes since it has many advantages, such as that low power consumption, thickness are thin, light-weight
For traditional CRT Displays panel device.
The main driving principle of liquid crystal display panel is：System board believes R/G/B compressed signals, control signal and power
Number etc. data be stored in the memory on printed circuit board (Printed Circuit Board, PCB), on printed circuit board
Sequence controller (Timing Controller, TCON) IC call and handle the data in the memory after, by the data
It is sent to viewing area, so that liquid crystal display panel obtains required power supply and signal.However, due to the optics of different panels
The characteristics such as performance are different, different for the required data of different panels, and every time when booting, the sequence controller IC on PCB is needed
The data in memory are read, the characteristics such as the optical appearance of Display panel are adjusted further according to read data,
I other words a PCB, which can only be corresponded to, is adapted to a kind of panel of optical appearance characteristic, compatibility is poor.Therefore, there is an urgent need for one kind can
With the panel drive circuit of a variety of display panels of compatibility, to reduce the manufacturing cost of display panel.
Invention content
For problems of the prior art, the purpose of the present invention is to provide a kind of panel drive circuit, the drivings
Circuit may be implemented same PCB and be compatible with different liquid crystal display panels, improve PCB by selecting different memories
To the commonality of different liquid crystal display panels, the manufacturing cost of liquid crystal display panel is reduced.
In addition, another object of the present invention is to provide display device, the display device is using above-mentioned panel driving electricity
Road.
To achieve the goals above, embodiment of the present invention provides the following technical solutions：
The present invention provides a kind of panel drive circuit, including control circuit, first memory, second memory, selection electricity
Road and sequence controller, the output end of the first memory are connect with the first input end of the selection circuit, and described second
The output end of memory is connect with the second input terminal of the selection circuit, the control terminal of the selection circuit and control electricity
Road connects, and the output end of the selection circuit connects the sequence controller；
The control circuit outputs level signals control the selection circuit to the selection circuit and are deposited described first
The parameter information stored in the parameter information or the second memory of reservoir storage is sent to the sequence controller, when described
Sequence controller drives corresponding panel according to the parameter information, wherein the first memory and the second memory are deposited
The parameter information of storage corresponds respectively to different panels.
Wherein, the output end of the first memory includes the first data output end and the first output terminal of clock, the choosing
The first input end for selecting circuit includes the first data input pin and the first input end of clock, the second input terminal of the selection circuit
Including the second data input pin and second clock input terminal, the output end of the second memory include the second data output end and
Second clock output end, first data output end, first output terminal of clock respectively with first data input pin,
First input end of clock connects, and second data output end, the second clock output end are defeated with second data respectively
Enter end, the connection of second clock input terminal, the output end of the selection circuit includes data output end and output terminal of clock, the number
It is separately connected the data input pin of the sequence controller, input end of clock according to output end, the output terminal of clock；
The control circuit outputs level signals with control that the selection circuit will store in the first memory
One data information and the first clock information are sent in the sequence controller, or will stored in the second memory
Two data informations and second clock information are sent in the sequence controller.
Wherein, the selection circuit includes the first field-effect transistor, the second field-effect transistor, third field effect transistor
The source electrode of pipe and the 4th field-effect transistor, first field-effect transistor is electrically connected first data output end, described
The drain electrode of second field-effect transistor is electrically connected second data output end, the drain electrode of first field-effect transistor and institute
The source electrode for stating the second field-effect transistor is connected to the data input pin of the sequence controller, the third field-effect transistor
Source electrode be electrically connected first output terminal of clock, it is defeated that the drain electrode of the 4th field-effect transistor is electrically connected the second clock
Outlet, the drain electrode of the third field-effect transistor and the source electrode of the 4th field-effect transistor are connected to the timing control
The input end of clock of device, the first field-effect transistor, the second field-effect transistor, third field-effect transistor and the 4th field-effect
The grid of transistor is commonly connected to the control circuit.
Wherein, first field-effect transistor and the third field-effect transistor simultaneously turn on or end, and described
Two field-effect transistors and the 4th field-effect transistor end or are connected simultaneously, and first field-effect transistor and institute
State the state of the second field-effect transistor on the contrary, the third field-effect transistor and the 4th field-effect transistor state
On the contrary.
Wherein, first field-effect transistor and the third field-effect transistor are PMOS transistor, described second
Field-effect transistor and the 4th field-effect transistor are NMOS transistor；It is described when the control circuit output low level
First field-effect transistor and third field-effect transistor conducting and second field-effect transistor and 4th described
Effect transistor ends；Conversely, then first field-effect transistor and third field-effect transistor cut-off and described the
Two field-effect transistors and the 4th field-effect transistor conducting.
Wherein, the first memory and the second memory are band Electrically Erasable Programmable Read-Only Memory.
The present invention provides a kind of display device, wherein including the panel driving described in display panel and above-mentioned any one
Circuit.
Wherein, further include printed circuit board, the first memory, the second memory, the selection circuit and institute
It states sequence controller to be integrated in the printed circuit board, the control circuit is integrated in the panel.
Wherein, the sequence controller connects the display panel, and the sequence controller is connect by the selection circuit
The information for receiving the first memory or the second memory, to form the drive signal of the display panel.
The embodiment of the present invention has the following advantages that or advantageous effect：
In the present invention, it by the way that two memories are arranged to store different parameter informations, and is controlled by control circuit
Selection circuit gates any one in two memories, and the parameter information in the memory gated is transmitted to timing control
Device, then sequence controller two different panels are driven according to the parameter information received.It can make through the invention same
A printed circuit board is compatible with two different panels, reaches the suitability for enhancing printed circuit board, reduces panel production cost
Purpose.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
Obtain other attached drawings according to these attached drawings.
Fig. 1 is the circuit block diagram of the panel drive circuit of the embodiment of the present invention.
Fig. 2 is the circuit diagram of the panel drive circuit of the embodiment of the present invention.
Fig. 3 is the display device schematic diagram for having panel drive circuit shown in FIG. 1.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes, it is clear that described embodiment is only a part of the embodiment of the present invention, instead of all the embodiments.Base
Embodiment in the present invention, those of ordinary skill in the art are obtained all without making creative work
Other embodiments shall fall within the protection scope of the present invention.
In addition, the explanation of following embodiment is referred to the additional illustration, to illustrate the spy that the present invention can be used to implement
Determine embodiment.Direction terms mentioned in the present invention, for example, "upper", "lower", "front", "rear", "left", "right", "inner",
"outside", " side " etc. are only the directions with reference to annexed drawings, and therefore, the direction term used is to more preferably, more clearly say
It is bright and understand the present invention, rather than indicate or imply signified device or element must have a particular orientation, with specific side
Position construction and operation, therefore be not considered as limiting the invention.
In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, term " installation ", " phase
Even ", " connection " shall be understood in a broad sense, and can also be detachably connected, or integrally connect for example, it may be being fixedly connected
It connects；It can be mechanical connection；It can be directly connected, can also can be indirectly connected through an intermediary in two elements
The connection in portion.For the ordinary skill in the art, the tool of above-mentioned term in the present invention can be understood with concrete condition
Body meaning.
In addition, in the description of the present invention, unless otherwise indicated, the meaning of " plurality " is two or more.If this
The term for occurring " process " in specification, refers not only to independent process, when can not clearly be distinguished with other process, as long as
It can realize that the effect desired by the process is then also included in this term.In addition, the numerical value model indicated with "~" in this specification
It refers to the range that "~" front and back numerical value recorded is included as minimum value and maximum value to enclose.In the accompanying drawings, structure
Similar or identical is indicated by the same numeral.
Referring to Fig. 1, Fig. 1 is the circuit block diagram of the panel drive circuit of the present invention.Panel drive circuit 100 includes：Control
Circuit 10, first memory 20, second memory 30, selection circuit 40 and sequence controller 50 processed.The control circuit 10,
One memory 20, second memory 30 and the sequence controller 50 are respectively connected to the selection circuit 40.
Fig. 2 is please referred to, Fig. 2 is the circuit diagram of the panel drive circuit of the embodiment of the present invention.The present invention one is specific
Embodiment in, the output end 201 of the first memory 20 is connect with the first input end 41 of the selection circuit 40, described
The parameter information for controlling the sequential control circuit 50 is stored in first memory 20.The output end of the second memory 30
301 connect with the second input terminal 42 of the selection circuit 40, and the control sequential control is stored in the second memory 30
The parameter information of circuit 50 processed.The control terminal 43 of the selection circuit 40 is connect with the control circuit 10, the selection circuit
40 output end 44 connects the sequence controller 50.In inventive embodiments, the first memory 20 and second memory
The parameter information stored in 30 includes mainly the clock information and data information corresponding to different display panels.It is appreciated that
It is that the parameter information stored in first memory 20 and second memory 30 differs.
Please refer to Fig. 3, it is to be understood that the first memory 20, the second memory 30, the selection
Circuit 40 and the sequence controller 50 are integrated in same printed circuit board (Printed Circuit Board, PCB) 200.
The control circuit 10 can be integrated in a panel, and in one particular embodiment of the present invention, the control circuit 10 is integrated
In a panel 300 (hereinafter referred to as the first panel 300), i.e., the sequence controller 50 is arranged in pairs or groups panel be it is described the first
Panel 300.The first described panel 300 is connect with the printed circuit board 200, then the control circuit 10 generates low level letter
Number and be transmitted to the selection circuit 40, the selection circuit 40 connects the first memory according to the low level signal received
20 so that when the parameter information for corresponding to the first panel 300 stored in the first memory 20 is sent to described
Sequence controller 50, the sequence controller 50 is according to the parameter information received, to send out corresponding drive signal to described first
Kind panel 300.
It is understood that the control circuit 10 can also be integrated in another panel (hereinafter referred to as second of panel,
It is not shown) in, i.e., the sequence controller 50 is arranged in pairs or groups panel is second of panel, control circuit 10 in different panels
The level signal of generation is different.When printed circuit board 200 connects second of panel, the control circuit in second of panel
10 generation high level signals are simultaneously sent to the selection circuit 40, and the selection circuit 40 is gated according to the high level signal received
The second memory 30 so that the parameter information corresponding to second of panel stored in the second memory 30 is sent to
The sequence controller 50, the sequence controller 50 send out corresponding drive according to the parameter information stored in second memory 30
Signal is moved to second of panel.Wherein, the parameter information stored in the first memory 20 and second memory 30 is not
It is identical.
In the present invention, by the way that two memories are arranged to store different parameter informations, and pass through the control circuit
It controls the selection circuit and connects any one in two memories, and the parameter information in the memory having been turned on is transmitted to
Sequence controller, then sequence controller two different panels are driven according to the parameter information received.It through the invention can be with
So that same printed circuit board is compatible with two different panels, reach the suitability for enhancing printed circuit board, reduces panel life
Produce the purpose of cost.
It is exported specifically, the output end 201 of the first memory 20 includes the first data output end 21 and the first clock
End 22.The first input end 41 of the selection circuit 40 includes the first data input pin 411 and the first input end of clock 412, institute
The second input terminal 42 for stating selection circuit 40 includes the second data input pin 421 and second clock input terminal 422, the selection electricity
The output end 44 on road 40 includes data output end 441 and output terminal of clock 442.The output end 301 of the second memory 30 wraps
Include the second data output end 31 and second clock output end 32.First data output end 21 and first data input pin
411 connections, first output terminal of clock 22 are connect with first input end of clock 412, second data output end 31
It is connect with second data input pin 421, the second clock output end 32 is connect with the second clock input terminal 422.
The sequence controller 50 includes data input pin 51 and input end of clock 52.The data output end 441 connects the data
Input terminal 51, the output terminal of clock 442 connect the input end of clock 52.
Further specifically, the parameter information stored in the first memory 20 includes the first data information D1 and first
Clock information C1, and the first data information D1 and the first clock information C1 respectively by the first data output end 21 and first when
Clock output end 22 is sent in selection circuit 40.The parameter information stored in the second memory 30 includes the second data information
D2 and second clock information C2, and the second data information D2 and second clock information C2 pass through the second data output end 31 respectively
It is sent in selection circuit 40 with second clock output end 32, the selection circuit 40 is according to the electricity of the control circuit 10 received
Ordinary mail number (high level or low level) selects one group of parameter information in the first memory 20 or the second memory 30
And it is sent in the sequence controller 50.
In a specific embodiment of the invention, the selection circuit 40 include the first field-effect transistor T1, second
Effect transistor T2, third field-effect transistor T3 and the 4th field-effect transistor T4.The first field-effect transistor T1's
Source electrode (i.e. the first data input pin 411) is electrically connected first data output end 21, the second field-effect transistor T2's
Drain (i.e. the second data input pin 421) electrical connection second data output end 31, the first field-effect transistor T1's
Drain electrode is connected with the source electrode of the second field-effect transistor T2 collectively constitutes the data output end 441, and is connected to institute
State the data input pin 51 of sequence controller 50.Source electrode (i.e. the first input end of clock of the third field-effect transistor T3
412) first output terminal of clock 22, drain electrode (the i.e. second clock input terminal of the 4th field-effect transistor T4 are electrically connected
422) it is electrically connected the second clock output end 32, the drain electrode of the third field-effect transistor T3 and the 4th field-effect are brilliant
The source electrode of body pipe T4, which is connected, collectively constitutes the output terminal of clock 442, and the clock for being connected to the sequence controller 50 is defeated
Enter end 52.Wherein, the grid of the first field-effect transistor T1 is connected simultaneously with the grid of the second field-effect transistor T2
It is connected with the control terminal 43, the grid phase of the grid and the 4th field-effect transistor T4 of the third field-effect transistor T3
It connects and is connected with the control terminal 43, and the control circuit 10 is connected to by the control terminal 43.
It is understood that the first field-effect transistor T1 and the third field-effect transistor T3 simultaneously turn on or
Cut-off, the second field-effect transistor T2 and the 4th field-effect transistor T4 end simultaneously or conducting.That is, working as
When the first field-effect transistor T1 or third field-effect tube T3 are connected, then described second field-effect transistor T2 or the 4th
Effect pipe T4 is in cut-off state, to ensure first memory 20 and 30 one of both of second memory and the timing control
Device 50 is connected to.
Further specifically, the first field-effect transistor T1 and third field-effect transistor T3 is PMOS crystal
Pipe, the second field-effect transistor T2 and the 4th field-effect transistor T4 are NMOS transistor.It is understood that working as
When the control circuit 10 exports low level, the first field-effect transistor T1 and the third field-effect transistor T3 are led
It is logical, the second field-effect transistor T2 and the 4th field-effect transistor T4 cut-offs at this time；The control circuit 10 exports
When low level, then the first field-effect transistor T1 and third field-effect transistor T3 cut-offs, second field-effect
Transistor T2 and the 4th field-effect transistor T4 conductings.
Preferably, the first memory 20 and the second memory 30 are band Electrically Erasable Programmable Read-Only Memory
(Electrically Erasable Programmable Read-Only Memory, EEPROM).
Please continue to refer to Fig. 3, it is based on above-mentioned panel drive circuit, the present invention also provides a kind of display device 500, the displays
Device includes the panel drive circuit 100 and display panel 300 that above-mentioned Fig. 1 and Fig. 1 shown in Fig. 2 is the embodiment of the present invention.This
The display device 500 of invention further includes printed circuit board 200, and the first memory 20, institute are integrated on printed circuit board 200
State second memory 30, the selection circuit 40 and the sequence controller 50.
It is understood that the present invention display device 500 can include but is not limited to for：Electronic Paper, LCD TV, shifting
Any product or component with display function such as mobile phone, Digital Frame, tablet computer.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means particular features, structures, materials, or characteristics described in conjunction with this embodiment or example
It is included at least one embodiment or example of the invention.In the present specification, schematic expression of the above terms differ
Surely identical embodiment or example are referred to.Moreover, the particular features, structures, materials, or characteristics of description can be any one
It can be combined in any suitable manner in a or multiple embodiments or example.
Embodiments described above does not constitute the restriction to the technical solution protection domain.It is any in above-mentioned implementation
Modifications, equivalent substitutions and improvements etc., should be included in the protection model of the technical solution made by within the spirit and principle of mode
Within enclosing.
Claims (8)
1. a kind of panel drive circuit, which is characterized in that including control circuit, first memory, second memory, selection circuit
And sequence controller, the output end of the first memory are connect with the first input end of the selection circuit, described second deposits
The output end of reservoir is connect with the second input terminal of the selection circuit, the control terminal of the selection circuit and the control circuit
Connection, the output end of the selection circuit are connect with the sequence controller；
The control circuit outputs level signals control the selection circuit to the selection circuit by the first memory
The parameter information stored in the parameter information of storage or the second memory is sent to the sequence controller, the sequential control
Device processed drives corresponding panel according to the parameter information, wherein the first memory and second memory storage
Parameter information corresponds respectively to different panels；
The output end of the first memory includes the first data output end and the first output terminal of clock, and the of the selection circuit
One input terminal includes the first data input pin and the first input end of clock, and the second input terminal of the selection circuit includes the second number
According to input terminal and second clock input terminal, the output end of the second memory includes that the second data output end and second clock are defeated
Outlet, first data output end, first output terminal of clock are defeated with first data input pin, the first clock respectively
Enter end connection, second data output end, the second clock output end respectively with second data input pin, second when
Clock input terminal connects, and the output end of the selection circuit includes data output end and output terminal of clock, the data output end, institute
It states output terminal of clock and is separately connected the data input pin of the sequence controller, input end of clock；
The control circuit outputs level signals are to control the selection circuit by the stored in the first memory first number
It is believed that breath and the first clock information are sent in the sequence controller, or stored in the second memory second is counted
It is believed that breath and second clock information are sent in the sequence controller.
2. panel drive circuit as described in claim 1, which is characterized in that the selection circuit includes the first field effect transistor
Pipe, the second field-effect transistor, third field-effect transistor and the 4th field-effect transistor, first field-effect transistor
Source electrode is electrically connected first data output end, and the drain electrode of second field-effect transistor is electrically connected the second data output
End, the drain electrode of first field-effect transistor and the source electrode of second field-effect transistor are connected to the sequence controller
Data input pin, the source electrode of the third field-effect transistor is electrically connected first output terminal of clock, the 4th effect
The drain electrode of transistor is answered to be electrically connected the second clock output end, the drain electrode of the third field-effect transistor and 4th described
The source electrode of effect transistor is connected to the input end of clock of the sequence controller, the first field-effect transistor, the second field-effect
The grid of transistor, third field-effect transistor and the 4th field-effect transistor is commonly connected to the control circuit.
3. panel drive circuit as claimed in claim 2, which is characterized in that first field-effect transistor and the third
Field-effect transistor simultaneously turns on or ends, and second field-effect transistor and the 4th field-effect transistor end simultaneously
Or conducting, and the state of first field-effect transistor and second field-effect transistor is on the contrary, the third field-effect
The state of transistor and the 4th field-effect transistor is opposite.
4. panel drive circuit as claimed in claim 2, which is characterized in that first field-effect transistor and the third
Field-effect transistor is PMOS transistor, and second field-effect transistor and the 4th field-effect transistor are NMOS crystal
Pipe；When control circuit output low level, first field-effect transistor and third field-effect transistor conducting and
Second field-effect transistor and the 4th field-effect transistor cut-off；When control circuit output low level, then institute
State the first field-effect transistor and third field-effect transistor cut-off and second field-effect transistor and the described 4th
Field-effect transistor is connected.
5. panel drive circuit as described in claim 1, which is characterized in that the first memory and the second memory
For band Electrically Erasable Programmable Read-Only Memory.
6. a kind of display device, which is characterized in that including the panel driving described in display panel and claim 1-5 any one
Circuit.
7. display device as claimed in claim 6, which is characterized in that the display device further includes printed circuit board, described
First memory, the second memory, the selection circuit and the sequence controller are integrated in the printed circuit board,
The control circuit is integrated in the display panel.
8. display device as claimed in claim 7, which is characterized in that the sequence controller connects the display panel, institute
The parameter information that sequence controller receives the first memory or the second memory by the selection circuit is stated, with shape
At the drive signal of the display panel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610544304.3A CN105976780B (en) | 2016-07-11 | 2016-07-11 | A kind of panel drive circuit and display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610544304.3A CN105976780B (en) | 2016-07-11 | 2016-07-11 | A kind of panel drive circuit and display device |
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| CN105976780B true CN105976780B (en) | 2018-08-07 |
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Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018120141A1 (en) * | 2016-12-30 | 2018-07-05 | 深圳市柔宇科技有限公司 | Circuit board structure, in-plane drive circuit and display device |
| CN107680535B (en) * | 2017-09-29 | 2019-10-25 | 深圳市华星光电半导体显示技术有限公司 | The scan drive system of AMOLED display panel |
| CN109119040A (en) * | 2018-09-18 | 2019-01-01 | 惠科股份有限公司 | Display device, the driving configuration method of display device and display |
| CN110491332A (en) * | 2019-09-30 | 2019-11-22 | 京东方科技集团股份有限公司 | Driver, display device and its application method |
| CN111063314A (en) * | 2019-12-25 | 2020-04-24 | Tcl华星光电技术有限公司 | Display device |
| CN111833797A (en) * | 2020-07-28 | 2020-10-27 | 重庆惠科金渝光电科技有限公司 | Time sequence control plate, driving device and display device |
| CN111883037A (en) | 2020-07-28 | 2020-11-03 | 重庆惠科金渝光电科技有限公司 | Time sequence control plate, driving device and display device |
| CN112652274A (en) * | 2020-12-24 | 2021-04-13 | 联想(北京)有限公司 | Backlight control method and device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP4927311B2 (en) * | 2003-08-27 | 2012-05-09 | 株式会社日立製作所 | VIDEO DISPLAY DEVICE, DISPLAY UNIT DRIVE CIRCUIT USED FOR THE SAME |
| KR100539263B1 (en) * | 2004-05-14 | 2005-12-27 | 삼성전자주식회사 | Dual panel driving system and driving method |
| CN101192399A (en) * | 2006-11-29 | 2008-06-04 | 群康科技(深圳)有限公司 | Double screen driving circuit |
| KR101482263B1 (en) * | 2008-03-05 | 2015-01-13 | 삼성전자주식회사 | Device and method for distinguishing display panel |
| KR101319342B1 (en) * | 2008-11-25 | 2013-10-16 | 엘지디스플레이 주식회사 | Multi-panel display and method of driving the same |
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