CN105957832A - Wiring method of superconducting quantum bit system for surface coding scheme and wiring board - Google Patents
Wiring method of superconducting quantum bit system for surface coding scheme and wiring board Download PDFInfo
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- CN105957832A CN105957832A CN201610317372.6A CN201610317372A CN105957832A CN 105957832 A CN105957832 A CN 105957832A CN 201610317372 A CN201610317372 A CN 201610317372A CN 105957832 A CN105957832 A CN 105957832A
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- insulating barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Abstract
The invention provides a wiring method of a superconducting quantum bit system for a surface coding scheme and a wiring board, and belongs to the field of a quantum system. The wiring board comprises a quantum chip substrate, a plurality of insulating layers, a wiring layer and a plurality of grounding layers, wherein the quantum chip substrate is provided with a plurality of quantum bits and a plurality of couplers, and the insulating layers are arranged at the lower surface of the quantum chip substrate in a covering manner; the wiring layer is arranged in the insulating layers of the plurality of insulating layers, and the wiring layer is connected with the quantum bits and/or the couplers; and the plurality of grounding layers are correspondingly arranged at the upper surfaces and the lower surfaces of the plurality of insulating layers. According to the wiring method provided by the invention of the superconducting quantum bit system for the surface coding scheme and the wiring board, a problem that the quantum bit de-coherence time is reduced because key devices such as the quantum bits are covered with an insulating film is avoided through the wiring board provided with the quantum chip substrate, the insulating layers and the grounding layers.
Description
Technical field
The present invention relates to quantized system field, particularly relate to a kind of for encoded surface scheme Superconducting Quantum ratio
The wiring method of special system and wiring plate.
Background technology
Quantum calculation is decomposed at big prime factors, and the solving speed aspect of the mathematical problems such as global search is better than
The traditional counting algorithm known.People achieve some simple quantum in multiple different quantum regime and calculate
Method, superconductive quantum bit system is one of the most most promising system.
The most fragile yet with existing quantum-bit systems, the various noises in environment all can cause quantum
The quick decoherence of bit system, it is impossible to complete more complicated quantum algorithm.In order to overcome this problem, one
Aspect, people put forth effort on the decoherence time improving quantum-bit systems；On the other hand, Shor et al. uses for reference
The error correction coding scheme of classic computer, it is proposed that for the error correction coding scheme of quantum computing systems.
Along with theoretical development, there has been proposed the multiple error correction coding scheme for quantum computing systems, its
In encoded surface (English name Surface Code) scheme be hopeful most owing to following two reason becomes
One of encoding scheme: 1, error detection check code only comprises local check code, and this is particularly suitable for Superconducting Quantum
Bit system, because major part superconductive quantum bit system can only realize local coupling；2, higher fault-tolerant
Threshold value, the error rate of current superconductive quantum bit system has reached the fault-tolerant threshold value of encoded surface scheme and has wanted
Ask.Encoded surface scheme requires quantum-bit systems to be arranged in certain Colloidal particles, each quantum ratio
Spy can realize coupling with the controlled of the bit of neighbouring quantum.In actual quantum-bit systems, except
Outside quantum bit, system also comprises many functional arrangements.
If quantum bit and all circuits are all placed in approximately the same plane, quantum bit and line, line and line it
Between can inevitably occur overlapping.But quantum-bit systems is the most fragile, quantum bit covers
Insulating barrier may result in the decoherence time of quantum bit and greatly reduces, and ultimately resulting in it cannot work.
The wiring of the superconductive quantum bit system how realizing encoded surface scheme is that everybody compares the one of care at present
Individual problem.
Summary of the invention
It is an object of the present invention to provide a kind of cloth for encoded surface scheme superconductive quantum bit system
Line plate, it is possible to avoid covering dielectric film on the Primary Components such as quantum bit, when causing quantum bit decoherence
Between decline problem.
Especially, the invention provides a kind of wiring for encoded surface scheme superconductive quantum bit system
Plate, including:
Quantum chip substrate, described quantum chip substrate is provided with several quantum bits and several couple
Device, direct-coupling or by described between any two adjacent quantum bits in several quantum bits described
Corresponding bonder coupling in several bonders；
Several insulating barriers；Described insulating barrier covers the lower surface being arranged on described quantum chip substrate；
Wiring layer, described wiring layer is arranged in the insulating barrier in several insulating barriers described, described wiring layer
It is connected with described quantum bit and/or described bonder；And
Several ground planes；Several ground planes described are correspondingly arranged in the upper surface of several insulating barriers described
And lower surface.
Further, the quantum bit on described quantum chip substrate is with lattice-like arrangement.
Further, described quantum chip substrate is provided with several holes, and described wiring layer is by through described
The lead-in wire in hole is connected with the control line of the control line of described quantum bit or described bonder.
Further, several holes described are arranged at several quantum bits described and several bonders described
The gap location formed.
Further, several ground planes described are metal level.
Further, in the same insulating barrier during described wiring layer is arranged on several insulating barriers described.
Further, in the different insulating barrier during described wiring layer is arranged on several insulating barriers described.
Present invention also offers a kind of wiring method for encoded surface scheme superconductive quantum bit system, should
Being used in the wiring plate of the superconductive quantum bit system with quantum chip substrate, insulating barrier, ground plane, it is special
Levy and be, connect up in the lower section of described quantum chip substrate, described quantum chip substrate punches, described
It is routed through described hole and the connection on described quantum chip substrate.
Further, described wiring is one layer or multilamellar；Described wiring is arranged on same described insulating barrier
Or in different described insulating barriers.
Further, the upper and lower surface of described insulating barrier is coated with the ground plane of metal material.
The wiring method for encoded surface scheme superconductive quantum bit system of present invention offer and wiring plate,
It is provided by the wiring plate of quantum chip substrate, insulating barrier, ground plane, it is to avoid close at quantum bit etc.
Cover dielectric film on key device, cause the problem that the quantum bit decoherence time declines.
Accompanying drawing explanation
Some describing the present invention the most by way of example, and not by way of limitation in detail are concrete
Embodiment.Reference identical in accompanying drawing denotes same or similar parts or part.Art technology
Personnel are it should be understood that what these accompanying drawings were not necessarily drawn to scale.In accompanying drawing:
Fig. 1 is a kind of for encoded surface scheme superconductive quantum bit system according to an embodiment of the invention
The structural representation of wiring plate；
Fig. 2 is a kind of for encoded surface scheme superconductive quantum bit system according to an embodiment of the invention
The schematic top plan view of wiring plate.
Detailed description of the invention
Embodiment 1
Fig. 1 is a kind of for encoded surface scheme superconductive quantum bit system according to an embodiment of the invention
The structural representation of wiring plate, Fig. 2 is a kind of for encoded surface side according to an embodiment of the invention
The schematic top plan view of the wiring plate of case superconductive quantum bit system.As it is shown in figure 1, it is a kind of for encoded surface
The wiring plate of scheme superconductive quantum bit system, including: quantum chip substrate 1, several insulating barriers 2,
Several ground planes 3 and wiring layer 4.Several quantum bit 11 (figures it are provided with on quantum chip substrate 1
2 illustrate) and several bonders 12 (Fig. 2 illustrates), several quantum bits 11 (Fig. 2 illustrates) described
In direct-coupling or by several bonders 12 (figures described between any two adjacent quantum bits 11
2 illustrate) in corresponding bonder 12 couple；Insulating barrier 2 covers and is arranged on described quantum chip substrate
The lower surface of 1；Wiring layer 4 is arranged in described insulating barrier 2, described wiring layer 4 and described quantum bit
11 (Fig. 2 illustrates) and/or described bonder 12 (Fig. 2 illustrates) connect；Described ground plane 3 correspondence sets
It is placed in the upper and lower surface of several insulating barriers 2 described.
Specifically, as in figure 2 it is shown, the quantum bit 11 on quantum chip substrate 1 is with two-dimentional lattice-like
Arrangement, each quantum bit 11 can realize coupling with the controlled of neighbouring quantum bit 11, or quantum
Bit 11 can realize coupling with the controlled of neighbouring bonder 12.Each quantum bit 11 amount of having
The control line 14 of sub-bit, each bonder 12 is respectively provided with the control line 15 of bonder, quantum bit
The control line 15 of control line 14 and bonder protrudes and is arranged on quantum chip substrate 1, is used for and wiring layer
4 connect.Being provided with several holes 13 on quantum chip substrate 1, several holes 13 described are arranged at quantum
The gap location that on chip substrate 1, several quantum bits 11 and several bonders 12 are formed, described some
Size, shape and the position in individual hole 13 can select according to cabling requirement, alternatively, if described
The shape in dry hole 13 is circular or polygonal, preferably circular.Wiring layer 4 in insulating barrier 2
By control line 14 or the control line 15 of bonder 12 of lead-in wire 41 and quantum bit 11 through hole 13
Connect.Of course, quantum chip substrate 1 being also provided with other element, its wiring can also be led to
Cross the lead-in wire through hole 13 to connect.Wiring layer 4 is positioned at the insulating barrier 2 of the lower section of quantum chip substrate 1.
The upper and lower surface of each described insulating barrier 2 all covers and is provided with ground plane 3, to reduce outside making an uproar
Sound or other factors are to the interference of circuit and the circuit interference to quantum bit 11.Ground plane 3 is gold
Belong to material, can be aluminium foil layer, tinfoil paper layer, wire netting or other conductive layer.So can avoid
The quantum bit decoherence time decline that dielectric film causes is covered on the Primary Components such as quantum bit.
In a specific embodiment, it is same that wiring layer 4 is arranged in several insulating barriers 2 described
In individual insulating barrier 2.It is applicable to institute's wiring topology relatively simple time, wiring layer 4 produce interference less.
In another particular embodiment of the invention, wiring layer 4 is different in being arranged on several insulating barriers 2 described
Insulating barrier 2 in.It is complex that it is applicable to institute's wiring topology, can produce bigger interference between wiring layer 4,
Now wiring layer 4 is separately positioned in different insulating barriers 2, then the upper and lower surface of each insulating barrier 2
Place all covers and is provided with ground plane 3, i.e. by ground plane 3 between the insulating barrier 2 of different wiring layers 4
Separate, thus reduce the crosstalk between different circuit, it is possible to increase the fidelity of signal.
Embodiment 2
Present invention also offers a kind of wiring method for encoded surface scheme superconductive quantum bit system, should
It is used in the superconductive quantum bit system foregoing with quantum chip substrate 1, insulating barrier 2, ground plane 3
The wiring plate of system, including: connect up in the lower section of described quantum chip substrate 1, at described quantum chip substrate
Punch 13 on 1, described in be routed through described hole 13 and the connection on described quantum chip substrate 1,
Described wiring forms wiring layer 4.
In one preferred embodiment, wiring layer 4 is arranged in the insulating barrier below quantum chip substrate 1
In 2, the insulating barrier 3 being equipped with wiring layer 4 can be one layer or multilamellar；Described wiring layer 4 can be arranged
In same described insulating barrier 2 or different described insulating barriers 2.Preferably, the upper table of insulating barrier 2
Face and lower surface are coated with the ground plane 3 of metal material.The metal material of ground plane 3 can be aluminium foil layer,
Tinfoil paper layer, wire netting or other conductive layer, do circuit reducing external noise or other factors
Disturb and the circuit interference to quantum bit 11.
The wiring plate for encoded surface scheme superconductive quantum bit system that the present invention provides, is provided by
Quantum chip substrate 1, several insulating barriers 2 and several ground planes 3, and it is arranged on quantum chip base
The hole 13 of 1 on sheet so that the wiring layer 4 in insulating barrier 2 is by hole 13 and quantum chip substrate 1
Element connects, it is to avoid covers dielectric film on the Primary Components such as quantum bit, causes quantum bit decoherence
The problem that time declines；By all covering in the upper and lower surface of insulating barrier 2, ground plane 3 is set, it is possible to reduce
External noise is to the interference of circuit and the circuit interference to quantum bit；It is separately positioned on by wiring layer 4
In different insulating barriers 2, then separated by ground plane 3 between the insulating barrier 2 of different wiring layers 4,
Thus reduce the crosstalk between different circuit, it is possible to increase the fidelity of signal.
The wiring method for encoded surface scheme superconductive quantum bit system that the present invention provides, by institute
Stating punching 13 on quantum chip substrate 1, described wiring layer 4 is by described hole 13 and described quantum chip base
Connection on sheet 1, it is to avoid cover dielectric film on the Primary Components such as quantum bit, cause quantum ratio
The problem that the special decoherence time declines；By all covering in the upper and lower surface of insulating barrier 2, ground plane 3 is set,
External noise can be reduced to the interference of circuit and the circuit interference to quantum bit；By wiring layer 4 points
It is not arranged in different insulating barriers 2, then passes through ground plane between the insulating barrier 2 of different wiring layers 4
3 separate, thus reduce the crosstalk between different circuit, it is possible to increase the fidelity of signal.
So far, although those skilled in the art will appreciate that and the most detailed illustrate and describing the present invention's
Exemplary embodiment, but, without departing from the spirit and scope of the present invention, still can be according to the present invention
Disclosure directly determines or derives other variations or modifications of many meeting the principle of the invention.Therefore,
The scope of the present invention is it is understood that and regard as covering other variations or modifications all these.
Claims (10)
1. the wiring plate for encoded surface scheme superconductive quantum bit system, it is characterised in that including:
Quantum chip substrate, described quantum chip substrate is provided with several quantum bits and several couple
Device, direct-coupling or by described between any two adjacent quantum bits in several quantum bits described
Corresponding bonder coupling in several bonders；
Several insulating barriers；Described insulating barrier covers the lower surface being arranged on described quantum chip substrate；
Wiring layer, described wiring layer is arranged in the insulating barrier in several insulating barriers described, described wiring layer
It is connected with described quantum bit and/or described bonder；And
Several ground planes；Several ground planes described are correspondingly arranged in the upper surface of several insulating barriers described
And lower surface.
Wiring plate the most according to claim 1, it is characterised in that the amount on described quantum chip substrate
Sub-bit is with lattice-like arrangement.
Wiring plate the most according to claim 1 and 2, it is characterised in that on described quantum chip substrate
Be provided with several holes, described wiring layer by through described hole lead-in wire and the control line of described quantum bit or
The control line of described bonder connects.
Wiring plate the most according to claim 3, it is characterised in that several holes described are arranged at described
The gap location that several quantum bits and several bonders described are formed.
5. according to the wiring plate according to any one of claim 1-4, it is characterised in that described several connect
Stratum is metal level.
6. according to the wiring plate according to any one of claim 1-5, it is characterised in that described wiring layer sets
Put in the same insulating barrier in several insulating barriers described.
7. according to the wiring plate according to any one of claim 1-5, it is characterised in that described wiring layer sets
Put in the different insulating barrier in several insulating barriers described.
8., for a wiring method for encoded surface scheme superconductive quantum bit system, apply in the amount of having
Sub-chip substrate, insulating barrier, the wiring plate of superconductive quantum bit system of ground plane, it is characterised in that
Described quantum chip substrate lower section wiring, on described quantum chip substrate punch, described in be routed through institute
State hole and the connection on described quantum chip substrate.
Wiring method the most according to claim 8, it is characterised in that described wiring is one layer or many
Layer；Described wiring is arranged in same described insulating barrier or different described insulating barriers.
Wiring method the most according to claim 8 or claim 9, it is characterised in that described insulating barrier upper
Surface and lower surface are coated with the ground plane of metal material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610317372.6A CN105957832B (en) | 2016-05-12 | 2016-05-12 | Wiring method and wiring board for surface coding scheme superconducting qubit system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610317372.6A CN105957832B (en) | 2016-05-12 | 2016-05-12 | Wiring method and wiring board for surface coding scheme superconducting qubit system |
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| Publication Number | Publication Date |
|---|---|
| CN105957832A true CN105957832A (en) | 2016-09-21 |
| CN105957832B CN105957832B (en) | 2020-09-22 |
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| CN201610317372.6A Active CN105957832B (en) | 2016-05-12 | 2016-05-12 | Wiring method and wiring board for surface coding scheme superconducting qubit system |
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Cited By (9)
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|---|---|---|---|---|
| CN107564868A (en) * | 2017-07-07 | 2018-01-09 | 清华大学 | A kind of integrated encapsulation structure and method of Superconducting Quantum computing chip |
| CN109376870A (en) * | 2018-10-18 | 2019-02-22 | 清华大学 | A kind of superconductive quantum bit chip |
| CN109376866A (en) * | 2018-09-17 | 2019-02-22 | 合肥本源量子计算科技有限责任公司 | The operation method and device of the recording method of metadata and device, quantum program |
| CN109597347A (en) * | 2018-04-28 | 2019-04-09 | 合肥本源量子计算科技有限责任公司 | A kind of quantum chip feedback |
| WO2019106417A1 (en) * | 2017-11-28 | 2019-06-06 | International Business Machines Corporation | System and method for routing signals in complex quantum systems |
| CN111598248A (en) * | 2020-05-18 | 2020-08-28 | 南京希凌陆信息科技有限公司 | Superconducting quantum chip and method for realizing control phase gate |
| CN112423474A (en) * | 2019-08-23 | 2021-02-26 | 中国科学技术大学 | Preparation method of circuit board and circuit board |
| CN113725208A (en) * | 2021-08-13 | 2021-11-30 | 中国科学院物理研究所 | Three-dimensional quantum chip and preparation method thereof |
| CN114580338A (en) * | 2022-02-21 | 2022-06-03 | 北京百度网讯科技有限公司 | Analog wiring method, manufacturing method, chip, device, equipment and storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107564868B (en) * | 2017-07-07 | 2019-08-02 | 清华大学 | A kind of integrated encapsulation structure and method of Superconducting Quantum computing chip |
| CN107564868A (en) * | 2017-07-07 | 2018-01-09 | 清华大学 | A kind of integrated encapsulation structure and method of Superconducting Quantum computing chip |
| JP2021504948A (en) * | 2017-11-28 | 2021-02-15 | インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ | Systems and methods for routing signals in composite quantum systems |
| GB2582085B (en) * | 2017-11-28 | 2022-05-11 | Ibm | System and method for routing signals in complex quantum systems |
| WO2019106417A1 (en) * | 2017-11-28 | 2019-06-06 | International Business Machines Corporation | System and method for routing signals in complex quantum systems |
| US10347605B2 (en) | 2017-11-28 | 2019-07-09 | International Business Machines Corporation | System and method for routing signals in complex quantum systems |
| JP7026791B2 (en) | 2017-11-28 | 2022-02-28 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Systems and methods for routing signals in complex quantum systems |
| US10658340B2 (en) | 2017-11-28 | 2020-05-19 | International Business Machines Corporation | Signal routing in complex quantum systems |
| CN111357020B (en) * | 2017-11-28 | 2023-08-25 | 国际商业机器公司 | System and method for routing signals in complex quantum systems |
| CN111357020A (en) * | 2017-11-28 | 2020-06-30 | 国际商业机器公司 | System and method for routing signals in complex quantum systems |
| GB2582085A (en) * | 2017-11-28 | 2020-09-09 | Ibm | System and method for routing signals in complex quantum systems |
| CN109597347A (en) * | 2018-04-28 | 2019-04-09 | 合肥本源量子计算科技有限责任公司 | A kind of quantum chip feedback |
| CN109597347B (en) * | 2018-04-28 | 2020-06-12 | 合肥本源量子计算科技有限责任公司 | Quantum chip feedback control method |
| CN109376866A (en) * | 2018-09-17 | 2019-02-22 | 合肥本源量子计算科技有限责任公司 | The operation method and device of the recording method of metadata and device, quantum program |
| CN109376870A (en) * | 2018-10-18 | 2019-02-22 | 清华大学 | A kind of superconductive quantum bit chip |
| CN109376870B (en) * | 2018-10-18 | 2021-04-23 | 清华大学 | Superconducting quantum bit chip |
| CN112423474A (en) * | 2019-08-23 | 2021-02-26 | 中国科学技术大学 | Preparation method of circuit board and circuit board |
| CN111598248A (en) * | 2020-05-18 | 2020-08-28 | 南京希凌陆信息科技有限公司 | Superconducting quantum chip and method for realizing control phase gate |
| CN111598248B (en) * | 2020-05-18 | 2024-03-12 | 南京优算量子科技有限公司 | Superconducting quantum chip and method for realizing control of phase gate |
| CN113725208A (en) * | 2021-08-13 | 2021-11-30 | 中国科学院物理研究所 | Three-dimensional quantum chip and preparation method thereof |
| CN114580338A (en) * | 2022-02-21 | 2022-06-03 | 北京百度网讯科技有限公司 | Analog wiring method, manufacturing method, chip, device, equipment and storage medium |
| CN114580338B (en) * | 2022-02-21 | 2023-02-28 | 北京百度网讯科技有限公司 | Analog wiring method, manufacturing method, chip, device, equipment and storage medium |
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|---|---|
| CN105957832B (en) | 2020-09-22 |
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