CN105957832B - Wiring method and wiring board for surface coding scheme superconducting qubit system - Google Patents
Wiring method and wiring board for surface coding scheme superconducting qubit system Download PDFInfo
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- CN105957832B CN105957832B CN201610317372.6A CN201610317372A CN105957832B CN 105957832 B CN105957832 B CN 105957832B CN 201610317372 A CN201610317372 A CN 201610317372A CN 105957832 B CN105957832 B CN 105957832B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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Abstract
The invention provides a wiring method and a wiring board for a surface coding scheme superconducting qubit system, and belongs to the field of quantum systems. The wiring board comprises a quantum chip substrate, a plurality of insulating layers, a wiring layer and a plurality of grounding layers, wherein a plurality of quantum bits and a plurality of couplers are arranged on the quantum chip substrate, and the insulating layers cover the lower surface of the quantum chip substrate; the wiring layer is arranged in an insulating layer of the plurality of insulating layers and is connected with the quantum bit and/or the coupler; the plurality of grounding layers are correspondingly arranged on the upper surfaces and the lower surfaces of the plurality of insulating layers. The wiring method and the wiring board for the surface coding scheme superconducting qubit system provided by the invention have the advantages that the problem of reduced qubit decoherence time caused by the fact that the insulating film is covered on key devices such as qubits and the like is solved through the wiring board provided with the quantum chip substrate, the insulating layer and the grounding layer.
Description
Technical Field
The invention relates to the field of quantum systems, in particular to a wiring method and a wiring board for a surface coding scheme superconducting qubit system.
Background
The quantum computation is superior to the known classical computation algorithm in the aspect of solving speed of mathematical problems such as large prime factorization, global search and the like. Some simple quantum algorithms have been implemented in a number of different quantum systems, superconducting qubit systems being one of the most promising of them.
However, the existing qubit system is very fragile, and various noises in the environment can cause the fast decoherence of the qubit system, so that a more complex quantum algorithm cannot be completed. To overcome this problem, on the one hand, efforts are being made to increase the decoherence time of qubit systems; on the other hand, Shor et al propose an error correction coding scheme for quantum computing systems, with reference to the error correction coding scheme of classical computers.
With the development of theory, various error correction coding schemes for quantum computing systems have been proposed, and the Surface coding (Surface Code) scheme is one of the most promising coding schemes for the following two reasons: 1. the error detection check code only comprises a local check code, which is particularly suitable for the superconducting qubit system, because most superconducting qubit systems can only realize local coupling; 2. the error rate of the superconducting qubit system reaches the fault-tolerant threshold requirement of the surface coding scheme at present due to a higher fault-tolerant threshold. Surface coding schemes require that the qubit system be arranged in a two-dimensional lattice structure, each qubit enabling controllable coupling to bits of adjacent quanta. In a practical qubit system, the system contains many operating lines in addition to the qubits.
If the qubit and all the lines are placed in the same plane, the qubit and the lines, and the lines and lines will inevitably overlap. However, qubit systems are extremely fragile and the insulating layer overlying the qubit may cause the decoherence time of the qubit to be greatly reduced, eventually rendering it inoperable. The wiring of superconducting qubit systems for implementing surface coding schemes is a problem of considerable interest today.
Disclosure of Invention
It is an object of the present invention to provide a wiring board for a surface coding scheme superconducting qubit system that avoids the problem of reduced qubit de-coherence time caused by the covering of critical devices such as qubits with an insulating film.
In particular, the present invention provides a wiring board for a surface coding scheme superconducting qubit system, comprising:
the quantum chip comprises a quantum chip substrate, wherein a plurality of qubits and a plurality of couplers are arranged on the quantum chip substrate, and any two adjacent qubits in the plurality of qubits are directly coupled or coupled through the corresponding couplers in the plurality of couplers;
a plurality of insulating layers; the insulating layer covers the lower surface of the quantum chip substrate;
a wiring layer disposed within an insulating layer of the number of insulating layers, the wiring layer connected with the qubit and/or the coupler; and
a plurality of ground planes; the plurality of grounding layers are correspondingly arranged on the upper surfaces and the lower surfaces of the plurality of insulating layers.
Further, the qubits on the quantum chip substrate are arranged in a lattice.
Furthermore, a plurality of holes are formed in the quantum chip substrate, and the wiring layer is connected with the control line of the qubit or the control line of the coupler through a lead wire penetrating through the holes.
Further, the number of holes is disposed at a gap formed by the number of qubits and the number of couplers.
Furthermore, the plurality of grounding layers are all metal layers.
Further, the wiring layer is disposed in the same one of the insulating layers.
Further, the wiring layers are disposed within different ones of the plurality of insulating layers.
The invention also provides a wiring method for the surface coding scheme superconducting qubit system, which is applied to a wiring board of the superconducting qubit system with a quantum chip substrate, an insulating layer and a grounding layer.
Further, the wiring is one or more layers; the wirings are provided in the same insulating layer or different insulating layers.
Furthermore, the upper surface and the lower surface of the insulating layer are covered with metal grounding layers.
The wiring method and the wiring board for the surface coding scheme superconducting qubit system provided by the invention have the advantages that the problem of reduced qubit decoherence time caused by the fact that the insulating film is covered on key devices such as qubits and the like is solved through the wiring board provided with the quantum chip substrate, the insulating layer and the grounding layer.
Drawings
Some specific embodiments of the invention will be described in detail hereinafter, by way of illustration and not limitation, with reference to the accompanying drawings. The same reference numbers in the drawings identify the same or similar elements or components. Those skilled in the art will appreciate that the drawings are not necessarily drawn to scale. In the drawings:
FIG. 1 is a schematic diagram of the structure of a wiring board for a surface coding scheme superconducting qubit system in accordance with an embodiment of the present invention;
fig. 2 is a schematic top view of a wiring board for a surface coding scheme superconducting qubit system in accordance with an embodiment of the invention.
Detailed Description
Example 1
Fig. 1 is a schematic structural diagram of a wiring board for a surface coding scheme superconducting qubit system in accordance with an embodiment of the present invention, and fig. 2 is a schematic top view of a wiring board for a surface coding scheme superconducting qubit system in accordance with an embodiment of the present invention. As shown in fig. 1, a wiring board for a surface coding scheme superconducting qubit system, comprising: quantum chip substrate 1, a number of insulating layers 2, a number of ground layers 3 and a wiring layer 4. A plurality of qubits 11 (shown in fig. 2) and a plurality of couplers 12 (shown in fig. 2) are disposed on the quantum chip substrate 1, and any two adjacent qubits 11 in the plurality of qubits 11 (shown in fig. 2) are directly coupled or coupled through the corresponding coupler 12 in the plurality of couplers 12 (shown in fig. 2); the insulating layer 2 covers the lower surface of the quantum chip substrate 1; a wiring layer 4 is disposed within the insulating layer 2, the wiring layer 4 being connected to the qubits 11 (shown in fig. 2) and/or the couplers 12 (shown in fig. 2); the ground layer 3 is correspondingly disposed on the upper and lower surfaces of the plurality of insulating layers 2.
Specifically, as shown in fig. 2, qubits 11 on a quantum chip substrate 1 are arranged in a two-dimensional lattice, each qubit 11 enabling controllable coupling with an adjacent qubit 11, or a qubit 11 enabling controllable coupling with an adjacent coupler 12. Each qubit 11 has a qubit control line 14, each coupler 12 has a coupler control line 15, and the qubit control lines 14 and the coupler control lines 15 are arranged protruding on the quantum chip substrate 1 for connection to the wiring layer 4. A plurality of holes 13 are formed in the quantum chip substrate 1, the plurality of holes 13 are formed in the quantum chip substrate 1 at the gaps formed by the plurality of quantum bits 11 and the plurality of couplers 12, the size, shape and position of the plurality of holes 13 can be selected according to the wiring requirements, and optionally, the plurality of holes 13 are circular or polygonal, preferably circular. The wiring layer 4 within the insulating layer 2 is connected to the control line 14 of the qubit 11 or the control line 15 of the coupler 12 by a lead 41 passing through the aperture 13. Of course, other components may be provided on the quantum chip substrate 1, and the wiring may be connected by wires passing through the holes 13. The wiring layer 4 is located in the insulating layer 2 below the quantum chip substrate 1. The upper surface and the lower surface of each insulating layer 2 are covered with a ground layer 3 to reduce interference of external noise or other factors on the lines and interference of the lines on the qubits 11. The grounding layer 3 is made of metal, and may be an aluminum foil layer, a tin foil layer, a metal mesh, or other conductive layer. Therefore, the quantum bit de-coherence time reduction caused by covering an insulating film on a critical device such as a quantum bit can be avoided.
In a specific embodiment, the wiring layer 4 is disposed within the same insulating layer 2 of the plurality of insulating layers 2. This is suitable for the case where the wiring layer 4 generates less interference when the wiring route is simple.
In another specific embodiment, the wiring layer 4 is disposed within a different one of the plurality of insulating layers 2. The wiring layer 4 is arranged in different insulating layers 2 respectively, and the upper surface and the lower surface of each insulating layer 2 are covered with the grounding layers 3, namely, the insulating layers 2 of different wiring layers 4 are separated by the grounding layers 3, so that crosstalk among different lines is reduced, and the fidelity of signals can be improved.
Example 2
The invention also provides a wiring method for a surface coding scheme superconducting qubit system, applied to the wiring board of the superconducting qubit system with the quantum chip substrate 1, the insulating layer 2 and the grounding layer 3, comprising: and wiring is arranged below the quantum chip substrate 1, a hole 13 is formed in the quantum chip substrate 1, the wiring is connected with a circuit on the quantum chip substrate 1 through the hole 13, and the wiring forms a wiring layer 4.
In a preferred embodiment, the wiring layer 4 is arranged in the insulating layer 2 below the quantum chip substrate 1, and the insulating layer 3 provided with the wiring layer 4 can be one or more layers; the wiring layers 4 may be provided in the same insulating layer 2 or in different insulating layers 2. Preferably, the upper and lower surfaces of the insulating layer 2 are covered with a ground layer 3 made of a metal material. The metal material of the ground layer 3 may be an aluminum foil layer, a tin foil layer, a metal mesh or other conductive layer to reduce interference of external noise or other factors on the line and interference of the line on the qubit 11.
According to the wiring board for the surface coding scheme superconducting qubit system, the quantum chip substrate 1, the insulating layers 2, the grounding layers 3 and the holes 13 formed in the quantum chip substrate 1 are arranged, so that the wiring layer 4 in the insulating layer 2 is connected with elements on the quantum chip substrate 1 through the holes 13, and the problem that the quantum bit decoupling time is reduced due to the fact that insulating films cover critical devices such as qubits and the like is solved; the upper surface and the lower surface of the insulating layer 2 are covered with the grounding layer 3, so that the interference of external noise to a circuit and the interference of the circuit to a quantum bit can be reduced; the wiring layers 4 are respectively arranged in the different insulating layers 2, and the insulating layers 2 of the different wiring layers 4 are separated by the grounding layer 3, so that crosstalk between different lines is reduced, and the fidelity of signals can be improved.
According to the wiring method for the surface coding scheme superconducting qubit system, the hole 13 is formed in the quantum chip substrate 1, the wiring layer 4 is connected with the line on the quantum chip substrate 1 through the hole 13, and the problem that the quantum bit decoherence time is reduced due to the fact that an insulating film is covered on key devices such as a qubit and the like is solved; the upper surface and the lower surface of the insulating layer 2 are covered with the grounding layer 3, so that the interference of external noise to a circuit and the interference of the circuit to a quantum bit can be reduced; the wiring layers 4 are respectively arranged in the different insulating layers 2, and the insulating layers 2 of the different wiring layers 4 are separated by the grounding layer 3, so that crosstalk between different lines is reduced, and the fidelity of signals can be improved.
Thus, it should be understood by those skilled in the art that while exemplary embodiments of the present invention have been illustrated and described in detail herein, many other variations or modifications which are consistent with the principles of the invention may be directly determined or derived from the disclosure of the present invention without departing from the spirit and scope of the invention. Accordingly, the scope of the invention should be understood and interpreted to cover all such other variations or modifications.
Claims (9)
1. A wiring board for a surface coding scheme superconducting qubit system, comprising:
the quantum chip comprises a quantum chip substrate, wherein a plurality of qubits and a plurality of couplers are arranged on the quantum chip substrate, and any two adjacent qubits in the plurality of qubits are directly coupled or coupled through the corresponding couplers in the plurality of couplers;
a plurality of insulating layers; the insulating layer is arranged below the quantum chip substrate in a covering mode;
a wiring layer disposed within an insulating layer of the plurality of insulating layers; and
a plurality of ground planes; the plurality of grounding layers are correspondingly arranged on the upper surfaces and the lower surfaces of the plurality of insulating layers;
the quantum chip substrate is provided with a plurality of holes, and the wiring layer is connected with the control line of the quantum bit or the control line of the coupler through a lead wire passing through the holes;
wherein, the number is at least two.
2. The wiring board of claim 1, wherein the qubits on the quantum chip substrate are arranged in a lattice.
3. The wiring board of claim 1, wherein the number of holes are disposed at a gap formed by the number of qubits and the number of couplers.
4. The wiring board of any of claims 1-3, wherein the plurality of ground layers are all metal layers.
5. The wiring board according to any of claims 1-3, wherein the wiring layer is disposed within a same one of the insulating layers.
6. The wiring board of any of claims 1-3, wherein the wiring layer is disposed within a different one of the number of insulating layers.
7. A wiring method for a surface coding scheme superconducting qubit system, applied to the wiring board of the superconducting qubit system having the quantum chip substrate, the insulating layer, and the ground layer as claimed in any of claims 1 to 6, wherein a wiring layer is disposed under the quantum chip substrate, a hole is punched in the quantum chip substrate, and the wiring layer is connected to a line on the quantum chip substrate through the hole.
8. The routing method according to claim 7, wherein the routing layer is one or more layers; the wiring layers are arranged in the same insulating layer or different insulating layers.
9. The wiring method according to claim 7 or 8, wherein the upper surface and the lower surface of the insulating layer are covered with a ground layer of a metal material.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610317372.6A CN105957832B (en) | 2016-05-12 | 2016-05-12 | Wiring method and wiring board for surface coding scheme superconducting qubit system |
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| CN201610317372.6A CN105957832B (en) | 2016-05-12 | 2016-05-12 | Wiring method and wiring board for surface coding scheme superconducting qubit system |
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| CN105957832A CN105957832A (en) | 2016-09-21 |
| CN105957832B true CN105957832B (en) | 2020-09-22 |
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| CN107564868B (en) * | 2017-07-07 | 2019-08-02 | 清华大学 | A kind of integrated encapsulation structure and method of Superconducting Quantum computing chip |
| US10347605B2 (en) | 2017-11-28 | 2019-07-09 | International Business Machines Corporation | System and method for routing signals in complex quantum systems |
| CN109613876B (en) * | 2018-04-28 | 2024-05-07 | 本源量子计算科技（合肥）股份有限公司 | Multichannel quantum measurement and control system |
| CN109376866B (en) * | 2018-09-17 | 2021-03-12 | 合肥本源量子计算科技有限责任公司 | Method and device for recording metadata and method and device for running quantum program |
| CN109376870B (en) * | 2018-10-18 | 2021-04-23 | 清华大学 | Superconducting quantum bit chip |
| CN112423474A (en) * | 2019-08-23 | 2021-02-26 | 中国科学技术大学 | Preparation method of circuit board and circuit board |
| CN111598248B (en) * | 2020-05-18 | 2024-03-12 | 南京优算量子科技有限公司 | Superconducting quantum chip and method for realizing control of phase gate |
| CN113725208A (en) * | 2021-08-13 | 2021-11-30 | 中国科学院物理研究所 | Three-dimensional quantum chip and preparation method thereof |
| CN114580338B (en) * | 2022-02-21 | 2023-02-28 | 北京百度网讯科技有限公司 | Analog wiring method, manufacturing method, chip, device, equipment and storage medium |
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| US6911664B2 (en) * | 2002-04-15 | 2005-06-28 | D-Wave Systems, Inc. | Extra-substrate control system |
| US8738105B2 (en) * | 2010-01-15 | 2014-05-27 | D-Wave Systems Inc. | Systems and methods for superconducting integrated circuts |
| CN102740583B (en) * | 2011-03-31 | 2015-05-27 | 富士康(昆山)电脑接插件有限公司 | Circuit board |
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