CN105929888A - Low-dropout regulator - Google Patents

Abstract

The invention belongs to the technical field of integrated circuits and relates to a low-dropout regulator. The main technical scheme is that a control logic unit comprises a fully differential structure, a low-pass filter and a high-pass filter; an ADC (analog-to-digital converter) comprises a bias circuit, a differential common-source circuit and a comparator; a power tube comprises a buffer and a PMOS (positive channel metal oxide semiconductor), and the buffer comprises two inverters; a power tube array comprises 124 power tubes arranged symmetrically according to certain law. The low-dropout regulator has the beneficial effects that the circuit structure is novel, the complexity of the control logic unit is simplified, the transient response speed is increased, and power consumption is reduced, so that the circuit is more applicable to nano-SOC (system-on-chip) integration.

Description

A kind of low pressure difference linear voltage regulator

Technical field

The invention belongs to technical field of integrated circuits, relate to a kind of low pressure difference linear voltage regulator.

Background technology

In Power Management Design, voltage stabilizing is the most basic and modal function of electric power management circuit, and LDO is that regulated power supply manages core Circuit the most commonly used in sheet, is widely present in communication, electronics and SOC system that some are independent.The research master of LDO at present Concentrating on simulation control field, the LDO that traditional simulation controls mainly is made up of four parts, and reference voltage circuit, error are put Big device, adjustment pipe and resistance-feedback network.But the supply voltage that the ic manufacturing technology of advanced person needs are low, and low electricity Source voltage cannot make the gain that the amplifier holding in the LDO that simulation controls is enough.Another shortcoming of the LDO that simulation controls is to account for Ground area is relatively big, is not easy to realize the integrated of nanoscale SOC.And the number of traditional numerically controlled LDO power MOS pipe is relatively Many, thus cause transient response time longer.

Summary of the invention

To be solved by this invention, it is simply that for problem present in above-mentioned tradition LDO, propose a kind of numerically controlled has fast The LDO of speed response characteristic.

The technical scheme is that a kind of low pressure difference linear voltage regulator, including control logic, ADC, power MOS array, First electric capacity C1, the second electric capacity C2, inductance L, the first resistance R1, the second resistance R2, the 3rd resistance R3, the 4th resistance R4, the first constant pressure source V1, the second constant pressure source V2, the 3rd constant pressure source V3 and load current source I1；The electricity of described control logic The power end of source, the power end of ADC and power MOS array all connects the positive pole of the first constant pressure source V1, the first constant pressure source Minus earth；The first voltage input end controlling logic is connected with its second voltage input end by the first electric capacity C1, controls to patrol The second voltage input end collected is followed by the positive pole of the second constant pressure source, the minus earth of the second constant pressure source by the second resistance R2；Control The negative input of the first output termination ADC of logic processed, controls the positive input meeting ADC of the second output of logic； The power MOS array of the output of ADC；The outfan of power MOS array be followed by controlling logic by the first resistance R1 First voltage input end；After the outfan of power MOS array passes sequentially through inductance L, the 3rd resistance R2 and the second electric capacity C2 Ground connection；The outfan of power MOS array and the junction point of inductance L are followed by the positive pole of the 3rd constant pressure source by the 4th resistance R4, 4th resistance R4's is in parallel with load current source I1, the minus earth of the 3rd constant pressure source；

First voltage input end of described control logic is the feedback voltage of power MOS array output, controls the second electricity of logic Voltage on the basis of pressure input, described control logic is for amplifying the pressure reduction of feedback voltage with reference voltage by fully differential result After, then exported by low pass filter and high pass filter；

Described ADC is made up of biasing circuit, difference common source amplifying circuit and multiple comparator, the negative input of each comparator Connecing the negative input of ADC, the positive input of comparator connects the positive input of ADC, for controlling logic output After two paths of signals compares, power MOS array is arrived in output, and power MOS array is constituted two parts by multiple identical power tubes Symmetrical structure, the input signal of a part of structure and the input signal of another part are reverse, particularly: when output electricity When pressure is higher than reference voltage, i.e. feedback voltage is more than reference voltage, then the first outfan controlling logic is more than the second outfan, In ADC, the negative input of comparator is more than positive input simultaneously, if the input voltage of ADC has reached the upset of ADC Point, in power MOS array, the input signal of a part of structure is low level, and corresponding power MOS array can be opened, will The value of output voltage is pulled low to the output valve of standard；When output voltage is less than reference voltage, i.e. feedback voltage is less than reference voltage, The first outfan then controlling logic is less than the second outfan, and in ADC, the negative input of comparator inputs less than forward simultaneously End, if the input voltage of ADC has reached the upset point of ADC, the input signal of another part structure in power MOS array For low level, corresponding power MOS array can be opened, and the value of output voltage is pulled to the output valve of standard.

Beneficial effects of the present invention is, the complexity controlling logic is simplified, and improves transient response speed, also drops simultaneously Low power consumption so that it is integrated that circuit is more suitable for nanometer SOC.

Accompanying drawing explanation

The overall logic structural representation of Fig. 1 present invention；

Fig. 2 is the schematic diagram of the ADC output of the present invention；

Fig. 3 is the schematic diagram of the ADC output of the present invention；

Fig. 4 is the transient response schematic diagram of the integrated circuit of the present invention.

Detailed description of the invention

Below in conjunction with the accompanying drawings, technical scheme is described in detail:

As it is shown in figure 1, a kind of low pressure difference linear voltage regulator of the present invention, including control logic, ADC, power MOS array, First electric capacity C1, the second electric capacity C2, inductance L, the first resistance R1, the second resistance R2, the 3rd resistance R3, the 4th resistance R4, the first constant pressure source V1, the second constant pressure source V2, the 3rd constant pressure source V3 and load current source I1；The electricity of described control logic The power end of source, the power end of ADC and power MOS array all connects the positive pole of the first constant pressure source V1, the first constant pressure source Minus earth；The first voltage input end controlling logic is connected with its second voltage input end by the first electric capacity C1, controls to patrol The second voltage input end collected is followed by the positive pole of the second constant pressure source, the minus earth of the second constant pressure source by the second resistance R2；Control The negative input of the first output termination ADC of logic processed, controls the positive input meeting ADC of the second output of logic； The power MOS array of the output of ADC；The outfan of power MOS array be followed by controlling logic by the first resistance R1 First voltage input end；After the outfan of power MOS array passes sequentially through inductance L, the 3rd resistance R2 and the second electric capacity C2 Ground connection；The outfan of power MOS array and the junction point of inductance L are followed by the positive pole of the 3rd constant pressure source by the 4th resistance R4, 4th resistance R4's is in parallel with load current source I1, the minus earth of the 3rd constant pressure source；

First voltage input end of described control logic is the feedback voltage of power MOS array output, controls the second electricity of logic Voltage on the basis of pressure input, described control logic is for amplifying the pressure reduction of feedback voltage with reference voltage by fully differential result After, then exported by low pass filter and high pass filter；

Described ADC is made up of biasing circuit, difference common source amplifying circuit and multiple comparator, the negative input of each comparator Connecing the negative input of ADC, the positive input of comparator connects the positive input of ADC, for controlling logic output After two paths of signals compares, power MOS array is arrived in output, and power MOS array is constituted two parts by multiple identical power tubes Symmetrical structure, the input signal of a part of structure and the input signal of another part are reverse, particularly: when output electricity When pressure is higher than reference voltage, i.e. feedback voltage is more than reference voltage, then the first outfan controlling logic is more than the second outfan, In ADC, the negative input of comparator is more than positive input simultaneously, if the input voltage of ADC has reached the upset of ADC Point, in power MOS array, the input signal of a part of structure is low level, and corresponding power MOS array can be opened, will The value of output voltage is pulled low to the output valve of standard；When output voltage is less than reference voltage, i.e. feedback voltage is less than reference voltage, The first outfan then controlling logic is less than the second outfan, and in ADC, the negative input of comparator inputs less than forward simultaneously End, if the input voltage of ADC has reached the upset point of ADC, the input signal of another part structure in power MOS array For low level, corresponding power MOS array can be opened, and the value of output voltage is pulled to the output valve of standard.

Control logic of the present invention includes fully differential structure, low pass filter, high pass filter.The enable of fully differential structure End EN is connected with power vd D with input VDDO, and VSSO is connected to the ground, and bias current is provided by constant-current source I2, I2 one end Being connected to power vd D, the other end is connected to the input Ibias of fully differential structure, and the outfan of fully differential structure is low pass filtered Input V1, V2 of ripple device, high pass filter uses structure in parallel with low pass filter, and the output of wave filter is control and patrols Output Vfb_out, the Vref_out collected.Described fully differential structure by the first to the 7th PMOS P1 to P7, the eight to the second Ten NMOS tube N1 to N14, phase inverter I1, the first resistance R1, the second resistance R2, electric capacity C1 are constituted.Phase inverter I1's is defeated The grid entering end and P1, N1 connects input signal EN, and the outfan of phase inverter I1 is connected to the grid of N4, N13, N14, The drain electrode of N1 connects the drain electrode of input signal Ibias, source electrode and N2 and is connected, N2 use grid leak short circuit structure, N2, N3, N7, The grid of N8 is connected with the drain electrode of N4, and source ground VSSO, the P2 grid leak short circuit of N2, N3, N4 is also connected to the drain electrode of N3, The grid of P2, P3, P6, P7 is connected with the drain electrode of P1, and the source electrode of P1, P2, P3, P6, P7 meets power vd D；Resistance R1, R2, the 4th PMOS P4, the 5th PMOS P5, NMOS tube N5, N6, N7, N8, electric capacity C1 constitutes full-differential circuits, The drain terminal of P3 is connected with R1, R2, and R1, R2 are connected with the source of P4, P5 the most respectively, and P4, P5 are as full-differential circuits Input, its grid connects input signal Vfb and Vref respectively, and the drain terminal of P4 connects grid and the drain electrode of N7, the P5 of N5 Drain terminal connect the grid of N6 and the drain electrode of N8, the drain electrode of N5, N6 is connected with the junction point of P1, R1, R2, N5, N6, The source ground VSSO of N7, N8, the grid of N5, N12, the drain electrode of N13, the source electrode of N10 meet outfan V1, N6, N11 The source electrode of grid, the drain electrode of N14 and N9 meet outfan V2, electric capacity C1 and be connected between V1, V2；The drain electrode of P6 and N9 Grid be connected with the drain electrode of N11, the drain electrode of P7 is connected with the grid of N10 and the drain electrode of N12, and the drain electrode of N9, N10 connects Power vd D, source N9 of P6, P7, the drain terminal of N10 meet power vd D, and the source of N11, N12, N13, N14 connects ground VSSO.Described low pass filter and high pass filter are in parallel, by the first to the 8th PMOS P1 to P8, the first to the 2nd NMOS Pipe N1 to N2, first resistance R1 the second resistance R2, constant-current source I3 are constituted.Outfan V1, V2 of fully differential structure are as low The input of bandpass filter, V1 connects the grid of N1, and V2 connects the grid of N2, and the drain electrode of N1 is connected with the drain electrode of P1, N2 Drain electrode be connected with the drain electrode of P2, the drain electrode of P1, P1, P4 grid be connected, the drain electrode of P2, P2, P3 grid be connected, The drain electrode of P3 and the drain electrode of termination an outfan Vfb_out, P4 of resistance R1 and the one of resistance R2 terminate outfan Vref_out, The drain electrode of P1, P2, P3, P4 connects power vd D, and N1, N2 and R1, the other end of R2 are connected to ground VSSO；The drain electrode of P6, The grid of P5, P6 is connected, and the drain electrode of P6 is connected to the drain electrode of ground VSSO, P5 and the source of P7, P8 by connecting constant-current source I3 The most connected, the grid of P7 is connected with input Vref, and the grid of P8 is connected with input Vfb, and the drain electrode of P7 is connected to output The drain electrode of end Vfb_out, P8 is connected to outfan Vref_out.

ADC of the present invention includes biasing circuit, difference common source amplifying circuit, 11 comparators.Circuits is that ADC carries For bias voltage, the outfan of difference common source amplifying circuit provides grid voltage for two NMOS tube in comparator, it is achieved voltage Conversion to electric current.Comparator uses FLASH structure parallel output, can improve the speed of comparator.Comparator is all by electricity Stream mirror realizes, as shown in Figure 2 and Figure 3, when grid voltage difference added by two NMOS tube in comparator, by arranging electricity Flow the ratio between two-way electric current in mirror, it is achieved the upset point that comparator output is different, obtain the thermometer code of ADC stepped form Output, ADC output step value is 10mv.Phase inverter is connected with comparator as buffer, improves the output of comparator.Described Biasing circuit is made up of the first PMOS P1, first to fourth NMOS tube N1 to N4.The drain electrode of N1, N1, N2 grid phase Even, the drain electrode of N3, N3, N4 grid are connected, and the source electrode of N1 connects the drain electrode of N3, and the source electrode of N2 connects the drain electrode of N4, the leakage of N1 Pole is connected to power vd D by constant-current source I1, and the drain electrode of N3 is connected to the drain electrode of P1；Described difference common source amplifying circuit is by Two PMOS P2 and the 5th to the 8th NMOS tube N5 to N8 are constituted, and P1, P2 grid is connected, and the source electrode of P1, P2 connects power supply The drain electrode of VDD, P2 connects the source electrode of P3, P4, and the grid classification of P3, P4 connects input VN, VP of ADC, N5, N8 grid leak Short circuit, the grid of N7, the drain electrode of N5, N6 be connected with the drain electrode of P3, the grid of N6, the drain electrode phase of drain electrode and P4 of N7, N8 Even, the source ground VSSO of N5, N6, N7, N8；Described 11 comparators use the structure of current mirrors, by the 9th to the 30 NMOS tube N9 to N30, the 7th to the 28th PMOS P7 to P28, first to the 11st phase inverter I1 Constituting to I11, each of which comparator is all to be made up of two PMOS, two NMOS tube and a phase inverter, first Individual comparator is made up of P7, P8, N9, N10, I1, and second comparator is made up of P9, P10, N11, N12, I2, the Three comparators are made up of P11, P12, N13, N14, I3, and the 4th comparator is by P13, P14, N15, N16, I4 structure Becoming, the 5th comparator is made up of P15, P16, N17, N18, I5, the 6th comparator by P17, P18, N19, N20, I6 is constituted, and the 7th comparator is made up of P19, P20, N21, N22, I7, the 8th comparator by P21, P22, N23, N24, I8 are constituted, and the 9th comparator is made up of P23, P24, N25, N26, I9, the tenth comparator by P25, P26, N27, N28, I10 constitute, the 11st comparator is made up of P27, P28, N29, N30, I11, P7, P9, P11, P13, P15, P17, P19, P21, P23, P25, P27 grid with drain electrode be connected, P7 and P8, P9 and P10, P11 and P12, P13 and P14, P15 and P16, P17 and P18, P19 and P20, P21 and P22, P23 and P24, P25 and P26, P27 Being connected with P28 grid, the source electrode of P7 to P28 meets power vd D, the source ground VSSO, N9 of N9 to N20, N11, N13, The grid of N15, N17, N19, N22, N24, N26, N28, N30 is connected with the drain electrode of P3, N10, N12, N13, N16, The grid of N18, N20, N21, N23, N25, N27, N29 is connected with the drain electrode of P4, the inside PMOS of the first to the tenth one-level Pipe, NOS manage, the connected mode of phase inverter is identical, and as a example by first comparator, the drain electrode of P7 connects the drain electrode of N9, P8's Drain electrode is connected with the drain electrode of N10 and the input of I1, and the output of I1 is the outfan of first comparator, and first to the tenth The output of one comparator is respectively comp, nq<1>to nq<5>, q<1>to q<5>.

Power MOS array of the present invention is made up of 124 identical power tube I1 to I124, power MOS array defeated Enter to hold nq<1>to nq<5>, pq<1>to pq<5>respectively with ten outfan q<1 of ADC>to q<5>, nq<1>to nq<5> Be connected, the input nq<1 of power MOS array>to nq<5>62 power tubes being connected and input pq<1>to pq<5> Connected 62 power tubes use full symmetric distribution mode, and the outfan of power MOS array is the outfan of integrated circuit Vout.The power tube of the input termination varying number of power MOS array, forms ten different little arrays corresponding to input. When the input of ADC changes the upset point meeting ADC, a certain output of ADC can occur level to overturn, thus directly Reflection is turned on and off a little array on power MOS array.When output voltage is higher than reference voltage, feed back to entirety The input of circuit is that Vfb is more than Vref, i.e. the input of ADC is that Vn is more than Vp, if the input voltage of ADC has reached ADC Upset point, input pq<1 in power MOS array>to pq<5>in part input be low level, corresponding little array meeting Open, the value of output voltage is pulled low to the output valve of standard.When output voltage is less than reference voltage, feed back to integrated circuit Input be that Vfb is less than Vref, i.e. the input of ADC is that Vn is less than Vp, if the input voltage of ADC has reached ADC's Upset point, input nq<1 in power MOS array>to nq<5>in part input be low level, corresponding little array can be held Open, the value of output voltage is pulled to the output valve of standard.

Fig. 4 gives the Transient waveform of the present invention.Above for load current over time, below for output electricity Pressure is over time.

Claims (1)

1. a low pressure difference linear voltage regulator, including control logic, ADC, power MOS array, the first electric capacity C1, the Two electric capacity C2, inductance L, the first resistance R1, the second resistance R2, the 3rd resistance R3, the 4th resistance R4, the first constant pressure source V1, the second constant pressure source V2, the 3rd constant pressure source V3 and load current source I1；The power end of described control logic, the electricity of ADC The power end of source and power MOS array all connects the positive pole of the first constant pressure source V1, the minus earth of the first constant pressure source；Control is patrolled The first voltage input end collected is connected with its second voltage input end by the first electric capacity C1, controls the second voltage input of logic End is followed by the positive pole of the second constant pressure source, the minus earth of the second constant pressure source by the second resistance R2；Control the first output of logic The negative input of termination ADC, controls the positive input meeting ADC of the second output of logic；The power of the output of ADC MOS array；First voltage input end being followed by control logic by the first resistance R1 of the outfan of power MOS array； The outfan of power MOS array passes sequentially through ground connection after inductance L, the 3rd resistance R2 and the second electric capacity C2；Power MOS battle array The junction point of outfan and the inductance L of row is followed by the positive pole of the 3rd constant pressure source by the 4th resistance R4, the 4th resistance R4 with bear Carry current source I1 in parallel, the minus earth of the 3rd constant pressure source；

First voltage input end of described control logic is the feedback voltage of power MOS array output, controls the second electricity of logic Voltage on the basis of pressure input, described control logic is for amplifying the pressure reduction of feedback voltage with reference voltage by fully differential result After, then exported by low pass filter and high pass filter；

Described ADC is made up of biasing circuit, difference common source amplifying circuit and multiple comparator, the negative input of each comparator Connecing the negative input of ADC, the positive input of comparator connects the positive input of ADC, for controlling logic output After two paths of signals compares, power MOS array is arrived in output, and power MOS array is constituted two parts by multiple identical power tubes Symmetrical structure, the input signal of a part of structure and the input signal of another part are reverse, particularly: when output electricity When pressure is higher than reference voltage, i.e. feedback voltage is more than reference voltage, then the first outfan controlling logic is more than the second outfan, In ADC, the negative input of comparator is more than positive input simultaneously, if the input voltage of ADC has reached the upset of ADC Point, in power MOS array, the input signal of a part of structure is low level, and corresponding power MOS array can be opened, will The value of output voltage is pulled low to the output valve of standard；When output voltage is less than reference voltage, i.e. feedback voltage is less than reference voltage, The first outfan then controlling logic is less than the second outfan, and in ADC, the negative input of comparator inputs less than forward simultaneously End, if the input voltage of ADC has reached the upset point of ADC, the input signal of another part structure in power MOS array For low level, corresponding power MOS array can be opened, and the value of output voltage is pulled to the output valve of standard.