CN105914239B - A kind of preparation method of N-type double-side cell - Google Patents
A kind of preparation method of N-type double-side cell Download PDFInfo
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- CN105914239B CN105914239B CN201610220225.7A CN201610220225A CN105914239B CN 105914239 B CN105914239 B CN 105914239B CN 201610220225 A CN201610220225 A CN 201610220225A CN 105914239 B CN105914239 B CN 105914239B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 151
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 150
- 239000010703 silicon Substances 0.000 claims abstract description 150
- 238000009792 diffusion process Methods 0.000 claims abstract description 56
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 55
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 53
- 229910052796 boron Inorganic materials 0.000 claims abstract description 53
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 23
- 239000011574 phosphorus Substances 0.000 claims abstract description 23
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 23
- 230000004888 barrier function Effects 0.000 claims abstract description 14
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 10
- 238000002161 passivation Methods 0.000 claims description 9
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical compound [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 claims description 8
- 229910000029 sodium carbonate Inorganic materials 0.000 claims description 4
- 239000003292 glue Substances 0.000 claims description 3
- 229910021645 metal ion Inorganic materials 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 238000007650 screen-printing Methods 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims 1
- 238000004026 adhesive bonding Methods 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 42
- 238000000034 method Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000010422 painting Methods 0.000 description 1
- 239000005297 pyrex Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a kind of preparation method of N-type double-side cell, including：Two-sided thermal oxide is carried out to silicon chip, oxide layer is all generated in the upper and lower surface of the silicon chip；Negtive photoresist is applied to the lower surface of the silicon chip；Remove the oxide layer of the upper surface of the silicon chip；Remove the negtive photoresist of the lower surface of the silicon chip；Back-to-back boron diffusion is carried out to the silicon chip；Negtive photoresist is applied to the boron extended surface of the silicon chip；Remove the oxide layer of the lower surface of the silicon chip；Remove the negtive photoresist of the upper surface of the silicon chip；Back-to-back phosphorus diffusion is carried out to the silicon chip.The preparation method of the N-type double-side cell, by all protecting barrier layer by gluing before boron diffusion and phosphorus diffusion, and then the high Double side diffusion knot of quality is obtained, can finally obtain efficient cell piece.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of preparation method of N-type double-side cell.
Background technology
In the market in factory typically be all p-type polycrystalline cell piece, and this efficiency is not high.With entering for technology
Step, the production cost of N-type silicon chip is also further reducing, and the efficiency of monocrystalline is higher than polycrystalline, therefore occurs in industry
The production and application of N-type battery slice.The Boron diffusion method of face N-type silicon chip has also had, therefore N-type double-side cell uses
And give birth to.
The method of existing N-type double-side cell Double side diffusion, it is to deposit SiN and SiO by CVD to be used as mask, uses
To stop the barrier layer of another diffusion in diffusion.Because the SiN and SiO that pass through CVD be not clean, then bring boiler tube diffusion meeting into
Boiler tube is polluted, and after diffusion, SiN is difficult to clean up.The Double side diffusion finally made is unholiness, causes last efficiency not
It is high.
The content of the invention
It is an object of the invention to provide a kind of preparation method of N-type double-side cell, the Double side diffusion for obtaining high quality connects, obtained
Obtain efficient cell piece.
In order to solve the above technical problems, the embodiments of the invention provide a kind of preparation method of N-type double-side cell, including：
Two-sided thermal oxide is carried out to silicon chip, oxide layer is all generated in the upper and lower surface of the silicon chip；
Negtive photoresist is applied to the lower surface of the silicon chip；
Remove the oxide layer of the upper surface of the silicon chip；
Remove the negtive photoresist of the lower surface of the silicon chip；
Back-to-back boron diffusion is carried out to the silicon chip；
Negtive photoresist is applied to the boron extended surface of the silicon chip；
Remove the oxide layer of the lower surface of the silicon chip；
Remove the negtive photoresist of the upper surface of the silicon chip；
Back-to-back phosphorus diffusion is carried out to the silicon chip.
Wherein, the thickness of the oxide layer is 80nm.
Wherein, the lower surface to the silicon chip applies negtive photoresist and included：
Negtive photoresist is applied in the lower surface of the silicon chip with sol evenning machine, protects the oxide layer of the lower surface of the silicon chip；
The silicon chip that lower surface is coated to negtive photoresist is placed on 110 DEG C of dryer and dried 10 minutes, until glue is done；
Wherein, the rotating speed of the sol evenning machine is 3.75 thousand rpms, and the time is 30 seconds.
Wherein, the oxide layer of the upper surface for removing the silicon chip, including：
The silicon chip is immersed in the HF solution that volume ratio is 10% 5 minutes, removes the oxidation of the silicon chip upper surface
Layer.
Wherein, the negtive photoresist for removing the silicon chip lower surface, including：
The silicon chip is immersed in the sodium carbonate liquor that mass ratio is 1% 10 minutes, removes the silicon chip lower surface
Negtive photoresist；
The silicon chip for removing lower surface negtive photoresist is soaked 1 minute in 70 DEG C of hot water；
Silicon chip is immersed in HCl solution, removes metal ion.
Wherein, it is described to the back-to-back boron diffusion of silicon chip progress, including：
The upper table of the silicon chip is faced outwardly, the boron diffusion that puts in, institute are close in the lower surface with oxide layer face-to-face
The upper surface for stating silicon chip obtains uniform boron diffusion, and the boron diffusingsurface obtains 80nm BSG, as barrier layer, sheet resistance 70/
□。
Wherein, back-to-back phosphorus diffusion is carried out to the silicon chip, including：
It is put into after the boron diffusingsurface of the silicon chip is close to face-to-face in boiler tube and carries out phosphorus diffusion, forms PSG.
Wherein, after the back-to-back phosphorus diffusion to silicon chip progress, in addition to：
The BSG and PSG of the silicon chip surface are removed, is included in silicon chip being immersed in the HF solution that volume ratio is 10% and soaks
Bubble 8 minutes, BSG, PSG of the silicon chip surface are removed.
Wherein, after the BSG and PSG for removing the silicon chip surface, in addition to：
The boron extended surface of the silicon chip is passivated, including makes one layer of 6nm oxidation in the boron extended surface of the silicon chip of ALD equipment
Aluminum passivation boron extended surface, the silicon chip for making aluminium oxide passivation boron extended surface is annealed.
Wherein, after the boron extended surface of the passivation silicon chip, in addition to：
Two-sided PECVD plated films are carried out to the silicon chip；
Two-sided silk-screen printing is carried out to the silicon chip.
The preparation method for the N-type double-side cell that the embodiment of the present invention is provided, compared with prior art, have following excellent
Point：
The preparation method for the N-type double-side cell that the embodiment of the present invention is provided, including：Two-sided thermal oxide is carried out to silicon chip,
Oxide layer is all generated in the upper and lower surface of the silicon chip；Negtive photoresist is applied to the lower surface of the silicon chip；Remove the silicon chip
Upper surface oxide layer；Remove the negtive photoresist of the lower surface of the silicon chip；Back-to-back boron diffusion is carried out to the silicon chip；To described
The boron extended surface of silicon chip applies negtive photoresist；Remove the oxide layer of the lower surface of the silicon chip；Remove the negtive photoresist of the upper surface of the silicon chip；It is right
The silicon chip carries out back-to-back phosphorus diffusion.
The preparation method of the N-type double-side cell, with negtive photoresist protection mask is applied twice, avoid carrying SiN into boiler tube expansion
Dissipate, preferably protect another side not extended influence to and negtive photoresist can also easily be removed.By expanding in boron diffusion and phosphorus
Barrier layer is all protected by gluing before dissipating, and then obtains the high Double side diffusion knot of quality, can finally obtain efficient battery
Piece.
In summary, the preparation method for the N-type double-side cell that the embodiment of the present invention is provided, by boron diffusion and
Barrier layer is all protected by gluing before phosphorus diffusion, and then obtains the high Double side diffusion knot of quality, can finally be obtained efficient
Cell piece.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are the present invention
Some embodiments, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis
These accompanying drawings obtain other accompanying drawings.
Fig. 1 is that the step flow of the preparation method of the N-type double-side cell in a kind of concrete mode of the embodiment of the present invention is shown
It is intended to；
Fig. 2 is the technique during the once specific manufacture craft of the preparation method of the N-type double-side cell in the present invention
Parameter and steps flow chart.
Embodiment
Just as described in the background section, due to needing to carry out boron diffusion in the upper surface of silicon chip, lower surface carries out phosphorus expansion
Dissipate, if preventing the next influence of another diffusion zone as barrier layer without good mask and removing when spreading around the shadow of expansion
Ring, then another side must largely can be destroyed, it is impossible to good pure knot is obtained, it is final to influence cell piece efficiency.
Based on this, the embodiments of the invention provide a kind of preparation method of N-type double-side cell, including：Silicon chip is carried out double
Face thermal oxide, oxide layer is all generated in the upper and lower surface of the silicon chip；Negtive photoresist is applied to the lower surface of the silicon chip；Remove
The oxide layer of the upper surface of the silicon chip；Remove the negtive photoresist of the lower surface of the silicon chip；Back-to-back boron expansion is carried out to the silicon chip
Dissipate；Negtive photoresist is applied to the boron extended surface of the silicon chip；Remove the oxide layer of the lower surface of the silicon chip；Remove the upper surface of the silicon chip
Negtive photoresist；Back-to-back phosphorus diffusion is carried out to the silicon chip.
In summary, the preparation method of N-type double-side cell provided in an embodiment of the present invention, covered with negtive photoresist protection is applied twice
Film, avoids carrying SiN and enters boiler tube diffusion, preferably protects another side not extended influence to and negtive photoresist can also be light
Remove on ground.By all protecting barrier layer by gluing before boron diffusion and phosphorus diffusion, and then obtain the high two-sided expansion of quality
Dissipating bind, it can finally obtain efficient cell piece.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Embodiment be described in detail.
Detail is elaborated in the following description in order to fully understand the present invention.But the present invention can with it is a variety of not
Other manner described here is same as to implement, those skilled in the art can do class in the case of without prejudice to intension of the present invention
Like popularization.Therefore the present invention is not limited to the specific embodiments disclosed below.
Fig. 1-2 is refer to, Fig. 1 is the preparation method of the N-type double-side cell in a kind of concrete mode of the embodiment of the present invention
Step schematic flow sheet；Fig. 2 is the once specific manufacture craft process of the preparation method of the N-type double-side cell in the present invention
In technological parameter and steps flow chart.
In a kind of embodiment, the preparation method of the N-type double-side cell, including：
Step 10, two-sided thermal oxide is carried out to silicon chip, oxide layer is all generated in the upper and lower surface of the silicon chip；
Step 20, negtive photoresist is applied to the lower surface of the silicon chip；
Step 30, the oxide layer of the upper surface of the silicon chip is removed；
Step 40, the negtive photoresist of the lower surface of the silicon chip is removed；
Step 50, back-to-back boron diffusion is carried out to the silicon chip；
Step 60, negtive photoresist is applied to the boron extended surface of the silicon chip；
Step 70, the oxide layer of the lower surface of the silicon chip is removed；
Step 80, the negtive photoresist of the upper surface of the silicon chip is removed；
Step 90, back-to-back phosphorus diffusion is carried out to the silicon chip.
It should be noted that the thickness of the process conditions and oxide layer of the invention to carrying out two-sided thermal oxide to silicon chip is not
It is specifically limited, the oxide layer functions as barrier layer or mask, and the effect of negtive photoresist is protection barrier layer, oxide layer
Thickness is usually 80nm.
The preparation method of the N-type double-side cell, with negtive photoresist protection mask is applied twice, avoid carrying SiN into boiler tube expansion
Dissipate, preferably protect another side not extended influence to and negtive photoresist can also easily be removed.By expanding in boron diffusion and phosphorus
Barrier layer is all protected by gluing before dissipating, and then obtains the high Double side diffusion knot of quality, can finally obtain efficient battery
Piece.
Typically the lower surface painting negtive photoresist of the silicon chip is included：Negtive photoresist is applied in the lower surface of the silicon chip with sol evenning machine, is protected
Protect the oxide layer of the lower surface of the silicon chip；The silicon chip that lower surface is coated to negtive photoresist is placed on 110 DEG C of dryer and dried 10 minutes,
Until glue is done.
The rotating speed of the sol evenning machine is 3.75 thousand rpms, and the time is 30 seconds.
It should be noted that the parameter of specific spin coating of the present invention to sol evenning machine is not specifically limited, to the tool of negtive photoresist
The species of body is not specifically limited, as long as oxide layer can be protected.
The oxide layer on the silicon chip is removed in the present invention, oxide layer is typically removed using HF solution, including：By the silicon
Piece is immersed in the HF solution that volume ratio is 10% 5 minutes, removes the oxide layer of the silicon chip upper surface.
The negtive photoresist of the silicon chip surface is removed in the present invention, negtive photoresist is typically removed using sodium carbonate liquor, including：By described in
Silicon chip is immersed in the sodium carbonate liquor that mass ratio is 1% 10 minutes, removes the negtive photoresist of the silicon chip lower surface；Following table will be removed
The silicon chip of face negtive photoresist soaks 1 minute in 70 DEG C of hot water；Silicon chip is immersed in HCl solution, removes metal ion.
The present invention is not limited concentration, species and the soak time of taking out the solution of oxide layer and negtive photoresist on silicon chip
It is fixed, as long as other layers of silicon chip, which are not done, while removing clean influences, but normally due to oxidated layer thickness and
The thickness of negtive photoresist is smaller, to ensure removal effect, is typically chosen using the relatively low solution of concentration.
Because all multiple silicon chips are carried out when carrying out boron diffusion or phosphorus diffusion simultaneously, work effect can be so improved
Rate, it is general using in back-to-back fashion while being so diffused to given side, another side to be formed and protected, it is described
Silicon chip carries out back-to-back boron diffusion, including：
The upper table of the silicon chip is faced outwardly, the boron diffusion that puts in, institute are close in the lower surface with oxide layer face-to-face
The upper surface for stating silicon chip obtains uniform boron diffusion, and the boron diffusingsurface obtains 80nm BSG, as barrier layer, sheet resistance 70/
□。
Back-to-back phosphorus diffusion is carried out to the silicon chip, including：It is put into after the boron diffusingsurface of the silicon chip is close to face-to-face
Phosphorus diffusion is carried out in boiler tube, forms PSG.Because boron is diffused with very thick barrier layer, is led and spread by memory in back-to-back fashion,
It can prevent to extend influence to boron diffusingsurface.
After completing to carry out back-to-back phosphorus diffusion to the silicon chip, in addition to：
Step 100, the BSG and PSG of the silicon chip surface are removed, is included in and silicon chip is immersed in the HF that volume ratio is 10%
Soaked 8 minutes in solution, BSG, PSG of the silicon chip surface are removed.
BSG in the present invention represents Pyrex, and PSG represents phosphorosilicate glass, ALD passivation expressions Al2O3。
Wherein, after the BSG and PSG for removing the silicon chip surface, in addition to：
The boron extended surface of the silicon chip is passivated, including makes one layer of 6nm oxidation in the boron extended surface of the silicon chip of ALD equipment
Aluminum passivation boron extended surface, the silicon chip for making aluminium oxide passivation boron extended surface is annealed.
Wherein, after the boron extended surface of the passivation silicon chip, in addition to：
Step 110, two-sided PECVD plated films are carried out to the silicon chip；
Step 120, two-sided silk-screen printing is carried out to the silicon chip.
As Fig. 2 be the present invention N-type double-side cell preparation method in produce once during specific process parameter
Step, wherein, LZ represents that load zone are loading area；CZ represents area centered on center zone；Temperature be the row of blank all
Represent the identical of temperature and lastrow；The 9th step and the 11st step represent wait temperature to set in Wait for
Point limits, i.e. waiting temperature are to setting value；13rd step table wait for BBR3wanted (valve) OFF.
In summary, the preparation method of N-type double-side cell provided in an embodiment of the present invention, covered with negtive photoresist protection is applied twice
Film, avoids carrying SiN and enters boiler tube diffusion, preferably protects another side not extended influence to and negtive photoresist can also be light
Remove on ground.By all protecting barrier layer by gluing before boron diffusion and phosphorus diffusion, and then obtain the high two-sided expansion of quality
Dissipating bind, it can finally obtain efficient cell piece.
The preparation method of N-type double-side cell provided by the present invention is described in detail above.It is used herein
Specific case is set forth to the principle and embodiment of the present invention, and the explanation of above example is only intended to help and understands this
The method and its core concept of invention.It should be pointed out that for those skilled in the art, this hair is not being departed from
On the premise of bright principle, some improvement and modification can also be carried out to the present invention, these are improved and modification also falls into power of the present invention
In the protection domain that profit requires.
Claims (10)
- A kind of 1. preparation method of N-type double-side cell, it is characterised in that including：Two-sided thermal oxide is carried out to silicon chip, oxide layer is all generated in the upper and lower surface of the silicon chip；Negtive photoresist is applied to the lower surface of the silicon chip；Remove the oxide layer of the upper surface of the silicon chip；Remove the negtive photoresist of the lower surface of the silicon chip；Back-to-back boron diffusion is carried out to the silicon chip；Negtive photoresist is applied to the boron extended surface of the silicon chip；Remove the oxide layer of the lower surface of the silicon chip；Remove the negtive photoresist of the upper surface of the silicon chip；Back-to-back phosphorus diffusion is carried out to the silicon chip.
- 2. the preparation method of N-type double-side cell as claimed in claim 1, it is characterised in that the thickness of the oxide layer is 80nm。
- 3. the preparation method of N-type double-side cell as claimed in claim 1, it is characterised in that the following table to the silicon chip Face, which applies negtive photoresist, to be included：Negtive photoresist is applied in the lower surface of the silicon chip with sol evenning machine, protects the oxide layer of the lower surface of the silicon chip；The silicon chip that lower surface is coated to negtive photoresist is placed on 110 DEG C of dryer and dried 10 minutes, until glue is done；Wherein, the rotating speed of the sol evenning machine is 3.75 thousand rpms, and the time is 30 seconds.
- 4. the preparation method of N-type double-side cell as claimed in claim 1, it is characterised in that described to remove the upper of the silicon chip The oxide layer on surface, including：The silicon chip is immersed in the HF solution that volume ratio is 10% 5 minutes, removes the oxide layer of the silicon chip upper surface.
- 5. the preparation method of N-type double-side cell as claimed in claim 1, it is characterised in that described to remove the silicon chip following table The negtive photoresist in face, including：The silicon chip is immersed in the sodium carbonate liquor that mass ratio is 1% 10 minutes, removes the negtive photoresist of the silicon chip lower surface；The silicon chip for removing lower surface negtive photoresist is soaked 1 minute in 70 DEG C of hot water；Silicon chip is immersed in HCl solution, removes metal ion.
- 6. the preparation method of N-type double-side cell as claimed in claim 1, it is characterised in that described to be carried on the back to the silicon chip Backrest boron spreads, including：The upper table of the silicon chip is faced outwardly, the boron diffusion that puts in, the silicon are close in the lower surface with oxide layer face-to-face The upper surface of piece obtains uniform boron diffusion, and the boron diffusingsurface obtains 80nm BSG, and as barrier layer, sheet resistance is 70/.
- 7. the preparation method of N-type double-side cell as claimed in claim 6, it is characterised in that carried out to the silicon chip back-to-back Phosphorus diffusion, including：It is put into after the boron diffusingsurface of the silicon chip is close to face-to-face in boiler tube and carries out phosphorus diffusion, forms PSG.
- 8. the preparation method of N-type double-side cell as claimed in claim 7, it is characterised in that carried out described to the silicon chip After back-to-back phosphorus diffusion, in addition to：The BSG and PSG of the silicon chip surface are removed, is included in silicon chip being immersed in the HF solution that volume ratio is 10% and soaks 8 Minute, BSG, PSG of the silicon chip surface are removed.
- 9. the preparation method of N-type double-side cell as claimed in claim 8, it is characterised in that remove the silicon chip table described After the BSG and PSG in face, in addition to：The boron extended surface of the silicon chip is passivated, including it is blunt with aluminum oxide of the ALD equipment in one layer of 6nm of boron extended surface making of the silicon chip Change boron extended surface, the silicon chip for making aluminium oxide passivation boron extended surface is annealed.
- 10. the preparation method of N-type double-side cell as claimed in claim 9, it is characterised in that in the passivation silicon chip After boron extended surface, in addition to：Two-sided PECVD plated films are carried out to the silicon chip；Two-sided silk-screen printing is carried out to the silicon chip.
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| CN103887347A (en) * | 2014-03-13 | 2014-06-25 | 中国东方电气集团有限公司 | Double-face P-type crystalline silicon battery structure and manufacturing method thereof |
| CN104538501A (en) * | 2015-01-15 | 2015-04-22 | 中利腾晖光伏科技有限公司 | N-type double-sided battery and manufacturing method thereof |
| CN104733555A (en) * | 2014-12-31 | 2015-06-24 | 江苏顺风光电科技有限公司 | Efficient N-type double-sided solar cell and preparation method thereof |
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| US20110068367A1 (en) * | 2009-09-23 | 2011-03-24 | Sierra Solar Power, Inc. | Double-sided heterojunction solar cell based on thin epitaxial silicon |
| US20110186120A1 (en) * | 2009-11-05 | 2011-08-04 | Guardian Industries Corp. | Textured coating with various feature sizes made by using multiple-agent etchant for thin-film solar cells and/or methods of making the same |
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| CN103887347A (en) * | 2014-03-13 | 2014-06-25 | 中国东方电气集团有限公司 | Double-face P-type crystalline silicon battery structure and manufacturing method thereof |
| CN104733555A (en) * | 2014-12-31 | 2015-06-24 | 江苏顺风光电科技有限公司 | Efficient N-type double-sided solar cell and preparation method thereof |
| CN104538501A (en) * | 2015-01-15 | 2015-04-22 | 中利腾晖光伏科技有限公司 | N-type double-sided battery and manufacturing method thereof |
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