CN105914239A - N type double-faced battery manufacture method - Google Patents
N type double-faced battery manufacture method Download PDFInfo
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- CN105914239A CN105914239A CN201610220225.7A CN201610220225A CN105914239A CN 105914239 A CN105914239 A CN 105914239A CN 201610220225 A CN201610220225 A CN 201610220225A CN 105914239 A CN105914239 A CN 105914239A
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- described silicon
- boron
- diffusion
- type double
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- 238000000034 method Methods 0.000 title abstract description 7
- 238000004519 manufacturing process Methods 0.000 title abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 151
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 150
- 239000010703 silicon Substances 0.000 claims abstract description 150
- 238000009792 diffusion process Methods 0.000 claims abstract description 64
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 53
- 229910052796 boron Inorganic materials 0.000 claims abstract description 53
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 23
- 230000004888 barrier function Effects 0.000 claims abstract description 14
- 230000003647 oxidation Effects 0.000 claims abstract description 11
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 11
- 239000003292 glue Substances 0.000 claims description 54
- 238000002360 preparation method Methods 0.000 claims description 29
- 229910052698 phosphorus Inorganic materials 0.000 claims description 21
- 239000011574 phosphorus Substances 0.000 claims description 21
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 19
- 238000002161 passivation Methods 0.000 claims description 9
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical compound [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 claims description 8
- 229910000029 sodium carbonate Inorganic materials 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 230000008859 change Effects 0.000 claims description 3
- 229910021645 metal ion Inorganic materials 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 238000007650 screen-printing Methods 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 abstract 5
- 238000004026 adhesive bonding Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000010422 painting Methods 0.000 description 4
- 230000007480 spreading Effects 0.000 description 4
- 238000003892 spreading Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002386 leaching Methods 0.000 description 1
- 238000011068 loading method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000005297 pyrex Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses an N type double-faced battery manufacture method which comprises the following steps: a silicon wafer is subjected to double face thermal oxidation operation, oxidation layers are formed on an upper surface and a lower surface of the silicon wafer, negative photoresist is coated on the lower surface of the silicon wafer, the oxidation layer on the upper surface of the silicon wafer is removed, the negative photoresist coated on the lower surface of the silicon wafer is removed, the silicon wafer is subjected to back-to-back boron diffusion operation, the negative photoresist is coated on a boron diffusion face of the silicon wafer, oxidation layer on the lower surface of the silicon wafer is removed, the negative photoresist on the upper surface of the silicon wafer is removed, and the silicon wafer is subjected to back-to-back phosphor diffusion operation. According to the N type double-faced battery manufacture method, barrier layers are coated with the photoresist and well protected before boron diffusion and phosphor diffusion, a high quality double-faced diffusion junction can be obtained, and finally a high efficiency battery cell can be obtained.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of N-type double-side cell
Preparation method.
Background technology
General in factory in the market is all p-type polycrystalline cell piece, and this efficiency is not
High.Along with the progress of technology, the production cost of N-type silicon chip is also further reducing, and single
Brilliant efficiency is higher than polycrystalline, because occurring in that production and the application of N-type battery slice in the industry.
Just having had the Boron diffusion method of N-type silicon chip, therefore N-type double-side cell uses and gives birth to.
The method of existing N-type double-side cell Double side diffusion, is to deposit SiN by CVD
With SiO as mask, it is used for stopping the barrier layer of another diffusion in diffusion.Owing to passing through
SiN and SiO of CVD is clean, then brings boiler tube diffusion into and can pollute boiler tube, and after spreading,
SiN is difficult to clean up.The Double side diffusion finally made is unholiness, causes the most inefficient.
Summary of the invention
It is an object of the invention to provide the preparation method of a kind of N-type double-side cell, it is thus achieved that high-quality
Double side diffusion connect, it is thus achieved that efficient cell piece.
For solving above-mentioned technical problem, embodiments provide a kind of N-type double-side cell
Preparation method, including:
Silicon chip is carried out Double-side hot oxidation, and the upper and lower surface at described silicon chip all generates oxygen
Change layer；
The following table topcoating of described silicon chip is born glue；
Remove the oxide layer of the upper surface of described silicon chip；
Remove the negative glue of the lower surface of described silicon chip；
Described silicon chip is carried out back-to-back boron diffusion；
The boron extended surface of described silicon chip is coated with negative glue；
Remove the oxide layer of the lower surface of described silicon chip；
Remove the negative glue of the upper surface of described silicon chip；
Described silicon chip is carried out back-to-back phosphorus diffusion.
Wherein, the thickness of described oxide layer is 80nm.
Wherein, the described following table topcoating to described silicon chip is born glue and is included:
Bear glue with sol evenning machine in the following table topcoating of described silicon chip, protect the lower surface of described silicon chip
Oxide layer；
The silicon chip that lower surface coats negative glue is placed on the dehydrator of 110 degree baking 10 minutes, until
Glue is done；
Wherein, the rotating speed of described sol evenning machine is 3.75 thousand rpms, and the time is 30 seconds.
Wherein, the oxide layer of the upper surface of the described silicon chip of described removing, including:
Described silicon chip is immersed in the HF solution that volume ratio is 10% 5 minutes, removes described
The oxide layer of silicon chip upper surface.
Wherein, the negative glue of described removing described silicon chip lower surface, including:
Described silicon chip is immersed in the sodium carbonate liquor that mass ratio is 1% 10 minutes, removes institute
State the negative glue of silicon chip lower surface；
Removing lower surface is born the silicon chip of glue soak 1 minute in the hot water of 70 degree；
Silicon chip is immersed in HCl solution, removes metal ion.
Wherein, described described silicon chip is carried out back-to-back boron diffusion, including:
By the upper surface of described silicon chip outwardly, the lower surface with oxide layer is close to put face-to-face
Entering boron diffusion, the upper surface of described silicon chip obtains the diffusion of uniform boron, and described boron diffusingsurface obtains
Obtaining the BSG of 80nm, as barrier layer, sheet resistance is 70.
Wherein, described silicon chip is carried out back-to-back phosphorus diffusion, including:
Put into after the boron diffusingsurface of described silicon chip is close to face-to-face in boiler tube and carry out phosphorus diffusion, shape
Become PSG.
Wherein, described described silicon chip is carried out back-to-back phosphorus diffusion after, also include:
Remove BSG and PSGS of described silicon chip surface, be included in and silicon chip is immersed in volume ratio
It is that the HF solution of 10% soaks 8 minutes, BSG, PSG of described silicon chip surface are removed.
Wherein, after BSG and PSGS of the described silicon chip surface of described removing, also include:
It is passivated the boron extended surface of described silicon chip, including using the ALD equipment boron extended surface at described silicon chip
Make the aluminium oxide passivation boron extended surface of one layer of 6nm, to the silicon chip making aluminium oxide passivation boron extended surface
Anneal.
Wherein, after the boron extended surface of the described silicon chip of described passivation, also include:
Described silicon chip is carried out two-sided PECVD plated film；
Described silicon chip is carried out two-sided silk screen printing.
The preparation method of the N-type double-side cell that the embodiment of the present invention is provided, with prior art phase
Ratio, has the advantage that
The preparation method of the N-type double-side cell that the embodiment of the present invention is provided, including: to silicon chip
Carrying out Double-side hot oxidation, the upper and lower surface at described silicon chip all generates oxide layer；To institute
The following table topcoating stating silicon chip bears glue；Remove the oxide layer of the upper surface of described silicon chip；Remove described
The negative glue of the lower surface of silicon chip；Described silicon chip is carried out back-to-back boron diffusion；To described silicon chip
Boron extended surface is coated with negative glue；Remove the oxide layer of the lower surface of described silicon chip；Remove the upper of described silicon chip
The negative glue on surface；Described silicon chip is carried out back-to-back phosphorus diffusion.
The preparation method of described N-type double-side cell, bears glue protection mask with twice painting, it is to avoid take
Band SiN enters boiler tube diffusion, and preferably protection another side is not extended influence to, and negative glue
Can also easily remove.By all protecting resistance by gluing before spreading in boron diffusion and phosphorus
Barrier, and then obtain the Double side diffusion knot that quality is high, finally can obtain efficient cell piece.
In sum, the preparation method of the described N-type double-side cell that the embodiment of the present invention is provided,
By all protecting barrier layer by gluing before spreading in boron diffusion and phosphorus, and then obtain quality
High Double side diffusion knot, finally can obtain efficient cell piece.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below
The accompanying drawing used required in embodiment or description of the prior art will be briefly described, aobvious and
Easily insight, the accompanying drawing in describing below is some embodiments of the present invention, common for this area
From the point of view of technical staff, on the premise of not paying creative work, it is also possible to according to these accompanying drawings
Obtain other accompanying drawing.
Fig. 1 is the preparation side of the N-type double-side cell in a kind of concrete mode of the embodiment of the present invention
The steps flow chart schematic diagram of method；
Fig. 2 is the most concrete making work of the preparation method of the N-type double-side cell in the present invention
Technological parameter during skill and steps flow chart.
Detailed description of the invention
The most as described in the background section, owing to needing the upper surface at silicon chip to carry out boron diffusion,
Lower surface carries out phosphorus diffusion, stops another kind diffusion without good mask as barrier layer
The impact that brings and when removing diffusion around the impact expanded, then another side can largely must be by
Destroy, it is impossible to obtain good pure knot, finally affect cell piece efficiency.
Based on this, embodiments provide the preparation method of a kind of N-type double-side cell, bag
Including: silicon chip is carried out Double-side hot oxidation, the upper and lower surface at described silicon chip all generates oxygen
Change layer；The following table topcoating of described silicon chip is born glue；Remove the oxide layer of the upper surface of described silicon chip；
Remove the negative glue of the lower surface of described silicon chip；Described silicon chip is carried out back-to-back boron diffusion；To institute
The boron extended surface stating silicon chip is coated with negative glue；Remove the oxide layer of the lower surface of described silicon chip；Remove described
The negative glue of the upper surface of silicon chip；Described silicon chip is carried out back-to-back phosphorus diffusion.
In sum, the preparation method of the N-type double-side cell that the embodiment of the present invention provides, with two
Glue protection mask is born in secondary painting, it is to avoid carries SiN and enters boiler tube diffusion, preferably protects another side
Do not extended influence to, and negative glue can also easily be removed.By expanding in boron diffusion and phosphorus
All protect barrier layer by gluing before Saning, and then obtain the Double side diffusion knot that quality is high,
After can obtain efficient cell piece.
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, knot below
Close accompanying drawing the detailed description of the invention of the present invention is described in detail.
Elaborate detail in the following description so that fully understanding the present invention.But this
Bright can be different from alternate manner described here implement with multiple, those skilled in the art can
To do similar popularization in the case of intension of the present invention.Therefore the present invention is not by following public affairs
The restriction being embodied as opened.
Refer to the N-type in a kind of concrete mode that Fig. 1-2, Fig. 1 are the embodiment of the present invention double
The steps flow chart schematic diagram of the preparation method of face battery；Fig. 2 is the two-sided electricity of the N-type in the present invention
Technological parameter during the most concrete processing technology of the preparation method in pond and steps flow chart.
In a kind of detailed description of the invention, the preparation method of described N-type double-side cell, including:
Step 10, carries out Double-side hot oxidation to silicon chip, in the upper and lower surface of described silicon chip
All generate oxide layer；
Step 20, bears glue to the following table topcoating of described silicon chip；
Step 30, removes the oxide layer of the upper surface of described silicon chip；
Step 40, removes the negative glue of the lower surface of described silicon chip；
Step 50, carries out back-to-back boron diffusion to described silicon chip；
Step 60, is coated with negative glue to the boron extended surface of described silicon chip；
Step 70, removes the oxide layer of the lower surface of described silicon chip；
Step 80, removes the negative glue of the upper surface of described silicon chip；
Step 90, carries out back-to-back phosphorus diffusion to described silicon chip.
It should be noted that the present invention to silicon chip is carried out Double-side hot oxidation process conditions and
The thickness of oxide layer is not specifically limited, described oxide layer function as barrier layer or mask,
The effect of negative glue is protection barrier layer, and the thickness of oxide layer is usually 80nm.
The preparation method of described N-type double-side cell, bears glue protection mask with twice painting, it is to avoid take
Band SiN enters boiler tube diffusion, and preferably protection another side is not extended influence to, and negative glue
Can also easily remove.By all protecting resistance by gluing before spreading in boron diffusion and phosphorus
Barrier, and then obtain the Double side diffusion knot that quality is high, finally can obtain efficient cell piece.
The general following table topcoating to described silicon chip is born glue and is included: with sol evenning machine under described silicon chip
Surface is coated with negative glue, protects the oxide layer of the lower surface of described silicon chip；Lower surface is coated negative glue
Silicon chip is placed on the dehydrator of 110 degree baking 10 minutes, until glue is done.
The rotating speed of described sol evenning machine is 3.75 thousand rpms, and the time is 30 seconds.
It should be noted that the parameter of the concrete spin coating of sol evenning machine is not done concrete limit by the present invention
Fixed, the concrete kind of negative glue is not specifically limited, as long as oxide layer can be protected.
Removing the oxide layer on described silicon chip in the present invention, general employing HF solution removes oxidation
Layer, including: described silicon chip is immersed in the HF solution that volume ratio is 10% 5 minutes, removes
Go the oxide layer of described silicon chip upper surface.
Removing the negative glue of described silicon chip surface in the present invention, general employing sodium carbonate liquor removes negative
Glue, including: described silicon chip is immersed in the sodium carbonate liquor that mass ratio is 1% 10 minutes,
Remove the negative glue of described silicon chip lower surface；The hot water that the silicon chip of glue is at 70 degree is born by removing lower surface
Middle immersion 1 minute；Silicon chip is immersed in HCl solution, removes metal ion.
The present invention is to the oxide layer on taking-up silicon chip and the concentration of solution, kind and the leaching of negative glue
The bubble time does not limits, as long as other layer on silicon chip while removing totally does not do impact i.e.
Can, but normally due to the thickness of oxidated layer thickness and negative glue is less, for ensureing removal effect,
It is typically chosen the solution using concentration relatively low.
Owing to when carrying out boron diffusion or phosphorus diffusion, the most multiple silicon chips are carried out, so simultaneously
Work efficiency can be improved, typically use in back-to-back fashion, so given side can be carried out
While diffusion, another side being formed protection, described silicon chip carries out back-to-back boron diffusion, including:
By the upper surface of described silicon chip outwardly, the lower surface with oxide layer is close to put face-to-face
Entering boron diffusion, the upper surface of described silicon chip obtains the diffusion of uniform boron, and described boron diffusingsurface obtains
Obtaining the BSG of 80nm, as barrier layer, sheet resistance is 70.
Described silicon chip is carried out back-to-back phosphorus diffusion, including: by the boron diffusingsurface face of described silicon chip
Opposite is put into after being close in boiler tube and is carried out phosphorus diffusion, forms PSG.Owing to boron is diffused with the thickest
Barrier layer, by the neck diffusion of in back-to-back fashion memory, can stop the boron diffusion that extends influence
Face.
After completing described silicon chip is carried out back-to-back phosphorus diffusion, also include:
Step 100, removes BSG and PSGS of described silicon chip surface, is included in and is soaked by silicon chip
Bubble in the HF solution that volume ratio is 10% soak 8 minutes, by the BSG of described silicon chip surface,
PSG removes.
BSG in the present invention represents that Pyrex, PSG represent phosphorosilicate glass, and ALD is passivated
Expression Al2O3。
Wherein, after BSG and PSGS of the described silicon chip surface of described removing, also include:
It is passivated the boron extended surface of described silicon chip, including using the ALD equipment boron extended surface at described silicon chip
Make the aluminium oxide passivation boron extended surface of one layer of 6nm, to the silicon chip making aluminium oxide passivation boron extended surface
Anneal.
Wherein, after the boron extended surface of the described silicon chip of described passivation, also include:
Step 110, carries out two-sided PECVD plated film to described silicon chip；
Step 120, carries out two-sided silk screen printing to described silicon chip.
Such as Fig. 2 be the present invention N-type double-side cell preparation method in produce once during
Concrete technology parameter step, wherein, LZ represents that load zone is loading area；CZ represents
District centered by center zone；The provisional capital that temperature is blank represents that temperature is identical with lastrow；
In Wait for, the 9th step and the 11st step represent wait temperature to set point limits,
I.e. waiting temperature is to setting value；13rd step table wait for BBR3wanted (valve)
OFF。
In sum, the preparation method of the N-type double-side cell that the embodiment of the present invention provides, with two
Glue protection mask is born in secondary painting, it is to avoid carries SiN and enters boiler tube diffusion, preferably protects another side
Do not extended influence to, and negative glue can also easily be removed.By expanding in boron diffusion and phosphorus
All protect barrier layer by gluing before Saning, and then obtain the Double side diffusion knot that quality is high,
After can obtain efficient cell piece.
Above the preparation method of N-type double-side cell provided by the present invention is carried out detailed Jie
Continue.Principle and the embodiment of the present invention are set forth by specific case used herein,
The explanation of above example is only intended to help to understand method and the core concept thereof of the present invention.Should
When pointing out, for those skilled in the art, without departing from the principle of the invention
On the premise of, it is also possible to the present invention is carried out some improvement and modification, and these improve and modify also
Fall in the protection domain of the claims in the present invention.
Claims (10)
1. the preparation method of a N-type double-side cell, it is characterised in that including:
Silicon chip is carried out Double-side hot oxidation, and the upper and lower surface at described silicon chip all generates oxygen
Change layer；
The following table topcoating of described silicon chip is born glue；
Remove the oxide layer of the upper surface of described silicon chip；
Remove the negative glue of the lower surface of described silicon chip；
Described silicon chip is carried out back-to-back boron diffusion；
The boron extended surface of described silicon chip is coated with negative glue；
Remove the oxide layer of the lower surface of described silicon chip；
Remove the negative glue of the upper surface of described silicon chip；
Described silicon chip is carried out back-to-back phosphorus diffusion.
2. the preparation method of N-type double-side cell as claimed in claim 1, it is characterised in that
The thickness of described oxide layer is 80nm.
3. the preparation method of N-type double-side cell as claimed in claim 1, it is characterised in that
The described following table topcoating to described silicon chip is born glue and is included:
Bear glue with sol evenning machine in the following table topcoating of described silicon chip, protect the lower surface of described silicon chip
Oxide layer；
The silicon chip that lower surface coats negative glue is placed on the dehydrator of 110 degree baking 10 minutes, until
Glue is done；
Wherein, the rotating speed of described sol evenning machine is 3.75 thousand rpms, and the time is 30 seconds.
4. the preparation method of N-type double-side cell as claimed in claim 1, it is characterised in that
The oxide layer of the upper surface of the described silicon chip of described removing, including:
Described silicon chip is immersed in the HF solution that volume ratio is 10% 5 minutes, removes described
The oxide layer of silicon chip upper surface.
5. the preparation method of N-type double-side cell as claimed in claim 1, it is characterised in that
The negative glue of described removing described silicon chip lower surface, including:
Described silicon chip is immersed in the sodium carbonate liquor that mass ratio is 1% 10 minutes, removes institute
State the negative glue of silicon chip lower surface；
Removing lower surface is born the silicon chip of glue soak 1 minute in the hot water of 70 degree；
Silicon chip is immersed in HCl solution, removes metal ion.
6. the preparation method of N-type double-side cell as claimed in claim 1, it is characterised in that
Described described silicon chip is carried out back-to-back boron diffusion, including:
By the upper surface of described silicon chip outwardly, the lower surface with oxide layer is close to put face-to-face
Entering boron diffusion, the upper surface of described silicon chip obtains the diffusion of uniform boron, and described boron diffusingsurface obtains
Obtaining the BSG of 80nm, as barrier layer, sheet resistance is 70.
7. the preparation method of N-type double-side cell as claimed in claim 6, it is characterised in that
Described silicon chip is carried out back-to-back phosphorus diffusion, including:
Put into after the boron diffusingsurface of described silicon chip is close to face-to-face in boiler tube and carry out phosphorus diffusion, shape
Become PSG.
8. the preparation method of N-type double-side cell as claimed in claim 7, it is characterised in that
Described described silicon chip is carried out back-to-back phosphorus diffusion after, also include:
Remove BSG and PSGS of described silicon chip surface, be included in and silicon chip is immersed in volume ratio
It is that the HF solution of 10% soaks 8 minutes, BSG, PSG of described silicon chip surface are removed.
9. the preparation method of N-type double-side cell as claimed in claim 8, it is characterised in that
After BSG and PSGS of the described silicon chip surface of described removing, also include:
It is passivated the boron extended surface of described silicon chip, including using the ALD equipment boron extended surface at described silicon chip
Make the aluminium oxide passivation boron extended surface of one layer of 6nm, to the silicon chip making aluminium oxide passivation boron extended surface
Anneal.
10. the preparation method of N-type double-side cell as claimed in claim 9, it is characterised in that
After the boron extended surface of the described silicon chip of described passivation, also include:
Described silicon chip is carried out two-sided PECVD plated film；
Described silicon chip is carried out two-sided silk screen printing.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106206859A (en) * | 2016-09-09 | 2016-12-07 | 浙江晶科能源有限公司 | A kind of preparation method of N-type double-side cell |
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