CN105892608A - Novel reset wake-upcircuit - Google Patents

Novel reset wake-upcircuit Download PDF

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Publication number
CN105892608A
CN105892608A CN201610274309.9A CN201610274309A CN105892608A CN 105892608 A CN105892608 A CN 105892608A CN 201610274309 A CN201610274309 A CN 201610274309A CN 105892608 A CN105892608 A CN 105892608A
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CN
China
Prior art keywords
circuit
wake
resistance
chip
feet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610274309.9A
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Chinese (zh)
Inventor
赵旭
陈凌飞
司永孝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Tuzheng Information Technology Co Ltd
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Shanghai Tuzheng Information Technology Co Ltd
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Priority to CN201610274309.9A priority Critical patent/CN105892608A/en
Publication of CN105892608A publication Critical patent/CN105892608A/en
Pending legal-status Critical Current

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24Resetting means
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751Error or fault detection not based on redundancy
    • G06F11/0754Error or fault detection not based on redundancy by exceeding limits
    • G06F11/0757Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Amplifiers (AREA)

Abstract

The invention discloses a novel reset wake-up circuit. The circuit comprises a master chip control circuit, an wake-up input circuit connected to the master chip control circuit and an wake-up output circuit connected to the master chip control circuit. The novel reset wake-up circuit has the beneficial effects of high stability, low power consumption, simple circuit and wide applicable range, and can be applied to any circuits needing reset wake-up.

Description

Novel resetting wake-up circuit
Technical field
The present invention relates to safety-security area, especially relate to be applicable to the novel resetting of the equipment such as smart lock, safety cabinet Wake-up circuit.
Background technology
It is well known that smart lock, safety cabinet etc. are the products that safety-security area operation is relatively broad, but existing Smart lock, the reset wake-up circuit of the product such as safety cabinet there is poor reliability, instability, fraud that power consumption is high End, and, circuit is the most considerably complicated, portable weak.
Summary of the invention
It is an object of the invention to provide a kind of novel resetting wake-up circuit, its stability is high, highly reliable, and And simple circuit, low in energy consumption, portable strong.
For solving above-mentioned technical problem, embodiments of the present invention provide a kind of novel resetting wake-up circuit, its Including: master chip control circuit;Be connected to described master chip control circuit wakes up input circuit up;It is connected to described Master chip control circuit wake up output circuit up;The described input circuit that wakes up up includes: be connected to successively wake up element up Electric capacity C5, diode D2, this wake up up element be connected to power supply AVCC, described diode D2 another termination In master chip control circuit, the two of described electric capacity C5 are terminated with the resistance R10 of ground connection, resistance R11 respectively, Described diode D2 outfan is connected to the resistance R12 of ground connection, electric capacity C6 respectively;Described wake up output circuit bag up Include: be connected to the resistance R1 of master chip control circuit, described resistance R1 and be connected to audion Q1, this audion Q1 Grounded emitter, the colelctor electrode of audion is connected to 3 feet of control chip U2,3 feet of control chip and three 4 feet being connected to be connected to the resistance R2, control chip U2 of power supply AVCC between the pipe collector of pole are connected to power supply AVCC, and 4 feet of control chip U2 connect and have the electric capacity C1 of ground connection, 2 feet of described control chip U2 connect Having CMOS tube Tr1, the source electrode of CMOS tube Tr1 is connected to power supply AVCC, and CMOS tube Tr1 source electrode with Being connected to resistance R3 between 2 feet of control chip U2, the drain electrode of described CMOS tube Tr1 is connected to power supply VCC, And the drain electrode of described CMOS tube Tr1 is further connected with the resistance R4 and electric capacity C2 of ground connection.
Further, waking up element described in up is button key.
Further, described control chip U2 is IMP811TEUS chip.
Further, described master chip control circuit uses STM32F030F4 chip.
There is advantages that
1, stability is high, low in energy consumption;
2, circuit is simple, applied widely, can be used for any needs in reset wake-up circuit;
3, this circuit can serve as outer watchdog, coordinates software to prevent system in case of system halt, necessarily may be used after deadlock To recover.
Accompanying drawing explanation
Fig. 1 is novel resetting wake-up circuit theory diagram;
Fig. 2 is master chip control circuit figure;
Fig. 3 is for waking up output circuit figure up;
Fig. 4 is for waking up input circuit figure up;
Fig. 5 is the utilization schematic diagram of novel resetting wake-up circuit.
Detailed description of the invention
For the technological means making the present invention realize, creation characteristic, reach purpose and be easy to understand with effect, Below in conjunction with specific embodiment, the present invention is expanded on further.
As it is shown in figure 1, a kind of novel resetting wake-up circuit, comprising: master chip control circuit 1 and being connected to The waking up input circuit 2 up, wake up output circuit 3 up of described master chip control circuit.
Wherein, seeing Fig. 2, master chip control circuit uses STM32F030F4 chip, this STM32F030F4 1 foot of chip passes through resistance R13 ground connection, and 2 feet, 3 feet, 7-10 foot, 11-14 foot, 17-20 foot are empty Pin, 4 feet pass through electric capacity C8 ground connection, and, 4 feet are connected to power supply VCC by resistance R16, and 5 feet are connected to Power supply VCC, 6 feet connect the interface MO_WKUP waking up input, output circuit up, 15 foot ground connection, and 16 feet are connected to electricity Source VCC.
Shown in Figure 4, described in wake up input circuit 2 up and include: be connected to successively the electric capacity C5 of button key, two Pole pipe D2, this button key are connected to power supply AVCC, and the other end of described diode D2 is connected to master chip control Circuit, the two of described electric capacity C5 are terminated with the resistance R10 of ground connection, resistance R11, described diode D2 respectively Outfan is connected to the resistance R12 of ground connection, electric capacity C6 respectively.
Shown in Figure 3, use the output circuit 3 that wakes up up of IMP811TEUS chip to include: to be connected to master chip The resistance R1 (playing metering function) of control circuit, described resistance R1 are connected to audion Q1 and (play switch to make With), the grounded emitter of this audion Q1, the colelctor electrode of audion is connected to 3 feet of control chip U2, control It is connected to be connected to power supply AVCC between 3 feet and the transistor collector of coremaking sheet (using IMP811TEUS chip) Resistance R2 (playing pull-up effect), 4 feet of control chip U2 are connected to power supply AVCC, and control chip U2 4 feet connect and have the electric capacity C1 (playing filter action) of ground connection, 2 feet of described control chip U2 are connected to CMOS Pipe Tr1 (plays on-off action), and the source electrode of CMOS tube Tr1 is connected to power supply AVCC, and in CMOS tube Tr1 Source electrode and 2 feet of control chip U2 between be connected to resistance R3 (playing pull-up effect), described CMOS tube The drain electrode of Tr1 is connected to power supply VCC, and the drain electrode of described CMOS tube Tr1 be further connected with ground connection resistance R4 and Electric capacity C2, here, resistance R4 and electric capacity C2 forms RC filter circuit, plays filter action, IMP811TEUS 1 foot ground connection of chip.This wakes up up in output circuit, by chip or other can produce end of high level End controls audion and opens, IMP811 chip 3 foot Low level effective, and IMP811 starts working, 2 foot outputs Low level, and then make CMOS tube open, AVCC Yu VCC turns on, and produces voltage at VCC.
Explanation is simply used below for this reset wake-up circuit:
Seeing Fig. 5, first this circuit wake source is button, it is also possible to be designed to other external control signals.When Button is pressed, and produces of short duration high level signal at M0_WKUP, and this signal can make audion Q1 open, IMP811 Chip operation makes CMOS tube open, AVCC with VCC connects, and has voltage and then powers to MCU, make at VCC MCU works.IMP811 chip has individual characteristic: after 140ms, if IMP811 three-prong (MR) becomes High level, then the reset foot output high level of IMP811 chip, CMOS tube closedown, AVCC Yu VCC breaks Open, and then make MCU quit work.So, MCU can be by the work of house dog register controlled IMP811 Time, control VCC, and then control power consumption.
It will be understood by those skilled in the art that the respective embodiments described above are to realize being embodied as of the present invention Example, and in actual applications, can to it, various changes can be made in the form and details, without departing from this Bright spirit and scope.

Claims (4)

1. a novel resetting wake-up circuit, it is characterised in that comprising:
Master chip control circuit;
Be connected to described master chip control circuit wakes up input circuit up;
Be connected to described master chip control circuit wakes up output circuit up;
The described input circuit that wakes up up includes: being connected to wake up up the electric capacity C5 of element, diode D2 successively, this wakes up up Element is connected to power supply AVCC, and the other end of described diode D2 is connected to master chip control circuit, described electric capacity The two of C5 are terminated with the resistance R10 of ground connection, resistance R11 respectively, and described diode D2 outfan is connected to respectively The resistance R12 of ground connection, electric capacity C6;
The described output circuit that wakes up up includes: is connected to the resistance R1 of master chip control circuit, described resistance R1 and is connected to Audion Q1, the grounded emitter of this audion Q1, the colelctor electrode of audion is connected to the 3 of control chip U2 Foot, is connected to be connected to the resistance R2 of power supply AVCC between 3 feet and the transistor collector of control chip, control core 4 feet of sheet U2 are connected to power supply AVCC, and 4 feet of control chip U2 connect the electric capacity C1 having ground connection, described 2 feet of control chip U2 are connected to CMOS tube Tr1, and the source electrode of CMOS tube Tr1 is connected to power supply AVCC, and It is connected to resistance R3 between source electrode and 2 feet of control chip U2 of CMOS tube Tr1, described CMOS tube Tr1 Drain electrode is connected to power supply VCC, and the drain electrode of described CMOS tube Tr1 is further connected with the resistance R4 and electric capacity C2 of ground connection.
Novel resetting wake-up circuit the most according to claim 1, it is characterised in that described in wake up element up For button key.
Novel resetting wake-up circuit the most according to claim 1, it is characterised in that described control chip U2 is IMP811TEUS chip.
Novel resetting wake-up circuit the most according to claim 1, it is characterised in that described master chip control Circuit processed uses STM32F030F4 chip.
CN201610274309.9A 2016-04-28 2016-04-28 Novel reset wake-upcircuit Pending CN105892608A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610274309.9A CN105892608A (en) 2016-04-28 2016-04-28 Novel reset wake-upcircuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610274309.9A CN105892608A (en) 2016-04-28 2016-04-28 Novel reset wake-upcircuit

Publications (1)

Publication Number Publication Date
CN105892608A true CN105892608A (en) 2016-08-24

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112583403A (en) * 2020-12-11 2021-03-30 重庆西南集成电路设计有限责任公司 Circuit and method for indicating single chip microcomputer in wake-up stop state by using phase-locked loop locking

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1908856A (en) * 2005-08-05 2007-02-07 中兴通讯股份有限公司 Position restoration circuit device
US20100293396A1 (en) * 2009-05-15 2010-11-18 Asustek Computer Inc. Power control circuit and method of computer system
WO2012168895A1 (en) * 2011-06-09 2012-12-13 Indesit Company S.P.A. Household appliance with stand-by wake-up system
CN103558774A (en) * 2013-09-24 2014-02-05 康佳集团股份有限公司 Arbitrary key wakeup control device and terminal
CN203643779U (en) * 2013-10-31 2014-06-11 深圳市金正方科技股份有限公司 Outage wake-up circuit of ammeter metering terminal
CN205594569U (en) * 2016-04-28 2016-09-21 上海图正信息科技股份有限公司 Novel awakening circuit resets

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1908856A (en) * 2005-08-05 2007-02-07 中兴通讯股份有限公司 Position restoration circuit device
US20100293396A1 (en) * 2009-05-15 2010-11-18 Asustek Computer Inc. Power control circuit and method of computer system
WO2012168895A1 (en) * 2011-06-09 2012-12-13 Indesit Company S.P.A. Household appliance with stand-by wake-up system
CN103558774A (en) * 2013-09-24 2014-02-05 康佳集团股份有限公司 Arbitrary key wakeup control device and terminal
CN203643779U (en) * 2013-10-31 2014-06-11 深圳市金正方科技股份有限公司 Outage wake-up circuit of ammeter metering terminal
CN205594569U (en) * 2016-04-28 2016-09-21 上海图正信息科技股份有限公司 Novel awakening circuit resets

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112583403A (en) * 2020-12-11 2021-03-30 重庆西南集成电路设计有限责任公司 Circuit and method for indicating single chip microcomputer in wake-up stop state by using phase-locked loop locking
CN112583403B (en) * 2020-12-11 2022-09-23 重庆西南集成电路设计有限责任公司 Circuit and method for indicating single chip microcomputer in wake-up stop state by using phase-locked loop locking

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