CN205594569U - Novel awakening circuit resets - Google Patents
Novel awakening circuit resets Download PDFInfo
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- CN205594569U CN205594569U CN201620374177.2U CN201620374177U CN205594569U CN 205594569 U CN205594569 U CN 205594569U CN 201620374177 U CN201620374177 U CN 201620374177U CN 205594569 U CN205594569 U CN 205594569U
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- wake
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- 230000009286 beneficial effect Effects 0.000 abstract 1
- 230000002618 waking effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005265 energy consumption Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
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Abstract
The utility model discloses a novel awakening circuit resets, it includes main chip control circuit, connect in main chip control circuit awaken input circuit up and connect in main chip control circuit awaken output circuit up. The beneficial effects of the utility model are that: stability is high, the low power dissipation, the circuit is simple, and application scope is wide, can be used to any needs and resets among the awakening circuit.
Description
Technical field
This utility model relates to safety-security area, especially relates to be applicable to the novel of the equipment such as smart lock, safety cabinet
Reset wake-up circuit.
Background technology
It is well known that smart lock, safety cabinet etc. are the products that safety-security area operation is relatively broad, but existing
Smart lock, the reset wake-up circuit of the product such as safety cabinet there is poor reliability, instability, fraud that power consumption is high
End, and, circuit is the most considerably complicated, portable weak.
Utility model content
The purpose of this utility model is to provide a kind of novel resetting wake-up circuit, and its stability is high, highly reliable,
And simple circuit, low in energy consumption, portable strong.
For solving above-mentioned technical problem, embodiment of the present utility model provides a kind of novel resetting and wakes up electricity up
Road, comprising: master chip control circuit；Be connected to described master chip control circuit wakes up input circuit up；Connect
Output circuit is waken up up in described master chip control circuit；The described input circuit that wakes up up includes: be connected to successively call out
Wake up the electric capacity C5 of element, diode D2, and this wakes up element up and is connected to power supply AVCC, and described diode D2's is another
One end is connected to master chip control circuit, and the two of described electric capacity C5 are terminated with the resistance R10 of ground connection, resistance respectively
R11, described diode D2 outfan is connected to the resistance R12 of ground connection, electric capacity C6 respectively；Described wake up output up
Circuit includes: being connected to the resistance R1 of master chip control circuit, described resistance R1 and be connected to audion Q1, these are three years old
The grounded emitter of pole pipe Q1, the colelctor electrode of audion is connected to 3 feet of control chip U2, the 3 of control chip
4 feet being connected to be connected to the resistance R2 of power supply AVCC, control chip U2 between foot and transistor collector are connected to
Power supply AVCC, and 4 feet of control chip U2 connect and have the electric capacity C1 of ground connection, the 2 of described control chip U2
Foot is connected to CMOS tube Tr1, and the source electrode of CMOS tube Tr1 is connected to power supply AVCC, and in the source of CMOS tube Tr1
Being connected to resistance R3 between pole and 2 feet of control chip U2, the drain electrode of described CMOS tube Tr1 is connected to power supply VCC,
And the drain electrode of described CMOS tube Tr1 is further connected with the resistance R4 and electric capacity C2 of ground connection.
Further, waking up element described in up is button key.
Further, described control chip U2 is IMP811TEUS chip.
Further, described master chip control circuit uses STM32F030F4 chip.
This utility model has the advantages that
1, stability is high, low in energy consumption；
2, circuit is simple, applied widely, can be used for any needs in reset wake-up circuit；
3, this circuit can serve as outer watchdog, coordinates software to prevent system in case of system halt, necessarily may be used after deadlock
To recover.
Accompanying drawing explanation
Fig. 1 is novel resetting wake-up circuit theory diagram；
Fig. 2 is master chip control circuit figure；
Fig. 3 is for waking up output circuit figure up；
Fig. 4 is for waking up input circuit figure up；
Fig. 5 is the utilization schematic diagram of novel resetting wake-up circuit.
Detailed description of the invention
For the technological means making this utility model realize, creation characteristic, reach purpose and effect and be readily apparent from
Solve, below in conjunction with specific embodiment, this utility model is expanded on further.
As it is shown in figure 1, a kind of novel resetting wake-up circuit, comprising: master chip control circuit 1 and being connected to
The waking up input circuit 2 up, wake up output circuit 3 up of described master chip control circuit.
Wherein, seeing Fig. 2, master chip control circuit uses STM32F030F4 chip, this STM32F030F4
1 foot of chip passes through resistance R13 ground connection, and 2 feet, 3 feet, 7-10 foot, 11-14 foot, 17-20 foot are empty
Pin, 4 feet pass through electric capacity C8 ground connection, and, 4 feet are connected to power supply VCC by resistance R16, and 5 feet are connected to
Power supply VCC, 6 feet connect the interface MO_WKUP waking up input, output circuit up, 15 foot ground connection, and 16 feet are connected to electricity
Source VCC.
Shown in Figure 4, described in wake up input circuit 2 up and include: be connected to successively the electric capacity C5 of button key, two
Pole pipe D2, this button key are connected to power supply AVCC, and the other end of described diode D2 is connected to master chip control
Circuit, the two of described electric capacity C5 are terminated with the resistance R10 of ground connection, resistance R11, described diode D2 respectively
Outfan is connected to the resistance R12 of ground connection, electric capacity C6 respectively.
Shown in Figure 3, use the output circuit 3 that wakes up up of IMP811TEUS chip to include: to be connected to master chip
The resistance R1 (playing metering function) of control circuit, described resistance R1 are connected to audion Q1 and (play switch to make
With), the grounded emitter of this audion Q1, the colelctor electrode of audion is connected to 3 feet of control chip U2, control
It is connected to be connected to power supply AVCC between 3 feet and the transistor collector of coremaking sheet (using IMP811TEUS chip)
Resistance R2 (playing pull-up effect), 4 feet of control chip U2 are connected to power supply AVCC, and control chip U2
4 feet connect and have the electric capacity C1 (playing filter action) of ground connection, 2 feet of described control chip U2 are connected to CMOS
Pipe Tr1 (plays on-off action), and the source electrode of CMOS tube Tr1 is connected to power supply AVCC, and in CMOS tube Tr1
Source electrode and 2 feet of control chip U2 between be connected to resistance R3 (playing pull-up effect), described CMOS tube
The drain electrode of Tr1 is connected to power supply VCC, and the drain electrode of described CMOS tube Tr1 be further connected with ground connection resistance R4 and
Electric capacity C2, here, resistance R4 and electric capacity C2 forms RC filter circuit, plays filter action, IMP811TEUS
1 foot ground connection of chip.This wakes up up in output circuit, by chip or other can produce end of high level
End controls audion and opens, IMP811 chip 3 foot Low level effective, and IMP811 starts working, 2 foot outputs
Low level, and then make CMOS tube open, AVCC Yu VCC turns on, and produces voltage at VCC.
Explanation is simply used below for this reset wake-up circuit:
Seeing Fig. 5, first this circuit wake source is button, it is also possible to be designed to other external control signals.When
Button is pressed, and produces of short duration high level signal at M0_WKUP, and this signal can make audion Q1 open, IMP811
Chip operation makes CMOS tube open, AVCC with VCC connects, and has voltage and then powers to MCU, make at VCC
MCU works.IMP811 chip has individual characteristic: after 140ms, if IMP811 three-prong (MR) becomes
High level, then the reset foot output high level of IMP811 chip, CMOS tube closedown, AVCC Yu VCC breaks
Open, and then make MCU quit work.So, MCU can be by the work of house dog register controlled IMP811
Time, control VCC, and then control power consumption.
It will be understood by those skilled in the art that the respective embodiments described above be realize of the present utility model specifically
Embodiment, and in actual applications, can to it, various changes can be made in the form and details, without departing from
Spirit and scope of the present utility model.
Claims (4)
1. a novel resetting wake-up circuit, it is characterised in that comprising:
Master chip control circuit；
Be connected to described master chip control circuit wakes up input circuit up；
Be connected to described master chip control circuit wakes up output circuit up；
The described input circuit that wakes up up includes: being connected to wake up up the electric capacity C5 of element, diode D2 successively, this wakes up up
Element is connected to power supply AVCC, and the other end of described diode D2 is connected to master chip control circuit, described electric capacity
The two of C5 are terminated with the resistance R10 of ground connection, resistance R11 respectively, and described diode D2 outfan is connected to respectively
The resistance R12 of ground connection, electric capacity C6；
The described output circuit that wakes up up includes: is connected to the resistance R1 of master chip control circuit, described resistance R1 and is connected to
Audion Q1, the grounded emitter of this audion Q1, the colelctor electrode of audion is connected to the 3 of control chip U2
Foot, is connected to be connected to the resistance R2 of power supply AVCC between 3 feet and the transistor collector of control chip, control core
4 feet of sheet U2 are connected to power supply AVCC, and 4 feet of control chip U2 connect the electric capacity C1 having ground connection, described
2 feet of control chip U2 are connected to CMOS tube Tr1, and the source electrode of CMOS tube Tr1 is connected to power supply AVCC, and
It is connected to resistance R3 between source electrode and 2 feet of control chip U2 of CMOS tube Tr1, described CMOS tube Tr1
Drain electrode is connected to power supply VCC, and the drain electrode of described CMOS tube Tr1 is further connected with the resistance R4 and electric capacity C2 of ground connection.
Novel resetting wake-up circuit the most according to claim 1, it is characterised in that described in wake up element up
For button key.
Novel resetting wake-up circuit the most according to claim 1, it is characterised in that described control chip
U2 is IMP811TEUS chip.
Novel resetting wake-up circuit the most according to claim 1, it is characterised in that described master chip control
Circuit processed uses STM32F030F4 chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620374177.2U CN205594569U (en) | 2016-04-28 | 2016-04-28 | Novel awakening circuit resets |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620374177.2U CN205594569U (en) | 2016-04-28 | 2016-04-28 | Novel awakening circuit resets |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205594569U true CN205594569U (en) | 2016-09-21 |
Family
ID=56933295
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620374177.2U Expired - Fee Related CN205594569U (en) | 2016-04-28 | 2016-04-28 | Novel awakening circuit resets |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205594569U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105892608A (en) * | 2016-04-28 | 2016-08-24 | 上海图正信息科技股份有限公司 | Novel reset wake-upcircuit |
-
2016
- 2016-04-28 CN CN201620374177.2U patent/CN205594569U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105892608A (en) * | 2016-04-28 | 2016-08-24 | 上海图正信息科技股份有限公司 | Novel reset wake-upcircuit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20190603 Address after: 214000 Xishan District, Wuxi City, Jiangsu Province, 78 Danshan Road, Anzhen Street, 12th Floor, Block A, Xidong Chuangrong Building Patentee after: TUZHENG (WUXI) RESEARCH INSTITUTE Co.,Ltd. Address before: Room 1117, Building 88 Hengxi Road, Yangpu District, Shanghai, 20114 Patentee before: SHANGHAI TUZHENG INFORMATION TECHNOLOGY Co.,Ltd. |
|
| TR01 | Transfer of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160921 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |