CN105870055A - Manufacturing method for array substrate - Google Patents
Manufacturing method for array substrate Download PDFInfo
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- CN105870055A CN105870055A CN201610206328.8A CN201610206328A CN105870055A CN 105870055 A CN105870055 A CN 105870055A CN 201610206328 A CN201610206328 A CN 201610206328A CN 105870055 A CN105870055 A CN 105870055A
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- layer
- metal oxide
- metal
- manufacture method
- gate insulator
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 239000000758 substrate Substances 0.000 title claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims abstract description 44
- 239000002184 metal Substances 0.000 claims abstract description 44
- 238000002161 passivation Methods 0.000 claims abstract description 42
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 40
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 40
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052733 gallium Inorganic materials 0.000 claims abstract description 7
- 229910052738 indium Inorganic materials 0.000 claims abstract description 7
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000012212 insulator Substances 0.000 claims description 40
- 238000000034 method Methods 0.000 claims description 40
- 229920002120 photoresistant polymer Polymers 0.000 claims description 17
- 238000000059 patterning Methods 0.000 claims description 12
- 238000005240 physical vapour deposition Methods 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 9
- 238000001039 wet etching Methods 0.000 claims description 6
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 229910052725 zinc Inorganic materials 0.000 claims description 5
- 239000011701 zinc Substances 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical group O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 claims description 3
- 230000001105 regulatory effect Effects 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 150000001875 compounds Chemical class 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract description 5
- 230000000149 penetrating effect Effects 0.000 abstract description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 abstract 2
- 230000035515 penetration Effects 0.000 abstract 1
- 239000011787 zinc oxide Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 120
- 239000004973 liquid crystal related substance Substances 0.000 description 15
- 238000005286 illumination Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 5
- 238000000354 decomposition reaction Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 239000010409 thin film Substances 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000002835 absorbance Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 150000002343 gold Chemical class 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000002459 sustained effect Effects 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- AKJVMGQSGCSQBU-UHFFFAOYSA-N zinc azanidylidenezinc Chemical compound [Zn++].[N-]=[Zn].[N-]=[Zn] AKJVMGQSGCSQBU-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Nonlinear Science (AREA)
- Manufacturing & Machinery (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
The invention provides a manufacturing method for an array substrate. The manufacturing method comprises the steps of forming a first metal layer on a substrate, wherein the first metal layer comprises a gate electrode; forming a patterned gate insulation layer on the substrate for covering the first metal layer, and forming a metal oxide layer on the gate insulation layer; forming a second metal layer on the gate insulation layer, wherein the second metal layer comprises a drain electrode and a source electrode; the metal oxide layer is positioned between the drain electrode and the source electrode; forming a passivation layer on the gate insulation layer and the second metal layer; and a forming a transparent conductive layer on the passivation layer. Compared with the prior art, the metal oxide layer, such as indium gallium zinc oxide, is taken as the hard mark plate, so that the passivation layer with the steep pattern edge can be formed by penetrating through the hard mask layer so as to further reduce L0 light leak conditions and improve the penetration rate of incident lights.
Description
Technical field
The present invention relates to technical field of liquid crystal display, particularly relate to the array in a kind of liquid crystal display
The manufacture method of substrate.
Background technology
Currently, liquid crystal display has been widely used in every field as the one of flat faced display
In, it has the advantage such as low-power consumption, thin type light weight.As a rule, liquid crystal display includes a liquid crystal
Panel, this liquid crystal panel includes the thin-film transistor array base-plate (array with pixel electrode
Substrate), there is the colored filter substrate (color filter substrate) of public electrode and fill out
Fill the liquid crystal layer between thin-film transistor array base-plate and colored filter substrate.Due to pixel electrode
The voltage each applied with public electrode is different thus can produce vertical electric field, by the two electrode
Control to be applied to the electric field intensity of liquid crystal layer to control the absorbance of incident illumination, and then realize liquid crystal
The control that panel is bright Yu dark.
In the prior art, a kind of design of thin-film transistor array base-plate is to use PSA
(Polymer Sustained Alignment, polymer-stabilized alignment) technology, utilizes UV light line traffic control
The orientation of liquid crystal molecule processed, not only can save projection and slit, also can improve the deflection speed of liquid crystal molecule
Degree, can reach 4ms the soonest, improves pixel aperture ratio.Another design is to use TDE (Three
Dimensionally shaped pixel Electrode, the pixel electrode of 3D shape) technology, at glass
Form a gate insulator on substrate, above gate insulator, then form the protection of a patterning
Layer (patterned passivation layer), then pixel electrode layer is covered in this patterning protective layer.
Compared to PSA technology, when the gap (gap) of liquid crystal molecule is less, TDE technology still can be real
The highest penetrance.
Additionally, in the production process of liquid crystal display, some pixel cannot normally show, causes picture
The point defect of element.In general, point defect can be divided into bright spot and dim spot, in order to ensure liquid crystal panel
Display quality, generally will be carried out after completing the manufacturing process of array base palte and colored filter substrate
Completely black picture inspection and complete white picture inspection, to find the point defect of liquid crystal panel.Owing to human eye is to bright
Point is very sensitive and is easily recognized, and the most often watches for dull gray rank L0 and whether there is light leak now
As.In existing TDE processing procedure, when especially passivation layer forms predetermined pattern through dry etching process,
The pattern edge of patterned passivation layer and the angle of horizontal direction the most shallower (such as 70 degree), enter
And near this position, occur in that obvious L0 light leak condition.
In view of this, how to design the process scheme of a kind of new array base palte, or to existing battle array
Row basal plate making process improves, and to improve the L0 light leak condition of passivation layer pattern adjacent edges, is lifted into
Penetrate light transmittance, be the problem that person skilled is urgently to be resolved hurrily in the industry.
Summary of the invention
Manufacture method for array base palte of the prior art occurs near the pattern edge of passivation layer
The defects such as L0 light leak, the invention provides the manufacture method of a kind of array base palte.
According to one aspect of the present invention, it is provided that the manufacture method of a kind of array base palte, including following
Step:
Forming a first metal layer in the top of a substrate, described the first metal layer includes a grid；
Form a gate insulator patterned in the top of described substrate to cover described first metal
Layer, and form a metal oxide layer in the top of described gate insulator, described metal oxide layer
With described grid just to setting；
Form one second metal level in the top of described gate insulator, wherein said second metal level bag
Include a drain electrode and a source electrode, the conduct between described drain electrode and described source electrode of described metal oxide layer
One active layers；
Form a passivation layer in described gate insulator and the top of described second metal level；And
Form a transparency conducting layer in the top of described passivation layer.
An embodiment wherein, uses half light regulating hood (half-tone) mode to form described gate insulator
Layer and described metal oxide layer.
An embodiment wherein, the described gate insulator of above-mentioned formation and described metal oxide layer
Step also includes: use physical vapour deposition (PVD) (Physical Vapor Deposition, PVD) mode shape
Become a smooth metal oxide layer in the top of described gate insulator；It is coated with a photoresist layer in institute
State the top of metal oxide layer；Multiple through holes of formation one patterning are in described photoresist layer, with cruelly
Expose a part for this metal oxide layer；The partial metal oxide layer exposed is carried out for the first time
Wet etching, so that described metal oxide layer to carry out patterned process, thus it is exhausted to expose described grid
A part for edge layer；The part of grid pole insulating barrier exposed is carried out dry ecthing, and to described photoresist
Layer carries out ashing process；And the described metal oxide layer of patterning is carried out second time wet etching,
With remove in described metal oxide layer, be positioned at the other parts outside described grid area just above.
An embodiment wherein, described metal oxide layer is indium gallium zinc (IGZO) material.
An embodiment wherein, the pattern edge of described passivation layer is not less than with the angle of horizontal direction
70 degree.
An embodiment wherein, the pattern edge of described passivation layer and the angle of horizontal direction are 86
Degree.
An embodiment wherein, described passivation layer is silicon oxide, silicon oxynitride or silicon nitride material.
An embodiment wherein, described transparency conducting layer is tin indium oxide (ITO) material.
An embodiment wherein, described array base palte is suitable to a flat-panel display devices.
Use the manufacture method of the array base palte of the present invention, be initially formed the first metal layer in a substrate
Top, the gate insulator being subsequently formed patterning in the top of substrate and forms a metal oxide layer
In the top of gate insulator, then form the second metal level in the top of gate insulator, then shape
Become a passivation layer in gate insulator and the top of the second metal level, eventually form a transparency conducting layer in
The top of passivation layer.Compared to prior art, the present invention is by the metal-oxide of such as indium gallium zinc
Layer is as hard mask layer, and permeable hard mask layer forms the passivation layer with precipitous shape pattern edge,
And then improve L0 light leak condition, and promote the penetrance of incident illumination.
Accompanying drawing explanation
Reader is after the detailed description of the invention having read the present invention referring to the drawings, it will more clearly
Solve various aspects of the invention.Wherein,
Figure 1A and Figure 1B is shown respectively in a kind of array base palte processing procedure of prior art, uses photoresist
View before and after passivation layer is etched；
The decomposition of the manufacture method that Fig. 2 A to Fig. 2 F is shown respectively a kind of array base palte of prior art is shown
It is intended to；
The decomposition of the manufacture method that Fig. 3 A to Fig. 3 F is shown respectively another array base palte of prior art is shown
It is intended to；
Fig. 4 is shown according to the flow chart element of the manufacture method of the array base palte of one embodiment of the present invention
Figure；
Fig. 5 A to Fig. 5 E illustrates the decomposing schematic representation of the manufacture method of the array base palte of Fig. 4；And
What Fig. 6 A to Fig. 6 F was shown respectively in Fig. 5 B forms gate insulator and metal oxide layer
Decomposing schematic representation.
Detailed description of the invention
In order to make techniques disclosed in this application content more detailed and complete, can refer to accompanying drawing and basis
The following various specific embodiments of invention, labelling identical in accompanying drawing represents same or analogous assembly.
But, it will be understood by those within the art that, embodiment provided hereinafter is not used for
Limit the scope that the present invention is contained.Additionally, accompanying drawing is used only for schematically being illustrated, not
Draw according to its life size.
With reference to the accompanying drawings, the detailed description of the invention to various aspects of the present invention is made further to retouch in detail
State.
Figure 1A and Figure 1B is shown respectively in a kind of array base palte processing procedure of prior art, uses photoresist
View before and after passivation layer is etched.Wherein, Figure 1A is for utilizing photoresist 100 to blunt
Changing layer 102 and carry out the state before dry ecthing (dry etch), Figure 1B is for utilizing photoresist 100 right
Passivation layer 102 carries out the state after dry ecthing.
Figure 1A Yu Figure 1B contrast is understood, after dry ecthing, is positioned at the photoetching above passivation layer 102
A part (shown in dotted line) that glue 100 is etched, and the passivation layer below photoresist 100 is also
Being affected by etching, defining with horizontal direction angle at its pattern edge is the slope of a.Due to
For directly to contact between photoresist 100 with passivation layer 102, passivation layer 102 also can be etched one
Point, so that the slope at pattern edge is shallower.Such as, when angle corresponding to this slope is 70 degree,
Near the slit location of patterned passivation layer 102, when the thickness of passivation layer is 0.2um, it is right
1316 are drastically dropped to from 4220 than degree；When the thickness of passivation layer is 0.5um, its contrast from
4220 more drop to 625.Additionally, experimental data also indicates that, when the passivation layer of same thickness, when
When above-mentioned angle is 45 degree, the penetrance of incident illumination is only 0.145；When angle increases to 70 degree,
The penetrance of incident illumination also can slightly be promoted to 0.154, but still there will be dull gray rank L0 light leak
Situation.
The decomposition of the manufacture method that Fig. 2 A to Fig. 2 F is shown respectively a kind of array base palte of prior art is shown
It is intended to.
As shown in Figure 2 A, the first metal layer (first metal layer) 202 it is initially formed in substrate 200
Top, this first metal layer 202 includes a grid (gate electrode).As shown in Figure 2 B,
Gate insulator (gate is formed in the top of the top of the first metal layer 202 and substrate 200
Insulation layer) 204, and also it is logical that light need to be used to cover on formation one above the first metal layer 202
Hole (through hole).In fig. 2 c, the top in gate insulator 204 forms a non-crystalline silicon half
Conductor layer 206.In figure 2d, the second metal of patterning is formed in the top of gate insulator 204
Layer (second metal layer), this second metal level includes source electrode (source electrode) 208 Hes
Drain electrode (drain electrode) 210.As shown in Figure 2 E, the passivation layer (passivation of a patterning is formed
Layer) 212 in gate insulator 204 and the top of the second metal level.As shown in Figure 2 F, at pattern
The passivation layer surface changed and the passivation layer groove (groove) of correspondence are filled a transparency conducting layer 214.
From the foregoing, the source electrode 208 on the second metal level and the employing amorphous silicon semiconductor between 210 that drains
Layer is as active layers, when making with photoresist passivation layer to be etched, and its pattern edge and level side
To angle less, easily cause the bad situation of dull gray rank L0 light leak.
The decomposition of the manufacture method that Fig. 3 A to Fig. 3 F is shown respectively another array base palte of prior art is shown
It is intended to.
It is similar to Fig. 2 A～Fig. 2 F, in the processing procedure decomposing schematic representation of Fig. 3 A～Fig. 3 F, its main region
It is not, when forming amorphous silicon semiconductor layer 206 in figure 3b, it is not necessary to use extra light to cover on
The top of the first metal layer 202 forms through hole.In fig. 3d, at gate insulator 204 and the second gold medal
When belonging to the top formation passivation layer 212 of layer, just form the through hole above the first metal layer 202.No matter
How, still use non-crystalline silicon partly to lead due to the source electrode 208 on the second metal level and between drain electrode 210
Body layer is as active layers, when making to be etched passivation layer with photoresist, its pattern edge and level
The angle in direction is less, also easily causes the bad situation of dull gray rank L0 light leak.
Fig. 4 is shown according to the flow chart element of the manufacture method of the array base palte of one embodiment of the present invention
Figure.Fig. 5 A to Fig. 5 E illustrates the decomposing schematic representation of the manufacture method of the array base palte of Fig. 4.
With reference to Fig. 4 and combine Fig. 5 A～5E, step S11 is first carried out, forms the first metal layer 302
In the top of substrate 300, this first metal layer 302 includes a grid (such as Fig. 5 A).Then perform
Step S13, forms a gate insulator 304 patterned in the top of substrate 300 to cover first
Metal level 302, and form a metal oxide layer 306 in the top of gate insulator 304, this gold
Belong to oxide skin(coating) 304 with grid just to arranging (such as Fig. 5 B).Such as, half light regulating hood can be used
(half-tone) mode forms gate insulator 304 and metal oxide layer 306.It is preferred that metal
Oxide skin(coating) 306 is indium gallium zinc (IGZO) material.
Then, in step S15, form the second metal level in the top of gate insulator 304.The
Two metal levels include drain electrode 310 and a source electrode 308.Metal oxide layer 306 is positioned at drain electrode 310
And as an active layers (such as Fig. 5 C) between source electrode 308.Then perform step S17, form a passivation
Layer 312 is in the top (such as Fig. 5 D) of gate insulator 304 and the second metal level.Finally perform step
S19, forms a transparency conducting layer 314 in the top (such as Fig. 5 E) of passivation layer 312.It is preferred that it is blunt
Changing layer 312 is silicon oxide, silicon oxynitride or silicon nitride material.Transparency conducting layer 314 is tin indium oxide
(ITO) material.
What Fig. 6 A to Fig. 6 F was shown respectively in Fig. 5 B forms gate insulator and metal oxide layer
Decomposing schematic representation.
With reference to Fig. 6 A, after forming gate insulator 304, use physical vapour deposition (PVD) (Physical
Vapor Deposition, PVD) mode forms a smooth metal oxide layer 306 in gate insulator
The top of layer 304.Then, be coated with a photoresist layer 316 in metal oxide layer 306 top (as
Fig. 6 B).The most in figure 6 c, multiple through holes (through hole) of a patterning are formed in photoetching
Glue-line 316, to expose a part for this metal oxide layer 306.The most in figure 6d, to cruelly
The partial metal oxide layer 306 exposed carries out wet etching (first wet etch) for the first time, with to gold
Belong to oxide skin(coating) 306 and carry out patterned process, thus expose a part for gate insulator 304.
In Fig. 6 E, the part of grid pole insulating barrier 304 exposed is carried out dry ecthing (dry etch), and right
Photoresist layer 316 carries out ashing process (ash process).Such as Fig. 6 F, the burning to patterning
Nitride layer 306 carries out second time wet etching (second wet etch), with removing metao oxide layer 306
In the other parts being positioned at outside grid area just above.
From the foregoing, compared to prior art, the present invention is by the burning of such as indium gallium zinc
Nitride layer 306 is as hard mask layer, when using photoresist layer to be etched, can pass through hard mask layer
Form the passivation layer with precipitous shape pattern edge, and then improve L0 light leak condition, and promote incidence
The penetrance of light.Experimental data shows, when this angle is 45 degree, the penetrance of incident illumination is 0.145；
When this angle is 70 degree, the penetrance of incident illumination is 0.154；And when this angle is 86 degree, enter
The penetrance penetrating light is increased to 0.182, and the amplitude of lifting is (0.182-0.154)/0.154, and i.e. 18.18%.
Use the manufacture method of the array base palte of the present invention, be initially formed the first metal layer in a substrate
Top, the gate insulator being subsequently formed patterning in the top of substrate and forms a metal oxide layer
In the top of gate insulator, then form the second metal level in the top of gate insulator, then shape
Become a passivation layer in gate insulator and the top of the second metal level, eventually form a transparency conducting layer in
The top of passivation layer.Compared to prior art, the present invention is by the metal-oxide of such as indium gallium zinc
Layer is as hard mask layer, and permeable hard mask layer forms the passivation layer with precipitous shape pattern edge,
And then improve L0 light leak condition, and promote the penetrance of incident illumination.
Above, the detailed description of the invention of the present invention is described with reference to the accompanying drawings.But, in this area
Those of ordinary skill is it is understood that in the case of without departing from the spirit and scope of the present invention, it is also possible to
The detailed description of the invention of the present invention is made various change and replacement.These changes and replacement all fall at this
In bright claims limited range.
Claims (9)
1. the manufacture method of an array base palte, it is characterised in that this manufacture method comprises the following steps:
Forming a first metal layer in the top of a substrate, described the first metal layer includes a grid；
Form a gate insulator patterned in the top of described substrate to cover described first metal
Layer, and form a metal oxide layer in the top of described gate insulator, described metal oxide layer
With described grid just to setting；
Form one second metal level in the top of described gate insulator, wherein said second metal level bag
Include a drain electrode and a source electrode, the conduct between described drain electrode and described source electrode of described metal oxide layer
One active layers；
Form a passivation layer in described gate insulator and the top of described second metal level；And
Form a transparency conducting layer in the top of described passivation layer.
The manufacture method of array base palte the most according to claim 1, it is characterised in that use half
Light regulating hood mode forms described gate insulator and described metal oxide layer.
The manufacture method of array base palte the most according to claim 2, it is characterised in that above-mentioned shape
The step becoming described gate insulator and described metal oxide layer also includes:
Physical vapour deposition (PVD) mode is used to form a smooth metal oxide layer in described gate insulator
Top；
It is coated with a photoresist layer in the top of described metal oxide layer；
Multiple through holes of formation one patterning are in described photoresist layer, to expose this metal oxide layer
A part；
The partial metal oxide layer exposed is carried out wet etching for the first time, with to described burning
Nitride layer carries out patterned process, thus exposes a part for described gate insulator；
The part of grid pole insulating barrier exposed is carried out dry ecthing, and described photoresist layer is ashed
Process；And
The described metal oxide layer of patterning is carried out second time wet etching, to remove described metal oxygen
In compound layer, be positioned at the other parts outside described grid area just above.
The manufacture method of array base palte the most according to claim 1, it is characterised in that described gold
Belonging to oxide skin(coating) is indium gallium zinc material.
The manufacture method of array base palte the most according to claim 1, it is characterised in that described blunt
Change the pattern edge of layer with the angle of horizontal direction not less than 70 degree.
The manufacture method of array base palte the most according to claim 5, it is characterised in that described blunt
Changing the pattern edge of layer with the angle of horizontal direction is 86 degree.
The manufacture method of array base palte the most according to claim 1, it is characterised in that described blunt
Change layer is silicon oxide, silicon oxynitride or silicon nitride material.
The manufacture method of array base palte the most according to claim 1, it is characterised in that described
Bright conductive layer is tin indium oxide material.
The manufacture method of array base palte the most according to claim 1, it is characterised in that described battle array
Row substrate is suitable to a flat-panel display devices.
Priority Applications (1)
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108594550A (en) * | 2018-04-25 | 2018-09-28 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and preparation method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108594550A (en) * | 2018-04-25 | 2018-09-28 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and preparation method thereof |
| CN108594550B (en) * | 2018-04-25 | 2020-07-28 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and manufacturing method thereof |
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