CN105845663A - Semiconductor device, manufacturing method therefor, and electronic device - Google Patents
Semiconductor device, manufacturing method therefor, and electronic device Download PDFInfo
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- CN105845663A CN105845663A CN201510014320.7A CN201510014320A CN105845663A CN 105845663 A CN105845663 A CN 105845663A CN 201510014320 A CN201510014320 A CN 201510014320A CN 105845663 A CN105845663 A CN 105845663A
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Abstract
The invention provides a semiconductor device, a manufacturing method therefor, and an electronic device. The semiconductor device comprises a first substrate which comprises a first metal interconnection structure and a first bonding layer; a second substrate which comprises a second metal interconnection structure, a protection layer and a silicon through hole located at one side of the second metal interconnection structure, and also comprises insulating layers located on a side wall of the silicon through hole and at the bottom, diffusion blocking layers on the insulating layers, metal interconnection layers on the surfaces of the diffusion blocking layers, and a second bonding layer on the protection layer on the front surface of the second substrate, wherein the total thickness of the insulating layers, the diffusion blocking layers and the metal interconnection layers is less than the radius of the silicon through hole. The surface of the second bonding layer on the front surface of the second substrate is bonded with the surface of the first bonding layer of the first substrate, and a gap is formed in the silicon through hole. The semiconductor device provided by the invention is good in heat dissipation performance, and guarantees the conductivity of the silicon through hole.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor device and
Manufacture method and electronic installation.
Background technology
For adapting to the requirement of integrated circuit high density, compact, chip-stacked technology has become as collection
Become the trend of circuit development.The components and parts manufactured by 3D encapsulation technology, high packing density exists
While the power density making device improves, the heat that encapsulation unit volume accommodates will necessarily be caused
Amount increases.Generally, Joule heat the high temperature caused often is substantially reduced integrated circuit
Performance/the reliability of device.The operating temperature of device raises, and crash rate also can increase.Do not conform to
The thermal design of reason will induce a series of integrity problem, and as there is hot-spot, temperature is divided
Cloth is unequal.Therefore, use 3D encapsulation technology to manufacture components and parts, be necessary for thinking better of envelope
The heat dissipation problem of dress body.
Prior art discloses a kind of air duct interconnection structure for 3-D encapsulation, it is proposed that
A kind of method increasing air duct interconnection structure in chip stack structure, by packaging body
Heat remove from chip internal.But this method has the drawback that air duct is not led
Electricity, can significantly reduce the RC delay performance of interconnection structure.
Therefore, it is necessary to propose a kind of new structure and manufacture method, to solve prior art
Not enough.
Summary of the invention
Introducing the concept of a series of reduced form in Summary, this will be concrete real
Execute in mode part and further describe.The Summary of the present invention is not meant to
Attempt to limit key feature and the essential features of technical scheme required for protection, less
Mean the protection domain attempting to determine technical scheme required for protection.
In order to overcome the problem that presently, there are, one embodiment of the invention provides a kind of quasiconductor
Device, it is characterised in that including:
First substrate, is positioned at first metal interconnection structure on described first substrate surface, is positioned at institute
State first bonded layer on first substrate surface, and described first bonded layer exposes part described
One metal interconnection structure；
Second substrate, described second substrate includes the second gold medal being positioned at the front of described second substrate
Belong to interconnection structure, be positioned at the protective layer in described second substrate front, and described protective layer exposed portion
Divide described second metal interconnection structure, be positioned at described second substrate front, and be positioned at the second metal
The silicon through hole of interconnection structure side, also includes the insulation being positioned at described through-silicon via sidewall and bottom
Layer, and
The second metal interconnection structure of exposing described in being positioned at, the front of the described second substrate of part
With the diffusion impervious layer on described insulating barrier, it is positioned at the metal interconnection on described diffusion impervious layer surface
Layer, and it is positioned at the second bonded layer on the protective layer in described second substrate front, described second
Bonded layer exposes and is positioned at the metal interconnecting layer on described second substrate surface, wherein, described insulation
Layer, diffusion impervious layer, the gross thickness of metal interconnecting layer are less than the radius of described silicon through hole；
The second bonded layer surface in described second substrate front and the first key of described first substrate
Closing layer surface to be bonded mutually, described silicon through hole is relative with described first metal interconnection structure exposed
Should, described metal interconnecting layer links mutually with described first metal interconnection structure and the second metal respectively
Structure is electrically connected, and is formed with space in described silicon through hole.
Further, the material of described metal interconnecting layer is tungsten or aluminum or copper.
Further, being formed with the first semiconductor device in described first substrate, described the first half lead
Body device is electrically connected with described first metal interconnection structure.
Further, being formed with the second semiconductor device in described second substrate, described the second half lead
Body device is electrically connected with described second metal interconnection structure.
Further, the metal interconnecting layer in described second bonded layer also covers described silicon through hole.
Further, in described insulating barrier, diffusion impervious layer, metal interconnecting layer and described silicon through hole
The gross thickness of the second bonded layer less than the radius of described silicon through hole.
Further, the second bonded layer in described silicon through hole, metal interconnecting layer, diffusion impervious layer
It is less than 2 μm with the gross thickness of insulating barrier.
Further, the diameter range of described silicon through hole is 5～15 μm.
Another embodiment of the present invention provides the manufacture method of a kind of semiconductor device, including:
Offer first substrate and second substrate, wherein,
Described first substrate part surface is formed the first metal interconnection structure, and is formed
At first bonded layer on described first substrate surface, and described first bonded layer exposes part institute
State the first metal interconnection structure, and
It is formed with the second metal interconnection structure in described second substrate front, and covers described
The protective layer of two metal interconnection structures；
The front of described protective layer and part second substrate is performed etching formation silicon through hole；
Insulating barrier is formed in sidewall and the bottom of described silicon through hole；
Thinning described protective layer, until the second metal interconnection structure surface described in expose portion；
At described insulating barrier, the described protective layer of part and the second metal interconnection structure table exposed
Face forms diffusion impervious layer；
Described diffusion impervious layer surface is formed metal interconnecting layer, wherein said insulating barrier, expansion
Scattered barrier layer, the gross thickness of metal interconnecting layer are less than the radius of described silicon through hole；
Described protective layer forms the second bonded layer, the end face of described second bonded layer with
The end face of described metal interconnecting layer flushes；
The first bonded layer by the second bonded layer on described second substrate Yu described first substrate
It is bonded, and makes the surface of the metal interconnecting layer of described exposure link mutually with described first metal
Structure is corresponding, forms space in described silicon through hole.
Further, described second bonded layer also covers the metal interconnecting layer in described silicon through hole, its
In, the second key in described insulating barrier, diffusion impervious layer, metal interconnecting layer and described silicon through hole
Close the gross thickness radius less than described silicon through hole of layer.
Further, deep reaction ion etching technique or Bosch technique is used to form described silicon through hole.
Further, the method forming described second bonded layer comprises the following steps:
Formation of deposits second on the surface of described metal interconnecting layer and the protective layer of described exposure
Bonding material layer；
Perform cmp step, until the surface of metal interconnecting layer described in expose portion.
Further, the material of described first bonded layer and described second bonded layer is silicon oxide.
Further, described bonding technology is the melted bonding of silicon oxide.
Further, the formation process of described metal interconnecting layer includes that sputtering, plasma substrate are regulated the flow of vital energy
Deposition, high density plasma CVD, low-pressure chemical vapor deposition or atomic layer mutually
Deposition.
Further, being formed with the first semiconductor device in described first substrate, described the first half lead
Body device is electrically connected with described first metal interconnection structure；It is formed with in described second substrate
Two semiconductor device, described second semiconductor device is with described second metal interconnection structure electricity even
Connect.
Further, the method for thinning described protective layer is cmp or lithographic method.
The embodiment of the present invention three provides a kind of electronic installation, including aforesaid semiconductor device.
In sum, according to the manufacture method of the present invention, formed between the substrate of two bondings
Having the silicon through hole in space, this space can utilize air will to produce in Semiconductor substrate in device
Heat pass, improve the heat dispersion of device, silicon through hole also can be by bonding simultaneously
The metal interconnection structure of substrate is electrically connected, it is ensured that its electric conductivity.
Accompanying drawing explanation
The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention.Attached
Figure shows embodiments of the invention and description thereof, is used for explaining the principle of the present invention.
In accompanying drawing:
Figure 1A-Fig. 1 I shows that the manufacture method of semiconductor device according to the invention is real successively
Execute the generalized section of obtained device；
Fig. 2 shows the work that the manufacture method of semiconductor device according to the invention is implemented successively
Process flow figure.
Detailed description of the invention
In the following description, a large amount of concrete details is given to provide to the present invention more
Understand thoroughly.It is, however, obvious to a person skilled in the art that the present invention
Can be carried out without these details one or more.In other example, in order to keep away
Exempt to obscure with the present invention, technical characteristics more well known in the art are not described.
It should be appreciated that the present invention can implement in different forms, and it is not construed as office
It is limited to embodiments presented herein.On the contrary, it is open thoroughly with complete to provide these embodiments to make
Entirely, and will fully convey the scope of the invention to those skilled in the art.In the accompanying drawings,
In order to clear, the size in Ceng He district and relative size may be exaggerated.The most identical attached
Figure labelling represents identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... adjacent ", " connect
To " or " being coupled to " other element or during layer, its can directly on other element or layer,
Adjacent thereto, be connected or coupled to other element or layer, or can exist element between two parties or
Layer.On the contrary, when element be referred to as " directly exist ... on ", " with ... direct neighbor ", " directly connect
Receive " or " being directly coupled to " other element or during layer, the most there is not element between two parties or layer.
Although it should be understood that and term first, second, third, etc. can being used to describe various element, portion
Part, district, floor and/or part, these elements, parts, district, floor and/or part the most should be by
These terms limit.These terms are used merely to distinguish an element, parts, district, floor or portion
Divide and another element, parts, district, floor or part.Therefore, without departing from present invention teach that
Under, the first element discussed below, parts, district, floor or part be represented by the second element,
Parts, district, floor or part.
Spatial relationship term such as " ... under ", " ... below ", " following ", " ...
Under ", " ... on ", " above " etc., here can describe for convenience and be used
Thus shown in figure a element or feature and other element or the relation of feature are described.Should
Understanding, in addition to the orientation shown in figure, spatial relationship term is intended to also include using and grasping
The different orientation of the device in work.Such as, if the device upset in accompanying drawing, then, describe
To take for " below other element " or " under it " or " under it " element or feature
To for other element or feature " on ".Therefore, exemplary term " ... below " and " ...
Under " upper and lower two orientations can be included.Device can additionally be orientated (90-degree rotation or other
Orientation) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as this
Bright restriction.When using at this, " ", " " and " described/to be somebody's turn to do " of singulative
It is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " forms " and/or " including ", when using in this specification, determine described feature,
The existence of integer, step, operation, element and/or parts, but be not excluded for one or more its
The existence of its feature, integer, step, operation, element, parts and/or group or interpolation.
When using at this, term "and/or" includes any and all combination of relevant Listed Items.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description
Suddenly, in order to the technical scheme that the explaination present invention proposes.Presently preferred embodiments of the present invention describes in detail
As follows, but in addition to these describe in detail, the present invention can also have other embodiments.
Embodiment one
Next, with reference to Figure 1A-Fig. 1 I and Fig. 2 making side to the semiconductor device of the present invention
Method is described in detail.
First, with reference to Fig. 1 H, it is provided that first substrate 10, have in described first substrate 10
First semiconductor device 101, is formed with the first gold medal on described first substrate 10 part surface
Genus interconnection structure 104, and it is formed at first bonded layer 103 on described first substrate 10 surface,
And described first bonded layer 103 exposes described first metal interconnection structure 104 of part.
Described first substrate 10 includes the first Semiconductor substrate 100, is positioned at the first quasiconductor lining
The first semiconductor device 101 at the end 100, cover described first semiconductor device 101,
The interlayer dielectric layer (not shown) on semi-conductive substrate 100 surface, is positioned at described interlayer dielectric
Interconnection structure 102 in Ceng.
Exemplarily, described first Semiconductor substrate 100 can be silicon substrate, germanium substrate, absolutely
One in silicon substrate, glass substrate on edge body, in the present embodiment, described first quasiconductor lining
The end 100 is silicon substrate.Described first semiconductor device 101 can be MOS transistor, two
One or more in pole pipe, memorizer, electric capacity, resistance, inductance.In the present embodiment, with
One MOS transistor carries out exemplary theory as the first semiconductor device 101 to the present invention
Bright.
Described interlayer dielectric layer includes one or more layers dielectric layer, one or more layers dielectric layer described
Inside having interconnection structure 102, described interconnection structure 102 includes metal level and is positioned at adjacent metal
Conductive plunger between Ceng, utilizes described interconnection structure 102 by described first semiconductor device
101 are electrically connected with the first metal interconnection structure 104.
Described first metal interconnection structure 104 can only include metal interconnecting layer, it is also possible to for gold
Belong to the combination of interconnection layer and conductive plunger.The material of described first metal interconnection structure 104 is permissible
Any applicable metal material being well known to those skilled in the art, such as copper, aluminum, tungsten etc..
In the present embodiment, described first metal interconnection structure 104 only includes layer of metal interconnection layer, institute
State the first metal interconnection structure 104 to be electrically connected with interconnection structure 102.
The material of described first bonded layer 104 is silicon oxide, silicon nitride or silicon oxynitride etc., institute
State the first bonded layer 104 for protecting the first metal interconnection structure 104 to exempt from interfered by outside.
In the present embodiment, the material of described first bonded layer 104 is silicon oxide.For follow-up needs
It is bonded with second substrate on the first bonded layer 104 surface, when employing Direct Bonding technique will
When described first bonded layer 104 surface is bonded with second substrate, due to the key of second substrate
The material in conjunction face mostly is silicon oxide, therefore, can realize silicon oxide-silicon oxide bonding, and technique becomes
Ripe, cost can be reduced.
With reference to Figure 1A, it is provided that second substrate 20, in described second substrate 20, it is formed with second
Semiconductor device 201, is formed with the second metal interconnection structure in described second substrate 20 front
203, described second metal interconnection structure 203 is with described second semiconductor device 201 electricity even
Connect, be formed with the guarantor covering described second metal interconnection structure 203 in second substrate 20 front
Sheath.
Further, described second substrate 20 also includes the second Semiconductor substrate 200, is positioned at
Second semiconductor device 201 on the second Semiconductor substrate 200 surface, covers described the second half and leads
The interlayer dielectric layer 202 on body device the 201, second Semiconductor substrate 200 surface, is positioned at described
Part the second metal interconnection structure 203 in interlayer dielectric layer 202.
Exemplarily, described second Semiconductor substrate 200 can be silicon substrate, germanium substrate, absolutely
One in silicon substrate, glass substrate on edge body, in the present embodiment, described second quasiconductor lining
The end 200 is silicon substrate.Described second semiconductor device 201 can be MOS transistor, two
One or more in pole pipe, memorizer, electric capacity, resistance, inductance.In the present embodiment, with
One MOS transistor carries out exemplary theory as the second semiconductor device 201 to the present invention
Bright.
Described interlayer dielectric layer 202 includes that one or more layers dielectric layer, described one or more layers are situated between
There is in matter layer part the second metal interconnection structure 203, described second metal interconnection structure 203
Including metal level and the conductive plunger between adjacent metal, the second metal is utilized to link mutually
Structure 203 is by described second semiconductor device 201 and the metal interconnecting layer electricity in silicon through hole afterwards
Learn and connect.
Exemplarily, part second metal interconnection structure 203 in described second substrate front it is positioned at
Metal interconnecting layer can be only included, it is also possible to for the combination of metal interconnecting layer Yu conductive plunger.Institute
That states that the material of the second metal interconnection structure 203 can be well known to those skilled in the art is any
The metal material being suitable for, such as copper, aluminum, tungsten etc..In the present embodiment, the second metal links mutually
Structure 203 is electrically connected with the metal interconnecting layer formed in silicon through hole afterwards.
The material of described protective layer 204 is silicon oxide, silicon nitride or silicon oxynitride etc., described guarantor
Sheath 204 is exempted from interfered by outside for protection the second metal interconnection structure 203.In this enforcement
In example, the material of described protective layer 204 is silicon oxide.
With reference to Figure 1B, the front of described protective layer 204 and part second substrate 20 is carved
Erosion forms silicon through hole 205.
In the present embodiment, utilize deep reaction ion etching (DRIE) technique to described protective layer
204 and part second substrate 20 perform etching, formed silicon through hole 205, described silicon through hole 205
Diameter range be 5 μm～15 μm.Described etching stopping in described second substrate 20,
Do not run through whole second substrate 20.
In other examples, the technique forming described silicon through hole can also be any applicable for other
Technique, such as Bosch (Bosch) technique etc..
With reference to Fig. 1 C, at the sidewall of described silicon through hole 205 and bottom and protective layer 204
Surface forms insulating barrier 206.
Exemplarily, the material of described insulating barrier 206 is silicon oxide, forms described insulating barrier
The method of 206 can be plasma enhanced chemical vapor deposition, low-pressure chemical vapor deposition work
Skill, high density plasma CVD technique etc., owing to above-mentioned depositing operation has relatively
Good Step Coverage ability, can form insulating barrier in the silicon through hole of bigger depth-to-width ratio.
With reference to Fig. 1 D, thinning described protective layer 204, until the second metal described in expose portion
Interconnection structure 203 surface；
It is preferred that the method for thinning described protective layer can be cmp or etching side
Method.In one example, by etching technics, be first pointed on protective layer 204 surface is exhausted
Edge layer 206 performs etching, and is etching described protective layer 204, until described in expose portion second
The surface of metal interconnection structure 203.
In other examples, it is possible to the method using cmp, it is achieved remove and be positioned at guarantor
Insulating barrier 206 on sheath 204, and protective layer 204 is carried out thinning, until expose portion
The surface of described second metal interconnection structure 203.
Through above-mentioned steps, only sidewall and bottom at silicon through hole 205 is also made to be formed with insulation
Layer 206.
With reference to Fig. 1 E, described insulating barrier 206, described protective layer 204 and expose second
Metal interconnection structure 204 surface forms diffusion impervious layer 207, at described diffusion impervious layer 207
On surface formed metal interconnecting layer 208, wherein said insulating barrier 206, diffusion impervious layer 207,
The gross thickness of metal interconnecting layer 208 is less than the radius of described silicon through hole 205.
Diffusion impervious layer 207 may be a silicon-containing layer, one carbon-containing bed a, nitrogenous layer, one contain
Hydrogen layer or a metal or metal compound layer.The material of metal or metal compound layer such as tantalum,
Tantalum nitride, titanium, titanium nitride, zirconium nitride, titanium nitride zirconium, tungsten, tungsten nitride, its alloy or its
Constituent.Diffusion impervious layer 207 is coated with by such as physical vapour deposition (PVD), ald, rotation
The processing procedure of cloth (spin-on) deposition or other proper method is formed.Diffusion impervious layer 207 can be in
Between the temperature of-40～400 DEG C and about formation under the pressure of 0.1～100 millitorrs (mTorr).
Additionally, diffusion impervious layer 207 also potentially includes multiple film layer.Described diffusion impervious layer 207 is used
During after preventing, the metal in the metal interconnecting layer in silicon through hole is diffused into second substrate 20.
The material of metal interconnecting layer 208 can be tungsten or the metal material such as aluminum or copper, can be by low
Pressure chemical vapor deposition (LPCVD), plasma auxiliary chemical vapor deposition (PECVD), gold
Belong to the heavy of organic chemical vapor deposition (MOCVD) and ald (ALD) or other advanced person
Long-pending technology is formed.It is preferred that the material of metal interconnecting layer 208 is tungsten material.
In the present embodiment, metal interconnecting layer 208 is partially filled with described silicon through hole 205, so that
Described insulating barrier 206, diffusion impervious layer 207, the gross thickness of metal interconnecting layer 208 are less than institute
State the radius of silicon through hole 205, in silicon through hole, leave space.
With reference to Fig. 1 F, remove part diffusion impervious layer 207 and metal interconnecting layer 208, exposed portion
Divide the surface of described protective layer 204.Any method well known to those skilled in the art can be used to enter
The described removal technique of row, such as dry etching or wet etching etc..
With reference to Fig. 1 G, the surface of described protective layer and described metal interconnecting layer 208 is formed
Second bonded layer 209.
The material of described second bonded layer 209 is silicon oxide, silicon nitride or silicon oxynitride etc., position
Described second bonded layer 209 in through hole is for protecting metal interconnecting layer 208 from the external world
Interference, the bonding after simultaneously can be additionally used in.In the present embodiment, described second bonded layer
The material of 209 is silicon oxide.
Afterwards, carry out cmp, until exposing the surface of described metal interconnecting layer 208,
To form smooth the second bonded layer 209, the metal interconnecting layer 208 of exposure after bonding with
First metal interconnection structure 103 realizes being electrically connected.
Control the second bonded layer 209 in described silicon through hole 205, metal interconnecting layer 208, expand
Dissipate the gross thickness radius less than silicon through hole 205 of barrier layer 207 and insulating barrier 206, so that
All the time space is remained with in through hole 205.It is preferred that the second key controlled in described silicon through hole
Close the gross thickness of layer, metal interconnecting layer, diffusion impervious layer and insulating barrier less than 2 μm.
With reference to Fig. 1 I, by the second bonded layer 209 on described second substrate 20 with described first
First bonded layer 104 of substrate 10 is bonded, and makes the metal interconnecting layer 208 of described exposure
Surface corresponding with described first metal interconnection structure 103, in described silicon through hole formed sky
Gap.
In the present embodiment, with the material of described first bonded layer 104 as silicon oxide, described second
The material of bonded layer 209 is silicon oxide, is bonded.Alternatively, described bonding technology is oxygen
The melted bonding of SiClx.Said method is only exemplarily, it is also possible to according to bonding pattern reasonably
Select the first bonded layer and the material of the second bonded layer.
After above-mentioned bonding steps, in the silicon through hole between first substrate 10 and second substrate 20
Defining space, this space can utilize the heat that air will produce in Semiconductor substrate in device
Passing, the metal interconnecting layer 208 being simultaneously used for silicon through-hole surfaces links mutually with the first metal
Structure and the second metal interconnection structure are all electrically connected, and the most also can well ensure leading of silicon through hole
Electrical property.
It is also with backgrind technique afterwards and the back side of described second substrate is carried out thinning, directly
Bottom surface to exposing metal interconnection layer.
The manufacture method proposed by the present invention again, also can be bonded multiple present invention of comprising successively and carry
The substrate of the silicon through hole gone out, to realize the encapsulation to multiple substrates.Utilize multiple with space
While silicon through hole realizes dispelling the heat Semiconductor substrate, also can take into account the electric conductivity of silicon through hole.
In sum, according to the manufacture method of the present invention, formed between the substrate of two bondings
Having the silicon through hole in space, this space can utilize air will to produce in Semiconductor substrate in device
Heat pass, improve the heat dispersion of device, silicon through hole also can be by bonding simultaneously
The metal interconnection structure of substrate is electrically connected, it is ensured that its electric conductivity.
With reference to Fig. 2, it is shown that the work of the step that one detailed description of the invention of the present invention is implemented successively
Process flow figure, for schematically illustrating the flow process of whole manufacturing process.
In step 201, it is provided that first substrate and second substrate, in described first substrate part
It is formed with the first metal interconnection structure on surface, and is formed at the of described first substrate surface
One bonded layer, and it is formed with the second metal interconnection structure in described second substrate front, cover
The protective layer of described second metal interconnection structure；
In step 202., the front of described protective layer and part second substrate is performed etching shape
Become silicon through hole；
In step 203, insulating barrier is formed on sidewall and bottom at described silicon through hole；
In step 204, thinning described protective layer, until the second metal described in expose portion is mutual
Even body structure surface；
In step 205, described insulating barrier, the described protective layer of part and expose second
Metal interconnection structure surface forms diffusion impervious layer；
In step 206, described diffusion impervious layer surface forms metal interconnecting layer, wherein
Described insulating barrier, diffusion impervious layer, the gross thickness of metal interconnecting layer are less than the half of described silicon through hole
Footpath；
In step 207, described protective layer forms the second bonded layer, described second
The end face of bonded layer flushes with the end face of described metal interconnecting layer；
In a step 208, by the second bonded layer on described second substrate and described first substrate
The first bonded layer be bonded, and make the surface and described the of the metal interconnecting layer of described exposure
One metal interconnection structure is corresponding, forms space in described silicon through hole.
Embodiment two
Below, with reference to Fig. 1 I, the structure of the semiconductor device that the present invention proposes is carried out specifically
Bright.
With reference to Fig. 1 I, described semiconductor device includes: first substrate 10, is positioned at described first
First metal interconnection structure 103 on substrate 10 surface, is positioned at described first substrate 10 surface
First bonded layer 104, and described first bonded layer 104 to expose described first metal of part mutual
Link structure 103.
Described first substrate 10 also includes the first Semiconductor substrate 100, is positioned at the first quasiconductor
The first semiconductor device 101 on substrate 100, cover described first semiconductor device 101,
The interlayer dielectric layer (not shown) on the first Semiconductor substrate 100 surface, is positioned at described interlayer and is situated between
Interconnection structure 102 in electric layer.
Exemplarily, described first Semiconductor substrate 100 can be silicon substrate, germanium substrate, absolutely
One in silicon substrate, glass substrate on edge body, in the present embodiment, described first quasiconductor lining
The end 100 is silicon substrate.Described first semiconductor device 101 can be MOS transistor, two
One or more in pole pipe, memorizer, electric capacity, resistance, inductance.In the present embodiment, with
One MOS transistor carries out exemplary theory as the first semiconductor device 101 to the present invention
Bright.
Described interlayer dielectric layer includes one or more layers dielectric layer, one or more layers dielectric layer described
Inside having interconnection structure 102, described interconnection structure 102 includes metal level and is positioned at adjacent metal
Conductive plunger between Ceng, utilizes described interconnection structure 102 by described first semiconductor device
101 are electrically connected with the first metal interconnection structure 104.
Described first metal interconnection structure 104 can only include metal interconnecting layer, it is also possible to for gold
Belong to the combination of interconnection layer and conductive plunger.The material of described first metal interconnection structure 104 is permissible
Any applicable metal material being well known to those skilled in the art, such as copper, aluminum, tungsten etc..
In the present embodiment, described first metal interconnection structure 104 only includes layer of metal interconnection layer, institute
State the first metal interconnection structure 104 to be electrically connected with interconnection structure 102.
The material of described first bonded layer 104 is silicon oxide, silicon nitride or silicon oxynitride etc., institute
State the first bonded layer 104 for protecting the first metal interconnection structure 104 to exempt from interfered by outside.
In the present embodiment, the material of described first bonded layer 104 is silicon oxide.Described first bonding
The medium that layer 104 is also bonded with second substrate 20 as described first substrate 10.
Described semiconductor device also includes that second substrate 20, described second substrate 20 include being positioned at
Second metal interconnection structure 203 in described second substrate 20 front, is positioned at described second substrate
The protective layer 204 in 20 fronts, and the second metal interconnection described in described protective layer 204 expose portion
Structure 203, is positioned at described second substrate 20 front, and is positioned at the second metal interconnection structure 203
The silicon through hole 205 of side, the diameter range of described silicon through hole is 5～15 μm.
Further, described second substrate 20 also includes the second Semiconductor substrate 200, is positioned at
Second semiconductor device 201 on the second Semiconductor substrate 200 surface, covers described the second half and leads
The interlayer dielectric layer 202 on body device the 201, second Semiconductor substrate 200 surface, is positioned at described
Part the second metal interconnection structure 203 in interlayer dielectric layer 202.
Exemplarily, described second Semiconductor substrate 200 can be silicon substrate, germanium substrate, absolutely
One in silicon substrate, glass substrate on edge body, in the present embodiment, described second quasiconductor lining
The end 200 is silicon substrate.Described second semiconductor device 201 can be MOS transistor, two
One or more in pole pipe, memorizer, electric capacity, resistance, inductance.In the present embodiment, with
One MOS transistor carries out exemplary theory as the second semiconductor device 201 to the present invention
Bright.
Described interlayer dielectric layer 202 includes that one or more layers dielectric layer, described one or more layers are situated between
There is in matter layer part the second metal interconnection structure 203, described second metal interconnection structure 203
Including metal level and the conductive plunger between adjacent metal, the second metal is utilized to link mutually
Structure 203 is by described second semiconductor device 201 and the metal interconnecting layer 208 in silicon through hole 205
It is electrically connected.
Exemplarily, part second metal interconnection structure 203 in described second substrate front it is positioned at
Metal interconnecting layer can be only included, it is also possible to for the combination of metal interconnecting layer Yu conductive plunger.Institute
That states that the material of the second metal interconnection structure 203 can be well known to those skilled in the art is any
The metal material being suitable for, such as copper, aluminum, tungsten etc..In the present embodiment, the second metal links mutually
Structure 203 is electrically connected with the metal interconnecting layer formed in silicon through hole afterwards.
Also include the insulating barrier 206 being positioned at described silicon through hole 205 sidewall and lower surface, be positioned at
Described expose the second metal interconnection structure 203, the front of the described second substrate of part 20
With the diffusion impervious layer 207 on described insulating barrier 206；It is positioned at described diffusion impervious layer 207 table
The metal interconnecting layer 208 in face, and it is positioned at the protective layer 204 in described second substrate 20 front
On the second bonded layer 209, described second bonded layer 209 exposes described metal interconnecting layer 208
End face.Alternatively, described insulating barrier 206, diffusion impervious layer 207, metal interconnecting layer 208
Gross thickness less than the radius of described silicon through hole 205.Namely in described silicon through hole 205, there is sky
Gap.
The material of described insulating barrier 206 is silicon oxide, and the method forming described insulating barrier 206 can
Think plasma enhanced chemical vapor deposition, low-pressure chemical vapor deposition process, high density etc.
Gas ions chemical vapor deposition method etc..
Diffusion impervious layer 207 may be a silicon-containing layer, one carbon-containing bed a, nitrogenous layer, hydrogeneous
Layer or a metal or metal compound layer.The material of metal or metal compound layer such as tantalum, nitrogen
Change tantalum, titanium, titanium nitride, zirconium nitride, titanium nitride zirconium, tungsten, tungsten nitride, its alloy or its group
Become thing.Exemplarily, the material of described metal interconnecting layer is tungsten or aluminum or copper.
In one example, described second bonded layer 209 also covers in described silicon through hole 205
Metal interconnecting layer 208.Described insulating barrier, diffusion impervious layer, metal interconnecting layer and described silicon are logical
The gross thickness of the second bonded layer in hole is less than the radius of described silicon through hole.It is preferred that described silicon
The gross thickness of the second bonded layer, metal interconnecting layer, diffusion impervious layer and insulating barrier in through hole is little
In 2 μm.
Alternatively, the material of described second bonded layer 209 is silicon oxide, silicon nitride or nitrogen oxidation
Silicon etc..
With continued reference to Fig. 1 I, second bonded layer 209 surface in described second substrate 20 front with
First bonded layer 104 surface of described first substrate 10 is bonded mutually, described silicon through hole 205 with
The first metal interconnection structure 103 exposed is corresponding, is formed free in described silicon through hole
Gap, described metal interconnecting layer 208 respectively with described first metal interconnection structure 103 and the second gold medal
Belong to interconnection structure 203 to be electrically connected.
The semiconductor device of the present invention, is formed with space, beneficially Semiconductor substrate in silicon through hole
In heat transmit from space, perfect heat-dissipating, the metal interconnecting layer of silicon through hole and bonding
It is electrically connected between two substrates, it is ensured that electric conductivity.
Embodiment three
The present invention additionally also provides for a kind of electronic installation, and it includes partly leading described in embodiment two
Body device, or include using the semiconductor device that in embodiment one, method makes.
Semiconductor device owing to including has good radiating effect and performance, this electronic installation
There is above-mentioned advantage equally.
This electronic installation, can be mobile phone, panel computer, notebook computer, net book, trip
Gaming machine, television set, VCD, DVD, navigator, photographing unit, video camera, recording pen,
Any electronic product such as MP3, MP4, PSP or equipment, it is also possible to be that there is above-mentioned quasiconductor
The intermediate products of device, such as: there is the cell phone mainboard etc. of this integrated circuit.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-mentioned
Embodiment is only intended to citing and descriptive purpose, and is not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that the present invention not office
It is limited to above-described embodiment, more kinds of modification can also be made according to the teachings of the present invention and repair
Change, within these variants and modifications all fall within scope of the present invention.The present invention's
Protection domain is defined by the appended claims and equivalent scope thereof.
Claims (18)
1. a semiconductor device, it is characterised in that including:
First substrate, is positioned at first metal interconnection structure on described first substrate surface, is positioned at institute
State first bonded layer on first substrate surface, and described first bonded layer exposes part described
One metal interconnection structure；
Second substrate, described second substrate includes the second gold medal being positioned at the front of described second substrate
Belong to interconnection structure, be positioned at the protective layer in described second substrate front, and described protective layer exposed portion
Divide described second metal interconnection structure, be positioned at described second substrate front, and be positioned at the second metal
The silicon through hole of interconnection structure side, also includes the insulation being positioned at described through-silicon via sidewall and bottom
Layer, and
The second metal interconnection structure of exposing described in being positioned at, the front of the described second substrate of part
With the diffusion impervious layer on described insulating barrier, it is positioned at the metal interconnection on described diffusion impervious layer surface
Layer, and it is positioned at the second bonded layer on the protective layer in described second substrate front, described second
Bonded layer exposes and is positioned at the metal interconnecting layer on described second substrate surface, wherein, described insulation
Layer, diffusion impervious layer, the gross thickness of metal interconnecting layer are less than the radius of described silicon through hole；
The second bonded layer surface in described second substrate front and the first key of described first substrate
Closing layer surface to be bonded mutually, described silicon through hole is relative with described first metal interconnection structure exposed
Should, described metal interconnecting layer links mutually with described first metal interconnection structure and the second metal respectively
Structure is electrically connected, and is formed with space in described silicon through hole.
2. semiconductor device as claimed in claim 1, it is characterised in that described metal is mutual
Even the material of layer is tungsten or aluminum or copper.
3. semiconductor device as claimed in claim 1, it is characterised in that described first base
Being formed with the first semiconductor device in plate, described first semiconductor device is mutual with described first metal
Link structure to be electrically connected.
4. semiconductor device as claimed in claim 1, it is characterised in that described second base
Being formed with the second semiconductor device in plate, described second semiconductor device is mutual with described second metal
Link structure to be electrically connected.
5. semiconductor device as claimed in claim 1, it is characterised in that described second key
Close layer and also cover the metal interconnecting layer in described silicon through hole.
6. semiconductor device as claimed in claim 5, it is characterised in that described insulating barrier,
The gross thickness of the second bonded layer in diffusion impervious layer, metal interconnecting layer and described silicon through hole is less than
The radius of described silicon through hole.
7. semiconductor device as claimed in claim 6, it is characterised in that described silicon through hole
The gross thickness of interior the second bonded layer, metal interconnecting layer, diffusion impervious layer and insulating barrier is less than 2
μm。
8. semiconductor device as claimed in claim 1, it is characterised in that described silicon through hole
Diameter range be 5～15 μm.
9. the manufacture method of a semiconductor device, it is characterised in that including:
Offer first substrate and second substrate, wherein,
Described first substrate part surface is formed the first metal interconnection structure, and is formed
At first bonded layer on described first substrate surface, and described first bonded layer exposes part institute
State the first metal interconnection structure, and
It is formed with the second metal interconnection structure in described second substrate front, and covers described
The protective layer of two metal interconnection structures；
The front of described protective layer and part second substrate is performed etching formation silicon through hole；
Insulating barrier is formed in sidewall and the bottom of described silicon through hole；
Thinning described protective layer, until the second metal interconnection structure surface described in expose portion；
At described insulating barrier, the described protective layer of part and the second metal interconnection structure table exposed
Face forms diffusion impervious layer；
Described diffusion impervious layer surface is formed metal interconnecting layer, wherein said insulating barrier, expansion
Scattered barrier layer, the gross thickness of metal interconnecting layer are less than the radius of described silicon through hole；
Described protective layer forms the second bonded layer, the end face of described second bonded layer with
The end face of described metal interconnecting layer flushes；
The first bonded layer by the second bonded layer on described second substrate Yu described first substrate
It is bonded, and makes the surface of the metal interconnecting layer of described exposure link mutually with described first metal
Structure is corresponding, forms space in described silicon through hole.
10. manufacture method as claimed in claim 9, it is characterised in that described second bonding
Layer also covers the metal interconnecting layer in described silicon through hole, wherein, described insulating barrier, diffusion barrier
The gross thickness of the second bonded layer in layer, metal interconnecting layer and described silicon through hole is led to less than described silicon
The radius in hole.
11. manufacture methods as claimed in claim 9, it is characterised in that use deep reaction from
Sub-etching technics or Bosch technique form described silicon through hole.
12. manufacture methods as claimed in claim 10, it is characterised in that form described
The method of two bonded layers comprises the following steps:
Formation of deposits second on the surface of described metal interconnecting layer and the protective layer of described exposure
Bonding material layer；
Perform cmp step, until the surface of metal interconnecting layer described in expose portion.
13. manufacture methods as claimed in claim 9, it is characterised in that described first bonding
The material of layer and described second bonded layer is silicon oxide.
14. manufacture methods as claimed in claim 9, it is characterised in that described bonding technology
For the melted bonding of silicon oxide.
15. manufacture methods as claimed in claim 9, it is characterised in that described metal interconnects
The formation process of layer includes sputtering, plasma physical vapor deposition, high-density plasma
Learn vapour deposition, low-pressure chemical vapor deposition or ald.
16. manufacture methods as claimed in claim 9, it is characterised in that described first substrate
Inside it is formed with the first semiconductor device, described first semiconductor device and described first metal interconnection
Structure is electrically connected；The second semiconductor device it is formed with in described second substrate, described the second half
Conductor device is electrically connected with described second metal interconnection structure.
17. manufacture methods as claimed in claim 9, it is characterised in that thinning described protection
The method of layer is cmp or lithographic method.
18. 1 kinds of electronic installations, it is characterised in that include as any one of claim 1-8
Described semiconductor device.
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