CN108122791A - A kind of wafer-level packaging method and semiconductor devices - Google Patents
A kind of wafer-level packaging method and semiconductor devices Download PDFInfo
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- CN108122791A CN108122791A CN201611067765.2A CN201611067765A CN108122791A CN 108122791 A CN108122791 A CN 108122791A CN 201611067765 A CN201611067765 A CN 201611067765A CN 108122791 A CN108122791 A CN 108122791A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02381—Side view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16147—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area disposed in a recess of the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81009—Pre-treatment of the bump connector or the bonding area
- H01L2224/8102—Applying permanent coating to the bump connector in the bonding apparatus, e.g. in-situ coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
Abstract
The present invention provides a kind of wafer-level packaging method and semiconductor devices, the described method includes：Bottom wafers and top wafer are provided, the bottom wafers have first surface and second surface, the first weld pad is formed on the first surface of the bottom wafers, the top wafer has first surface and second surface, the second weld pad is formed on the first surface of the top wafer；The second surface of the top wafer is bonded to the first surface of the bottom wafers, is bonded the bottom wafers and the top wafer gapless；It is formed and penetrates through the first through hole of the top wafer to expose the first weld pad on the bottom wafers first surface；It is formed on the first surface of the top wafer and in the first through hole and reroutes layer to connect the second weld pad on the top wafer first surface and the first weld pad on the bottom wafers first surface.Method using the present invention while function is realized, can reduce package dimension and thickness, cost-effective.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of wafer-level packaging method and semiconductor devices.
Background technology
In integrated circuit technology, semiconductor packages refers to process to obtain solely according to product type and functional requirement by wafer
The process of vertical chip.Increasingly increase with the demand of the miniaturization of electronic component, lightweight and multifunction, cause semiconductor package
Dress density is continuously increased, thus must reduce area shared when package dimension and encapsulation.Exactly these factors promote upside-down mounting
Chip package (Flip Chip Packaging), chip size packages (CSP, Chip Scale Package) and wafer scale
The development of (WLP, Wafer Level Packaging) etc. is encapsulated, to substitute traditional wire bond package (Wire Bond
Package).The size of traditional wire bond package is big, and input/output (I/O) port number is less.With wire bond package
Mode is compared, and Flip-Chip Using mode has packaging density height, and excellent radiation performance, I/O port densities are high and reliability is high
The advantages that, size and weight can be greatly reduced.Wafer-level packaging is that most of or whole encapsulation is carried out directly on wafer, is surveyed
Program is tried, is then cut again, based on it encapsulates (BGA, Ball Grid Array Package) with welded ball array, is
A kind of chip size packages by improving have become the important component of Advanced Packaging.
In the application with the raising required chip computing function, multi-chip stacking technique also has been enter into production, but with
The closed assembly chip thickness that Flip-Chip Using mode is realized can greatly increase, and production cost is high.
It is an object of the invention to provide a kind of wafer-level packaging method, to solve above-mentioned technical problem.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will in specific embodiment part into
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.
In view of the deficiencies of the prior art, the present invention provides a kind of wafer-level packaging method, the described method includes：Bottom is provided
Wafer and top wafer, the bottom wafers have each other relative first surface and a second surface, and the of the bottom wafers
The first weld pad is formed on one surface, the top wafer has each other relative first surface and second surface, the top
The second weld pad is formed on the first surface of wafer；The second surface of the top wafer is bonded to the of the bottom wafers
One surface is bonded the bottom wafers and the top wafer gapless；Form the first through hole for penetrating through the top wafer
To expose the first weld pad on the bottom wafers first surface；On the first surface of the top wafer and described first is logical
It is formed in hole and reroutes layer to connect the second weld pad on the top wafer first surface and the bottom wafers first surface
On the first weld pad.
Further, the second surface of the top wafer is bonded to by the bottom wafers using the method that melten gel is bonded
First surface.
Further, the method for forming the first through hole for penetrating through the top wafer includes deep reaction ion etching.
Further, forming the method for rerouting layer includes：On the first surface of the top wafer and described the
Seed Layer is formed in one through hole, then the plating metal in the Seed Layer, to form the rewiring layer.
Further, the plating metal includes copper.
Further, the Seed Layer includes the titanium and copper that are sequentially depositing.
Further, after described the step of forming the first through hole for penetrating through the top wafer, it is additionally included in the top
The first insulating layer is formed on the first surface of wafer, then etches first insulating layer, until exposing the bottom wafers
Second weld pad of the first weld pad and the top wafer.
Further, after described the step of forming rewiring layer, further include and etch away the unwanted portion of the rewiring layer
The step of dividing.
Further, it is described to etch away the rewiring unwanted first surface for being partly comprised in the top wafer of layer
Then upper coating photoresist exposes, develops.
Further, it is described etch away the rewiring layer unwanted part after, be additionally included in the top wafer
The step of metal coupling is formed on the second weld pad on first surface.
Further, the method for forming metal coupling includes：Second is formed on the first surface of the top wafer
Insulating layer then by exposing, developing, exposes the rewiring layer on the second weld pad of the top wafer as input/output
Port, and form metal coupling on the rewiring layer on second weld pad of exposing.
Further, the material of the metal coupling includes tin.
The present invention also provides a kind of semiconductor devices, including：Bottom wafers have each other relative first surface and second
Surface is formed with the first weld pad on the first surface of the bottom wafers；Top wafer, have each other relative first surface and
Second surface is formed with the second weld pad on the first surface of the top wafer；Penetrate through the first through hole of the top wafer, institute
State the first weld pad on the first through hole exposing bottom wafers first surface；On the first surface of the top wafer and institute
The rewiring layer formed in first through hole is stated, the rewiring layer connects the second weld pad on the first surface of the top wafer
With the first weld pad on the bottom wafers first surface, wherein, the bottom wafers and the top wafer gapless fitting.
Further, it is additionally included in the first insulation formed between the first surface of the top wafer and the rewiring layer
Layer.
Further, the rewiring layer includes：Seed Layer and the metal electroplated in the Seed Layer.
Further, the plating metal includes copper.
Further, the Seed Layer includes the titanium and copper that are sequentially depositing.
Further, in addition on the first surface of the top wafer the second of the covering rewiring layer formed is absolutely
Edge layer, the second insulating layer have the opening for exposing the layer of the rewiring on second weld pad.
Further, the metal coupling formed on the rewiring layer in addition on second weld pad of exposing.
Further, the material of the metal coupling includes tin.
In conclusion the method according to the invention, top wafer and bottom wafers are bonded, then in top crystal column surface
It is formed and reroutes layer, seamlessly connection top wafer and the input/output end port of bottom wafers, so as to fulfill wafer-level packaging.
While the closed assembly chip functions of Flip-Chip Using are realized, it is possible to reduce package dimension and thickness, it is cost-effective, it solves
The problem of existing multi-chip package production technology.
Description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Fig. 1 is the technical process schematic diagram of the semiconductor devices of the embodiment of the present invention one.
The semiconductor devices that the step of Fig. 2A -2F are and are implemented successively according to the method for the embodiment of the present invention one obtains respectively
Schematic cross sectional view；
Specific embodiment
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to illustrate proposition of the present invention
Wafer-level packaging method.Obviously, execution of the invention be not limited to semiconductor applications technical staff be familiar with it is special
Details.Presently preferred embodiments of the present invention is described in detail as follows, however in addition to these detailed descriptions, the present invention can also have it
His embodiment.
It should be appreciated that it when the term " comprising " and/or " including " is used in this specification, indicates described in presence
Feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of other one or more features, entirety,
Step, operation, element, component and/or combination thereof.
Multi-chip stacking technique according to prior art mainly realized in a manner of Flip-Chip Using, but with flip-chip
The closed assembly chip thickness that packaged type is realized can greatly increase, and production cost is high.
Embodiment one
Presence in view of the above problems, the present invention propose a kind of wafer-level packaging method, as shown in Figure 1, it include with
Lower key step：
In step S101, bottom wafers and top wafer are provided, the bottom wafers have the first table relative to each other
Face and second surface, the first weld pad is formed on the first surface of the bottom wafers, and the top wafer has relative to each other
First surface and second surface, be formed with the second weld pad on the first surface of the top wafer；
In step s 102, the second surface of the top wafer is bonded to the first surface of the bottom wafers, is made
The bottom wafers and top wafer gapless fitting；
In step s 103, formed and penetrate through the first through hole of the top wafer to expose the bottom wafers first surface
On the first weld pad；
In step S104, on the first surface of the top wafer and the first through hole in formed reroute layer with
Connect the second weld pad on the top wafer first surface and the first weld pad on the bottom wafers first surface.
The method according to the invention, top wafer and bottom wafers are bonded, and then at top, crystal column surface forms weight cloth
Line layer seamlessly connects top wafer and the input/output end port of bottom wafers, so as to fulfill wafer-level packaging.It is realizing
While the closed assembly chip functions of cartridge chip encapsulation, it is possible to reduce package dimension and thickness, it is cost-effective, solve existing multicore
The problem of piece production process for encapsulating.
With reference to Fig. 2A-Fig. 2 F, it is shown the step of according to embodiments of the present invention one method is implemented successively and obtains respectively
The schematic cross sectional view of the semiconductor devices obtained.
First, bottom wafers 201 and top wafer 202 are provided, wherein, the bottom wafers 201 have relative to each other
First surface and second surface are formed with the first weld pad 203, the top wafer 202 on the first surface of the bottom wafers
With each other relative first surface and second surface, the second weld pad is formed on the first surface of the top wafer 202
204.The second surface of the top wafer 202 is bonded to the first surface of the bottom wafers 201, makes the bottom wafers
201 and 202 gapless of top wafer fitting, as shown in Figure 2 A.Specifically, using the method for melten gel bonding by the top
The second surface of wafer 202 is bonded to the first surface of the bottom wafers 201.The material of first weld pad 203 or the second weld pad 204
Material can be the arbitrary of the one or more in the metals such as aluminium (Al), copper (Cu), silver (Ag), gold (Au), nickel (Ni) and tungsten (W)
Combination, preferably aluminium.When melten gel is bonded, first to the first surface and the second of the top wafer 202 of the bottom wafers 201
Surface is chemically treated, and makes to generate adsorption capacity between the two, then is bonded, and specific process parameter is with reference to of the prior art
Melten gel bonding parameter, details are not described herein.
Next, the first through hole 205 for penetrating through the top wafer 202 is formed, to expose the bottom wafers 202 first
The first weld pad 203 on surface, as shown in Figure 2 B.The method for forming the first through hole 205 for penetrating through the top wafer 202
Including deep reaction ion etching (DRIE, Deep Reactive Ion Etch), but also it is not limited to the method.Specifically
Ground in the deep reaction ion etching step, selects gas hexa-fluoride (SF6) to be used as process gas, applies radio-frequency power supply,
So that hexa-fluoride reaction air inlet forms high ionization, operating pressure is controlled in the etching step as 20mTorr-8Torr, frequency work(
Rate is 600W, and 13.5MHz, Dc bias can the continuous control in -500V-1000V.Above-mentioned numerical value is only as an example, can root
It is suitably adjusted according to specific device.
Then, the first insulating layer 206 is formed in the first surface of the top wafer 202, then etches described first absolutely
Edge layer 206, until expose the first weld pad 203 of the bottom wafers 201 and the second weld pad 204 of the top wafer 202, with
The second through hole 207 for penetrating through the top wafer and the third through-hole 208 for penetrating through first insulating layer 206 are formed, such as Fig. 2 C
It is shown.First insulating layer 206 selects organic insulation, the organic insulation include polyimides (PI,
Polyimide) or epoxy resin (Epoxy), preferred polyimides.Forming the method for first insulating layer 206 includes：Institute
It states and is coated with insulation material layer on the first surface of top wafer 202, then baked, to form first insulating layer 206,
Concrete technology is with reference to the prior art, and details are not described herein.Etching the technique of first insulating layer includes deep reaction ion etching
Technique, but the method is also not limited to, any etching technics well known to those skilled in the art also can be used and carved
Erosion.Concrete technology is with reference to the prior art, and details are not described herein.
Then, formed on the first surface of the top wafer 202 and in the first through hole 205 and reroute layer
(RDL, Redistribution Layer) 209, with connect the second weld pad 204 on 202 first surface of top wafer with
The first weld pad 203 on 201 first surface of bottom wafers, as shown in Figure 2 D.Form the method bag of the rewiring layer 209
It includes：On the first surface of the top wafer 202 and Seed Layer is formed in the first through hole 205, then in the seed
Plating metal on layer, to form the rewiring layer 209.
The Seed Layer is made of the Ti and Cu being sequentially depositing.Using electrochemistry galvanoplastic plating metal, the electroplating gold
Belong to for copper.The reason for deposited seed layer, is：The rewiring layer of semiconductor devices is formed using electrochemistry galvanoplastic, plating is formed
It is crucial that generating electric current by the metal layer on surface makes Metal deposition.And the first insulating layer of 202 first surface of top wafer
206 be nonconducting, so cannot carry out rerouting layer plating, it is therefore desirable to be re-formed in nonconducting first surface of insulating layer
One layer of metal layer, as Seed Layer, layer is rerouted convenient for plating.The original that the Seed Layer is made of the Ti and Cu being sequentially depositing
Because being：Extended meeting forms Ti layers of effect and is that Ti layers can be used as diffusion barrier using copper as layer is rerouted after in the present invention
Layer, to prevent the adhesion strength that copper to first insulating layer 206 spreads and increase Cu layers, Cu is plating seed layer, convenient for electricity
Chemical-electrical copper facing RDL wiring layers.Therefore Seed Layer is the lamination of Ti and Cu.The deposition method of the Seed Layer can select chemistry
(CVD) method of vapor deposition, physical vapour deposition (PVD) (PVD) method or atomic layer deposition (ALD) method etc..Concrete technology is with reference to existing skill
Art, details are not described herein.
Using electrochemistry galvanoplastic electro-coppering RDL wiring layers, detailed process is：Power supply is added in Ti/Cu Seed Layers and institute
Between stating the first insulating layer 206, Ti/Cu Seed Layers are used as cathode as anode, first insulating layer 206, after applying voltage,
It reacts as the copper in the Ti/Cu Seed Layers of anode and changes into copper ion and electronics, while as described the first of cathode
The copper ion of seed layer surface near insulating layer 206 combines to form the copper for being plated in the seed layer surface with electronics.As excellent
Choosing can also use additive in plating, and the additive is flat dose, accelerator and inhibitor.Finally, copper RDL is completed
The plating of wiring layer, you can formed and reroute layer 209.Concrete technology is with reference to the prior art, and details are not described herein.
Then, after the first surface coating photoresist (PR, Photo Resist) of the top wafer 202, exposure is passed through
Light, development etch away unwanted part in the rewiring layer, retain the rewiring layer 209 of needs, as shown in Figure 2 E.Light
Photoresist is a kind of photosensitive front and rear, the solubility meeting organic compound that great changes will take place in specific developer solution.Photoresist
Including positive photoresist and negative photoresist.Here, it is preferred that the unexposed portion of negative photoresist, i.e. negative photoresist be dissolved in it is aobvious
Shadow liquid, the developed solvent dissolving during development；Part through overexposure becomes insoluble due to crosslinking and can harden,
It cannot be washed off insoluble in developer solution in developer solution, the pattern that negative photo glue-line retains after development and mask plate shading
Pattern is opposite.Then remaining photoresist is removed, the cleaning method includes wet clean process, and concrete technology is with reference to existing skill
Art, details are not described herein.
Finally, second insulating layer 210 is formed on the first surface of the top wafer 202, then by exposing, showing
Shadow exposes the rewiring layer 209 on the second weld pad 204 of the top wafer 202 as input/output end port, and is exposing
Second weld pad 204 on rewiring layer 209 on formed metal coupling 211, as shown in Figure 2 F.The second insulating layer
210 select organic insulation, and the organic insulation includes polyimides (polyimide-PI) or epoxy resin
(Epoxy), preferred polyimides.Forming the method for the second insulating layer 210 includes：The first of the top wafer 202
Insulation material layer is coated on surface, is then baked, to form the second insulating layer 210, concrete technology is with reference to existing skill
Art, details are not described herein.The material of the metal coupling 211 can be tin, Xi Yin, tin-lead, tin silver copper, tin silver-colored zinc, tin zinc, tin
One or more kinds of any combination in bismuth indium, tin indium, Sillim, tin copper, tin zinc indium or tin silver antimony, and can include living
Property agent, preferably tin.The metal coupling 211 can be by being deposited (evaporation), plating (electroplating), nothing
Electricity plating (electroless plating), sputter (sputtering) or print process (stencil printing) method shape
Into on the second weld pad 204 on 202 first surface of top wafer, then preferred print process is made using reflow soldering process
Metal layer flows back into metal coupling 211.
The input/output end port for completing the top wafer of the semiconductor devices of encapsulation is metal coupling 211.The top is brilliant
Metal coupling 211 on 202 first surfaces of circle is by rerouting layer 209, with first on 201 first surface of bottom wafers
Weld pad 203 connects, so as to fulfill wafer-level packaging.
In conclusion the method according to the invention, top wafer and bottom wafers are bonded, then in top crystal column surface
It is formed and reroutes layer, seamlessly connection top wafer and the input/output end port of bottom wafers, so as to fulfill wafer-level packaging.
While the closed assembly chip functions of Flip-Chip Using are realized, it is possible to reduce package dimension and thickness, it is cost-effective, it solves
The problem of existing multi-chip package production technology.
Embodiment two
The present invention also provides a kind of semiconductor devices, as shown in Figure 2 F, including：Bottom wafers 201 have toward each other
First surface and second surface are formed with the first weld pad 203 on the first surface of the bottom wafers 201；Top wafer 202,
With each other relative first surface and second surface, the second weld pad is formed on the first surface of the top wafer 202
204；The first through hole 205 of the top wafer 202 is penetrated through, the first through hole 205 exposes 201 first table of bottom wafers
The first weld pad 203 on face；The heavy cloth formed on the first surface of the top wafer 202 and in the first through hole 205
Line layer 209, the rewiring layer 209 connect the second weld pad 204 and the bottom on the first surface of the top wafer 202
The first weld pad 203 on 201 first surface of wafer, wherein, the bottom wafers 201 and 202 gapless of top wafer patch
It closes.
Wherein, the rewiring layer 209 includes：On the first surface of the top wafer 202 and the first through hole
The Seed Layer formed in 205 and the metal electroplated in the Seed Layer.The plating metal includes copper.The Seed Layer includes
The titanium and copper being sequentially depositing.
Optionally, the semiconductor devices is additionally included in the first surface of the top wafer 202 and the rewiring layer
The first insulating layer 206 formed between 209.
Optionally, the semiconductor devices also includes the covering institute formed on the first surface of the top wafer 202
The second insulating layer 210 for rerouting layer 209 is stated, the second insulating layer 210 has the heavy cloth exposed on second weld pad 204
The opening of line layer 209.
Further, the semiconductor devices also includes shape on the rewiring layer 209 on second weld pad 204 of exposing
Into metal coupling 211.The material of the metal coupling 211 can be tin, Xi Yin, tin-lead, tin silver copper, tin silver-colored zinc, tin zinc, tin
One or more kinds of any combination in bismuth indium, tin indium, Sillim, tin copper, tin zinc indium or tin silver antimony, and can include living
Property agent, preferably tin.
The input/output end port of the top wafer of the semiconductor devices is metal coupling 211.The top wafer 202
Metal coupling 211 on first surface is by rerouting layer 209, with the first weld pad on 201 first surface of bottom wafers
203 connections, so as to fulfill wafer-level packaging.
Optionally, semiconductor devices of the present invention can select the method described in embodiment one to manufacture, and realize
While the closed assembly chip functions of cartridge chip encapsulation, it is possible to reduce package dimension and thickness.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in the range of described embodiment.In addition people in the art
Member is it is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (20)
1. a kind of wafer-level packaging method, which is characterized in that comprise the following steps：
Bottom wafers and top wafer are provided, the bottom wafers have each other relative first surface and second surface, described
The first weld pad is formed on the first surface of bottom wafers, the top wafer has each other relative first surface and the second table
Face is formed with the second weld pad on the first surface of the top wafer；
The second surface of the top wafer is bonded to the first surface of the bottom wafers, makes bottom wafers and described
Top wafer gapless fitting；
It is formed and penetrates through the first through hole of the top wafer to expose the first weld pad on the bottom wafers first surface；
It is formed on the first surface of the top wafer and in the first through hole and reroutes layer to connect the top wafer
The second weld pad on first surface and the first weld pad on the bottom wafers first surface.
2. according to the method described in claim 1, it is characterized in that, using the method for melten gel bonding by the of the top wafer
Two surface bonds are to the first surface of the bottom wafers.
3. according to the method described in claim 1, it is characterized in that, the formation penetrates through the first through hole of the top wafer
Method includes deep reaction ion etching.
4. according to the method described in claim 1, it is characterized in that, forming the method for rerouting layer includes：On the top
On the first surface of portion's wafer and Seed Layer is formed in the first through hole, then the plating metal in the Seed Layer, with shape
Into the rewiring layer.
5. according to the method described in claim 4, it is characterized in that, the plating metal includes copper.
6. according to the method described in claim 4, it is characterized in that, the Seed Layer includes the titanium and copper that are sequentially depositing.
7. according to the method described in claim 1, it is characterized in that, in the first through hole for forming the perforation top wafer
The step of after, in addition to form the first insulating layer on the first surface of the top wafer, then etch first insulation
Layer, until exposing the first weld pad of the bottom wafers and the second weld pad of the top wafer.
8. according to the method described in claim 1, it is characterized in that, after described the step of forming rewiring layer, quarter is further included
The step of unwanted part of layer is rerouted described in eating away.
9. according to the method described in claim 8, it is characterized in that, described etch away the unwanted part bag of the rewiring layer
It includes and coats photoresist on the first surface of the top wafer, then expose, develop.
10. method according to claim 8 or claim 9, which is characterized in that it is described etch away it is described rewiring layer it is unwanted
Behind part, in addition on the second weld pad on the first surface of the top wafer formed metal coupling the step of.
11. according to the method described in claim 10, it is characterized in that, the method for forming metal coupling includes：Described
Second insulating layer is formed on the first surface of top wafer, then by exposing, developing, exposes the second weldering of the top wafer
Rewiring layer on pad forms metal as input/output end port on the rewiring layer on second weld pad of exposing
Convex block.
12. according to the method for claim 11, which is characterized in that the material of the metal coupling includes tin.
13. a kind of semiconductor devices, which is characterized in that including：
Bottom wafers have each other relative first surface and second surface, are formed on the first surface of the bottom wafers
First weld pad；
Top wafer has each other relative first surface and second surface, is formed on the first surface of the top wafer
Second weld pad；
The first through hole of the top wafer is penetrated through, the first through hole exposes the first weldering on the bottom wafers first surface
Pad；
The rewiring layer formed on the first surface of the top wafer and in the first through hole, the rewiring layer connection
The second weld pad on the first surface of the top wafer and the first weld pad on the bottom wafers first surface,
Wherein, the bottom wafers and top wafer gapless fitting.
14. semiconductor devices according to claim 13, which is characterized in that be additionally included in the first table of the top wafer
The first insulating layer formed between face and the rewiring layer.
15. semiconductor devices according to claim 13, which is characterized in that the rewiring layer includes：Seed Layer and
The metal electroplated in the Seed Layer.
16. semiconductor devices according to claim 15, which is characterized in that the plating metal includes copper.
17. semiconductor devices according to claim 15, which is characterized in that the Seed Layer include the titanium that is sequentially depositing and
Copper.
18. semiconductor devices according to claim 13, which is characterized in that be additionally included in the first table of the top wafer
The covering second insulating layer for rerouting layer formed on face, the second insulating layer, which has, to be exposed on second weld pad
Reroute the opening of layer.
19. semiconductor devices according to claim 18, which is characterized in that also include on second weld pad of exposing
Rewiring layer on the metal coupling that is formed.
20. semiconductor devices according to claim 19, which is characterized in that the material of the metal coupling includes tin.
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