CN105845097A - Shift register unit, driving method of shift register unit, gate drive circuit and display device - Google Patents
Shift register unit, driving method of shift register unit, gate drive circuit and display device Download PDFInfo
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- CN105845097A CN105845097A CN201610425494.7A CN201610425494A CN105845097A CN 105845097 A CN105845097 A CN 105845097A CN 201610425494 A CN201610425494 A CN 201610425494A CN 105845097 A CN105845097 A CN 105845097A
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- nodal point
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Shift Register Type Memory (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention discloses a shift register unit, a driving method of the shift register unit, a gate drive circuit and a display device. According to the shift register unit, an input module can control the potential of a first node so that a first output module is enabled to provide signals of a reference signal end to a signal output end under the control of the first node, the potential of the signal output end can be pulled down, a second output module is enabled to provide the signals of a second clock signal end to the signal output end under the control of the first node and normal output of the signal output end can be guaranteed; a reset module can provide the signals of the reference signal end to the signal output end under the control of a reset signal end so that the potential of the signal output end can be pulled down; and a control module can control the potential of a second node so that a third output module is enabled to provide the signals of the reference signal end to the signal output end under the control of the second node and the potential of the signal output end can be pulled down. Therefore, noise of the output signals of the signal output end of the shift register unit can be reduced.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of shift register cell, its driving method,
Gate driver circuit and display device.
Background technology
In display panels, generally by gate driver circuit each thin film transistor (TFT) to pixel region
The grid of (TFT, Thin Film Transistor) provides gate drive signal.Gate driver circuit can lead to
Cross array processes to be integrated on the array base palte of display panels, i.e. array base palte row cutting (Gate Driver
On Array, GOA) technique, this integrated technique not only saves cost, and can accomplish liquid crystal display
The design for aesthetic that panel both sides are symmetrical, meanwhile, also eliminates binding region and the fan-out of gate driver circuit
Wiring space, such that it is able to realize the design of narrow frame；Further, this integrated technique may be omitted with grid
The binding technique of pole scan-line direction, thus improve production capacity and yield.
At present, every grade of shift register cell in existing gate driver circuit, time mainly by one
Clock signal controls pull-down node, then controls pull-up node and signal outfan by pull-down node
Drop-down, but owing to the dutycycle of pull-down node is 50%, so signal outfan is in the scan period
It is pulled down in half the time, is in unsettled in second half time, so, cause signal outfan to export
The noise ratio of signal bigger.
Therefore, how to reduce the noise of signal of shift register cell output, be those skilled in the art urgently
Need to solve the technical problem that.
Summary of the invention
In view of this, a kind of shift register cell, its driving method, grid are embodiments provided
Drive circuit and display device, in order to reduce the noise of the signal of shift register cell output.
Therefore, embodiments provide a kind of shift register cell, including: input module, reset
Module, control module, the first output module, the second output module and the 3rd output module；Wherein,
First control end of described input module is connected with signal input part respectively with input, and second controls end
Being connected with the first clock signal terminal, outfan is connected with primary nodal point, for respectively at described first clock letter
Number end and described signal input part control under the signal of described signal input part is supplied to described first segment
Point；
The control end of described reseting module is connected with reset signal end, and input is connected with reference signal end, the
One outfan is connected with described primary nodal point, and the second outfan is connected with signal output part, for described multiple
Under the control of position signal end the signal of described reference signal end is respectively supplied to described primary nodal point and described
Signal output part；
First control end of described control module is connected with described primary nodal point, first input end and described reference
Signal end be connected, the first outfan is connected with secondary nodal point, second control end and the second input respectively with institute
Stating the first clock signal terminal to be connected, the second outfan is connected with described secondary nodal point, at described first segment
Under the control of point, the signal of described reference signal end is supplied to described secondary nodal point and when described first
Under the control of clock signal end, the signal of described first clock signal terminal is supplied to described secondary nodal point；
The control end of described first output module is connected with described primary nodal point, input and described reference signal
End is connected, and outfan is connected with described signal output part, is used for described under the control of described primary nodal point
The signal of reference signal end is supplied to described signal output part；
The control end of described second output module is connected with described primary nodal point, input and second clock signal
End is connected, and outfan is connected with described signal output part, is used for described under the control of described primary nodal point
The signal of second clock signal end is supplied to described signal output part；
The control end of described 3rd output module is connected with described secondary nodal point, input and described reference signal
End is connected, and the first outfan is connected with described primary nodal point, and the second outfan is connected with described signal output part,
For the signal of described reference signal end being respectively supplied to described first under the control of described secondary nodal point
Node and described signal output part.
In a kind of possible implementation, at the above-mentioned shift register cell that the embodiment of the present invention provides
In, also include: the 4th output module；
The control end of described 4th output module is connected with described first clock signal terminal, input and described ginseng
Examining signal end to be connected, outfan is connected with described signal output part, at described first clock signal terminal
Under control, the signal of described reference signal end is supplied to described signal output part.
In a kind of possible implementation, at the above-mentioned shift register cell that the embodiment of the present invention provides
In, described first output module, specifically include: the first switching transistor；
The grid of described first switching transistor is connected with described primary nodal point, described first switching transistor
Source electrode is connected with described reference signal end, the drain electrode of described first switching transistor and described signal output part phase
Even.
In a kind of possible implementation, at the above-mentioned shift register cell that the embodiment of the present invention provides
In, described second output module, specifically include: second switch transistor and electric capacity；Wherein,
The grid of described second switch transistor is connected with described primary nodal point, described second switch transistor
Source electrode is connected with described second clock signal end, and the drain electrode of described second switch transistor exports with described signal
End is connected；
Described electric capacity is connected between the grid of described second switch transistor and drain electrode.
In a kind of possible implementation, at the above-mentioned shift register cell that the embodiment of the present invention provides
In, described 3rd output module, specifically include: the 3rd switching transistor and the 4th switching transistor；Wherein,
The grid of described 3rd switching transistor is connected with described secondary nodal point, described 3rd switching transistor
Source electrode is connected with described reference signal end, the drain electrode of described 3rd switching transistor and described primary nodal point phase
Even；
The grid of described 4th switching transistor is connected with described secondary nodal point, described 4th switching transistor
Source electrode is connected with described reference signal end, the drain electrode of described 4th switching transistor and described signal output part phase
Even.
In a kind of possible implementation, at the above-mentioned shift register cell that the embodiment of the present invention provides
In, described 4th output module, specifically include: the 5th switching transistor；
The grid of described 5th switching transistor is connected with described first clock signal terminal, described 5th switch crystalline substance
The source electrode of body pipe is connected with described reference signal end, and the drain electrode of described 5th switching transistor is defeated with described signal
Go out end to be connected.
In a kind of possible implementation, at the above-mentioned shift register cell that the embodiment of the present invention provides
In, described input module, specifically include: the 6th switching transistor and the 7th switching transistor；
The grid of described 6th switching transistor is connected with described signal input part respectively with source electrode, and the described 6th
The drain electrode of switching transistor is connected with described primary nodal point；
The grid of described 7th switching transistor is connected with described first clock signal terminal, described 7th switch crystalline substance
The source electrode of body pipe is connected with described signal input part, the outfan and described first of described 7th switching transistor
Node is connected.
In a kind of possible implementation, at the above-mentioned shift register cell that the embodiment of the present invention provides
In, described reseting module, specifically include: the 8th switching transistor and the 9th switching transistor；Wherein,
The grid of described 8th switching transistor is connected with described reset signal end, described 8th switching transistor
Source electrode be connected with described reference signal end, the drain electrode of described 8th switching transistor and described primary nodal point phase
Even；
The grid of described 9th switching transistor is connected with described reset signal end, described 9th switching transistor
Source electrode be connected with described reference signal end, the drain electrode of described 9th switching transistor and described signal output part
It is connected.
In a kind of possible implementation, at the above-mentioned shift register cell that the embodiment of the present invention provides
In, described control module, specifically include: the tenth switching transistor, the 11st switching transistor, the 12nd
Switching transistor and the 13rd switching transistor；Wherein,
The grid of described tenth switching transistor is connected with described primary nodal point, described tenth switching transistor
Source electrode is connected with described reference signal end, the drain electrode of described tenth switching transistor and described secondary nodal point phase
Even；
The grid of described 11st switching transistor is connected with described primary nodal point, described 11st switch crystal
The source electrode of pipe is connected with described reference signal end, the drain electrode of described 11st switching transistor and described Section three
Point is connected；
Described twelvemo is closed the grid of transistor and is connected with described first clock signal terminal respectively with source electrode, institute
The drain electrode stating twelvemo pass transistor is connected with described 3rd node；
The grid of described 13rd switching transistor is connected with described 3rd node, described 13rd switch crystal
The source electrode of pipe is connected with described first clock signal terminal, the drain electrode of described 13rd switching transistor and described the
Two nodes are connected.
The embodiment of the present invention additionally provides the driving method of a kind of shift register cell, including:
In the first stage, the signal inputting a signal into end under the control of the first clock signal terminal is supplied to first
Node, is supplied to signal output part by the signal of reference signal end under the control of described primary nodal point；Institute
State, under the control of the first clock signal terminal, the signal of described first clock signal terminal is supplied to secondary nodal point,
Under the control of described secondary nodal point, the signal of described reference signal end is respectively supplied to described primary nodal point and
Described signal output part；
In second stage, under the control of described signal input part, the signal of described signal input part is supplied to
Described primary nodal point, is supplied to described under the control of described primary nodal point by the signal of second clock signal end
Signal output part；Under the control of described first clock signal terminal, the signal of described first clock signal terminal is carried
Supply described secondary nodal point, under the control of described secondary nodal point, the signal of described reference signal end is carried respectively
Supply described primary nodal point and described signal output part；
In the phase III, under the control of described primary nodal point, the signal of described second clock signal end is provided
To described signal output part, under the control of described primary nodal point, the signal of described reference signal end is supplied to
Described secondary nodal point；
In fourth stage, under the control of described reset signal end, the signal of described reference signal end is carried respectively
Supply described primary nodal point and described signal output part, by described with reference to letter under the control of described primary nodal point
Number end signal be supplied to described signal output part；By described under the control of described first clock signal terminal
The signal of one clock signal terminal is supplied to described secondary nodal point, by described ginseng under the control of described secondary nodal point
The signal examining signal end is respectively supplied to described primary nodal point and described signal output part；
In the 5th stage, under the control of described primary nodal point, the signal of described reference signal end is supplied to institute
State signal output part.
In a kind of possible implementation, in the above-mentioned driving method that the embodiment of the present invention provides, also wrap
Include:
In first stage, second stage and fourth stage, by institute under the control of described first clock signal terminal
The signal stating reference signal end is supplied to described signal output part.
The embodiment of the present invention additionally provides a kind of gate driver circuit, and the embodiment of the present invention including cascade provides
Above-mentioned shift register cell；Wherein,
In addition to first order shift register cell, the described signal of remaining every one-level shift register cell is defeated
Go out end to be connected with the described reset signal end of the upper level shift register cell being adjacent respectively；
In addition to afterbody shift register cell, the described signal of remaining every one-level shift register cell
Outfan described signal input part with the next stage shift register cell being adjacent respectively is connected；
The described signal input part of first order shift register cell is connected with frame start signal end.
The embodiment of the present invention additionally provides a kind of display device, including: the above-mentioned grid that the embodiment of the present invention provides
Pole drive circuit.
The invention discloses a kind of shift register cell, its driving method, gate driver circuit and display dress
Putting, in this shift register cell, input module can control the current potential of primary nodal point so that first is defeated
Go out module, under the control of primary nodal point, the signal of reference signal end is supplied to signal output part, can drag down
The current potential of signal output part so that second clock can be believed under the control of primary nodal point by the second output module
The signal of number end is supplied to signal output part, it is ensured that the normal output of signal output part；Reseting module can be
Under the control of reset signal end, the signal of reference signal end is supplied to signal output part, signal can be dragged down defeated
Go out the current potential of end；Control module can control the current potential of secondary nodal point so that the 3rd output module is at second section
Under the control of point, the signal of reference signal end is supplied to signal output part, the electricity of signal output part can be dragged down
Position；As such, it is possible to reduce the noise of the signal output part output signal of shift register cell.
Accompanying drawing explanation
One of structural representation of shift register cell that Fig. 1 provides for the embodiment of the present invention；
The two of the structural representation of the shift register cell that Fig. 2 provides for the embodiment of the present invention；
Fig. 3 a and Fig. 3 b is respectively the concrete structure signal of the shift register cell that the embodiment of the present invention provides
One of figure；
Fig. 4 a and Fig. 4 b is respectively the concrete structure signal of the shift register cell that the embodiment of the present invention provides
The two of figure；
Fig. 5 is the input and output sequential chart of the shift register cell shown in Fig. 4 a；
The structural representation of the gate driver circuit that Fig. 6 provides for the embodiment of the present invention.
Detailed description of the invention
Below in conjunction with the accompanying drawings, to the embodiment of the present invention provide shift register cell, its driving method, grid
The detailed description of the invention of pole drive circuit and display device is described in detail.
A kind of shift register cell that the embodiment of the present invention provides, as it is shown in figure 1, include: input module
1, reseting module 2, control module the 3, first output module the 4, second output module 5 and the 3rd output mould
Block 6；Wherein,
First control end 1a of input module 1 is connected with signal input part Input respectively with input 1b,
Second controls end 1c and the first clock signal terminal CLKB is connected, and outfan 1d is connected with primary nodal point P1,
For inputting a signal into end under the control of the first clock signal terminal CLKB and signal input part Input respectively
The signal of Input is supplied to primary nodal point P1；
The control end 2a of reseting module 2 is connected with reset signal end Reset, input 2b and reference signal
End Vref is connected, and the first outfan 2c is connected with primary nodal point P1, and the second outfan 2d exports with signal
End Output is connected, for being divided by the signal of reference signal end Vref under the control of reset signal end Reset
You can well imagine supply primary nodal point P1 and signal output part Output；
First control end 3a of control module 3 is connected with primary nodal point P1, first input end 3b and reference
Signal end Vref is connected, and the first outfan 3c is connected with secondary nodal point P2, and second controls end 3d and second
Input 3e is connected with the first clock signal terminal CLKB respectively, the second outfan 3f and secondary nodal point P2
It is connected, for the signal of reference signal end Vref being supplied to secondary nodal point under the control of primary nodal point P1
P2 and under the control of the first clock signal terminal CLKB, the signal of the first clock signal terminal CLKB being carried
Supply secondary nodal point P2；
The control end 4a of the first output module 4 is connected with primary nodal point P1, input 4b and reference signal
End Vref is connected, and outfan 4c is connected with signal output part Output, for the control at primary nodal point P1
Under system, the signal of reference signal end Vref is supplied to signal output part Output；
The control end 5a of the second output module 5 is connected with primary nodal point P1, input 5b and second clock
Signal end CLK is connected, and outfan 5c is connected with signal output part Output, at primary nodal point P1
Control under the signal of second clock signal end CLK is supplied to signal output part Output；
The control end 6a of the 3rd output module 6 is connected with secondary nodal point P2, input 6b and reference signal
End Vref is connected, and the first outfan 6c is connected with primary nodal point P1, and the second outfan 6d exports with signal
End Output is connected, for being carried respectively by the signal of reference signal end Vref under the control of secondary nodal point P2
Supply primary nodal point P1 and signal output part Output.
The above-mentioned shift register cell that the embodiment of the present invention provides, input module 1 can control primary nodal point
The current potential of P1 so that the first output module 4 can be by reference signal end Vref under the control of primary nodal point P1
Signal be supplied to signal output part Output, the current potential of signal output part Output can be dragged down so that
The signal of second clock signal end CLK can be provided under the control of primary nodal point P1 by two output modules 5
To signal output part Output, it is ensured that the normal output of signal output part Output；Reseting module 2
Under the control of reset signal end Reset, the signal of reference signal end Vref can be supplied to signal output part
Output, can drag down the current potential of signal output part Output；Control module 3 can control secondary nodal point
The current potential of P2 so that the 3rd output module 6 can be by reference signal end Vref under the control of secondary nodal point P2
Signal be supplied to signal output part Output, the current potential of signal output part Output can be dragged down；So,
The noise of the signal of the signal output part Output output of shift register cell can be reduced, it is ensured that signal is defeated
Go out the stability of the signal holding Output to export.
In the specific implementation, in the above-mentioned shift register cell that the embodiment of the present invention provides, reference signal end
The current potential of Vref is electronegative potential.
Below in conjunction with specific embodiment, the present invention is described in detail.It should be noted that the present embodiment
In be to preferably explain the present invention, but be not intended to the present invention.
It is preferred that in the above-mentioned shift register cell that the embodiment of the present invention provides, as in figure 2 it is shown, also
May include that the 4th output module 7；
The control end 7a and the first clock signal terminal CLKB of the 4th output module 7 be connected, input 7b with
Reference signal end Vref is connected, and outfan 7c is connected with signal output part Output, at the first clock
Under the control of signal end CLKB, the signal of reference signal end Vref is supplied to signal output part Output；
So, the 4th output module 7 can be at the control drop-down low signal outfan of the first clock signal terminal CLKB
The current potential of Output, such that it is able to reduce the noise of the signal of signal output part Output output further,
Ensure the stability of the signal of signal output part Output output.
In the specific implementation, in the above-mentioned shift register cell that the embodiment of the present invention provides, such as Fig. 3 a
Shown in Fig. 3 b, the first output module 4, specifically may include that the first switching transistor T1；
The grid of the first switching transistor T1 is connected with primary nodal point P1, the source of the first switching transistor T1
Pole is connected with reference signal end Vref, the drain electrode of the first switching transistor Vref and signal output part Output
It is connected.
Specifically, in the above-mentioned shift register cell that the embodiment of the present invention provides, as shown in Figure 3 a,
First switching transistor T1 can be P-type transistor, or, as shown in Figure 3 b, the first switching transistor
T1 can also be N-type transistor, in this no limit.With the first switching transistor T1 as P-type transistor
As a example by, when the current potential of primary nodal point P1 is electronegative potential, the first switching transistor T1 is in the conduction state,
Being connected with signal output part Output by reference signal end Vref, the current potential making signal output part Output is
Electronegative potential, reference signal end Vref carries out noise reduction to signal output part Output.
More than it is merely illustrative of the concrete structure of the first output module 4 in shift register cell, specifically
During enforcement, the concrete structure of the first output module 4 is not limited to the said structure that the embodiment of the present invention provides, also
Can be other structures that skilled person will appreciate that, not limit at this.
In the specific implementation, in the above-mentioned shift register cell that the embodiment of the present invention provides, such as Fig. 3 a
Shown in Fig. 3 b, the second output module 5, specifically include: second switch transistor T2 and electric capacity C；Its
In,
The grid of second switch transistor T2 is connected with primary nodal point P1, the source of second switch transistor T2
Pole is connected with second clock signal end CLK, the drain electrode of second switch transistor T2 and signal output part
Output is connected；
Electric capacity C is connected between the grid of second switch transistor T2 and drain electrode.
Specifically, in the above-mentioned shift register cell that the embodiment of the present invention provides, as shown in Figure 3 a,
Second switch transistor T2 can be N-type transistor, or, as shown in Figure 3 b, second switch crystal
Pipe T2 can also be P-type transistor, in this no limit.Brilliant with second switch transistor T2 for N-type
As a example by body pipe, when the current potential of primary nodal point P1 is high potential, second switch transistor T2 is on shape
State, is connected second clock signal end CLK with signal output part Output；At second clock signal end CLK
Current potential when being high potential, the voltage signal of signal output part Output output high potential, due to electric capacity C
Boot strap and the existence of parasitic capacitance of second switch transistor T2, the electricity of signal output part Output
Position rising can make the current potential of primary nodal point P1 raise further, can improve second switch crystal further
The charging ability of pipe T2, it is ensured that the charging interval of pixel；Current potential at second clock signal end CLK is low
During current potential, the current potential of signal output part Output is electronegative potential.
More than it is merely illustrative of the concrete structure of the second output module 5 in shift register cell, specifically
During enforcement, the concrete structure of the second output module 5 is not limited to the said structure that the embodiment of the present invention provides, also
Can be other structures that skilled person will appreciate that, not limit at this.
In the specific implementation, in the above-mentioned shift register cell that the embodiment of the present invention provides, such as Fig. 3 a
Shown in Fig. 3 b, the 3rd output module 6, specifically may include that the 3rd switching transistor T3 and the 4th is opened
Close transistor T4；Wherein,
The grid of the 3rd switching transistor T3 is connected with secondary nodal point P2, the source of the 3rd switching transistor T3
Pole is connected with reference signal end Vref, and the drain electrode of the 3rd switching transistor T3 is connected with primary nodal point P1；
The grid of the 4th switching transistor T4 is connected with secondary nodal point P2, the source of the 4th switching transistor T4
Pole is connected with reference signal end Vref, the drain electrode of the 4th switching transistor T4 and signal output part Output
It is connected.
Specifically, in the above-mentioned shift register cell that the embodiment of the present invention provides, as shown in Figure 3 a,
3rd switching transistor T3 and the 4th switching transistor T4 can be N-type transistor, or, such as Fig. 3 b
Shown in, the 3rd switching transistor T3 and the 4th switching transistor T4 can also be P-type transistor, at this not
It is construed as limiting.As a example by the 3rd switching transistor T3 and the 4th switching transistor T4 are as N-type transistor,
When the current potential of secondary nodal point P2 is high potential, at the 3rd switching transistor T3 and the 4th switching transistor T4
In conducting state, reference signal end Vref is connected with primary nodal point P1 and signal output part Output respectively,
The current potential making primary nodal point P1 and signal output part Output is electronegative potential, and end Vref is the most right for reference signal
Primary nodal point P1 and signal output part Output carries out noise reduction.
More than it is merely illustrative of the concrete structure of the 3rd output module 6 in shift register cell, specifically
During enforcement, the concrete structure of the 3rd output module 6 is not limited to the said structure that the embodiment of the present invention provides, also
Can be other structures that skilled person will appreciate that, not limit at this.
In the specific implementation, in the above-mentioned shift register cell that the embodiment of the present invention provides, such as Fig. 4 a
Shown in Fig. 4 b, the 4th output module 7, specifically may include that the 5th switching transistor T5；
The grid of the 5th switching transistor T5 and the first clock signal terminal CLKB are connected, the 5th switch crystal
The source electrode of pipe T5 is connected with reference signal end Vref, and the drain electrode of the 5th switching transistor T5 exports with signal
End Output is connected.
Specifically, in the above-mentioned shift register cell that the embodiment of the present invention provides, as shown in fig. 4 a,
5th switching transistor T5 can be N-type transistor, or, as shown in Figure 4 b, the 5th switch crystal
Pipe T5 can also be P-type transistor, in this no limit.Brilliant with the 5th switching transistor T5 for N-type
As a example by body pipe, when the current potential of the first clock signal terminal CLKB is high potential, the 5th switching transistor T5
In the conduction state, reference signal end Vref is connected with signal output part Output, makes signal output part
The current potential of Output is electronegative potential, and reference signal end Vref carries out noise reduction to signal output part Output.
More than it is merely illustrative of the concrete structure of the 4th output module 7 in shift register cell, specifically
During enforcement, the concrete structure of the 4th output module 7 is not limited to the said structure that the embodiment of the present invention provides, also
Can be other structures that skilled person will appreciate that, not limit at this.
In the specific implementation, the embodiment of the present invention provide above-mentioned shift register cell in, as Fig. 3 a,
Shown in Fig. 3 b, Fig. 4 a and Fig. 4 b, input module 1, specifically may include that the 6th switching transistor T6
With the 7th switching transistor T7；
The grid of the 6th switching transistor T6 is connected with signal input part Input respectively with source electrode, the 6th switch
The drain electrode of transistor T6 is connected with primary nodal point P1；
The grid of the 7th switching transistor T7 and the first clock signal terminal CKLB are connected, the 7th switch crystal
The source electrode of pipe T7 is connected with signal input part Input, the outfan of the 7th switching transistor T7 and first segment
Point P1 is connected.
Specifically, in the above-mentioned shift register cell that the embodiment of the present invention provides, such as Fig. 3 a and Fig. 4 a
Shown in, the 6th switching transistor T6 and the 7th switching transistor T7 can be N-type transistor, or,
As is shown in figures 3b and 4b, the 6th switching transistor T6 and the 7th switching transistor T7 can also be P
Transistor npn npn, in this no limit.With the 6th switching transistor T6 and the 7th switching transistor T7 as N
As a example by transistor npn npn, when the current potential of signal input part Input is high potential, the 6th switching transistor T6
In the conduction state, input a signal into end Input and be connected with primary nodal point P1, make the electricity of primary nodal point P1
Position is high potential；When the current potential of the first clock signal terminal CLKB is high potential, the 7th switching transistor
T7 is in the conduction state, inputs a signal into end Input and is connected with primary nodal point P1；At signal input part Input
Current potential when being electronegative potential, the current potential making primary nodal point P1 is electronegative potential, at the electricity of signal input part Input
When position is high potential, the current potential making primary nodal point P1 is high potential.
More than it is merely illustrative of the concrete structure of input module 1 in shift register cell, is being embodied as
Time, the concrete structure of input module 1 is not limited to the said structure that the embodiment of the present invention provides, it is also possible to be this
Skilled person's other structures knowable, do not limit at this.
In the specific implementation, the embodiment of the present invention provide above-mentioned shift register cell in, as Fig. 3 a,
Shown in Fig. 3 b, Fig. 4 a and Fig. 4 b, reseting module 2, specifically may include that the 8th switching transistor T8
With the 9th switching transistor T9；Wherein,
The grid of the 8th switching transistor T8 is connected with reset signal end Reset, the 8th switching transistor T8
Source electrode be connected with reference signal end Vref, the drain electrode of the 8th switching transistor T8 and primary nodal point P1 phase
Even；
The grid of the 9th switching transistor T9 is connected with reset signal end Reset, the 9th switching transistor T9
Source electrode be connected with reference signal end Vref, the drain electrode of the 9th switching transistor T9 and signal output part Output
It is connected.
Specifically, in the above-mentioned shift register cell that the embodiment of the present invention provides, such as Fig. 3 a and Fig. 4 a
Shown in, the 8th switching transistor T8 and the 9th switching transistor T9 can be N-type transistor, or,
As is shown in figures 3b and 4b, the 8th switching transistor T8 and the 9th switching transistor T9 can also be P
Transistor npn npn, in this no limit.With the 8th switching transistor T8 and the 9th switching transistor T9 as N
As a example by transistor npn npn, when the current potential of reset signal end Reset is high potential, the 8th switching transistor T8
In the conduction state with the 9th switching transistor T9, by reference signal end Vref respectively with primary nodal point P1
Connecting with signal output part Output, the current potential making primary nodal point P1 and signal output part Output is low electricity
Position, reference signal end Vref carries out noise reduction to primary nodal point P1 and signal output part Output respectively.
More than it is merely illustrative of the concrete structure of reseting module 2 in shift register cell, is being embodied as
Time, the concrete structure of reseting module 2 is not limited to the said structure that the embodiment of the present invention provides, it is also possible to be this
Skilled person's other structures knowable, do not limit at this.
In the specific implementation, the embodiment of the present invention provide above-mentioned shift register cell in, as Fig. 3 a,
Shown in Fig. 3 b, Fig. 4 a and Fig. 4 b, control module 3, specifically may include that the tenth switching transistor T10,
11st switching transistor T11, twelvemo close transistor T12 and the 13rd switching transistor T13；Its
In,
The grid of the tenth switching transistor T10 is connected with primary nodal point P1, the tenth switching transistor T10
Source electrode is connected with reference signal end Vref, and the drain electrode of the tenth switching transistor T10 is connected with secondary nodal point P2；
The grid of the 11st switching transistor T11 is connected with primary nodal point P1, the 11st switching transistor T11
Source electrode be connected with reference signal end Vref, the drain electrode of the 11st switching transistor T11 and the 3rd node P3
It is connected；
Twelvemo is closed the grid of transistor T12 and is connected with the first clock signal terminal CLKB respectively with source electrode,
Twelvemo is closed the drain electrode of transistor T12 and is connected with the 3rd node P3；
The grid of the 13rd switching transistor T13 and the 3rd node P3 are connected, the 13rd switching transistor T13
Source electrode and the first clock signal terminal CLKB be connected, the drain electrode of the 13rd switching transistor T13 and second section
Point P2 is connected.
Specifically, in the above-mentioned shift register cell that the embodiment of the present invention provides, such as Fig. 3 a and Fig. 4 a
Shown in, the tenth switching transistor T10, the 11st switching transistor T11, twelvemo close transistor T12
Can be N-type transistor with the 13rd switching transistor T13, or, as is shown in figures 3b and 4b,
Tenth switching transistor T10, the 11st switching transistor T11, twelvemo close transistor T12 and the tenth
Three switching transistors T13 can also be P-type transistor, in this no limit.With the tenth switching transistor
T10, the 11st switching transistor T11, twelvemo close transistor T12 and the 13rd switching transistor T13
As a example by N-type transistor, when the current potential of primary nodal point P1 is high potential, the tenth switching transistor T10
In the conduction state with the 11st switching transistor T11, by reference signal end Vref and secondary nodal point P2 even
Connecing, the current potential making secondary nodal point P2 is electronegative potential, and secondary nodal point P2 is dropped by reference signal end Vref
Make an uproar；When the current potential of the first clock signal terminal CLKB is high potential, twelvemo is closed transistor T12 and is in
Conducting state, connects the first clock signal terminal CLKB and the 3rd node P3, makes the electricity of the 3rd node P3
Position is high potential, and now, the 13rd switching transistor T13 is in the conduction state, by the first clock signal terminal
CLKB is connected with secondary nodal point P2, and the current potential making secondary nodal point P2 is high potential.
More than it is merely illustrative of the concrete structure of control module 3 in shift register cell, is being embodied as
Time, the concrete structure of control module 3 is not limited to the said structure that the embodiment of the present invention provides, it is also possible to be this
Skilled person's other structures knowable, do not limit at this.
In the specific implementation, when signal input part Input, the first clock signal terminal CLKB and reset signal
When the effective impulse signal of end Reset input is high potential signal, the first switching transistor T1 can use P
Transistor npn npn, second switch transistor T2 to the 13rd switching transistor T13 can all use N-type crystal
Pipe；When having of signal input part Input, the first clock signal terminal CLKB and reset signal end Reset input
Effect pulse signal is when being low-potential signal, and the first switching transistor T1 can use N-type transistor, second
Switching transistor T2 can all use P-type transistor to the 13rd switching transistor T13；Do not limit at this
Fixed.
It should be noted that the switching transistor mentioned in the above embodiment of the present invention can be thin film transistor (TFT)
(TFT, Thin Film Transistor), it is also possible to be metal oxide semiconductor field effect tube (MOS,
Metal Oxide Semiconductor), do not limit at this.In being embodied as, these switching transistors
Source electrode and drain electrode according to transistor types and the difference of input signal, its function can be exchanged, at this not
Do concrete differentiation.
The above-mentioned shift register cell provided for the embodiment of the present invention, the embodiment of the present invention additionally provides one
Plant the driving method of shift register cell, including:
In the first stage, the signal inputting a signal into end under the control of the first clock signal terminal is supplied to first
Node, is supplied to signal output part by the signal of reference signal end under the control of primary nodal point；When first
Under the control of clock signal end, the signal of the first clock signal terminal is supplied to secondary nodal point, in the control of secondary nodal point
Under system, the signal of reference signal end is respectively supplied to primary nodal point and signal output part；
In second stage, the signal inputting a signal into end under the control of signal input part is supplied to first segment
Point, is supplied to signal output part by the signal of second clock signal end under the control of primary nodal point；First
Under the control of clock signal terminal, the signal of the first clock signal terminal is supplied to secondary nodal point, at secondary nodal point
Under control, the signal of reference signal end is respectively supplied to primary nodal point and signal output part；
In the phase III, under the control of primary nodal point, the signal of second clock signal end is supplied to signal defeated
Go out end, under the control of primary nodal point, the signal of reference signal end is supplied to secondary nodal point；
In fourth stage, under the control of reset signal end, the signal of reference signal end is respectively supplied to first
Node and signal output part, be supplied to signal output under the control of primary nodal point by the signal of reference signal end
End；Under the control of the first clock signal terminal, the signal of the first clock signal terminal is supplied to secondary nodal point,
Under the control of secondary nodal point, the signal of reference signal end is respectively supplied to primary nodal point and signal output part；
In the 5th stage, the signal of reference signal end is supplied to signal output under the control of primary nodal point
End.
The above-mentioned driving method that the embodiment of the present invention provides, under the control of the first clock signal terminal, signal is defeated
The signal entering end is supplied to primary nodal point, is supplied to by the signal of reference signal end under the control of primary nodal point
Signal output part, can drag down the current potential of signal output part；By reference signal under the control of reset signal end
The signal of end is respectively supplied to primary nodal point and signal output part, can drag down primary nodal point and signal output part
Current potential, under the control of primary nodal point, the signal of reference signal end is supplied to signal output part, Ke Yila
The current potential of low signal outfan；Under the control of the first clock signal terminal, the signal of the first clock signal terminal is carried
Supply secondary nodal point, is respectively supplied to primary nodal point by the signal of reference signal end under the control of secondary nodal point
And signal output part, the current potential of primary nodal point and signal output part can be dragged down, under the control of primary nodal point
The signal of reference signal end is supplied to signal output part, can drag down the current potential of signal output part, so,
The noise of the signal of the signal output part output of shift register cell can be reduced, it is ensured that signal output part is defeated
The stability of the signal gone out.
It is preferred that in the above-mentioned driving method that the embodiment of the present invention provides, also include:
In first stage, second stage and fourth stage, will be with reference to letter under the control of the first clock signal terminal
Number end signal be supplied to signal output part；As such, it is possible to drag down letter under the control of the first clock signal terminal
The current potential of number outfan, such that it is able to reduce the noise of the signal of signal output part output further, it is ensured that
The stability of the signal of signal output part output.
Below with the first switching transistor T1 as P-type transistor, second switch transistor T2 to the 13rd
As a example by switching transistor T13 is N-type transistor, the above-mentioned shift LD that the embodiment of the present invention is provided
The work process of the driving method of device unit is described.Such as, at the shift register list shown in Fig. 4 a
In unit, the first switching transistor T1 is P-type transistor, and second switch transistor T2 to the 13rd switchs
Transistor T13 is N-type transistor, and P-type transistor turns under electronegative potential effect, in high potential effect
Lower cut-off, each N-type transistor turns under high potential effect, ends under electronegative potential effect；Input signal
The effective impulse signal of end Input, the first clock signal terminal CLKB and reset signal end Reset is high potential
Signal, the signal of reference signal end Vref is low-potential signal.Input and output sequential chart corresponding for Fig. 4 a is such as
Shown in Fig. 5, specifically, five stages of t1～t5 in input and output sequential chart as shown in Figure 5 are chosen.
Representing high potential with 1 in described below, 0 represents electronegative potential.
At first stage t1, Input=0, Reset=0, owing to the current potential of signal input part Input is electronegative potential,
6th switching transistor T6 cut-off；Owing to the current potential of reset signal end Reset is electronegative potential, the 8th switch
Transistor T8 and the cut-off of the 9th switching transistor T9；At CLK=0, during CLKB=1, during due to first
The current potential of clock signal end CLKB is high potential, the 7th switching transistor T7 conducting, inputs a signal into end Input
Being connected with primary nodal point P1, the current potential making primary nodal point P1 is electronegative potential, now, and the first switching transistor
T1 turns on, and is connected with signal output part Output by reference signal end Vref, makes signal output part Output
Current potential be electronegative potential, reference signal end Vref carries out noise reduction to signal output part Output；Due to first
The current potential of clock signal terminal CLKB is high potential, and the 5th switching transistor T5 conducting, by reference signal end
Vref is connected with signal output part Output, and the current potential making signal output part Output is electronegative potential, reference
Signal end Vref carries out noise reduction to signal output part Output；Electricity due to the first clock signal terminal CLKB
Position be high potential, and twelvemo is closed transistor T12 and turned on, by the first clock signal terminal CLKB and Section three
Point P3 connects, and the current potential making the 3rd node P3 is high potential, the 13rd switching transistor T13 conducting, will
First clock signal terminal CLKB is connected with secondary nodal point P2, and the current potential making secondary nodal point P2 is high potential,
Now, the 3rd switching transistor T3 and the conducting of the 4th switching transistor T4, divide reference signal end Vref
It is not connected with primary nodal point P1 and signal output part Output, makes primary nodal point P1 and signal output part
The current potential of Output is electronegative potential, and reference signal end Vref is respectively to primary nodal point P1 and signal output part
Output carries out noise reduction；At CLK=1, during CLKB=0, owing to the current potential of primary nodal point P1 is electronegative potential,
Second switch transistor T2 ends, and the current potential of signal output part Output is electronegative potential；
In second stage t2, Input=1, Reset=0, CLK=0, CLKB=1, due to reset signal end
The current potential of Reset is electronegative potential, the 8th switching transistor T8 and the cut-off of the 9th switching transistor T9；Due to
The current potential of signal input part Input is high potential, the 6th switching transistor T6 conducting, inputs a signal into end
Input is connected with primary nodal point P1, and the current potential making primary nodal point P1 is high potential, now, to electric capacity C
Charging, second switch transistor T2 turns on, by second clock signal end CLK and signal output part Output
Connect, owing to the current potential of second clock signal end CLK is electronegative potential, make the electricity of signal output part Output
Position is still electronegative potential；Owing to the current potential of the first clock signal terminal CLKB is high potential, the 5th switching transistor
T5 turns on, and is connected with signal output part Output by reference signal end Vref, makes signal output part Output
Current potential be electronegative potential, reference signal end Vref carries out noise reduction to signal output part Output；Due to first
The current potential of clock signal terminal CLKB is high potential, and twelvemo closes transistor T12 conducting, by the first clock
Signal end CLKB and the 3rd node P3 connects, and the current potential making the 3rd node P3 is high potential, and the 13rd opens
Close transistor T13 conducting, the first clock signal terminal CLKB is connected with secondary nodal point P2, makes second section
The current potential of some P2 is high potential, now, and the 3rd switching transistor T3 and the conducting of the 4th switching transistor T4,
Reference signal end Vref is connected with primary nodal point P1 and signal output part Output respectively, makes primary nodal point
The current potential of P1 and signal output part Output is electronegative potential, and reference signal end Vref is respectively to primary nodal point P1
Noise reduction is carried out with signal output part Output；
At phase III t3, Input=0, Reset=0, CLK=1, CLKB=0, due to signal input part
The current potential of Input is electronegative potential, the 6th switching transistor T6 cut-off；Electricity due to reset signal end Reset
Position is electronegative potential, the 8th switching transistor T8 and the cut-off of the 9th switching transistor T9；Due to the first clock letter
Number end CLKB current potential be electronegative potential, the 5th switching transistor T5, the 7th switching transistor T7, the tenth
Two switching transistors T12 and the cut-off of the 13rd switching transistor T13；Due to the effect of electric capacity C, first
Node P1 still keeps high potential, owing to the current potential of second clock signal end CLK is high potential, makes signal defeated
The current potential going out to hold Output is high potential；Due to the boot strap of electric capacity C and second switch transistor T2
The existence of parasitic capacitance, the current potential rising of signal output part Output can make the current potential of primary nodal point P1 enter one
Step raises, and can improve the charging ability of second switch transistor T2 further, it is ensured that the charging of pixel
Time；Owing to the current potential of primary nodal point P1 is high potential, the tenth switching transistor T10 and the 11st switch
Transistor T11 turns on, and is connected with secondary nodal point P2 by reference signal end Vref, makes secondary nodal point P2's
Current potential is electronegative potential, and reference signal end Vref carries out noise reduction to secondary nodal point P2；
In fourth stage t4, Input=0, Reset=1, CLK=0, CLKB=1, due to signal input part
The current potential of Input is electronegative potential, the 6th switching transistor T6 cut-off；Electricity due to reset signal end Reset
Position is high potential, and the 8th switching transistor T8 and the conducting of the 9th switching transistor T9, by reference signal end
Vref is connected with primary nodal point P1 and signal output part Output respectively, makes primary nodal point P1 and signal defeated
The current potential going out to hold Output is electronegative potential, and primary nodal point P1 and signal are exported by reference signal end Vref respectively
End Output carries out noise reduction；Owing to the current potential of primary nodal point P1 is electronegative potential, the first switching transistor T1
Conducting, is connected reference signal end Vref with signal output part Output, makes signal output part Output's
Current potential is electronegative potential, and reference signal end Vref carries out noise reduction to signal output part Output；During due to first
The current potential of clock signal end CLKB is high potential, and twelvemo closes transistor T12 conducting, by the first clock letter
Number end CLKB and the 3rd node P3 connection, the current potential making the 3rd node P3 is high potential, now, the tenth
Three switching transistors T13 conductings, are connected the first clock signal terminal CLKB with secondary nodal point P2, make the
The current potential of two node P2 is high potential, now, and the 3rd switching transistor T3 and the 4th switching transistor T4
Conducting, is connected with primary nodal point P1 and signal output part Output respectively by reference signal end Vref, makes the
The current potential of one node P1 and signal output part Output is electronegative potential, and reference signal end Vref is respectively to first
Node P1 and signal output part Output carries out noise reduction；Owing to the current potential of the first clock signal terminal CLKB is
High potential, the 5th switching transistor T5 conducting, reference signal end Vref signal outfan Output is connected,
The current potential making signal output part Output is electronegative potential, and reference signal end Vref is to signal output part Output
Carry out noise reduction；
At the 5th stage t5, Input=0, Reset=0, CLK=1, CLKB=0, due to signal input part
The current potential of Input is electronegative potential, the 6th switching transistor T6 cut-off；Electricity due to reset signal end Reset
Position is electronegative potential, the 8th switching transistor T8 and the cut-off of the 9th switching transistor T9；Due to the first clock letter
Number end CLKB current potential be electronegative potential, the 5th switching transistor T5, the 7th switching transistor T7, the tenth
Two switching transistors T12 and the cut-off of the 13rd switching transistor T13；Owing to the current potential of primary nodal point P1 is
Electronegative potential, second switch transistor T2 ends, and the first switching transistor T1 conducting, by reference signal end
Vref signal outfan Output connects, and the current potential making signal output part Output is electronegative potential, with reference to letter
Number end Vref signal output part Output is carried out noise reduction.
At subsequent period of time, signal output part Output will export the voltage signal of electronegative potential always, until under
The arrival of one frame.
Above-mentioned be with the first switching transistor T1 as P-type transistor, second switch transistor T2 to the tenth
Three switching transistors T13 illustrate as a example by being N-type transistor, particularly for the first switching transistor
It is brilliant that T1 is N-type transistor, second switch transistor T2 to the 13rd switching transistor T13 is p-type
The operation principle of body pipe and above-mentioned first switching transistor T1 are P-type transistor, second switch transistor T2
The operation principle being N-type transistor to the 13rd switching transistor T13 is similar, does not repeats them here.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of gate driver circuit, such as Fig. 6 institute
Show, the above-mentioned shift register cell provided including the multiple embodiment of the present invention cascaded: SR (1),
SR (2) ... SR (n) ... SR (N-1), SR (N) (N number of shift register cell, 1≤n≤N altogether)；Wherein,
In addition to first order shift register cell SR (1), remaining every one-level shift register cell SR (n)
Signal output part Output_n (1≤n≤N) respectively and the upper level shift register cell that is adjacent
The reset signal end Reset of SR (n-1) is connected；
In addition to afterbody shift register cell SR (N), remaining every one-level shift register cell SR (n)
Signal output part Output_n (1≤n≤N) respectively and the next stage shift register cell that is adjacent
The signal input part Input of SR (n+1) is connected；
The signal input part Input of first order shift register cell SR (1) and frame start signal end STV phase
Even.
Specifically, each shift register cell in the above-mentioned gate driver circuit that the embodiment of the present invention provides
With the embodiment of the present invention provide above-mentioned shift register cell in function and structure the most identical, in place of repetition
Repeat no more.
Based on same inventive concept, embodiments provide a kind of display floater, implement including the present invention
The above-mentioned gate driver circuit that example provides.The enforcement of this display floater may refer to above-mentioned gate driver circuit
Implement, repeat no more in place of repetition.
Based on same inventive concept, embodiments provide a kind of display device, implement including the present invention
The above-mentioned display floater that example provides.This display device can apply to mobile phone, panel computer, television set, shows
Show any product with display function or the parts such as device, notebook computer, DPF, navigator.Should
The enforcement of display device may refer to the enforcement of above-mentioned display floater, repeats no more in place of repetition.
The embodiment of the present invention provide a kind of shift register cell, its driving method, gate driver circuit and
Display device, in this shift register cell, input module can control the current potential of primary nodal point so that
The signal of reference signal end is supplied to signal output part under the control of primary nodal point by the first output module, can
To drag down the current potential of signal output part so that the second output module can be by second under the control of primary nodal point
The signal of clock signal terminal is supplied to signal output part, it is ensured that the normal output of signal output part；Reseting module
Under the control of reset signal end, the signal of reference signal end can be supplied to signal output part, can drag down
The current potential of signal output part；Control module can control the current potential of secondary nodal point so that the 3rd output module exists
Under the control of secondary nodal point, the signal of reference signal end is supplied to signal output part, signal output can be dragged down
The current potential of end；As such, it is possible to reduce the noise of the signal output part output signal of shift register cell, protect
The stability of the signal of card signal output part output.
Obviously, those skilled in the art can carry out various change and modification without deviating from this to the present invention
Bright spirit and scope.So, if the present invention these amendment and modification belong to the claims in the present invention and
Within the scope of its equivalent technologies, then the present invention is also intended to comprise these change and modification.
Claims (13)
1. a shift register cell, it is characterised in that including: input module, reseting module, control
Molding block, the first output module, the second output module and the 3rd output module；Wherein,
First control end of described input module is connected with signal input part respectively with input, and second controls end
Being connected with the first clock signal terminal, outfan is connected with primary nodal point, for respectively at described first clock letter
Number end and described signal input part control under the signal of described signal input part is supplied to described first segment
Point；
The control end of described reseting module is connected with reset signal end, and input is connected with reference signal end, the
One outfan is connected with described primary nodal point, and the second outfan is connected with signal output part, for described multiple
Under the control of position signal end the signal of described reference signal end is respectively supplied to described primary nodal point and described
Signal output part；
First control end of described control module is connected with described primary nodal point, first input end and described reference
Signal end be connected, the first outfan is connected with secondary nodal point, second control end and the second input respectively with institute
Stating the first clock signal terminal to be connected, the second outfan is connected with described secondary nodal point, at described first segment
Under the control of point, the signal of described reference signal end is supplied to described secondary nodal point and when described first
Under the control of clock signal end, the signal of described first clock signal terminal is supplied to described secondary nodal point；
The control end of described first output module is connected with described primary nodal point, input and described reference signal
End is connected, and outfan is connected with described signal output part, is used for described under the control of described primary nodal point
The signal of reference signal end is supplied to described signal output part；
The control end of described second output module is connected with described primary nodal point, input and second clock signal
End is connected, and outfan is connected with described signal output part, is used for described under the control of described primary nodal point
The signal of second clock signal end is supplied to described signal output part；
The control end of described 3rd output module is connected with described secondary nodal point, input and described reference signal
End is connected, and the first outfan is connected with described primary nodal point, and the second outfan is connected with described signal output part,
For the signal of described reference signal end being respectively supplied to described first under the control of described secondary nodal point
Node and described signal output part.
2. shift register cell as claimed in claim 1, it is characterised in that also include: the 4th is defeated
Go out module；
The control end of described 4th output module is connected with described first clock signal terminal, input and described ginseng
Examining signal end to be connected, outfan is connected with described signal output part, at described first clock signal terminal
Under control, the signal of described reference signal end is supplied to described signal output part.
3. shift register cell as claimed in claim 1, it is characterised in that described first output mould
Block, specifically includes: the first switching transistor；
The grid of described first switching transistor is connected with described primary nodal point, described first switching transistor
Source electrode is connected with described reference signal end, the drain electrode of described first switching transistor and described signal output part phase
Even.
4. shift register cell as claimed in claim 1, it is characterised in that described second output mould
Block, specifically includes: second switch transistor and electric capacity；Wherein,
The grid of described second switch transistor is connected with described primary nodal point, described second switch transistor
Source electrode is connected with described second clock signal end, and the drain electrode of described second switch transistor exports with described signal
End is connected；
Described electric capacity is connected between the grid of described second switch transistor and drain electrode.
5. shift register cell as claimed in claim 1, it is characterised in that described 3rd output mould
Block, specifically includes: the 3rd switching transistor and the 4th switching transistor；Wherein,
The grid of described 3rd switching transistor is connected with described secondary nodal point, described 3rd switching transistor
Source electrode is connected with described reference signal end, the drain electrode of described 3rd switching transistor and described primary nodal point phase
Even；
The grid of described 4th switching transistor is connected with described secondary nodal point, described 4th switching transistor
Source electrode is connected with described reference signal end, the drain electrode of described 4th switching transistor and described signal output part phase
Even.
6. shift register cell as claimed in claim 2, it is characterised in that described 4th output mould
Block, specifically includes: the 5th switching transistor；
The grid of described 5th switching transistor is connected with described first clock signal terminal, described 5th switch crystalline substance
The source electrode of body pipe is connected with described reference signal end, and the drain electrode of described 5th switching transistor is defeated with described signal
Go out end to be connected.
7. shift register cell as claimed in claim 1, it is characterised in that described input module,
Specifically include: the 6th switching transistor and the 7th switching transistor；
The grid of described 6th switching transistor is connected with described signal input part respectively with source electrode, and the described 6th
The drain electrode of switching transistor is connected with described primary nodal point；
The grid of described 7th switching transistor is connected with described first clock signal terminal, described 7th switch crystalline substance
The source electrode of body pipe is connected with described signal input part, the outfan and described first of described 7th switching transistor
Node is connected.
8. shift register cell as claimed in claim 1, it is characterised in that described reseting module,
Specifically include: the 8th switching transistor and the 9th switching transistor；Wherein,
The grid of described 8th switching transistor is connected with described reset signal end, described 8th switching transistor
Source electrode be connected with described reference signal end, the drain electrode of described 8th switching transistor and described primary nodal point phase
Even；
The grid of described 9th switching transistor is connected with described reset signal end, described 9th switching transistor
Source electrode be connected with described reference signal end, the drain electrode of described 9th switching transistor and described signal output part
It is connected.
9. shift register cell as claimed in claim 1, it is characterised in that described control module,
Specifically include: the tenth switching transistor, the 11st switching transistor, twelvemo close transistor and the 13rd
Switching transistor；Wherein,
The grid of described tenth switching transistor is connected with described primary nodal point, described tenth switching transistor
Source electrode is connected with described reference signal end, the drain electrode of described tenth switching transistor and described secondary nodal point phase
Even；
The grid of described 11st switching transistor is connected with described primary nodal point, described 11st switch crystal
The source electrode of pipe is connected with described reference signal end, the drain electrode of described 11st switching transistor and described Section three
Point is connected；
Described twelvemo is closed the grid of transistor and is connected with described first clock signal terminal respectively with source electrode, institute
The drain electrode stating twelvemo pass transistor is connected with described 3rd node；
The grid of described 13rd switching transistor is connected with described 3rd node, described 13rd switch crystal
The source electrode of pipe is connected with described first clock signal terminal, the drain electrode of described 13rd switching transistor and described the
Two nodes are connected.
10. a driving method for the shift register cell as described in any one of claim 1-9, it is special
Levy and be, including:
In the first stage, the signal inputting a signal into end under the control of the first clock signal terminal is supplied to first
Node, is supplied to signal output part by the signal of reference signal end under the control of described primary nodal point；Institute
State, under the control of the first clock signal terminal, the signal of described first clock signal terminal is supplied to secondary nodal point,
Under the control of described secondary nodal point, the signal of described reference signal end is respectively supplied to described primary nodal point and
Described signal output part；
In second stage, under the control of described signal input part, the signal of described signal input part is supplied to
Described primary nodal point, is supplied to described under the control of described primary nodal point by the signal of second clock signal end
Signal output part；Under the control of described first clock signal terminal, the signal of described first clock signal terminal is carried
Supply described secondary nodal point, under the control of described secondary nodal point, the signal of described reference signal end is carried respectively
Supply described primary nodal point and described signal output part；
In the phase III, under the control of described primary nodal point, the signal of described second clock signal end is provided
To described signal output part, under the control of described primary nodal point, the signal of described reference signal end is supplied to
Described secondary nodal point；
In fourth stage, under the control of described reset signal end, the signal of described reference signal end is carried respectively
Supply described primary nodal point and described signal output part, by described with reference to letter under the control of described primary nodal point
Number end signal be supplied to described signal output part；By described under the control of described first clock signal terminal
The signal of one clock signal terminal is supplied to described secondary nodal point, by described ginseng under the control of described secondary nodal point
The signal examining signal end is respectively supplied to described primary nodal point and described signal output part；
In the 5th stage, under the control of described primary nodal point, the signal of described reference signal end is supplied to institute
State signal output part.
11. driving methods as claimed in claim 10, it is characterised in that also include:
In first stage, second stage and fourth stage, by institute under the control of described first clock signal terminal
The signal stating reference signal end is supplied to described signal output part.
12. 1 kinds of gate driver circuits, it is characterised in that include that the multiple of cascade appoint such as claim 1-9
One described shift register cell；Wherein,
In addition to first order shift register cell, the described signal of remaining every one-level shift register cell is defeated
Go out end to be connected with the described reset signal end of the upper level shift register cell being adjacent respectively；
In addition to afterbody shift register cell, the described signal of remaining every one-level shift register cell
Outfan described signal input part with the next stage shift register cell being adjacent respectively is connected；
The described signal input part of first order shift register cell is connected with frame start signal end.
13. 1 kinds of display devices, it is characterised in that including: raster data model as claimed in claim 12
Circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610425494.7A CN105845097A (en) | 2016-06-15 | 2016-06-15 | Shift register unit, driving method of shift register unit, gate drive circuit and display device |
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| CN201610425494.7A CN105845097A (en) | 2016-06-15 | 2016-06-15 | Shift register unit, driving method of shift register unit, gate drive circuit and display device |
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