CN105826249A - Metal layer manufacturing method, functional substrate and manufacturing method thereof, and display device - Google Patents

Metal layer manufacturing method, functional substrate and manufacturing method thereof, and display device Download PDF

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Publication number
CN105826249A
CN105826249A CN201610221405.7A CN201610221405A CN105826249A CN 105826249 A CN105826249 A CN 105826249A CN 201610221405 A CN201610221405 A CN 201610221405A CN 105826249 A CN105826249 A CN 105826249A
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China
Prior art keywords
insulating barrier
metal level
manufacture method
etching
substrate
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CN201610221405.7A
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Chinese (zh)
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CN105826249B (en
Inventor
张小祥
罗丽平
刘明悬
郭会斌
张治超
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Priority to CN201610221405.7A priority Critical patent/CN105826249B/en
Publication of CN105826249A publication Critical patent/CN105826249A/en
Priority to US15/541,580 priority patent/US10209584B2/en
Priority to PCT/CN2017/000062 priority patent/WO2017177725A1/en
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Publication of CN105826249B publication Critical patent/CN105826249B/en
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
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    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
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    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • H10K50/865—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. light-blocking layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/38—Anti-reflection arrangements
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

The invention relates to a metal layer manufacturing method, a functional substrate and manufacturing method thereof, and a display device. The metal layer manufacturing method includes the steps of: forming an insulating layer on a substrate; forming an etching buffer layer on the insulating layer; patterning the etching buffer layer and insulating layer so as to form a plurality of recessed micro-structures in the insulating layer; stripping the etching buffer layer; and forming a metal layer on the insulating layer, and forming raised parts filled to the plurality of recessed micro-structures on the surface of the metal layer close to the insulating layer. The metal layer manufacturing method can form a metal layer having an anti-reflection effect.

Description

Metal level manufacture method, function substrate and preparation method thereof and display device
Technical field
Embodiments of the invention relate to a kind of metal level manufacture method, function substrate and preparation method thereof and display device.
Background technology
Metal electrode and plain conductor are widely used in the display device such as liquid crystal display (LiquidCrystalDisplay, LCD) and OLED (OrganicLightEmittingDiodeDisplay, OLED).Such as, in common liquid crystal display, its array base palte includes grid, grid line, source-drain electrode or the data wire being made of metal.It addition, generally also include the touch control electrode being made of metal in the display device have touch controllable function.
In field of display devices, generally, metal electrode and plain conductor are by first forming a metal level on underlay substrate, then utilize patterning processes to pattern this metal level and are formed.Owing to the reflecting power of metal level is relatively strong, therefore, metal electrode and plain conductor have stronger reflecting power.
Summary of the invention
The present invention at least one embodiment provides a kind of metal level manufacture method, function substrate and preparation method thereof and display device.The manufacture method of this metal level is by forming insulating barrier under the metal layers, and forming multiple recessed micro structure on which insulating layer so that the metal level that is formed at this insulating barrier closes on to be formed on the surface of this insulating barrier is filled into the bossing of multiple recessed micro structure, thus form matsurface.Metal level closes on the surface of this insulating barrier can be emitted onto the luminous reflectance on this surface to different directions, can be used for solving the reflective problem of minute surface of metal level.
At least one embodiment of the present invention provides the manufacture method of a kind of metal level, comprising: form insulating barrier on underlay substrate；Described insulating barrier is formed etching cushion；Pattern described etching cushion and described insulating barrier to form multiple recessed micro structure in described insulating barrier；Peel off described etching cushion；And on described insulating barrier, forming metal level, described metal level closes on and is formed with the bossing being filled into the plurality of recessed micro structure on the surface of described insulating barrier.
Such as, in the manufacture method of a kind of metal level of one embodiment of the invention offer, described etching cushion forms photoresist；Utilize mask plate that described photoresist is exposed, develop and form photoetching agent pattern；For mask, described etching cushion and described insulating barrier are performed etching with described photoetching agent pattern, thus pattern described etching cushion and described insulating barrier to form multiple recessed micro structure in described insulating barrier.
Such as, in the manufacture method of a kind of metal level of one embodiment of the invention offer, during performing etching described etching cushion and described insulating barrier with described photoetching agent pattern for mask, the etch rate of described etching cushion is more than or equal to the etch rate of described insulating barrier.
Such as, in the manufacture method of a kind of metal level of one embodiment of the invention offer, the plurality of recessed micro structure includes micropore or very low power.
Such as, in the manufacture method of a kind of metal level provided in one embodiment of the invention, described micropore includes rounding taper hole, inversed taper platform hole or half ball.
Such as, in the manufacture method of a kind of metal level of one embodiment of the invention offer, the plurality of recessed micro structure is regularly arranged.
Such as, in the manufacture method of a kind of metal level of one embodiment of the invention offer, described etching cushion includes deep ultraviolet extinction oxide.
Such as, in the manufacture method of a kind of metal level of one embodiment of the invention offer, the thickness of described insulating barrier is
Such as, in the manufacture method of a kind of metal level of one embodiment of the invention offer, the plurality of recessed micro structure runs through or non-through in described insulating barrier.
At least one embodiment of the present invention provides the manufacture method of a kind of function substrate, comprising: form metal level on underlay substrate；And patterning described metal level to form conductive structure, described metal level uses the manufacture method of the described metal level of any of the above-described item to be formed.
Such as, in the manufacture method of a kind of function substrate of one embodiment of the invention offer, described conductive structure includes grid line, grid, data wire, source electrode, drain electrode or touch control electrode.
At least one embodiment of the present invention provides a kind of function substrate, comprising: underlay substrate, the insulating barrier being arranged on described underlay substrate and be arranged on the conductive structure on described insulating barrier；Described conductive structure includes metal level, has multiple recessed micro structure in described insulating barrier, and described metal level closes on and is formed with the bossing being filled into the plurality of recessed micro structure on the surface of described insulating barrier.
Such as, in a kind of function substrate that one embodiment of the invention provides, the plurality of recessed micro structure includes micropore or very low power.
Such as, in a kind of function substrate that one embodiment of the invention provides, described micropore includes rounding taper hole, inversed taper platform hole or half ball.
Such as, in a kind of function substrate that one embodiment of the invention provides, the plurality of recessed micro structure is regularly arranged.
Such as, in a kind of function substrate that one embodiment of the invention provides, described etching cushion includes deep ultraviolet extinction oxide.
Such as, in a kind of function substrate that one embodiment of the invention provides, the thickness of described insulating barrier is
Such as, in a kind of function substrate that one embodiment of the invention provides, the plurality of recessed micro structure runs through or non-through in described insulating barrier.
Such as, in a kind of function substrate that one embodiment of the invention provides, described conductive structure includes: grid line, grid, data wire, source electrode, drain electrode or touch control electrode.
At least one embodiment of the present invention provides a kind of display device, and it includes the function substrate described in any of the above-described item.
Such as, the display device of the offer of one embodiment of the invention also includes: color membrane substrates, liquid crystal layer, wherein, described liquid crystal layer is arranged between described function substrate and described color membrane substrates, and described function substrate is away from the exiting surface that one side is this display device of described liquid crystal layer.
Accompanying drawing explanation
In order to be illustrated more clearly that the technical scheme of disclosure embodiment, the accompanying drawing of embodiment will be briefly described below, it should be apparent that, the accompanying drawing in describing below merely relates to some embodiments of the disclosure, rather than restriction of this disclosure.
The flow chart of the manufacture method of a kind of metal level that Fig. 1 provides for one embodiment of the invention；
The schematic diagram forming insulating barrier on underlay substrate that Fig. 2 provides for one embodiment of the invention；
The schematic diagram forming etching cushion on the insulating layer that Fig. 3 provides for one embodiment of the invention；
The patterning that Fig. 4 a-4b provides for one embodiment of the invention etches cushion and the schematic diagram of insulating barrier；
The schematic diagram peeling off etching cushion that Fig. 5 provides for one embodiment of the invention；
The schematic diagram forming metal level on the insulating layer that Fig. 6 provides for one embodiment of the invention；
The patterning that Fig. 7 a-7c provides for one embodiment of the invention etches cushion and the process flow diagram of insulating barrier；
The floor map of multiple recessed micro structures in insulating barrier that Fig. 8 a-8d provides for one embodiment of the invention and insulating barrier；
The schematic diagram forming metal level on underlay substrate that Fig. 9 provides for one embodiment of the invention；
The schematic diagram of a kind of function substrate that Figure 10 provides for one embodiment of the invention；
The part plan schematic diagram of the another kind of function substrate that Figure 11 a provides for one embodiment of the invention；
Another kind of function substrate generalized section in C-C ' direction along Figure 11 a that Figure 11 b provides for one embodiment of the invention；
The floor map of touch control electrode in a kind of function substrate that Figure 12 provides for one embodiment of the invention；And
The schematic diagram of a kind of display device that Figure 13 provides for one embodiment of the invention.
Reference:
100-function substrate；101-underlay substrate；102-insulating barrier；1020-micro structure；1021-micropore；1022-very low power；The very low power of 1023-bending；103-etches cushion；104-metal level；1040-bossing；105-photoresist；106-photoetching agent pattern；107-conductive structure；1071-grid line；1072-grid；1073-data wire；1074-source electrode；1075-drains；1076-touch control electrode；108-mask plate；111-gate insulator；Another insulating barrier of 112-；113-flatness layer；114-pixel electrode；115-active layer pattern；116-via；150-exiting surface；200-color membrane substrates；300-liquid crystal layer.
Detailed description of the invention
For making the purpose of disclosure embodiment, technical scheme and advantage clearer, below in conjunction with the accompanying drawing of disclosure embodiment, the technical scheme of disclosure embodiment is clearly and completely described.Obviously, described embodiment is a part of this disclosure embodiment rather than whole embodiments.Embodiment of the disclosure based on described, the every other embodiment that those of ordinary skill in the art are obtained on the premise of without creative work, broadly fall into the scope of disclosure protection.
Unless otherwise defined, the disclosure use technical term or scientific terminology should be disclosure art in there is the ordinary meaning that the personage of general technical ability is understood." first ", " second " and the similar word that use in the disclosure are not offered as any order, quantity or importance, and are used only to distinguish different ingredients." include " or word that " comprising " etc. is similar means to occur that the element before this word or object are contained and occurs in the element of this word presented hereinafter or object and equivalent thereof, and be not excluded for other elements or object." connect " or word that " being connected " etc. is similar is not limited to physics or machinery connection, but electrical connection can be included, no matter be direct or indirectly.
Along with people constantly pursue for the display quality of display device, improve the focus that display quality becomes production firm and market is chased the most further.In common display device, the most in a liquid crystal display, its array base palte includes grid, grid line, source electrode, drain electrode or the data wire etc. being made of metal.These metal electrodes or plain conductor have stronger reflecting power, when light is irradiated on these metal electrodes and plain conductor, can produce direct reflection, thus affect display quality.After deliberation, present inventor thinks under study for action the surface of grid, grid line, source electrode, drain electrode or data wire is made matsurface, it is possible to resolve above-mentioned reflective problem, thus can improve display quality.But, these grids, grid line, source electrode, drain electrode or data wire are typically be formed directly on the array base palte of fragility and have less size, and common rough surface metallization processes is difficult to play a role.
Embodiments of the invention provide a kind of metal level manufacture method, function substrate and preparation method thereof and display device.The manufacture method of this metal level includes: form insulating barrier on underlay substrate；Form etching cushion on the insulating layer；Patterning etching cushion and insulating barrier are to form multiple recessed micro structure in a insulating layer；Peel off etching cushion；And forming metal level on the insulating layer, metal level closes on and is formed with the bossing being filled into multiple recessed micro structures on the surface of insulating barrier.It is filled into the bossing of micro structure owing to metal level closes on to be formed with on the surface of this insulating barrier, the luminous reflectance on this surface can be emitted onto to different directions, it is possible to resolve the specular reflection problems of metal level.
Below in conjunction with the accompanying drawings, the metal level manufacture method, function substrate and preparation method thereof and the display device that provide the embodiment of the present invention illustrate.
Embodiment one
The present embodiment provides the manufacture method of a kind of metal level, as it is shown in figure 1, it comprises the following steps 110～150.
Step 110: as shown in Figure 2, it is provided that underlay substrate 101, forms insulating barrier 102 on underlay substrate 101.
Such as, underlay substrate 101 can be glass substrate, quartz base plate, resin substrate or other substrates；The material of insulating barrier 102 can be silicon nitride (SiNx), silicon oxide (SiOX), silicon oxynitride (SiNxOy) or other insulant.
Step 120: as it is shown on figure 3, form etching cushion 103 on insulating barrier 102.
Such as, etching cushion 103 can include deep ultraviolet extinction oxide (deepultravioletlight-absorbingoxide, DUO), and specifically, etching cushion 103 can include organic siloxane polymer.
Step 130: patterning etching cushion 103 and insulating barrier 102 are to form multiple recessed micro structure 1020 in insulating barrier 102.
Such as, as shown in fig. 4 a, multiple recessed micro structures 1020 run through insulating barrier 102；Or, as shown in Figure 4 b, insulating barrier 102 is not run through, and the multiple recessed micro structure 1020 formed is formed at the top of insulating barrier 102.
Step 140: as it is shown in figure 5, peel off etching cushion 103.
Step 150: as shown in Figure 6, forms metal level 104 on insulating barrier 102, and metal level 104 closes on and is formed with the bossing 1040 being filled into multiple recessed micro structures 1020 on the surface of insulating barrier 102.
It should be noted that closing in the present embodiment refers to close, the close meaning；Recessed micro structure 1020 refers to removed part in insulating barrier 120 in patterning process in step 130；It addition, bossing 140 cooperates with recessed micro structure 1020 shape.
Such as, metal level 104 can be arbitrary monolayer or the most several lamination in chromium, molybdenum, aluminum, copper, aluminum, aluminium alloy, copper, copper alloy etc..
In the manufacture method of the metal level of the present embodiment offer, on insulating barrier 102, multiple recessed micro structure 1020 is etched by etching agent, then on insulating barrier 102, metal level 104 is formed so that the metal level 104 being formed on insulating barrier 102 closes on and is formed with the bossing 1040 being filled into multiple recessed micro structures 1020 on the surface of insulating barrier 102；It is to say, it is matsurface that metal level 104 closes on the surface of insulating barrier 102；When light is irradiated to the surface that metal level 104 closes on insulating barrier 102, light is reflected to all directions, it is to avoid produce overall direct reflection；Thus, metal level 104 closes on the surface of insulating barrier 102 and can play the effect of reflection-proof.Additionally, in display field, the etching precision of etching technics is typically about 2 μm, in order to be formed, there is smaller size of multiple recessed micro structure 1020, as shown in Fig. 4 a-4b, the etching cushion 103 formed on insulating barrier 102 can make the etched channels being formed in etching cushion 103 and insulating barrier 102 have V-shaped or inverted trapezoidal by controlling the time of the dosage of etching agent or etching so that the multiple recessed micro structure 1020 being formed in insulating barrier 102 be smaller in size than 2 μm.It should be noted that above-mentioned etched channels is being perpendicular on the direction of underlay substrate 101, after referring to etching agent etching etching cushion 103 and insulating barrier 102, the through hole that stays.
Such as, in the manufacture method of the metal level of the present embodiment one example offer, patterning etching cushion 103 and insulating barrier 102 include step 131～133 in detail below with the step 130 forming multiple recessed micro structure 1020 in insulating barrier 102.
Step 131: as shown in Figure 7a, forms photoresist 105 on etching cushion 103.
Step 132: as shown in Figure 7b, utilizes mask plate 108 to be exposed photoresist 105, develops to obtain photoetching agent pattern 106.
Step 133: as shown in Figure 7 c, performs etching etching cushion 103 and insulating barrier 102 with photoetching agent pattern 106 for mask, thus patterns etching cushion 103 and insulating barrier 102 to form multiple recessed micro structure 1020 in insulating barrier 102.
Such as, in the manufacture method of the metal level of the present embodiment one example offer, during performing etching etching cushion 103 and insulating barrier 102 with photoetching agent pattern 106 for mask, the etch rate of etching cushion 103 is more than or equal to the etch rate of insulating barrier 102.It is to say, can etch etching cushion 103 and time the etching agent of insulating barrier 102 performs etching using simultaneously, etching cushion 103 is set greater than equal to insulating barrier 102 relative to the etch rate of this etching agent relative to the etch rate of this etching agent.Thus, after etching agent has etched etching cushion 103, etching agent will not increase in the size of the etched channels of the formation of etching insulating layer 102, so that the multiple recessed micro structure 1020 being formed in insulating barrier 102 is smaller.Additionally, when the etch rate etching cushion 103 is equal to the etch rate of insulating barrier 102, the etched channels being formed in etching cushion 103 and insulating barrier 102 can have relatively regular V-shaped or inverted trapezoidal, beneficially controls the size of the multiple recessed micro structure 1020 being formed in insulating barrier 102.It should be noted that, the etch rate of etching cushion 103 can realize by choosing the material with different etching speed for same etching agent more than or equal to the etch rate of insulating barrier 102, or, realize by having the etching agent of different etching speed for the material selection of etching cushion 103 with insulating barrier 102.Certainly, the etch rate of etching cushion 103 may be alternatively provided as the etch rate less than insulating barrier 102, and the embodiment of the present invention does not limits at this.It addition, above-mentioned is essentially equal equal to being not limited to, it is possible to include that the etch rate etching cushion 103 is etching the situation within the 5% of etch rate of cushion 103 with the difference of the etch rate of insulating barrier 102.
Such as, in the manufacture method of the metal level of the present embodiment one example offer, multiple recessed micro structures 1020 can include micropore 1021 or very low power 1022, correspondingly make the bossing 1040 being filled into multiple recessed micro structure 1020 include small projection or raised line, thus the directional light being emitted onto projection or raised line reflexes to different directions.
Such as, Fig. 8 a-8d is insulating barrier 102 and is formed at the floor map of multiple recessed micro structures 1020 in insulating barrier 102, and as shown in Figure 8 a, the multiple recessed micro structure 1020 in insulating barrier 102 includes micropore 1021；As shown in Figure 8 b, the multiple recessed micro structure 1020 in insulating barrier 102 includes very low power 1022.Reflex to more different directions to be emitted onto bossing 1040, the multiple recessed micro structure 1020 in insulating barrier 102 can be set to more complicated structure；Such as, as shown in Figure 8 c, the multiple recessed micro structure 1020 in insulating barrier 102 can include the very low power 1023 of bending；As shown in figure 8d, the multiple recessed micro structure 1020 in insulating barrier 102 can include micropore 1021 and the combination of very low power 1022.Even so, embodiments of the invention are not limited to the above-mentioned situation illustrated.
Such as, above-mentioned micropore 1021 can include rounding taper hole, inversed taper platform hole or half ball etc..Correspondingly, the bossing 1040 being filled into above-mentioned micropore 1021 can include circular cone, frustum or hemisphere etc..
Such as, in the manufacture method of the metal level of the present embodiment one example offer, multiple recessed micro structures 1020 are regularly arranged.It should be noted that above-mentioned regularly arranged refer to multiple recessed micro structure 1020 in distribution in accordance with certain mode or with certain pattern period arrangement.
Such as, in the manufacture method of the metal level of the present embodiment one example offer, the thickness of insulating barrier 102 can beIt should be noted that, when the thickness of insulating barrier is configured to relatively thin, if directly etching micro structure in a insulating layer, owing in etching technics, the dosage of etching agent is relative to reasons such as the relatively thin more difficult controls of insulating barrier, the micro structure of formation is difficult to metal electrode or the wire being applicable to inherently have reduced size.Therefore, when the thickness of insulating barrier is configured to relatively thin, etching cushion may also operate as the effect consuming the etching agent of excess, so that a small amount of etching agent can arrive insulating barrier, thus etches small micro structure.
Embodiment two
The present embodiment provides the manufacture method of a kind of function substrate, comprises the following steps 210～220.
Step 210: as it is shown in figure 9, use the manufacture method of arbitrary metal level of above-described embodiment one offer to form metal level 104 on underlay substrate 101.
Such as, underlay substrate 101 can be glass substrate, quartz base plate, resin substrate or other substrates；Metal level 104 is chromium, molybdenum, aluminum, copper, aluminum, aluminium alloy, copper, arbitrary monolayer or the most several laminations in copper alloy etc..
Step 220: as shown in Figure 10, patterned metal layer 104 is to form conductive structure 107.
Such as, above-mentioned patterning can include coating photoresist, exposing, develop, etch and the step of stripping photoresist.
In the manufacture method of the function substrate of the present embodiment offer, owing to have employed the manufacture method of the metal level that above-described embodiment one provides, metal level 104 is formed with bossing 1040 on the surface of underlay substrate 101.It is to say, metal level 104 is matsurface near the surface of underlay substrate 101.Thus, by patterning conductive structure 107 that this metal level 104 formed near the surface of underlay substrate 101 also for matsurface.When light is irradiated to conductive structure 107 near the surface of underlay substrate 101, light is reflected to all directions.Thus, conductive structure 107 can play, near the surface of underlay substrate 101, the effect that anti-minute surface is reflective.
Such as, the manufacture method of the function substrate that the present embodiment one example provides may be used for making liquid crystal display (LiquidCrystalDisplay, or the array base palte of the display device such as OLED (OrganicLightEmittingDiodeDisplay, OLED) LCD).
Such as, as shown in fig. 11a, conductive structure 107 can include grid line 1071 and grid 1072；Grid line 1071 can be formed by patterning same layer metal level with grid 1072.Specifically, as shown in figure 11b, the manufacture method of the function substrate that the present embodiment provides comprises the steps that the manufacture method using the metal level described in embodiment one forms gate metal layer on underlay substrate 101, and pattern gate metal layer is to form grid line 1071 and grid 1072.
Such as, as shown in fig. 11a, conductive structure 107 may also comprise data wire 1073, source electrode 1074 or drain electrode 1075.Such as, as shown in figure 11b, the manufacture method of the function substrate that the present embodiment provides comprises the steps that formation gate insulator 111 on underlay substrate 101, grid line 1071 and grid 1072；On gate insulator 111, just position to grid 1072 is formed with active layer pattern 115；On gate insulator 111 and active layer pattern 115, source and drain metal level is formed by the manufacture method of the arbitrary metal level described in embodiment one；Pattern this source and drain metal level and set up separately in the both sides of active layer pattern 115 to form data wire 1073, source electrode 1074 and drain electrode 1075, this source electrode 1074 and drain electrode 1075.
Such as, as shown in figure 11b, the manufacture method of the function substrate that the present embodiment provides may also include that formation flatness layer 113 on the substrate of above-mentioned formation；The via 116 connecting drain electrode 1075 is formed in flatness layer 113；And on flatness layer 113, forming pixel electrode 114, this pixel electrode 114 is by via 116 and drain electrode 1074 electric connection.
Such as, as shown in figure 12, in order to realize touch controllable function, as a example by the touch electrode structure of self-capacitance, conductive structure 107 can include touch control electrode 1076.Specifically, the manufacture method of the function substrate that the present embodiment provides may also include the step forming touch control electrode 1076.Owing to touch control electrode 1076 can pattern formation by being initially formed metal level equally the most again, its concrete forming step does not repeats them here.Certainly, conductive structure 107 also can include the touch control electrode of mutual capacitance, and this is not restricted.Such as, the touch control electrode of mutual capacitance includes multiple touch-control drive electrode and multiple touch-control sensing electrode, and multiple touch-control drive electrodes can be arranged in parallel in the first direction, and multiple touch-control sensing electrodes can be arranged in parallel in a second direction, and first direction is perpendicular to second direction.Multiple touch-control drive electrodes and multiple touch-control sensing electrode mutually insulateds, such as, be provided with insulating barrier between layer and the layer at multiple touch-control sensing electrode place at multiple touch-control drive electrode places.
It should be noted that the present embodiment includes but not limited to make the function substrate of said structure, the manufacture method of the function substrate that the present embodiment provides can be also used for making the function substrate of other structures.
In the manufacture method of the function substrate of the present embodiment offer, the size of grid line, grid, data wire, source electrode, drain electrode and touch control electrode typically only several microns to tens microns, but, in display field, the etching precision of etching technics is typically about 2 μm.If directly using etching technics to etch micro structure on the insulating layer, due to the restriction of etching precision, these micro structures seem bigger relative to the size of grid line, grid, data wire, source electrode, drain electrode and touch control electrode.So that the effect of the rough surface of grid line, grid, data wire, source electrode, drain electrode and touch control electrode is more preferable, formation is needed to have smaller size of multiple recessed micro structure.The etching cushion formed on the insulating layer can make the etched channels being formed in etching cushion and insulating barrier have V-shaped or inverted trapezoidal by controlling the time of the dosage of etching agent or etching, so that form multiple recessed micro structure in a insulating layer is smaller in size than 2 μm.It addition, when the manufacture method of the function substrate that the present embodiment provides uses the manufacture method of arbitrary metal level of embodiment one offer, it has the beneficial effect corresponding with the manufacture method of this metal level, does not repeats them here.
Embodiment three
A kind of function substrate of the present embodiment offer, as shown in Figure 10, comprising: underlay substrate 101, the insulating barrier 102 being arranged on underlay substrate 101 and the conductive structure 107 being arranged on insulating barrier 102.Conductive structure 107 includes metal level 104, has multiple recessed micro structure 1020 in insulating barrier 102, and metal level 104 closes on and is formed with the bossing 1040 being filled into multiple recessed micro structures 1020 on the surface of insulating barrier 102.
Such as, underlay substrate 101 can be glass substrate, quartz base plate, resin substrate or other substrates；The material of insulating barrier 102 can be silicon nitride (SiNx), silicon oxide (SiOX), silicon oxynitride (SiNxOy) or other insulant；Metal level 104 is chromium, molybdenum, aluminum, copper, aluminum, aluminium alloy, copper, the arbitrary monolayer in copper alloy etc. or the most several laminations；Etching cushion 103 can include deep ultraviolet extinction oxide (deepultravioletlight-absorbingoxide, DUO), and specifically, etching cushion 103 can include organic siloxane polymer.
It should be noted that multiple recessed micro structures 1020 can run through insulating barrier 102；Or, multiple recessed micro structures 1020 do not extend through insulating barrier 102, are formed at the top of insulating barrier 102.
In the function substrate that the present embodiment provides, metal level 104 closes on and is formed with the bossing 1040 being filled into multiple recessed micro structures 1020 on the surface of insulating barrier 102.It is to say, it is matsurface that metal level 104 closes on the surface of insulating barrier 102；When light is irradiated to the surface that metal level 104 closes on insulating barrier 102, light is reflected to all directions；Thus, metal level 104 closes on the surface of insulating barrier 102 and can play the effect of reflection-proof.
Such as, in the function substrate that the present embodiment one example provides, multiple recessed micro structures 1020 can include micropore 1021 or very low power 1022, make the bossing 1040 being filled into multiple recessed micro structure 1020 include small projection or raised line, thus the directional light being emitted onto projection or raised line reflexes to different directions.
Such as, Fig. 8 a-8d is insulating barrier 102 and is formed at the floor map of multiple recessed micro structures 1020 in insulating barrier 102, and as shown in Figure 8 a, the multiple recessed micro structure 1020 in insulating barrier 102 includes micropore 1021；As shown in Figure 8 b, the multiple recessed micro structure 1020 in insulating barrier 102 includes very low power 1022.Reflex to more different directions to be emitted onto bossing 1040, the multiple recessed micro structure 1020 in insulating barrier 102 can be set to more complicated structure；Such as, as shown in Figure 8 c, the multiple recessed micro structure 1020 in insulating barrier 102 can include the very low power 1023 of bending；As shown in figure 8d, the multiple recessed micro structure 1020 in insulating barrier 102 can include micropore 1021 and the combination of very low power 1022.
Such as, above-mentioned micropore 1021 can include rounding taper hole, inversed taper platform hole or half ball.Correspondingly, the bossing 1040 being filled into above-mentioned micropore 1021 can include circular cone, frustum or hemisphere.
Such as, in the function substrate that the present embodiment one example provides, multiple recessed micro structures 1020 are regularly arranged.It should be noted that above-mentioned regularly arranged refer to multiple recessed micro structure 1020 in distribution in accordance with certain mode or with certain pattern period arrangement.
Such as, in the function substrate that the present embodiment one example provides, the thickness of insulating barrier isIt should be noted that when the function substrate that the present embodiment provides is applied to the array base palte of display device, due to the thinner thickness of insulating barrier, it is possible to reduce loss during light transmission, improve aperture opening ratio.
Such as, the function substrate that the present embodiment one example provides may be used for liquid crystal display (LiquidCrystalDisplay, or the array base palte of the display device such as OLED (OrganicLightEmittingDiodeDisplay, OLED) LCD).
Such as, as shown in fig. 11a, conductive structure 107 can include grid line 1071 or grid 1072；Grid line 1071 can be formed by patterning same layer metal level with grid 1072.Specifically, the function substrate that the present embodiment provides comprises the steps that underlay substrate 101；The insulating barrier 102 being arranged on underlay substrate 101 and the grid line 1071 being arranged on insulating barrier 102 and grid 1072.Insulating barrier 102 has multiple recessed micro structure 1020, and grid line 1071 or grid 1072 close on and be formed with the bossing 1040 being filled into multiple recessed micro structures 1020 on the surface of insulating barrier 102.
Such as, as shown in fig. 11a, conductive structure 107 may also include data wire 1073, source electrode 1074 or drain electrode 1075.Such as, as shown in figure 11b, the function substrate that the present embodiment provides may also include that the gate insulator 111 being arranged on underlay substrate 101, grid line 1071 and grid 1072；It is arranged on gate insulator 111 the active layer pattern 115 of just position to grid 1072；Another insulating barrier 112 being arranged on gate insulator 111 and active layer pattern 115；And it being arranged on the data wire 1073 on another insulating barrier 112, source electrode 1074 and drain electrode 1075, this source electrode 1074 and drain electrode 1075 are set up separately in the both sides of active layer pattern 115.Another insulating barrier 112 has multiple recessed micro structure 1120, and data wire 1073, source electrode 1074 or drain electrode 1075 close on and be formed with the bossing 1040 being filled into multiple recessed micro structures 1120 on the surface of another insulating barrier 112.
Such as, as shown in figure 11b, the function substrate that the present embodiment provides may also include that the flatness layer 113 being arranged on aforesaid substrate；It is arranged in flatness layer 113 via 116 for connecting drain electrode 1075；And at the pixel electrode 114 being arranged on flatness layer 113, this pixel electrode 114 is by via 116 and drain electrode 1074 electric connection.
Such as, as shown in figure 12, in order to realize touch controllable function, as a example by the touch electrode structure of self-capacitance, conductive structure 107 can include touch control electrode 1076.Certainly, conductive structure 107 also can include the touch control electrode of mutual capacitance touch electrode structure, and this is not restricted.
It should be noted that the present embodiment includes but not limited to the function substrate of said structure, the function substrate that the present embodiment provides can also include the function substrate of other structures.
Embodiment four
The present embodiment provides a kind of display device, and it includes arbitrary function substrate that above-described embodiment three provides.
It should be noted that, in the display device that the present embodiment provides, it is matsurface owing to the conductive structure on function substrate closes on the surface of insulating barrier, when light is irradiated to the display device with above-mentioned functions substrate, conductive structure closes on the surface of insulating barrier can reflect light to all directions without producing direct reflection, the effect of reflection-proof can be played, thus display quality can be improved.
Such as, in the display device that the present embodiment provides, as shown in figure 13, it also includes: color membrane substrates 200, liquid crystal layer 300；Liquid crystal layer 300 is arranged between function substrate 100 and color membrane substrates 200.Further, function substrate 100 is exiting surface 150 away from the one side of liquid crystal layer 300.
It should be noted that in the display device that the present embodiment provides, owing to function substrate is exiting surface away from the one side of liquid crystal layer, light is incident from color membrane substrates side, penetrates from function substrate side.Due to, the function substrate of this display device outwardly, additionally installation space in order to bend the flexible printed circuit board connecting this function substrate, thus border width can be reduced.It should be noted that, when this function substrate is as light emission side, owing to this function substrate has the effect of reflection-proof, when ambient light is irradiated to the conductive structure in function substrate, conductive structure closes on the surface of insulating barrier, and can to reflect light to all directions the most reflective without producing, and display quality can be greatly improved.
Have following some need explanation:
(1), in embodiment of the present invention accompanying drawing, the structure relating only to and the present embodiments relate to, other structures refer to be commonly designed.
(2) for clarity, in the accompanying drawing for describing embodiments of the invention, layer or the thickness of micro structure and size are exaggerated.Be appreciated that when the element of such as layer, film, region or substrate etc be referred to as being positioned at another element " on " or during D score, this element can be positioned at " directly " another element " on " or D score, or intermediary element can be there is.
(3) in the case of not conflicting, the feature in the same embodiment of the present invention and different embodiment can be mutually combined.
The above; being only the detailed description of the invention of the disclosure, but the protection domain of the disclosure is not limited thereto, any those familiar with the art is in the technical scope that the disclosure discloses; change can be readily occurred in or replace, all should contain within the protection domain of the disclosure.Therefore, the protection domain of the disclosure should be as the criterion with described scope of the claims.

Claims (21)

1. a manufacture method for metal level, including:
Underlay substrate is formed insulating barrier；
Described insulating barrier is formed etching cushion；
Pattern described etching cushion and described insulating barrier to form multiple recessed micro structure in described insulating barrier；
Peel off described etching cushion；And
Forming metal level on described insulating barrier, described metal level closes on and is formed with the bossing being filled into the plurality of recessed micro structure on the surface of described insulating barrier.
The most according to claim 1, the manufacture method of metal level, wherein, form photoresist on described etching cushion；Utilize mask plate that described photoresist is exposed, develop and form photoetching agent pattern；For mask, described etching cushion and described insulating barrier are performed etching with described photoetching agent pattern, thus pattern described etching cushion and described insulating barrier to form multiple recessed micro structure in described insulating barrier.
The manufacture method of metal level the most according to claim 2, wherein, during performing etching described etching cushion and described insulating barrier with described photoetching agent pattern for mask, the etch rate of described etching cushion is more than or equal to the etch rate of described insulating barrier.
The manufacture method of metal level the most according to claim 1 or claim 2, wherein, the plurality of recessed micro structure includes micropore or very low power.
The manufacture method of metal level the most according to claim 4, wherein, described micropore includes rounding taper hole, inversed taper platform hole or half ball.
The manufacture method of metal level the most according to claim 1 and 2, wherein, the plurality of recessed micro structure is regularly arranged.
The manufacture method of metal level the most according to claim 1 or claim 2, wherein, described etching cushion includes deep ultraviolet extinction oxide.
The manufacture method of metal level the most according to claim 1 or claim 2, wherein, the thickness of described insulating barrier is
The manufacture method of metal level the most according to claim 1 or claim 2, wherein, the plurality of recessed micro structure runs through or non-through in described insulating barrier.
10. a manufacture method for function substrate, including:
Underlay substrate is formed metal level；And
Patterning described metal level to form conductive structure, wherein, described metal level uses the manufacture method of metal level as described in any one of claim 1-9 to be formed.
The manufacture method of 11. function substrates according to claim 10, wherein, described conductive structure includes grid line, grid, data wire, source electrode, drain electrode or touch control electrode.
12. 1 kinds of function substrates, including: underlay substrate, the insulating barrier being arranged on described underlay substrate and be arranged on the conductive structure on described insulating barrier,
Wherein, described conductive structure includes metal level, wherein, has multiple recessed micro structure in described insulating barrier, and described metal level closes on and is formed with the bossing being filled into the plurality of recessed micro structure on the surface of described insulating barrier.
13. function substrates according to claim 12, wherein, the plurality of recessed micro structure includes micropore or very low power.
14. function substrates according to claim 13, wherein, described micropore includes rounding taper hole, inversed taper platform hole or half ball.
15. according to the arbitrary described function substrate of claim 12-14, and wherein, the plurality of recessed micro structure is regularly arranged.
16. according to the arbitrary described function substrate of claim 12-14, and wherein, described etching cushion includes deep ultraviolet extinction oxide.
17. according to the arbitrary described function substrate of claim 12-14, and wherein, the thickness of described insulating barrier is
18. according to the arbitrary described function substrate of claim 12-14, and wherein, the plurality of recessed micro structure runs through or non-through in described insulating barrier.
19. according to the arbitrary described function substrate of claim 12-14, and wherein, described conductive structure includes: grid line, grid, data wire, source electrode, drain electrode or touch control electrode.
20. 1 kinds of display devices, including the function substrate described in any one of claim 12-19.
21. display devices as claimed in claim 20, also include: color membrane substrates, liquid crystal layer, wherein, described liquid crystal layer is arranged between described function substrate and described color membrane substrates, and described function substrate is away from the exiting surface that one side is described display device of described liquid crystal layer.
CN201610221405.7A 2016-04-11 2016-04-11 Metal layer manufacturing method thereof, function substrate and preparation method thereof and display device Expired - Fee Related CN105826249B (en)

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107026121A (en) * 2017-05-17 2017-08-08 京东方科技集团股份有限公司 Preparation method, array base palte and the display device of array base palte
WO2017177725A1 (en) * 2016-04-11 2017-10-19 京东方科技集团股份有限公司 Manufacturing method for metal layer, functional substrate, and manufacturing method therefor and display apparatus
CN108346620A (en) * 2017-01-23 2018-07-31 京东方科技集团股份有限公司 Array substrate and preparation method thereof, display device
CN109633965A (en) * 2019-01-03 2019-04-16 京东方科技集团股份有限公司 Color membrane structure, display base plate and its manufacturing method, display device
CN109873002A (en) * 2019-02-26 2019-06-11 武汉华星光电半导体显示技术有限公司 The manufacturing method of array substrate and array substrate
WO2019127676A1 (en) * 2017-12-26 2019-07-04 深圳市华星光电半导体显示技术有限公司 Preparation method of array substrate and electrode wire pattern thereof, and liquid crystal display panel
CN110993622A (en) * 2019-12-13 2020-04-10 Tcl华星光电技术有限公司 Array substrate, preparation method thereof and display panel

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11889721B2 (en) * 2019-07-16 2024-01-30 Ordos Yuansheng Optoelectronics Co., Ltd. Display substrate, manufacturing method thereof and display device

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1707338A (en) * 2004-06-05 2005-12-14 Lg.菲利浦Lcd株式会社 Liquid crystal display device and fabricating method thereof
CN1815321A (en) * 2006-03-02 2006-08-09 广辉电子股份有限公司 Method for manufacturing down base plate for liquid crystal display device
CN101079429A (en) * 2006-05-24 2007-11-28 Lg.菲利浦Lcd株式会社 Thin film transistor array substrate and method for fabricating the same
CN101093325A (en) * 2006-06-19 2007-12-26 Lg.菲利浦Lcd株式会社 Array substrate for liquid crystal display device and method of fabricating the same
CN101477989A (en) * 2008-01-04 2009-07-08 群康科技(深圳)有限公司 Thin-film transistor substrates and manufacturing method therefor
CN102339772A (en) * 2010-07-16 2012-02-01 中芯国际集成电路制造(上海)有限公司 Method for detecting defects of through holes
CN104181741A (en) * 2014-08-04 2014-12-03 京东方科技集团股份有限公司 Display device, array substrate and production method of array substrate
CN105355589A (en) * 2015-10-13 2016-02-24 深圳市华星光电技术有限公司 Array substrate and manufacturing method thereof

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3753673B2 (en) 2001-06-20 2006-03-08 セイコーエプソン株式会社 Manufacturing method of liquid crystal display device
CN100543539C (en) 2006-06-02 2009-09-23 群康科技(深圳)有限公司 Method for manufacturing semi-reflective semi-transmitting liquid crystal display device
CN101556414B (en) 2008-04-10 2011-08-24 北京京东方光电科技有限公司 Semitransparent and half-reflection type liquid crystal display array base plate and manufacturing method thereof
DE102010002454A1 (en) * 2010-02-26 2011-09-01 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Metallization system of a semiconductor device with rounded connections, which are made by Hartmaskenverrundung
CN103325792A (en) 2013-05-23 2013-09-25 合肥京东方光电科技有限公司 Array substrate, preparation method and display device
CN104536194A (en) 2015-01-04 2015-04-22 京东方科技集团股份有限公司 Array substrate, method for manufacturing array substrate and display device
US20170104033A1 (en) 2015-10-13 2017-04-13 Shenzhen China Star Optoelectronics Technology Co., Ltd. Array substrate and manufacturing method for the same
CN105826249B (en) 2016-04-11 2019-08-06 京东方科技集团股份有限公司 Metal layer manufacturing method thereof, function substrate and preparation method thereof and display device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1707338A (en) * 2004-06-05 2005-12-14 Lg.菲利浦Lcd株式会社 Liquid crystal display device and fabricating method thereof
CN1815321A (en) * 2006-03-02 2006-08-09 广辉电子股份有限公司 Method for manufacturing down base plate for liquid crystal display device
CN101079429A (en) * 2006-05-24 2007-11-28 Lg.菲利浦Lcd株式会社 Thin film transistor array substrate and method for fabricating the same
CN101093325A (en) * 2006-06-19 2007-12-26 Lg.菲利浦Lcd株式会社 Array substrate for liquid crystal display device and method of fabricating the same
CN101477989A (en) * 2008-01-04 2009-07-08 群康科技(深圳)有限公司 Thin-film transistor substrates and manufacturing method therefor
CN102339772A (en) * 2010-07-16 2012-02-01 中芯国际集成电路制造(上海)有限公司 Method for detecting defects of through holes
CN104181741A (en) * 2014-08-04 2014-12-03 京东方科技集团股份有限公司 Display device, array substrate and production method of array substrate
CN105355589A (en) * 2015-10-13 2016-02-24 深圳市华星光电技术有限公司 Array substrate and manufacturing method thereof

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10209584B2 (en) 2016-04-11 2019-02-19 Boe Technology Group Co., Ltd. Manufacturing method of metal layer, functional substrate and manufacturing method thereof, and display device
WO2017177725A1 (en) * 2016-04-11 2017-10-19 京东方科技集团股份有限公司 Manufacturing method for metal layer, functional substrate, and manufacturing method therefor and display apparatus
CN108346620A (en) * 2017-01-23 2018-07-31 京东方科技集团股份有限公司 Array substrate and preparation method thereof, display device
US10833104B2 (en) 2017-01-23 2020-11-10 Boe Technology Group Co., Ltd. Array substrate and its fabricating method, display device
WO2018210167A1 (en) * 2017-05-17 2018-11-22 京东方科技集团股份有限公司 Manufacturing method for array substrate, array substrate and display device
CN107026121A (en) * 2017-05-17 2017-08-08 京东方科技集团股份有限公司 Preparation method, array base palte and the display device of array base palte
WO2019127676A1 (en) * 2017-12-26 2019-07-04 深圳市华星光电半导体显示技术有限公司 Preparation method of array substrate and electrode wire pattern thereof, and liquid crystal display panel
CN109633965A (en) * 2019-01-03 2019-04-16 京东方科技集团股份有限公司 Color membrane structure, display base plate and its manufacturing method, display device
CN109633965B (en) * 2019-01-03 2021-11-02 京东方科技集团股份有限公司 Color film structure, display substrate, manufacturing method of display substrate and display device
US11244985B2 (en) 2019-01-03 2022-02-08 Boe Technology Group Co., Ltd. Color film assembly, display substrate and method for fabricating same, and display apparatus
CN109873002A (en) * 2019-02-26 2019-06-11 武汉华星光电半导体显示技术有限公司 The manufacturing method of array substrate and array substrate
CN110993622A (en) * 2019-12-13 2020-04-10 Tcl华星光电技术有限公司 Array substrate, preparation method thereof and display panel
WO2021114385A1 (en) * 2019-12-13 2021-06-17 Tcl华星光电技术有限公司 Array substrate and method for manufacturing same, and display panel

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