CN105826215A - Semiconductor structure forming method - Google Patents
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- CN105826215A CN105826215A CN201510011859.7A CN201510011859A CN105826215A CN 105826215 A CN105826215 A CN 105826215A CN 201510011859 A CN201510011859 A CN 201510011859A CN 105826215 A CN105826215 A CN 105826215A
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Abstract
The invention provides a semiconductor structure forming method. The method comprises steps: a first wafer and a second wafer are provided, a MEMS ((Micro-Electro-Mechanical System) structure is formed in the first wafer, a TSV (Through-Silicon Via) structure is formed in the second wafer, and a wafer bonding structure formed by the first wafer and the second wafer can be used for making an MEMS-TSV bonding structure; and through wet etching by being immersed in an etching solution, wafer back thinning is synchronously carried out on the first wafer and the second wafer. The first wafer and the second wafer are little damaged, and the MEMS-TSV bonding structure production efficiency is effectively improved. As sealing is realized between the first wafer and the second wafer, the etching solution does not enter the wafer bonding structure from between the first wafer and the second wafer, the wafer bonding structure is not damaged, and the MEMS-TSV bonding structure quality is improved.
Description
Technical field
The present invention relates to semiconductor applications, is specifically related to the forming method of a kind of semiconductor structure.
Background technology
Along with the development of semiconductor technology, MEMS (Micro-Electro-MechanicalSystem, MEMS) becomes the study hotspot of current semiconductor technology.
MEMS is generally of the multiple structure of complexity, needs multiple wafer bonding to be formed together.Therefore, MEMS-TSV bonding structure becomes the primary study object of current MEMS manufacturing technology, such as, MEMS cavity structure and operating circuit is formed in the first wafer, TSV (through-siliconvia is formed in the second wafer, penetrate silicon interconnection) interconnection structure, afterwards by the first wafer and the second wafer bonding together, form the MEMS with complete function.After first wafer and the second wafer bonding, can also continue to be combined the second wafer and the trimorphism round key with MEMS cavity structure and operating circuit, form first, second, third wafer bonding wafer bonding structure together, to form increasingly complex MEMS.
Referring to figs. 1 to Fig. 4, it is shown that the sectional view of prior art a kind of MEMS-TSV bonding structure forming method.
With reference to Fig. 1, first wafer 20 includes the first substrate 21, the MEMS cavity structure 23 being positioned on the first substrate 21 and operating circuit 22, second wafer 10 includes the second substrate 11, it is positioned at the interconnection structure 13 on the second substrate 11, first wafer 20 and the second wafer 10 are linked together by wafer bonding parts 30, make MEMS cavity structure 23, operating circuit 22 and interconnection structure 13 electrically connect.Being formed with TSV structure 12 in the second substrate 11, described TSV structure 12 is connected with interconnection structure 13, for providing the input and output of the signal of telecommunication for operating circuit 22.Such first wafer 20 and the second wafer 10 bonding form MEMS-TSV bonding structure, and described MEMS-TSV bonding structure can be separated into multiple MEMS working cell.
With reference to Fig. 2, in prior art, less for the MEMS working cell volume making formation, after the first wafer 20 and the second wafer 10 are bonded together, the first wafer 20 are carried out thinning back side, i.e. removes the substrate 21 of segment thickness.Generally use technique first wafer 20 of mechanical lapping to carry out thinning back side, but mechanical lapping may damage substrate 21, and then MEMS cavity structure 23 and the performance of operating circuit 22 may be affected.
With reference to Fig. 3, Fig. 4, after thinning first wafer 20, also the second substrate 11 is carried out dry etching, make TSV structure 12 expose, described TSV structure 12 be formed metal terminal 14, metal terminal 14 is formed the insulating barrier 15 of exposed portion metal terminal 14.Described metal terminal 14, for being connected with external power source, provides the input and output of the signal of telecommunication for interconnection structure 13.
But the thickness that dry etching removes the second substrate 11 is relatively big, relatively costly, and the time can only be spent during batch production longer single-wafer operation.Production efficiency ratio is relatively low.
Summary of the invention
The problem that the present invention solves is to provide the forming method of a kind of semiconductor structure, improves the production efficiency of MEMS-TSV bonding structure.
For solving the problems referred to above, the present invention provides the forming method of a kind of semiconductor structure, including:
First wafer and the second wafer are provided, described first wafer are formed MEMS structure, described second wafer is formed with TSV structure；
Make described first wafer together with described second wafer bonding, form wafer bonding structure；
Region between first wafer and the second wafer is carried out encapsulation process；
Described wafer bonding structure is immersed in etching liquid, described wafer bonding structure is carried out wet etching, synchronize the first wafer and the second wafer are carried out thinning back side of silicon wafer.
Optionally, the etching liquid of described wet etching includes: TMAH solution.
Optionally, described first wafer is formed the operating circuit being connected with described MEMS structure, described second wafer is formed with the interconnection structure being connected with described TSV structure；Making described first wafer together with described second wafer bonding, formed in the step of wafer bonding structure, the operating circuit of described first wafer is connected with the interconnection structure of described second wafer.
Optionally, the step synchronizing to carry out the first wafer and the second wafer thinning back side of silicon wafer includes: make the TSV structure in the second wafer expose.
Optionally, the step synchronizing to carry out the first wafer and the second wafer thinning back side of silicon wafer includes: make the thickness of the first wafer reduce 200 to 400 microns.
Optionally, the step synchronizing to carry out the first wafer and the second wafer thinning back side of silicon wafer includes: make the thickness of the second wafer reduce 200 to 400 microns.
Optionally, after the region between the first wafer and the second wafer carries out the step of encapsulation process, before described wafer bonding structure being immersed in etching liquid, described forming method also includes: carry out pre-thinning to described second wafer rear.
Optionally, described second wafer rear is carried out pre-thinning step and includes: use mechanical lapping, dry etching or the method for wet etching, described second wafer rear is carried out pre-thinning.
Optionally, after synchronizing the first wafer and the second wafer are carried out thinning back side of silicon wafer, described forming method also includes: carry out the most thinning to described second wafer rear, makes the TSV structure in the second wafer expose.
Optionally, the step that the region between the first wafer and the second wafer carries out encapsulation process includes: the marginal area in the first wafer and the second wafer bonding face is formed and seals structure.
Optionally, marginal area in the first wafer and the second wafer bonding face forms the step of sealing structure and includes: the marginal area coating colloidal materials in the first wafer and the second wafer bonding face, described wafer bonding structure is toasted, makes described colloidal materials solidify, formed and seal structure.
Optionally, described colloidal materials is epoxy resin.
Compared with prior art, technical scheme has the advantage that
The present invention the first wafer is formed with MEMS structure, second wafer is formed with TSV structure, therefore the wafer bonding structure that the first wafer and the second wafer are formed can be used in making MEMS-TSV bonding structure, by immersing the wet etching in etching liquid, synchronize the first wafer and the second wafer are carried out thinning back side of silicon wafer, damage to the first wafer and the second wafer is less, is effectively increased the production efficiency of MEMS-TSV bonding structure.Due to the regional seal between the first wafer and the second wafer, MEMS-TSV bonding structure from entering wafer bonding structure between the first wafer and the second wafer, and then will not will not be caused damage, improve the quality of MEMS-TSV bonding structure by etching liquid.
Accompanying drawing explanation
Fig. 1 to Fig. 4 is the schematic diagram of prior art a kind of MEMS-TSV bonding structure forming method；
Fig. 5 to Fig. 9 be semiconductor structure of the present invention forming method one embodiment in the sectional view of each step；
Figure 10 to Figure 11 be semiconductor structure of the present invention forming method one embodiment in the sectional view of each step.
Detailed description of the invention
As stated in the Background Art, in the manufacture process of MEMS-TSV bonding structure, working cell volume for making formation is less, generally use the technique of mechanical lapping that the first wafer is carried out thinning back side of silicon wafer, but mechanical lapping may damage substrate the first wafer, and then may affect the performance of MEMS structure and operating circuit.After thinning first wafer, also the second wafer is carried out dry etching, make TSV structure expose, but the thickness of thinning second wafer of dry etching is relatively big, relatively costly, and can only be to single-wafer operation, spending the time longer during batch production, production efficiency ratio is relatively low.
In order to solve above-mentioned technical problem, the present invention proposes the forming method of a kind of semiconductor structure, the present invention the first wafer is formed with MEMS structure, second wafer is formed with TSV structure, therefore the wafer bonding structure that the first wafer and the second wafer are formed can be used in making MEMS-TSV bonding structure, by immersing the wet etching in etching liquid, synchronize the first wafer and the second wafer are carried out thinning back side of silicon wafer, damage to the first wafer and the second wafer is less, is effectively increased the production efficiency of MEMS-TSV bonding structure.Due to the regional seal between the first wafer and the second wafer, MEMS-TSV bonding structure from entering wafer bonding structure between the first wafer and the second wafer, and then will not will not be caused damage, improve the quality of MEMS-TSV bonding structure by etching liquid.
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with the accompanying drawings the specific embodiment of the present invention is described in detail.
With reference to Fig. 5 to Fig. 9, it is shown that the sectional view of forming method one each step of embodiment of semiconductor structure of the present invention.
With reference to Fig. 5, it is provided that the first wafer 200 and the second wafer 100.
In the present embodiment, described first wafer 200 includes the first substrate 201, second wafer 100 includes the second substrate 101, described first substrate 201 and the second substrate 101 are silicon substrate, in other embodiments, described substrate can also be other Semiconductor substrate such as germanium silicon substrate or silicon-on-insulator substrate, and this present invention is not done any restriction.
In the present embodiment, described first wafer 200 and the second wafer 100 are used for forming MEMS-TSV bonding structure.Described first wafer 200 includes the first substrate 201, and the first medium layer 204 that sequentially forms on the first substrate 201 and second dielectric layer 205, is formed with operating circuit 202, is formed with MEMS structure 203 in second dielectric layer 205 in first medium layer 204.
Specifically, in the present embodiment, the material of described first medium layer 204 is silicon oxide, and the material of described second dielectric layer 205 is silicon.As it is shown in figure 5, described MEMS structure 203 is to be positioned in second dielectric layer 205 structure comprising cavity.
Described second wafer 100 includes the second substrate 101 and the 3rd dielectric layer 110 formed on the second substrate 101, described 3rd dielectric layer 110 is formed with interconnection structure 103, described second substrate 101 is formed with TSV structure 102, described TSV structure 102 is connected with described interconnection structure 103, for after the first wafer and the second wafer bonding are together, described TSV structure 102 provides the input and output of the signal of telecommunication for interconnection structure 103.
In the present embodiment, the material of described 3rd dielectric layer 110 is silicon oxide, the material of described interconnection structure 103 is copper, and the material of described TSV structure 102 is copper, but the 3rd dielectric layer 110, interconnection structure 103, the material of TSV structure 102 are not limited by the present invention.In other embodiments, the material of described interconnection structure 103 and TSV structure 102 can also be aluminum.
In the present embodiment, described first wafer 200 is also formed with the first metal gasket 301, described second wafer 100 is also formed with the second metal gasket 302.Described first metal gasket 301 and the second metal gasket 302 are for being bonded together the first wafer 200 and the second wafer 100.
It should be noted that, in the present embodiment, the thickness H1 of described first substrate 201 is 700 microns, the thickness H2 of described second substrate 101 is 700 microns, but the thickness of described first substrate 201 and the second substrate 101 is not limited by the present invention, optionally, the thickness H1 of described first substrate 201 can be in the range of 600 to 800 microns, and the thickness H2 of described second substrate 101 can be in the range of 600 to 800 microns.Also, it should be noted in the present embodiment, described TSV structure 102 end is 600 microns with distance H3 on described second substrate 101 surface, and the most described TSV structure 102 end is 600 microns with the distance at described second wafer 100 back side.
With continued reference to Fig. 5, described first wafer 200 is bonded on the second wafer 100, forms wafer bonding structure.In the present embodiment, described wafer bonding structure is used for forming MEMS-TSV bonding structure.
Specifically, in the present embodiment, described first metal gasket 301 and the second metal gasket 302 is used described first wafer 200 and the second wafer 100 to be bonded together.In the present embodiment, the material of described first metal gasket 301 and the second metal gasket 302 is aluminum, and described first metal gasket 301 and the second metal gasket 302 can be by combining with germanium material generation eutectic reaction.But the concrete bonding technology of described first wafer 200 and the second wafer 100 is not limited by the present invention, does not limits the material of the first metal gasket 301 and the second metal gasket 302.
It should be noted that after described first wafer 200 and the second wafer 100 are bonded, the surface that the first wafer 200 is relative with the second wafer 100 is bonding face.
With continued reference to Fig. 5, the region between the first wafer 200 and the second wafer 100 is carried out encapsulation process.
In the present embodiment, the marginal area at the first wafer 200 and the second wafer 100 bonding face is formed and seals structure 303, makes to seal between the first wafer 200 and the second wafer 100.
Specifically, in the present embodiment, the marginal area at the first wafer 200 and the second wafer 100 bonding face is coated with colloidal materials, toasts described wafer bonding structure, makes described colloidal materials solidify, and is formed and seals structure 303.The syringe needle with colloid coating function can be used, around described wafer bonding structure one week, the marginal area of described first wafer 200 and the second wafer 100 bonding face is coated with colloidal materials.Using the mode of coating colloidal materials by the regional seal between described first wafer 200 and the second wafer 100, operational approach is simple and direct, and sealing effectiveness is preferable, but the present invention does not limits by the concrete grammar in the region between the first wafer and the second wafer.
It should be noted that in the present embodiment, described colloidal materials is epoxy resin.The solidification temperature of epoxy resin is relatively low, and the impact on wafer bonding structure is less, and sealing is strong, but the concrete material of described colloidal materials is not limited by the present invention.
With reference to Fig. 6, described wafer bonding structure is immersed in etching liquid, described wafer bonding structure is carried out wet etching, synchronize the first wafer 200 and the second wafer 100 are carried out thinning back side of silicon wafer.
Specifically, in the present embodiment, described first wafer 200 back side is the surface that the first substrate 201 deviates from first medium layer 204, and described second wafer 100 back side is the surface that the second substrate 101 deviates from the 3rd dielectric layer 110.
The purpose synchronizing the first wafer 200 and the second wafer 100 are carried out thinning back side of silicon wafer is, make wafer bonding structure thinning, so that the MEMS-TSV structural volume formed is less, and expose the TSV structure 102 in the second wafer 100, or make TSV structure 102 be more nearly the back side of the second wafer 100.
In the present embodiment, the step synchronizing the first wafer 200 and the second wafer 100 are carried out thinning back side of silicon wafer includes: remove the first substrate 201 of segment thickness, remove the second substrate 101 of segment thickness, make TSV structure 102 end in the second wafer 100 close to the back side of the second wafer 100.
It should be noted that in the present embodiment, owing to the first substrate 201 is identical with the material of the second substrate 101, it is the most identical with the speed of the second substrate 101 that etching liquid removes the first substrate 201.Therefore, when the first substrate 201 needing removal is identical with the thickness of the second substrate 101, use the wet etching that described wafer bonding structure is immersed etching liquid, can by a wet etching complete the first wafer 200 and the second wafer 100 thinning, and in the second wafer 100, TSV structure 102 end is close to the back side of the second wafer 100, is effectively increased production efficiency.
By immersing the wet etching in etching liquid, the first wafer 200 and the second wafer 100 being carried out thinning back side of silicon wafer, the damage to the first wafer 200 and the second wafer 100 is less.Thinning first wafer of method of mechanical lapping is used relative to prior art, the present invention uses wet etching that the first wafer 200 is carried out thinning back side of silicon wafer, it is not easy in the first wafer 200, semiconductor device in especially first substrate 201, circuit etc. cause damage, and then beneficially improve the quality of the MEMS-TSV bonding structure being subsequently formed.
In addition, due to regional seal between the first wafer 200 and the second wafer 100 in the present embodiment, etching liquid will not be from entering wafer bonding structure between the first wafer and the second wafer, and then first metal gasket the 301, second metal gasket 302 exposed between the first wafer 200 and the second wafer 100 and MEMS structure 203 or other semiconductor device will not be caused damage, and then improve the quality of the MEMS-TSV bonding structure being subsequently formed.
It should be noted that, when the first substrate 201 needing removal is different with the thickness of the second substrate 101, by immersing the wet etching in etching liquid, the first wafer 200 of same thickness and the second wafer 100 of segment thickness can be removed, for needing to remove the first wafer 200 or the second wafer 100 that thickness is bigger, can individually remove the first wafer 200 or the second wafer 100 of segment thickness before or after by immersing the wet etching in etching liquid.
In the present embodiment, being also formed with other semiconductor device being connected with MEMS structure 203 in the first wafer 200, therefore first wafer 200 back side needs thinning thickness to be 300 microns, and i.e. needing the first substrate 201 thickness removed is 300 microns.Owing to distance H3 of described TSV structure 102 end Yu described second substrate 101 surface is 600 microns, it is therefore desirable to the second substrate 101 thickness of removal is 600 microns, to expose TSV structure 102 end in the second wafer 100.
Therefore, in the present embodiment, by immersing the wet etching in etching liquid, synchronize the first wafer 200 and the second wafer 100 are carried out thinning back side of silicon wafer, remove 300 microns of first thick substrates 201, and 300 microns of second thick substrates 101, make the thickness H1 of the first substrate 201 be reduced to 400 microns, the thickness H1 of the second substrate 101 is also reduced to 400 microns.Due to before synchronizing the first wafer 200 and the second wafer 100 are carried out thinning back side of silicon wafer, described TSV structure 102 end is 600 microns with distance H3 on described second substrate 101 surface, remove 300 microns of second thick substrates 101, it is possible to make described TSV structure 102 end close to the second wafer rear.
By the present embodiment immerses the wet etching in etching liquid, the thickness H1 of the first substrate 201 and thickness H2 of the second substrate 101 is reduced 300 microns simultaneously, and the wet etching step in described immersion etching liquid can be to the operation simultaneously of multiple wafer bonding structures, it is effectively increased the speed of thinned wafer bonding structure, also improve the speed exposing described TSV structure 102 end, and then improve the production efficiency of MEMS-TSV bonding structure.
It should be noted that, the present invention is in the step synchronizing to carry out the first wafer 200 and the second wafer 100 thinning back side of silicon wafer, the thickness of thinning first wafer 200 and the second wafer 100 does not limits, optionally, by immersing the wet etching in etching liquid, the thickness of thinning first wafer 200 and the second wafer 100 can also be at 200 to 400 microns.
It can further be stated that, in the present embodiment, described wafer bonding structure is being immersed in etching liquid, described wafer bonding structure is carried out in the step of wet etching, the etching liquid used is TMAH (Tetramethylammonium hydroxide) solution, TMAH solution is preferable to the first substrate 201 and second substrate 101 etching effect of silicon materials, and other semiconductor device in the first wafer 200 and the second wafer 100 be cannot be easily caused damage.But the etching liquid that described wet etching is used by the present invention does not limits.
With reference to Fig. 7, after the wet etching step in described immersion etching liquid, described second wafer 100 back side is carried out the most thinning, makes the TSV structure 102 in the second wafer 100 expose.
Specifically, the present embodiment carries out to described second substrate 101 dry etching, continue to remove the second substrate 101 of segment thickness, make described TSV structure 102 end expose.
In the etching process of described dry etching, etching apparatus adsorbs the first wafer 200, makes etching gas individually perform etching the second substrate 101 on described second wafer 100, and therefore the first substrate 201 will not be impacted by dry etching.Dry etching is less on the impact of TSV structure 102, and after dry etching exposes described TSV structure 102 end, described TSV structure 102 can partly protrude from the second substrate 101 surface, being conducive to follow-up being formed after insulating barrier on the second substrate 101, described TSV structure 102 easily exposes insulating barrier.
After but the present invention is to the wet etching step in described immersion etching liquid, the concrete grammar continuing to remove the second substrate 101 of segment thickness does not limits, in other embodiments, it is also possible to use the method for mechanical lapping or wet etching to continue to remove the second substrate 101 of segment thickness.It is for instance possible to use diamond lap head carries out mechanical lapping to described second substrate 101 surface, the speed that the second substrate 101 is removed in mechanical lapping is very fast.It should be noted that mechanical lapping here or the method for wet etching, after being described first wafer 200 of absorption, individually the second wafer 100 is processed, to avoid damage to the first wafer 200.
With reference to Fig. 8, exposing described TSV structure 102 end at dry etching, after making described TSV structure 102 can partly protrude from the second substrate 101 surface, form insulating barrier 104 on described second substrate 101, described insulating barrier 104 exposes TSV structure 102 end.
Specifically, insulation material layer (not shown) can be covered on described second substrate 101 and described TSV structure 102, the insulation material layer on described TSV structure 102 end is removed by dry etching or wet etching, remaining insulation material layer forms described insulating barrier 104, and described insulating barrier 104 exposes TSV structure 102 end.
Described insulating barrier 104 is for making the metal terminal being subsequently formed and the second substrate 102 insulate.In the present embodiment, the material of described insulating barrier 104 is silicon oxide.
With reference to Fig. 9, described TSV structure 102 is formed metal terminal 105, metal terminal 105 is formed the protective layer 106 of exposed portion metal terminal 105.Described metal terminal 105, for being connected with external power source, provides the input and output of the signal of telecommunication for interconnection structure 103.
The forming method of described protective layer 106 includes; described TSV structure 102 and insulating barrier 104 are coated with photoresist; described photoresist is continued exposure imaging; remove the photoresist on part metals terminal 105; remaining photoresist forms described protective layer 106, has the opening of exposed portion metal terminal 105 in described protective layer 106.
The most i.e. defining MEMS-TSV bonding structure, the quality of the MEMS-TSV bonding structure that the present embodiment is formed is preferable, and production efficiency is higher.Described MEMS-TSV bonding structure can form MEMS working cell through techniques such as cutting encapsulation.
With reference to figures 10 to Figure 11, it is shown that the schematic diagram of another embodiment of forming method of semiconductor structure of the present invention.Another embodiment of the forming method of semiconductor structure of the present invention is roughly the same with the step of above-described embodiment, and step same as the previously described embodiments does not repeats them here, and part unlike the embodiments above is:
Refer to Figure 10, after sealing between the first wafer 200 and the second wafer frontside edge region, before described wafer bonding structure is immersed in etching liquid, described second wafer 100 back side is carried out pre-thinning.In the present embodiment, described second wafer 100 back side is carried out pre-thinning step and i.e. remove the second substrate 101 of segment thickness.
In the present embodiment, the thickness removing the second substrate 101 is 300 microns, and after removing the second substrate 101 of segment thickness, the thickness H2 of described second substrate 101 is reduced to 400 microns.
In the present embodiment, it is mechanical lapping that described second wafer 100 back side carries out pre-thinning method, specifically, can use diamond lap head that described second substrate 101 surface is carried out mechanical lapping, and the speed that the second substrate 101 is removed in mechanical lapping is very fast.But the present invention carries out pre-thinning concrete grammar to described second wafer 100 back side not to be limited, in other embodiments, it is also possible to use dry etching or wet etching to remove the second substrate 101 of segment thickness.It should be noted that dry etching here or the method for wet etching, after being described first wafer 200 of absorption, individually described second wafer 100 back side is carried out pre-thinning, to avoid damage to the first wafer 200.
With reference to Figure 11, described second wafer 100 back side carry out pre-thinning after, described wafer bonding structure is immersed in etching liquid, described wafer bonding structure is carried out wet etching, remove the first wafer 200 and second wafer 100 of segment thickness of segment thickness, make TSV structure 102 end in the second wafer 100 expose the surface in the second wafer 100 first wafer 200 direction dorsad.
In the present embodiment, described wafer bonding structure is immersed in etching liquid, described wafer bonding structure is carried out wet etching, the thickness removing the first substrate 201 and the second substrate 101 is 300 microns, after described wet etching, the thickness of described first substrate 201 is reduced to 400 microns, and described TSV structure 102 exposes the surface of the second substrate 101.
In the present embodiment, first using the method for mechanical lapping to remove the second substrate 101 of segment thickness, the speed removing the second substrate 101 is very fast.Immersed in etching liquid by circle bonding structure again, described wafer bonding structure is carried out wet etching, removes the first substrate 201 and the second substrate 101 of segment thickness simultaneously.The roughened finish that mechanical lapping can be formed on the second substrate 101 by wet etching is removed so that follow-up insulating barrier and the metal terminal pattern formed on the second substrate 101 surface is more preferable.
The foregoing is only the specific embodiment of the present invention; purpose is to make those skilled in the art be better understood from the spirit of the present invention; but protection scope of the present invention is not specifically described as restriction scope with this specific embodiment; any those skilled in the art is without departing from the spirit of the scope of the invention; the specific embodiment of the present invention can be made an amendment, without deviating from protection scope of the present invention.
Claims (12)
1. the forming method of a semiconductor structure, it is characterised in that including:
First wafer and the second wafer are provided, described first wafer are formed MEMS structure, described second wafer is formed with TSV structure；
Make described first wafer together with described second wafer bonding, form wafer bonding structure；
Region between first wafer and the second wafer is carried out encapsulation process；
Described wafer bonding structure is immersed in etching liquid, described wafer bonding structure is carried out wet etching, synchronize the first wafer and the second wafer are carried out thinning back side of silicon wafer.
2. forming method as claimed in claim 1, it is characterised in that the etching liquid of described wet etching includes: TMAH solution.
3. forming method as claimed in claim 1, it is characterised in that be formed with the operating circuit being connected with described MEMS structure in described first wafer, described second wafer is formed with the interconnection structure being connected with described TSV structure；Making described first wafer together with described second wafer bonding, formed in the step of wafer bonding structure, the operating circuit of described first wafer is connected with the interconnection structure of described second wafer.
4. forming method as claimed in claim 1, it is characterised in that the step synchronizing to carry out the first wafer and the second wafer thinning back side of silicon wafer includes: make the TSV structure in the second wafer expose.
5. forming method as claimed in claim 1, it is characterised in that the step synchronizing to carry out the first wafer and the second wafer thinning back side of silicon wafer includes: make the thickness of the first wafer reduce 200 to 400 microns.
6. forming method as claimed in claim 1, it is characterised in that the step synchronizing to carry out the first wafer and the second wafer thinning back side of silicon wafer includes: make the thickness of the second wafer reduce 200 to 400 microns.
7. forming method as claimed in claim 1, it is characterized in that, after the region between the first wafer and the second wafer carries out the step of encapsulation process, before described wafer bonding structure being immersed in etching liquid, described forming method also includes: carry out pre-thinning to described second wafer rear.
8. forming method as claimed in claim 7, it is characterised in that described second wafer rear is carried out pre-thinning step and includes: use mechanical lapping, dry etching or the method for wet etching, described second wafer rear is carried out pre-thinning.
9. forming method as claimed in claim 1, it is characterized in that, after synchronizing the first wafer and the second wafer are carried out thinning back side of silicon wafer, described forming method also includes: carry out the most thinning to described second wafer rear, makes the TSV structure in the second wafer expose.
10. forming method as claimed in claim 1, it is characterised in that the step that the region between the first wafer and the second wafer carries out encapsulation process includes: the marginal area in the first wafer and the second wafer bonding face is formed and seals structure.
11. forming methods as claimed in claim 10, it is characterized in that, marginal area in the first wafer and the second wafer bonding face forms the step of sealing structure and includes: the marginal area coating colloidal materials in the first wafer and the second wafer bonding face, described wafer bonding structure is toasted, make described colloidal materials solidify, formed and seal structure.
12. forming methods as claimed in claim 11, it is characterised in that described colloidal materials is epoxy resin.
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| CN111508828A (en) * | 2020-03-26 | 2020-08-07 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
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| CN101434374A (en) * | 2008-12-23 | 2009-05-20 | 中国科学院上海微系统与信息技术研究所 | Structure and implementing method of MEMS device disc grade chip size hermetic package |
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| CN104016298A (en) * | 2013-03-01 | 2014-09-03 | 台湾积体电路制造股份有限公司 | MEMS structures and methods of forming the same |
| CN103818874A (en) * | 2014-02-12 | 2014-05-28 | 北京时代民芯科技有限公司 | Novel packaging method of MEMS (Micro-electromechanical Systems) structure and processing circuit integrated system |
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| TWI660440B (en) * | 2017-01-31 | 2019-05-21 | 日商新川股份有限公司 | Manufacturing method and manufacturing device of semiconductor device |
| US10937758B2 (en) | 2017-01-31 | 2021-03-02 | Shinkawa Ltd. | Semiconductor-device manufacturing method and manufacturing apparatus |
| CN111508828A (en) * | 2020-03-26 | 2020-08-07 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
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