CN103832964A - Micro-electro-mechanical system device manufacturing method - Google Patents
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- CN103832964A CN103832964A CN201210469696.3A CN201210469696A CN103832964A CN 103832964 A CN103832964 A CN 103832964A CN 201210469696 A CN201210469696 A CN 201210469696A CN 103832964 A CN103832964 A CN 103832964A
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Abstract
The present invention relates to a micro-electro-mechanical system device manufacturing method, which comprises: S1: providing a first chip, wherein the first chip comprises a micro-electro-mechanical system device layer having a movable sensitive part and a first electrical bonding point; S2: providing a second chip, wherein the second chip comprises a substrate having a first surface and a second surface, an isolation part arranged on the substrate and extending toward the first surface direction from the second surface, and a second electrical bonding point arranged on the second surface, the substrate is further provided with an electrical connection part electrically connected with the second electrical bonding point, and the isolation part is enclosed surrounding the electrical connection part; S3: bonding the first chip and the second chip, making the second surface face the micro-electro-mechanical system device layer, and bonding the first electrical bonding point and the second electrical bonding point; S4: carrying out thinning operation on the substrate of the bonded second chip on the first surface so as to expose the isolation part; and S5: forming an electrical connection layer electrically connected with the external circuit on the first surface of the thinned substrate.
Description
Technical field
The present invention relates to a kind of manufacture method of mems device, belong to MEMS field.
Background technology
Micro-electromechanical technology is a new and high technology of high speed development in recent years.Compared with the respective devices of being made by conventional art, the device that micro-electromechanical technology is made is in volume, power consumption, weight and have in price fairly obvious advantage, and it adopts sophisticated semiconductor manufacturing process, can realize the batch manufacture of mems device, on market, the main application example of mems device comprises pressure sensor, acceleration transducer, gyroscope and silicon microphone etc. at present.
Mems device generally carrys out the size of perception device pressure, acceleration and angular speed etc. by electric capacity, resistance etc.; and the change of electric capacity, resistance is mainly produced by the spring equivalent system of device inside; therefore; this type of mems device all has responsive movable structure, conventionally by form the protection to device inside movable structure together with the sealing of lid of device and a similar cap.
In electronic components fabrication evolution, microminaturization, integrated and low cost have become the development trend of mems device encapsulation.Wafer-level packaging (WLP, Wafer Level Package) is a kind of technological trend of mems device encapsulation.
Great majority or whole packaging and testing programs are carried out in being commonly defined as directly of wafer-level packaging (WLP, Wafer Level Package) on wafer, cut afterwards (singulation) again and make single assembly.
Chinese patent was on February 3rd, 2010, and publication number CN 101638212 A disclose wafer-level vacuum encapsulation wire interconnecting structure of micro electro mechanical system and manufacture method thereof.In this patent documentation, on silicon substrate, open hole, through hole and silicon substrate surface have insulating barrier, and metal electrode passes through hole and is sealed, and between metal electrode and insulating barrier, has intermediate layer, and cover plate and silicon substrate bonding complete Vacuum Package.But the vacuum leakproofness of the mems structure that this kind of technique is made is poor etc.
Summary of the invention
The object of the present invention is to provide a kind of manufacture can reduce packaging cost and encapsulation volume and realize the method for the hermetically sealed mems device of mems device.
For realizing aforementioned object, the present invention adopts following technical scheme: a kind of manufacture method of mems device, described method comprises the steps:
S1: the first chip is provided, and described the first chip comprises mems device layer and be arranged at the first electrical bond chalaza on described mems device layer, and described mems device layer comprises movable sensitive portion;
S2: the second chip is provided, described the second chip comprise have the first surface that is oppositely arranged and second surface substrate, be arranged at the isolation part of extending towards first surface direction on described substrate and from the second surface of substrate, be arranged on the second electrical bond chalaza on described substrate second surface, described substrate also has the electric connection part with described the second electrical bond chalaza electrical connection, and described isolation part is around in the periphery of described electric connection part;
S3: the second chip bonding that the first chip that described S1 step is provided and described S2 step provide, the second surface of described substrate is towards the mems device layer of described the first chip, described the first electrical bond chalaza and the second electrical bond chalaza bonding;
S4: the substrate of the second chip after described S3 step bonding is carried out to attenuate operation to expose isolation part in its first surface;
S5: the first surface of the substrate after described S4 step attenuate forms the electrical connection layer with external circuitry electrical connection.
As a further improvement on the present invention, in described S26 step, the material that forms described the first electrical bond chalaza is germanium, and the material that forms described the second electrical bond chalaza is aluminium.
As a further improvement on the present invention, the material that forms described the first electrical bond chalaza is gold, and the material that forms described the second electrical bond chalaza is polysilicon.
As a further improvement on the present invention, the second chip providing in described S2 step adopts following technique to realize:
S21 a: substrate is provided, and the second surface that described substrate comprises first surface and is oppositely arranged with first surface is oxidized and obtains oxide layer on the second surface of described substrate;
S22: in the oxide layer obtaining in described S21 step, mapping forms a via hole image;
S23: form through hole according to obtaining via hole image in described S23 step on described substrate, be formed in the middle of described through hole and the described electric connection part being surrounded by described through hole;
S24: first deposit one deck silicon oxide layer in the through hole obtaining in described S23 step, then fills up to form described isolation part with polysilicon by the through hole that is deposited with silicon oxide layer;
S25: remove the oxide layer forming in S21 step;
S26: form described the second electrical bond chalaza on the second surface of substrate of removing oxide layer, the electric connection part electrical connection forming in described the second electrical bond chalaza and S23 step.
As a further improvement on the present invention, the second chip providing described in described S2 step also comprises the steps: after S26 step
S27: be again oxidized and obtain oxide layer on the second surface of the substrate forming after described S26 step, then draw a picture in oxide layer and form cavity figure;
S28: form cavity according to obtaining cavity figure in described S27 step on substrate;
S29: remove the oxide layer forming in described S27 step.
As a further improvement on the present invention, the through hole in described S23 step adopts deep trouth reactive ion etching process to realize, and the cavity in described S28 step adopts deep trouth reactive ion etching process to realize or adopts the mode of corrosive liquid wet etching to realize.
As a further improvement on the present invention, described S24 step can also adopt following steps to replace: S24 ': in the through hole obtaining in described S23 step, silicon oxide deposition is to form described isolation part.
As a further improvement on the present invention, the first chip providing in described S1 step also comprises the first packaging ring that is positioned at the first electrical bond chalaza outside, in described S26 step, in forming described the second electrical bond chalaza, be also formed with the second packaging ring that is positioned at the second electrical bond chalaza outside.
As a further improvement on the present invention, the electrical connection layer of described S5 step is concrete adopts following technique to form:
S51: the first surface silicon oxide deposition of the substrate after described S4 step attenuate is to form oxide layer;
S52: remove partial oxidation layer to expose electric connection part, then deposit the first metal layer form metal routing;
S53: deposit one deck passivation layer again;
S54: remove part passivation layer part metals cabling is exposed, simultaneously deposit the second metal level on the metal routing exposing.
The material of the passivation layer forming in described S53 step as a further improvement on the present invention, is silica or silicon nitride.
The material of the second metal level forming in described S54 step as a further improvement on the present invention, is aluminium or gold.
The invention has the beneficial effects as follows: because preparation method of the present invention adopts circle level encapsulation technology and by making movable sensitive portion be formed in a confined space after the second chip and the first chip bonding, thereby realize the hermetically sealed of mems device, make obtained mems device have advantages of that packaging cost is low and encapsulation volume is little, in addition, after having prepared, make mems device there is electro-magnetic screen function.
Brief description of the drawings
Fig. 1 is the structural representation of mems device in the first embodiment in the specific embodiment of the invention.
Fig. 2 to Fig. 9 is the flow chart of preparing the second chip of mems device in Fig. 1.
Figure 10 to Figure 19 is the flow chart of preparing mems device in Fig. 1.
Figure 20 is the top view of the second chip in the mems device of another embodiment in the specific embodiment of the invention.
Figure 21 is the top view of the second chip of mems device in another embodiment in the specific embodiment of the invention.
Figure 22 is the another kind of structural representation in the substrate preparation process of the second chip of Fig. 5.
Detailed description of the invention
Refer to Fig. 1, the mems device 10 in one embodiment of the invention comprise the first chip 1, with the second chip 2 of the first chip 1 phase bonding and be arranged on the second chip 2 in order to the electrical connection layer 3 of external circuitry electrical connection.In the present embodiment, the external circuitry of electrical connection layer 3 correspondence is ASIC circuit.
The first chip 1 can be MEMS (MEMS) sensor chips such as accelerator or gyroscope.In the present embodiment, this first chip 1 comprises the first substrate 11, is arranged on oxide layer 12 on the first substrate 11, is arranged on trace layer 13, sacrifice layer 14 and the mems device layer 15 in oxide layer 12 and is arranged on the first electrical bond chalaza 16 and the first packaging ring 17 on mems device layer 15.Mems device layer 15 is bascule, and mems device layer 15 comprises narrow groove 151, the movable sensitive portion 152 being formed by narrow groove 151 and the fixed part 153 that is positioned at movable sensitive portion 152 1 sides.Narrow groove 151 obtains by photoetching and etching.The first electrical bond chalaza 16 and the first packaging ring 17 are fixed on fixed part 153, and the first packaging ring 17 is positioned at the outside of the first electrical bond chalaza 16.The material of above-mentioned the first electrical bond chalaza 16 is germanium or gold, and the material of the first packaging ring 17 is with the material of the first electrical bond chalaza 16.
The second chip 2 comprise have the front 211 that is oppositely arranged and the back side 212 the second substrate 21, be arranged at the back side 211 of the second substrate 21 and with the second electrical bond chalaza 22 of the first electrical bond chalaza 16 bondings of the first chip 1 and with the second packaging ring 23 of the first packaging ring 17 bondings, the cavity 26 that is arranged on the isolation part 25 in the second substrate 21 and forms from the back side of the second substrate 21 212 indents.The second substrate 21 comprises in order to the electric connection parts 24 with 3 electrical connection of electrical connection layer by the second electrical bond chalaza 22.Isolation part 25 is around in the periphery of electric connection part 24, thereby by other part electrical isolation of electric connection part 24 and the second substrate 21.After the first chip 1 and the second chip 2 bondings, the back side 212 of the second substrate 21 arranges towards the first chip 1, cavity 26 is towards the movable sensitive portion 152 of this first chip 1, and it provides activity space when being positioned at the top of movable sensitive portion 152 and vibrating for movable sensitive portion 152.Electrical connection layer 3 is positioned at the front 211 of the second substrate 21.The second electrical bond chalaza 22 is fixed on electric connection part 24.The second packaging ring 23 is positioned at the outside of the second electrical bond chalaza 22.
In this example, isolation part 25 comprise connect the second substrate 21 through hole 251, be positioned at the polysilicon layer 252 of through hole 251 and be around in the silicon oxide layer 253 of polysilicon layer 252 peripheries.Really, above-mentioned polysilicon 252 and silicon oxide layer 523 also can replace by the silica being filled in through hole 251.
In the present embodiment, the material of above-mentioned the first electrical bond chalaza 16, the first packaging ring 17, the second electrical bond chalaza 22 and the second packaging ring 23 can be selected as follows: in the time that the first electrical bond chalaza 16 and the first packaging ring 17 are formed by germanium material, the second electrical bond chalaza 22 and 23 of second packaging rings of bonding are formed by aluminum respectively with the first electrical bond chalaza 16 being formed by germanium material and the first packaging ring 17.In the time that the first electrical bond chalaza 16 and the first packaging ring 17 are formed by gold copper-base alloy, the second electrical bond chalaza 22 and 23 of second packaging rings of bonding are formed by polycrystalline silicon material respectively with the first electrical bond chalaza 16 being formed by gold copper-base alloy and the first packaging ring 17.By adopting above-mentioned material, make the first electrical bond chalaza 16, the second electrical bond chalaza 22 and the first packaging ring 17, the second packaging ring 23 thin thickness, thereby reduced the volume of mems device 10 entirety.
Owing to thering is electric connection part 24 and the movable sensitive portion 152 of the first chip 1 is formed in seal cavity with the second substrate 21 of the second chip 2 of the first chip 1 bonding, make this mems device 10 have advantages of that packaging cost is low and encapsulation volume is little, simultaneously, on the second substrate 21 due to the second chip 2, be formed with again the cavity 26 for 152 activities of movable sensitive portion, so reduced again parasitic capacitance and the damping of mems device 10.
In the present invention, the preparation method of above-mentioned mems device 10 comprises that S1 step described as follows is to S5 step.
Incorporated by reference to Figure 10, S1: the first chip 1 is provided.This first chip 1 comprises the first substrate 11, be arranged on mems device layer 15 on the first substrate 11, be arranged at the first electrical bond chalaza 16 on mems device layer 15 and be arranged on mems device layer 15 and be positioned at first packaging ring 17 in the first electrical bond chalaza 16 outsides.Mems device layer 15 comprises movable sensitive portion 152 and is positioned at the fixed part 153 of movable sensitive portion 152 1 sides.This first electrical bond chalaza 16 and the first packaging ring 17 are fixed on fixed part 153.At this, because the first chip 1 is common MEMS sensor chip, and the technique that forms this first chip 1 is also common MEMS sensor chip preparing process, therefore do not repeat them here.
S2: the second chip 2 is provided.This second chip 2 comprises the second electrical bond chalaza 22 and the second packaging ring 23 on substrate 21, the second surface 212 that is arranged on the isolation part 25 of extending towards first surface 211 directions on substrate 21 and from the second surface 212 of substrate 21, the cavity 26 forming from second surface 212 indents and is arranged on substrate 21 with the first surface 211 that is oppositely arranged and second surface 212.Substrate 21 comprises the electric connection part 24 being electrically connected with the second electrical bond chalaza 22.Isolation part 25 is around in the periphery of electric connection part 24.The second packaging ring 23 is positioned at the outside of the second electrical bond chalaza 22.
Incorporated by reference to Figure 11, S3: the second chip 2 bondings that the first chip 1 that S1 step is provided and S2 step provide.The second surface 212 of the substrate 21 of the second chip 2 is towards the mems device layer 15 of the first chip 1, the first electrical bond chalaza 16 and the second electrical bond chalaza 22 bondings, the first packaging ring 17 and the second packaging ring 23 bondings, cavity 26 is arranged at the top of movable sensitive portion 152 to provide activity space to movable sensitive portion 152.
Incorporated by reference to Figure 12, S4: the substrate 21 of the second chip 2 after S3 step bonding is carried out to attenuate operation to expose isolation part 25 in its first surface 211.In this step, realize the attenuate of substrate 21 by the mode of CMP attenuate.Substrate 21 after attenuate is called the second substrate, and the second surface 212 of substrate 21 after attenuate is called the back side, and the first surface 211 of the substrate 21 after attenuate is called front.Refer to Figure 13, because in S23 step, to forming four in S24 step, to have cross sectional shape be circular electric connection part 24, so can be observed these four circular electric connection parts 24 in the front 211 of the second substrate 21, and in the present embodiment, this electric connection part 24 is symmetricly set on respectively the two ends of the second substrate 21.Really, this electric connection part 24 can also be arranged to other shapes and quantity, as be arranged to six cross sections and be quadrangle or oval-shaped electric connection part, and the isolation part 25 corresponding with it also can be other shapes, arrangement mode also can form according to concrete design other arrangement mode, refers to Figure 20 or Figure 21.
Incorporated by reference to Figure 18, S5: the first surface 211 of the substrate 21 after S4 step attenuate forms the electrical connection layer 3 with external circuitry electrical connection.
Incorporated by reference to Fig. 2 to Fig. 9, the concrete employing of the second chip 2 as following S21 step to S29 process in above-mentioned S2 step realize.
Incorporated by reference to Fig. 2, S21 a: substrate 21 is provided.The second surface 212 that this substrate 21 comprises first surface 211 and is oppositely arranged with first surface 211.On the second surface 212 of substrate 21, be oxidized and obtain oxide layer 204.This oxide layer 204 is silica material.The formation of this oxide layer 204 can adopt the technology modes such as low-pressure chemical vapor phase deposition (LPCVD), plasma chemical vapor deposition (PECVD) or thermal oxide.This substrate 21 can be silicon substrate.
Incorporated by reference to Fig. 3, S22: in the oxide layer 204 obtaining in S21 step, mapping forms via hole image 205; In this step, via hole image 205 is mainly removed the partial oxygen SiClx in oxide layer 204 by techniques such as photoetching, dry etching or wet etchings, thereby to obtain this via hole image 205.In the present embodiment, in oxide layer 204, form altogether four via hole images 205, and this via hole image 205 ringwise.Oxide layer 204 mainly plays mask effect.The preparation method of oxide layer 204 adopts various depositing technics, as: the processes such as low-pressure chemical vapor phase deposition (LPCVD), plasma chemical vapor deposition (PECVD) or thermal oxide.
Incorporated by reference to Fig. 4, S23: adopt deep trouth reactive ion etching (DRIE) thus technique according in S23 step, obtain via hole image on substrate 21, carry out etching form through hole 251, meanwhile, be formed in the middle of through hole 251 and the electric connection part 24 being surrounded by through hole 251.From this step, can find out, this electric connection part 24 is to isolate formed by through hole 251 from substrate.Owing to being formed with four via hole images and via hole image ringwise in S22 step, so in this step, four ringwise through holes 251 of corresponding formation, meanwhile, the cross sectional shape of four corresponding electric connection parts 24 is circular.
Incorporated by reference to Fig. 5, S24: the interior first silicon oxide deposition of through hole 251 obtaining in S23 step is to form silicon oxide layer 253, and then will be deposited in the through hole 251 of silicon oxide layer 253 to fill up forming polysilicon layer 252 with polysilicon, thereby finally form isolation part 25.Owing to being formed with four ringwise through holes 251 in S23 step, so in this step, corresponding be formed with four ringwise isolation parts 25.
Above-mentioned steps can also adopt following step to replace: S24 ': the interior silicon oxide deposition 207 of through hole 251 obtaining in S23 step, to form described isolation part 25 ', refers to Figure 22.
Incorporated by reference to Fig. 6, S25: adopt CMP grinding technics to remove the oxide layer forming in S21 step.
Incorporated by reference to Fig. 7, S26: on the second surface 212 of substrate 21 of removing oxide layer, adopt the techniques such as metal deposit, photoetching, corrosion form respectively in order to S1 step in the first electrical bond chalaza of the first chip and the second electrical bond chalaza 22 of the first packaging ring bonding and the second packaging ring 23.This first electrical bond chalaza 22 is formed on the electric connection part 24 forming in S23 step, is electrically connected thereby realize with electric connection part 24.
In above-mentioned steps, in the time that the material of formation the first electrical bond chalaza is germanium, the material that forms the second electrical bond chalaza 22 is aluminium; Be gold when forming the material of the first electrical bond chalaza, the material that forms the second electrical bond chalaza 22 is polysilicon.The material that forms the second packaging ring 23 passes through to adopt the collocation of above-mentioned material with the material that forms the second electrical bond chalaza 22, make the thin thickness of the first electrical bond chalaza 16, the second electrical bond chalaza 22 and the first packaging ring 17, the second packaging ring 23, thereby reduce the volume of mems device 10 entirety.
Incorporated by reference to Fig. 8, S27: be again oxidized and obtain oxide layer 209 on the second surface 212 of the substrate 21 forming after S26 step, then draw a picture in oxide layer 209 and form cavity figure.The oxide layer 209 forming in this step is identical with the process of the oxide layer forming in S21 to S22 and via hole image with the process of cavity figure.
S28: form cavity 26 according to obtaining cavity figure in S27 step on substrate 21.This cavity 26 is adopt deep trouth reactive ion etching process to realize or adopt the mode of corrosive liquid wet etching to realize.
Incorporated by reference to Fig. 9, S29: adopt CMP grinding technics to remove the oxide layer forming in S27 step.
Incorporated by reference to Figure 14 to Figure 19, the electrical connection layer 3 in above-mentioned S5 step adopts following S51 step to S54 process to form.
Incorporated by reference to Figure 14, S51: on the first surface 211 of the substrate 21 after S4 step attenuate, silicon oxide deposition forms oxide layer 301.This oxide layer 301 mainly plays mask effect.The preparation method of oxide layer 301 is the various depositing technics of employing, as: the processes such as low-pressure chemical vapor phase deposition (LPCVD), plasma chemical vapor deposition (PECVD) or thermal oxide.
Incorporated by reference to Figure 15, S52: remove partial oxidation layer 301 to expose electric connection part 24 by techniques such as photoetching, dry etching or wet etchings.Incorporated by reference to Figure 16 and Figure 17, then deposit the first metal layer 302 form metal routing 303.Metal routing 303 middle parts are divided into electrical connection signal routing.Metal routing 303 can be adjusted wiring form according to the different structure form of different design needs, external circuitry.Its object is the electric connecting point of rationally arranging, and realizes with the optimization of external circuitry etc. and being connected.In the present embodiment, the external circuitry of electrical connection layer 3 correspondence is ASIC circuit.
Incorporated by reference to Figure 18 and Figure 19, S53: deposit one deck passivation layer 304 is as protective layer again.This passivation layer 304 can adopt silica or silicon nitride material.Its preparation method adopts various depositing technics, as: the processes such as low-pressure chemical vapor phase deposition (LPCVD), plasma chemical vapor deposition (PECVD) or thermal oxide.Its object is that the metal routing forming in S52 step 303 is separated with the external world, plays shielding.
S54: remove the passivation layer 304 forming in part S53 step and make to need to expose with the part of extraneous bonding in metal routing 303, simultaneously deposit the second metal level 305 on the metal routing 303 exposing.The material of the second metal level 305 of forming is in this step aluminium or gold.
Manufacture method by above-mentioned mems device can realize the hermetically sealed of mems device 10, simultaneously, because this preparation method adopts circle level encapsulation technology and will movable sensitive portion will be formed in a confined space by the second chip 2 and the first chip 1 bonding, make obtained mems device 10 there is the advantage that packaging cost is low and encapsulation volume is little and there is electro-magnetic screen function.
In sum: mems device 10 tools of the present invention have the following advantages:
1, pass through S1 step to S5 step, realize circle grade integrated and encapsulation of mems device 10, reduced the volume of mems device 10.
2, owing to adopting the first chip 1 and the second chip 2 bondings and the movable sensitive portion 152 of the first chip 1 is formed in seal cavity, and scribing is carried out after mems device 10 is sealed, in the time of scribing, be easy to impaired problem so can solve mems device 10 movable sensitive portions 152, avoid adopting the expensive dicing methods such as laser, saved cost.
3, owing to adopting the first chip 1 and the second chip 2 bondings and the movable sensitive portion 152 of the first chip 1 is formed in seal cavity, can when integrated, complete the vacuum seal to mems device 10 or mems device 10 is enclosed in some specific inert gas.In addition, in follow-up encapsulation, can adopt Plastic Package mode, but not expensive metal or ceramic package reduce packaging cost.
4, same, owing to adopting the first chip 1 and the second chip 2 bondings and the movable sensitive portion 152 of the first chip 1 is formed in seal cavity, so this mems device 10 can be realized the effect of electromagnetic shielding.
5, in above-mentioned mems device 10 preparation methods, due to the first electrical bond chalaza 16 and corresponding germanium material and aluminum or corresponding gold copper-base alloy and the polycrystalline silicon material of adopting of adopting of the second electrical bond chalaza 22, the first packaging ring 17 and the second packaging ring 23, so can attenuate the first electrical bond chalaza 16 and the thickness of the second electrical bond chalaza 22, the first packaging ring 17 and the second packaging ring 23, thereby also reduce the volume of mems device 10 entirety.
Although be example object, the preferred embodiment of the present invention is disclosed, but those of ordinary skill in the art will recognize, in the situation that not departing from by the disclosed scope and spirit of the present invention of appending claims, various improvement, increase and replacement are possible.
Claims (11)
1. a manufacture method for mems device, is characterized in that: described method comprises the steps:
S1: the first chip is provided, and described the first chip comprises mems device layer and be arranged at the first electrical bond chalaza on described mems device layer, and described mems device layer comprises movable sensitive portion;
S2: the second chip is provided, described the second chip comprise have the first surface that is oppositely arranged and second surface substrate, be arranged at the isolation part of extending towards first surface direction on described substrate and from the second surface of substrate, be arranged on the second electrical bond chalaza on described substrate second surface, described substrate also has the electric connection part with described the second electrical bond chalaza electrical connection, and described isolation part is around in the periphery of described electric connection part;
S3: the second chip bonding that the first chip that described S1 step is provided and described S2 step provide, the second surface of described substrate is towards the mems device layer of described the first chip, described the first electrical bond chalaza and the second electrical bond chalaza bonding;
S4: the substrate of the second chip after described S3 step bonding is carried out to attenuate operation to expose isolation part in its first surface;
S5: the first surface of the substrate after described S4 step attenuate forms the electrical connection layer with external circuitry electrical connection.
2. the manufacture method of mems device according to claim 1, is characterized in that: in described S26 step, the material that forms described the first electrical bond chalaza is germanium, and the material that forms described the second electrical bond chalaza is aluminium.
3. the manufacture method of mems device according to claim 1, is characterized in that: the material that forms described the first electrical bond chalaza is gold, and the material that forms described the second electrical bond chalaza is polysilicon.
4. according to the manufacture method of the mems device described in claim 1 or 2 or 3, it is characterized in that: the second chip providing in described S2 step adopts following technique to realize:
S21 a: substrate is provided, and the second surface that described substrate comprises first surface and is oppositely arranged with first surface is oxidized and obtains oxide layer on the second surface of described substrate;
S22: in the oxide layer obtaining in described S21 step, mapping forms a via hole image;
S23: form through hole according to obtaining via hole image in described S23 step on described substrate, be formed in the middle of described through hole and the described electric connection part being surrounded by described through hole;
S24: first deposit one deck silicon oxide layer in the through hole obtaining in described S23 step, then fills up to form described isolation part with polysilicon by the through hole that is deposited with silicon oxide layer;
S25: remove the oxide layer forming in S21 step;
S26: form described the second electrical bond chalaza on the second surface of substrate of removing oxide layer, the electric connection part electrical connection forming in described the second electrical bond chalaza and S23 step.
5. the manufacture method of mems device according to claim 4, is characterized in that: the second chip providing described in described S2 step also comprises the steps: after S26 step
S27: be again oxidized and obtain oxide layer on the second surface of the substrate forming after described S26 step, then draw a picture in oxide layer and form cavity figure;
S28: form cavity according to obtaining cavity figure in described S27 step on substrate;
S29: remove the oxide layer forming in described S27 step.
6. the manufacture method of mems device according to claim 5, it is characterized in that: the through hole in described S23 step adopts deep trouth reactive ion etching process to realize, the cavity in described S28 step adopts deep trouth reactive ion etching process to realize or adopts the mode of corrosive liquid wet etching to realize.
7. the manufacture method of mems device according to claim 4, is characterized in that: described S24 step can also adopt following steps to replace: S24 ': in the through hole obtaining in described S23 step, silicon oxide deposition is to form described isolation part.
8. the manufacture method of mems device according to claim 3, it is characterized in that: the first chip providing in described S1 step also comprises the first packaging ring that is positioned at the first electrical bond chalaza outside, in described S26 step, in forming described the second electrical bond chalaza, be also formed with the second packaging ring that is positioned at the second electrical bond chalaza outside.
9. the manufacture method of mems device according to claim 1, is characterized in that: the following technique of the concrete employing of electrical connection layer of described S5 step forms:
S51: the first surface silicon oxide deposition of the substrate after described S4 step attenuate is to form oxide layer;
S52: remove partial oxidation layer to expose electric connection part, then deposit the first metal layer form metal routing;
S53: deposit one deck passivation layer again;
S54: remove part passivation layer part metals cabling is exposed, simultaneously deposit the second metal level on the metal routing exposing.
10. the manufacture method of mems device according to claim 9, is characterized in that: the material of the passivation layer forming in described S53 step is silica or silicon nitride.
The manufacture method of 11. mems devices according to claim 9, is characterized in that: the material of the second metal level forming in described S54 step is aluminium or gold.
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| CN105967140A (en) * | 2016-07-27 | 2016-09-28 | 上海华虹宏力半导体制造有限公司 | Method for forming MEMS wafer electrical connection through polycrystal germanium-silicon through hole |
| CN106365115A (en) * | 2015-07-23 | 2017-02-01 | 上海丽恒光微电子科技有限公司 | MEMS sensor and preparation method thereof |
| CN106744656A (en) * | 2016-12-02 | 2017-05-31 | 华进半导体封装先导技术研发中心有限公司 | A kind of mems device method for packing and structure |
| CN107235468A (en) * | 2017-05-22 | 2017-10-10 | 苏州敏芯微电子技术股份有限公司 | A kind of mems device and its manufacture method |
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| CN105967140A (en) * | 2016-07-27 | 2016-09-28 | 上海华虹宏力半导体制造有限公司 | Method for forming MEMS wafer electrical connection through polycrystal germanium-silicon through hole |
| CN105967140B (en) * | 2016-07-27 | 2017-08-25 | 上海华虹宏力半导体制造有限公司 | Utilize the method for poly-SiGe through hole formation MEMS wafer electrical connection |
| CN106744656A (en) * | 2016-12-02 | 2017-05-31 | 华进半导体封装先导技术研发中心有限公司 | A kind of mems device method for packing and structure |
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| CN109205550A (en) * | 2017-06-30 | 2019-01-15 | 台湾积体电路制造股份有限公司 | MEMS devices structure and forming method thereof |
| CN109205550B (en) * | 2017-06-30 | 2020-11-24 | 台湾积体电路制造股份有限公司 | MEMS device structure and method of forming the same |
| US10865100B2 (en) | 2017-06-30 | 2020-12-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming micro-electro-mechanical system (MEMS) structure |
| CN107963609A (en) * | 2017-11-16 | 2018-04-27 | 北京航天控制仪器研究所 | A kind of total silicon MEMS wafer-grade vacuum encapsulation methods based on anode linkage |
| CN107963609B (en) * | 2017-11-16 | 2019-07-12 | 北京航天控制仪器研究所 | A kind of total silicon MEMS wafer-grade vacuum encapsulation method based on anode linkage |
| CN109835865A (en) * | 2017-11-28 | 2019-06-04 | 台湾积体电路制造股份有限公司 | Wafer scale integrated MEMS device is realized by silicon column and smart cap |
| CN109835865B (en) * | 2017-11-28 | 2022-10-04 | 台湾积体电路制造股份有限公司 | Wafer-level integrated MEMS device realized through silicon column and intelligent cap |
| CN107986229A (en) * | 2017-12-04 | 2018-05-04 | 成都振芯科技股份有限公司 | A kind of boring device of micro electro mechanical device and its multiplexing method of preparation |
| CN107986229B (en) * | 2017-12-04 | 2020-09-29 | 成都振芯科技股份有限公司 | Opening device of micro-electro-mechanical device and preparation multiplexing method thereof |
| CN108083226A (en) * | 2017-12-05 | 2018-05-29 | 北京航天控制仪器研究所 | A kind of MEMS device wafer-grade vacuum encapsulation method |
| CN108083226B (en) * | 2017-12-05 | 2020-04-10 | 北京航天控制仪器研究所 | Wafer-level vacuum packaging method for MEMS (micro-electromechanical systems) device |
| CN110562910A (en) * | 2019-08-27 | 2019-12-13 | 华东光电集成器件研究所 | MEMS wafer level vacuum packaging method |
| CN111762752A (en) * | 2020-05-25 | 2020-10-13 | 深迪半导体(上海)有限公司 | MEMS device and method of manufacturing the same |
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