CN105793967A - 具有最大顺从性和自由表面弛豫的Ge和III-V族沟道半导体器件 - Google Patents
具有最大顺从性和自由表面弛豫的Ge和III-V族沟道半导体器件 Download PDFInfo
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- CN105793967A CN105793967A CN201380079044.1A CN201380079044A CN105793967A CN 105793967 A CN105793967 A CN 105793967A CN 201380079044 A CN201380079044 A CN 201380079044A CN 105793967 A CN105793967 A CN 105793967A
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Classifications
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract
说明了具有最大顺从性和自由表面弛豫的Ge和III?V族沟道半导体器件及制造这种Ge和III?V族沟道半导体器件的方法。例如,一种半导体器件包括布置在半导体衬底上的半导体鳍状物。半导体鳍状物具有中心突出或凹陷段,沿半导体鳍状物的长度与突出外侧段对间隔开。覆层区布置在半导体鳍状物的中心突出或凹陷段上。栅极叠置体布置在覆层区上。源极区/漏极区布置在半导体鳍状物的所述突出外侧段对中。
Description
技术领域
本发明的实施例属于半导体器件和工艺领域,具体而言,属于具有最大顺从性和自由表面弛豫的Ge和III-V族沟道半导体器件及制造这种Ge和III-V族沟道半导体器件的方法。
背景技术
过去几十年中,集成电路中部件的规模缩小是日益增长的半导体工业背后的驱动力。到越来越小的部件的规模缩小实现了功能单元在半导体芯片的有限基板面上增大的密度。例如,收缩晶体管尺寸允许在芯片上包含增大数量的存储或逻辑器件,导致制造出具有增大容量的产品。但对于更大容量的驱策并非没有问题。优化每一个器件的性能的必要性变得日益显著。
在集成电路器件的制造中,随着器件尺寸不断缩小,诸如鳍式场效应晶体管(fin-FET)的多栅晶体管已经变得更为普遍。在传统工艺中,通常在大块硅衬底或绝缘体上硅结构衬底上制造fin-FET。在一些实例中,由于其较低的成本和与现有高产量大块硅衬底基础结构的兼容性,大块硅衬底是优选的。
但多栅晶体管的规模缩小并非没有结果。随着微电子电路的这些基本结构单元的尺寸减小,并且随着在给定区域中制造的基本结构单元的绝对数量增大,对用于制造这些结构单元的半导体工艺的约束变得令人难以应对。
附图说明
图1A示出了现有技术的Ge/III-V族元素上Si非平面器件的斜角三维横截面图。
图1B示出了其上具有栅极线和源极触点/漏极触点的图1A的Ge/III-V族元素上Si非平面器件的平面图。
图1C是根据本发明实施例的显示各种器件架构的相对覆层参数的曲线图。
图2A-2C示出了根据本发明实施例的制造具有保留的2x栅极间距可容空间的短鳍器件的方法中的多个操作的横截面图,其中:
图2A示出了描绘具有2x栅极间距的总长,但具有与外侧段隔离的中心段的半导体鳍状物的平面图和横截面图;
图2B示出了描绘覆层在图2A的结构上的生长的横截面图;
图2C示出了描绘栅极线与源极触点/漏极触点在图2B的结构上形成的横截面图。
图3A-3D示出了根据本发明实施例的制造具有轴向沟道生长和保留的2x栅极间距可容空间的鳍式器件的方法中的多个操作的横截面图,其中:
图3A示出了描绘具有2x栅极间距的总长,但具有与外侧段隔离的中心段的半导体鳍状物的平面图和横截面图;
图3B示出了描绘图3A的鳍状物的中心段的凹陷的横截面图;
图3C示出了描绘覆层在图3B的结构上生长的横截面图;
图3D示出了描绘栅极线与源极触点/漏极触点在图3C的结构上形成的横截面图。
图4是根据本发明实施例的根据覆层成分的模拟外延层应力(GPa中)的曲线图。
图5A示出了根据本发明实施例的具有最大顺从性和自由面弛豫的Ge或III-V族沟道半导体器件的横截面图。
图5B示出了根据本发明实施例的沿图5A的半导体器件的a-a’轴得到的平面图。
图6示出了根据本发明一个实现方式的计算设备。
具体实施方式
说明了具有最大顺从性和自由面弛豫的Ge和III-V族沟道半导体器件及制造这种Ge和III-V族沟道半导体器件的方法。在以下说明中,阐述了多个特定细节,例如特定集成和材料状况,以便提供对本发明的实施例的透彻理解。对于本领域技术人员来说,显然,本发明的实施例的实践可以无需这些特定细节。在其他实例中,没有详细说明诸如集成电路设计布局的公知的特征,以免不必要地使得本发明的实施例模糊不清。而且,会理解,附图中所示的不同实施例是说明性表示,不一定按照比例绘制。
将高迁移率沟道材料集成到硅(Si)上的一个可能的方式是借助在Si纳米级模板上的薄覆层。本文所述的一个或多个实施例针对用于使得锗(Ge)和III-V族晶体管中的顺从性和自由面弛豫最大的技术。一个或多个实施例针对一个或多个覆层、顺从性外延、锗沟道区、III-V族材料沟道区、包括金属氧化物半导体(MOS)和互补金属氧化物半导体(CMOS)器件和复合半导体(III到V)器件的晶体管制造。
具体而言,本文所述的一个或多个实施例提供了用于改进适应III-V族和Ge沟道晶体管器件的外延生长质量的方案。为了提供背景,对于现有技术的三栅晶体管,将鳍状物长度设定为约2x栅极间距。因此,如果使用的话就必须在这个长度的鳍状物上生长覆层。相反,本文所述的一个或多个实施例使有源沟道鳍状物长度与设定为2x栅极间距的典型鳍状物长度脱离关系。这种脱离关系可以实现在较短鳍状物部分或段上改进的顺从性生长。另外,在一个此类实施例中,有源沟道鳍状物也可以凹陷,用以为在高性能器件的沟道区中的大多数理想III-V族材料或Ge外延生长提供进一步改进的顺从性/自由面弛豫。
具有用以提供顺从性效果的覆层的顺从性衬底或非平面半导体基体典型地包括在薄鳍式硅鳍状物或衬底上生长Ge或III-V族膜。这个布置不仅允许沉积膜,还允许薄Si-Fin(适应的)以适应膜中的一些晶格失配和应变,实现缺陷减少。作为参考点,具有形成于其上的覆层的硅鳍状物可以提供顺从性的衬底。Ge和III-V族的覆层形成于一部分鳍状物上,以提供高迁移率沟道层。覆层具有比硅鳍状物更大的晶格常数,因而使得两层应变。当使用窄鳍状物Wsi时实现了鳍状物对覆层的顺从性,导致有益的自由面效果。具体而言,薄硅鳍状物和覆层最终“顺从”或伸展以适应在其自由面的外延生长。
如上所述,现有技术的非平面器件具有设定为栅极线间距两倍的鳍状物长度。形成于例如硅鳍状物的这个鳍状物上的覆层形成在鳍状物的整个长度上。结果得到的顺从性效果在如此规模上可能不是最佳的,会导致更多数量的缺陷。作为现有方案的示例,图1A和1B分别示出了Ge/III-V族元素上Si非平面器件的斜角三维横截面图和平面图。参考图1A,器件100包括硅鳍状物102,具有宽度(d)和长度(L)。将硅鳍状物102显示为大块硅鳍状物,其中,鳍状物通过隔离区104延伸,耦合到下层硅衬底(未示出)。Ge或III-V族材料覆层106布置在鳍状物102的露出或突出部分的表面上。如图1A所示的,覆层具有厚度(t),沿鳍状物102的整个长度(L)延伸。参考图1B,从鳍状物上方显示了器件100,栅极线108和源极触点/漏极触点110形成于鳍状物上,即形成于覆层106上。如图1B所示的,鳍状物102的长度等于栅极间距。因而,器件100的覆层106延伸的程度为栅极线间距的两倍。
图1C是根据本发明实施例的显示各种器件架构的相对覆层参数的曲线图150。参考曲线图150,为在隔离层158上具有厚度(d)的有源区156上具有覆层154的薄硅器件152、为在具有宽度(d)并突出到隔离层168以上的有源区166上具有覆层164的传统三栅鳍式器件162、为具有围绕具有高度(d)的有源区176的覆层174的纳米带器件172、为具有围绕具有直径(d)的有源区186的覆层184的核壳纳米线器件182、和为在具有宽度(d)的有源区196上具有覆层194的轴向纳米线192确定匹配的最小面板尺寸。在曲线图150中为器件152、162、172、182和192显示了相对衬底顺从性、自由面弛豫和临界厚度(tc)。再次参考图1C,对于传统三栅器件的一个潜在缺点是鳍状物长度依赖于栅极间距,这需要(i)必须覆盖整个鳍状物长度(它是2x栅极间距),(ii)由于这个约束,不能使得有效覆盖的鳍状物沟道较短(要不然这会是对顺从性的改进),及(iii)不能利用有源沟道中的轴向覆层结构,要不然这会为顺从性提供最佳结构。
与图1A和1B的覆层三栅结构相反,其在图1C中作为基准,总体上,本文所述的一个或多个实施例提供了用于为了改进的生长/顺从性而制造基于较短鳍状物Si的段的方案。在第一示例中,图2A-2C示出了根据本发明实施例的制造具有保留的2x栅极间距可容空间的短鳍器件的方法中的多个操作的横截面图。
参考图2A,平面图和横截面图描绘了具有2x栅极间距的总长,但具有与外侧段206隔离的中心段204的半导体鳍状物202。鳍状物202突出到隔离区208上,隔离区208进一步布置在鳍状物202的中心段204与外侧段206之间。因而,鳍状物202有效地表示了切割为三个段的传统鳍状物。在一个实施例中,鳍状物202是大块硅鳍状物硅,隔离区由二氧化硅组成,如所示的。在一个实施例中,与传统大块三栅制造方案一致,鳍状物202首先形成于下层大块衬底中。隔离材料随后形成于鳍状物上,随后凹陷以露出鳍状物的突出部分。但根据本发明的一个实施例,鳍状物形成进一步包括在隔离沉积和凹陷之前的如所示的段的切割(例如借助图案化和蚀刻工艺)。会意识到,得到的鳍状物202是如所示的沿着源极到漏极区的单鳍状物,不只是多个鳍状物。
参考图2B,横截面图描绘覆层210在图2A的结构上的生长。具体而言,覆层210在鳍状物202的中心段204和外侧段206上外延生长。但代替沿整个鳍状物长度生长单一覆层区,在鳍状物202的中心段204上生长第一覆层区210A。在鳍状物202的外侧段206上生长第二覆层区210B。覆层区210A和210B在分界面211结合。但将覆层区210A形成为不同的区。这实现了最高质量的覆层生长和最佳衬底顺从性,因为区210A的生长局限于鳍状物202的中心区204。效果是相对于鳍状物的整个长度,缩短了生长的覆层210A的长度。通过减小长度,增强了在鳍状物202的沟道区的顺从性,在沟道区最需要它。会意识到,区210B沿着鳍状物202的较长部分延伸是非常好的,因此,具有比区210A更小的顺从性效果和/或更低的质量。
参考图2C,横截面图描绘了栅极线212与源极触点/漏极触点214在图2B的结构上的形成。具体而言,栅极线212形成于覆层区210A上面/之上。源极触点/漏极触点214形成于覆层区210B上面/之上。于是,得到的器件在栅极线212下面提供高顺从性覆层区210A。半导体器件的全部鳍状物202包括区206和204,连同覆层区210A和210B。会意识到,图2C的结构随后可以受到进一步的处理,诸如后端金属化,以便将器件包含在集成电路中,例如CMOS集成电路。
在第二示例中,图3A-3D示出了根据本发明实施例的制造具有轴向沟道生长和保留的2x栅极间距可容空间的鳍式器件的方法中的多个操作的横截面图。
参考图3A,平面图和横截面图描绘了具有2x栅极间距的总长,但具有与外侧段306隔离的中心段304的半导体鳍状物302。鳍状物302突出到隔离区308上,隔离区308进一步布置在鳍状物302的中心段304与外侧段306之间。因而,鳍状物302有效地表示了切割为三个段的传统鳍状物。在一个实施例中,鳍状物302是大块硅鳍状物硅,隔离区由二氧化硅组成,如所示的。在一个实施例中,与传统大块三栅制造方案一致,鳍状物302首先形成于下层大块衬底中。隔离材料随后形成于鳍状物上,随后凹陷以露出鳍状物的突出部分。但根据本发明的一个实施例,鳍状物形成进一步包括在隔离沉积和凹陷之前的如所示的段的切割(例如借助图案化和蚀刻工艺)。
参考图3B,横截面图描绘了鳍状物302的中心段304的凹陷。具体而言,中心段304凹陷以提供更改的鳍状物302A的凹陷中心段304A。会意识到,得到的鳍状物302A是如所示的沿着源极到漏极区的单鳍状物,不只是多个鳍状物。可以通过图案化和蚀刻工艺执行凹陷。在一个实施例中,执行凹陷以大约在隔离区308的高度提供凹陷的中心段304A,如图3B所示的。
参考图3C,横截面图描绘了覆层310在图3B的结构上的生长。具体而言,覆层310在鳍状物302的凹陷中心段304A和外侧段306上外延生长。但代替沿整个鳍状物长度生长单一覆层区,在鳍状物302A的凹陷中心段304上生长第一覆层区310A。在鳍状物302A的外侧段306上生长第二覆层区310B。覆层区310A和310B在分界面311结合。但将覆层区310A形成为不同的区。这实现了最高质量的覆层生长和最佳衬底顺从性,因为区310A的生长局限于鳍状物302A的凹陷中心区304A。效果是相对于鳍状物的整个长度,缩短了生长的覆层310A的长度。通过减小长度,增强了在鳍状物302A的沟道区的顺从性,在沟道区最需要它。会意识到,区310B沿着鳍状物302A的较长部分延伸是非常好的,因此,具有比区310A更小的顺从性效果和/或更低的质量。
参考图3D,横截面图描绘了栅极线312与源极触点/漏极触点314在图3C的结构上的形成。具体而言,栅极线312形成于覆层区310A上面/之上。源极触点/漏极触点314形成于覆层区310B上面/之上。于是,得到的器件在栅极线312下面提供高顺从性覆层区310A。半导体器件的全部鳍状物302A包括区306和304A,连同覆层区310A和310B。会意识到,图3D的结构随后可以受到进一步的处理,诸如后端金属化,以便将器件包含在集成电路中,例如CMOS集成电路。
在实施例中,覆层310具有比下层Si更低的带隙和更大的晶格常数。覆层310可以具有适合于传播很大一部分波函数的厚度,例如适合于禁止相当大部分的波函数进入Si鳍状物。但覆层310可以对于顺从性足够薄。在一个实施例中,覆层310的厚度约在10-50埃范围中。覆层310可以借助例如但不限于化学气相(CVD)或分子束外延(MBE)或其他类似的工艺来形成。
在第一实施例中,覆层310是锗(Ge)覆层,例如纯的或基本上纯的锗覆层。如本文通篇使用的,术语纯的或基本上纯的锗可以用于说明由极大量的锗,即使不是全部,组成的锗材料。但会理解,实际上,100%纯的Ge难以构成,因此可以包括极小百分比的Si。Si可以作为在Ge的沉积过程中不可避免的杂质或成分被包含,或者可以在沉积后处理过程中在扩散时“污染”Ge。因而,本文针对Ge覆层所述的实施例可以包括Ge材料,其包含相对少量的例如“杂质”级非Ge原子或核素,例如Si。此外,在可替换的实施例中,使用了SiGe,例如SixGey层,其中,0<x<100,0<y<100,具有相对于硅的高百分比Ge含量。
在第二实施例中,覆层310是III-V族材料覆层。即,在一个实施例中,覆层310由III族(例如硼、铝、镓或铟)或V族(例如氮、磷、砷或锑)元素组成。在一个实施例中,覆层310由二元成分(例如GaAs)组成,但也可以是基于三元或四元的III-V族材料等。
如上所述,在一个实施例中,图2A和3A的例示开始了鳍状物蚀刻和隔离氧化物沉积之后的浅槽隔离(STI)抛光后的工艺流程说明。会意识到,还去除了由于鳍状物202或302的制造而一度残留的人工产物。例如在一个实施例中,从鳍状物202或302的顶部表面去除了诸如氮化硅硬掩模层的硬掩模层和诸如二氧化硅层的衬垫氧化物层。在一个实施例中,相应的大块衬底及因此的鳍状物202或302在这个阶段是未掺杂的或者略微掺杂的。例如,在特定实施例中,大块衬底及因此的鳍状物202或302具有的硼掺杂剂杂质原子的浓度小于约1E17原子/cm3。但在其他实施例中,阱区离子注入和/或逆行注入已经或者将提供给鳍状物202或302和下层结构。在一个此类实施例中,露出的鳍状物202或302的这种掺杂会导致在相应大块衬底部分内的掺杂,在此邻近的鳍状物共享大块衬底中共同掺杂的区域。
在实施例中,再次参考图2A和3A,电介质层208或308由二氧化硅组成,例如用于浅槽隔离制造工艺中的。电介质层208或308可以借助化学气相沉积(CVD)或其他沉积工艺(例如ALD、PECVD、PVD、HDP辅助的CVD、低温CVD)来沉积,并可以借助化学机械抛光(CMP)技术来平面化。平面化还可以从鳍状物图案形成中去除任何人工产物,例如硬掩模层和/或衬垫氧化物层,如上所述。在一个实施例中,用以提供隔离区208或308的电介质层凹陷限定了初始Si沟道高度(HSI)。凹陷可以借助等离子体、蒸汽或湿法蚀刻工艺来执行。在一个实施例中,使用了对于硅鳍状物202或302有选择性的干法蚀刻工艺,干法蚀刻工艺基于从气体产生的等离子体,例如但不限于NF3、CHF3、C4F8、HBr和O2,具有在30-100mTorr范围中的典型压力和50-1000瓦的等离子体偏压。在相关于图2A-2C所述的过程的情况下,保留了初始Si沟道高度(HSI)。但在相关于图3A-3D所述的过程的情况下,在中心鳍状物部分凹陷后减小了初始Si沟道高度(HSI)。会意识到,用于顺从性衬底制造的覆层生长增大了总鳍状物高度,其基于HSI和上覆层厚度。
在实施例中,栅极线212或312图案化包括多晶硅光刻以借助随后的SiN硬掩模和多晶硅的蚀刻来限定多晶硅栅极(永久的或者用于取代栅极工艺的预留位置)。在一个实施例中,掩模形成于硬掩模上,掩模由形貌遮掩部分和抗反射涂层(ARC)组成。在一个此类特定实施例中,形貌遮掩部分是碳硬掩模(CHM)层,抗反射涂层是硅ARC层。形貌遮掩部分和ARC层可以借助传统光刻和蚀刻工艺技术来形成图案。在一个实施例中,掩模还包括最上面的光致抗蚀剂层,如本领域中已知的,并可以借助传统光刻和显影工艺来形成图案。在一个特定实施例中,光致抗蚀剂层暴露于光源的部分在显影光致抗蚀剂层后被去除。因而,形成图案的光致抗蚀剂层由正性光致抗蚀剂材料组成。在一个特定实施例中,光致抗蚀剂层由正性光致抗蚀剂材料组成,例如但不限于,248nm抗蚀剂,193nm抗蚀剂,157nm抗蚀剂,极远紫外(EUV)抗蚀剂、e-束印记层和具有邻叠氮萘醌敏化剂的酚醛树脂基体。在另一个特定实施例中,光致抗蚀剂层暴露于光源的部分在显影光致抗蚀剂层后保留。因而,光致抗蚀剂层由负性光致抗蚀剂材料组成。在一个特定实施例中,光致抗蚀剂层由负性光致抗蚀剂材料组成,例如但不限于,由聚-顺式-异戊二烯和聚-乙烯基-肉桂酸组成。
与图2C和2D中所示的结构有关的,图4是根据本发明实施例的根据覆层成分的模拟外延层应力(GPa中)的曲线图400。参考曲线图400,硅鳍状物上的InxGa1-xAs覆层的应力描绘为x增大的值的函数。数据线402表示对于无限长度的4nm宽Si鳍状物上的2nm厚覆层的应力。数据线404表示对于84nm长度的4nm宽Si鳍状物上的2nm厚覆层的应力。由于自由面弛豫,相对应力在较短鳍状物中降低。
一般地,再次参考图2A-2C和3A-3D,在一个实施例中,所述的方案可以用于N型(例如NMOS)或P型(例如PMOS)或者二者的器件制造。会理解,由以上示例性处理方案得到的结构,例如来自图2C和3D的结构,可以以相同或相似的形式用于随后的处理操作中来完成器件制造,例如PMOS和NMOS器件制造。作为完成的器件的示例,图5A和5B分别示出了本发明实施例的具有最大顺从性和自由面弛豫的Ge或III-V族沟道半导体器件的横截面图和(沿横截面图的a-a’轴得到的)平面图。
参考图5A,半导体结构或器件500包括从衬底502形成的并且在隔离区506内的非平面有源区(例如包括突出鳍状物部分504和鳍状物下区域505的鳍状物结构)。在所示的情况下,三个不同的鳍状物包括在单一器件中。形成沟道区覆层597以包围每一个鳍状物的突出区504。尽管未示出,但会意识到,每一个鳍状物的覆层597(如在垂直于纸面的方向上考虑的)都没有沿着整个鳍状物的长度延伸。代之以按照相关于图2A-2C和3A-3D所述的方式缩短了以提供增强的顺从性效果。
再次参考图5A,栅极限508布置在非平面有源区的突出部分504以及一部分隔离区506上。如所示的,栅极限508包括栅极电极550和栅极电介质层552。在一个实施例中,栅极限508还包括电介质端盖层554。还可以从这个透视图中见到栅极触点514和上覆栅极触点通孔516,连同上覆金属互连560,它们全都布置在夹层电介质叠置体或层570中。由图5A的透视图同样见到,在一个实施例中,栅极触点514布置在隔离区560上,但没有在非平面有源区上。
参考图5B,栅极线508显示为布置在突出鳍状物部分504上。可以从这个透视图见到突出鳍状物部分504的源极和漏极区504A和504B。在一个实施例中,源极和漏极区504A和504B是突出鳍状物部分504/597的原始材料的掺杂部分。在另一个实施例中,例如借助外延沉积去除了突出鳍状物部分504/597的材料,并代之以另一个半导体材料。在此情况下,还去除了局限于源极和漏极区的覆层部分。在任一情况下,源极和漏极区504A和504B都可以在电介质层506的高度下延伸,即进入鳍状物下区域505中。可替换地,源极和漏极区504A和504B没有在电介质层506的高度下延伸,或者在电介质层506的高度上或者与之共面。
在实施例中,半导体结构或器件500是非平面器件,例如但不限于fin-FET。但也可以制造三栅或类似的器件。在这个实施例中,相应的半导体沟道区由三维基体组成或形成。在一个此类实施例中,栅极线508的栅极电极叠置体至少围绕三维基体的顶部表面和一对侧壁,如图5A所示的。
衬底502可以由半导体材料组成,其可以经受制造过程,并且电荷可以在其中迁移。在一个实施例中,衬底502是大块衬底,由以电荷载流子掺杂的晶体硅层组成,电荷载流子例如但不限于,磷、砷、硼或其组合,用以形成有源区504/505。在一个实施例中,大块衬底502中硅原子的浓度大于99%。在另一个实施例中,大块衬底502由在不同晶体衬底顶上生长的外延层组成,例如在硼掺杂的大块硅单晶衬底顶上生长的硅外延层。可替换地,代替大块衬底,可以使用绝缘体上硅结构(SOI)衬底。在一个特定实施例中,衬底502及因此的鳍状物的冲突部分504由单晶硅组成,覆层597是Ge覆层或III-V组材料覆层,如上所述的。
隔离区506可以由适合于最终将永久栅极结构与下层大块衬底电隔离或对隔离有贡献的,或者隔离在下层大块衬底内形成的有源区的材料组成,例如隔离鳍状物有源区。例如,在一个实施例中,隔离区506由电介质材料组成,例如但不限于,二氧化硅、氮氧化硅、氮化硅、或碳掺杂的氮化硅。
栅极线508可以由栅极电极叠置体组成,其包括栅极电介质层552和栅极电极层550。在一个实施例中,栅极电极叠置体的栅极电极由金属栅极组成,栅极电介质由高K材料组成。例如,在一个实施例中,栅极电介质层由诸如但不限于氧化铪、氮氧化铪、硅酸铪、氧化镧、氧化锆、硅酸锆、氧化钽、钛酸锶钡、钛酸钡、钛酸锶、氧化钇、氧化铝、钽酸钪铅、和铌酸锌铅或其组合组成。而且,一部分栅极电介质层可以包括一个或几个单层的本征氧化物,其由覆层597的顶部几层形成。
在一个实施例中,栅极电极由金属层组成,例如但不限于,金属氮化物、金属碳化物、金属硅化物、金属铝化物、铪、锆、钛、钽、铝、钌、钯、铂、钴、镍、或导电金属氧化物。在一个特定实施例中,栅极电极由在金属功函数设定层上形成的非功函数设定填充材料组成。
与栅极电极叠置体相关的间隔体(未示出)可以由适合于最终将永久栅极结构与诸如自对准触点之类的邻近导电触点电隔离或者对隔离有贡献的材料组成。例如,在一个实施例中,间隔体由绝缘电介质材料组成,例如但不限于氧化硅、氮氧化硅、氮化硅或硼掺杂的氮化硅。
栅极触点514和上覆栅极触点通孔516可以由导电材料组成。在一个实施例中,一个或多个触点或通孔由金属类组成。金属类可以是诸如钨、镍或钴的纯金属,或者可以是合金,例如金属-金属合金或者金属-半导体合金(例如硅化物材料)。
在实施例中(尽管未示出),提供结构500包括形成触点图案,其基本上极佳地对准现有栅极图案,同时借助极其严格的配准预算而无需使用光刻步骤。在一个此类实施例中,这个方案实现了使用本征高选择性示范蚀刻(例如相对于传统实施的干法或等离子体蚀刻)来产生触点开口。在一个实施例中,通过利用现有栅极图案结合触点插塞光刻操作来形成触点图案。在一个此类实施例中,该方案实现了无需用以产生触点图案的另外的临界光刻操作,如传统方案中使用。在一个实施例中,不单独形成沟槽接触栅的图案,而是在多(栅极)线之间形成。例如,在一个此类实施例中,沟槽接触栅在选通光栅图案化之后但在选通光栅切割之前形成。
而且,栅极叠置体结构508可以由取代栅极工艺制造。在这个方案中,可以去除诸如多晶硅或氮化硅支柱材料的虚设栅材料,并以永久栅极电极材料代替。在一个此类实施例中,在这个过程中还形成永久栅极电介质层,与由较早处理完成相反。在一个实施例中,借助干法蚀刻或湿法蚀刻工艺去除虚设栅。在一个实施例中,虚设栅由多晶硅或非晶硅组成,借助包括使用SF6的干法蚀刻工艺去除。在另一个实施例中,虚设栅由多晶硅或非晶硅组成,借助包括使用NH4OH水溶液或氢氧化四甲铵的湿法蚀刻工艺去除。在一个实施例中,虚设栅由氮化硅组成,借助包括磷酸水溶液的湿法蚀刻去除。在一个实施例中,另外执行以永久栅极电介质层代替虚设栅电介质层。
在实施例中,本文所述的一个或多个方案实质上设想了虚设和取代栅极工艺结合虚设和取代触点工艺来得到结构500。在一个此类实施例中,在取代栅极工艺之后执行取代触点工艺,以允许至少一部分永久栅极叠置体的高温退火。例如,在一个此类具体实施例中,例如在形成栅极电介质层之后,以大于约600摄氏度的温度执行至少一部分永久栅极结构的退火。退火在形成永久触点之前执行。
再次参考图5A,半导体结构或器件500的布置将栅极触点设置在隔离区上。这个布置可以视为布局空间的无效使用。但在另一个实施例中,半导体器件具有接触栅极电极形成于有源区上的部分的触点结构。通常,在栅极的有源部分上并与沟槽触点通孔在同一层中形成栅极触点结构(例如通孔)之前(例如除此之外),本发明的一个或多个实施例包括首先使用栅极对准沟槽触点工艺。可以实施这个工艺来为半导体结构制造,例如集成电路制造,形成沟槽触点结构。在一个实施例中,将沟槽触点图案形成为与现有栅极图案对准。相反,传统方案典型地包括额外的光刻工艺,借助光刻触点图案与现有栅极图案的严格配置,并结合选择性触点蚀刻。例如,传统工艺可以包括多(栅极)栅的图案化与触点部件的单独图案化。
会理解,并非需要实践上述工艺的全部方案以属于本发明的实施例的精神和范围内。例如,在一个实施例中,在栅极叠置体的有源部分上制造栅极触点之前不必形成虚设栅。上述的栅极叠置体实际上可以是初始形成的永久栅极叠置体。此外,本文所述的工艺可以用于制造一个和多个半导体器件。半导体器件可以是晶体管或类似器件。例如,在一个实施例中,半导体器件是金属氧化物半导体场效应晶体管(MOS)晶体管,用于逻辑器件或存储器,或者是双极型晶体管。此外,在一个实施例中,半导体器件具有三维架构,例如fin-FET器件、三栅器件或独立凹陷的双栅极器件。一个或多个实施例尤其可以用于在14纳米(14)或更小技术节点制造半导体器件。
于是总体上,上述的一个或多个实施例允许有源沟道鳍状物长度与典型的鳍状物长度=2x栅极间距脱离关系。由于缩短了鳍状物,这允许更好的顺从性生长。另外,还可以使得有源沟道鳍状物凹陷,为在沟道中的III-V族或Ge外延生长提供甚至更好的顺从性/自由面弛豫。因而,诸如Ge或III-V族的创新高迁移率材料可以引入到晶体管沟道中,例如对于前者的PMOS和对于后者的NMOS。
图6示出了根据本发明一个实现方式的计算设备600。计算设备600容纳板602。板602可以包括多个组件,包括但不限于,处理器604和至少一个通信芯片606。处理器604物理且电耦合到板602。在一些实现方式中,至少一个通信芯片606也物理且电耦合到板602。在进一步的实现方式中,通信芯片606是处理器604的一部分。
取决于其应用,计算设备600可以包括其他组件,其会或不会物理且电耦合到板602。这些其他组件包括但不限于,易失性存储器(例如,DRAM)、非易失性存储器(例如ROM)、闪存、图形处理器、数字信号处理器、加密处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编码解码器、视频编码解码器、功率放大器、全球定位系统(GPS)设备、指南针、加速度计、陀螺仪、扬声器、相机和大容量储存设备(例如,硬盘驱动器、光盘(CD)、数字多用途盘(DVD)等等)。
通信芯片606实现了无线通信,用于往来于计算设备600传送数据。术语“无线”及其派生词可以用于描述可以例如通过非固态介质借助使用调制电磁辐射传送数据的电路、设备、系统、方法、技术、通信信道等。该术语并非暗示相关设备不包含任何导线,尽管在一些实施例中它们可以不包含。通信芯片606可以实施多个无线标准或协议中的任意一个,包括但不限于,Wi-Fi(IEEE 802.11族)、WiMAX(IEEE 802.16族)、IEEE 802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、其派生物,以及被指定为3G、4G、5G及之后的任何其他无线协议。计算设备600可以包括多个通信芯片606。例如,第一通信芯片606可以专用于近距离无线通信,例如Wi-Fi和蓝牙,第二通信芯片606可以专用于远距离无线通信,例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等。
计算设备600的处理器604包括封装在处理器604内的集成电路晶片。在本发明的实施例的一些实现方式中,处理器的集成电路晶片包括一个或多个器件,例如根据本发明的实现方式构成的具有最大顺从性和自由面弛豫的一个或多个器件,例如Ge或III-V族沟道半导体器件。术语“处理器”可以指代任何设备或设备的部分,其处理来自寄存器和/或存储器的电子数据,将该电子数据转变为可以存储在寄存器和/或存储器中的其他电子数据。
通信芯片606也包括封装在通信芯片606内的集成电路晶片。根据本发明的另一个实现方式,通信芯片的集成电路晶片包括一个或多个器件,例如根据本发明的实现方式构成的具有最大顺从性和自由面弛豫的Ge或III-V族沟道半导体器件。
在进一步的实现方式中,容纳在计算设备600中的另一个组件可以包含集成电路晶片,其包括一个或多个器件,例如根据本发明的实现方式构成的具有最大顺从性和自由面弛豫的Ge或III-V族沟道半导体器件。
在多个实施例中,计算设备600可以是膝上型电脑、上网本电脑、笔记本电脑、超级本电脑、智能电话、平板电脑、个人数字助理(PDA)、超移动PC、移动电话、台式计算机、服务器、打印机、扫描器、监视器、机顶盒、娱乐控制单元、数码相机、便携式音乐播放器、或数码摄像机。在进一步的实现方式中,计算设备600可以是处理数据的任何其他电子设备。
因而,本发明的实施例包括具有最大顺从性和自由面弛豫的Ge或III-V族沟道半导体器件和制造这种Ge或III-V族沟道半导体器件的方法。
在一个实施例中,一种半导体器件包括半导体鳍状物,布置在半导体衬底上。半导体鳍状物具有中心突出段,沿半导体鳍状物的长度与突出外侧段对间隔开。覆层区布置在半导体鳍状物的中心突出段上。栅极叠置体布置在覆层区上。源极区/漏极区布置在半导体鳍状物的所述突出外侧段对中。
在一个实施例中,半导体器件进一步包括第二覆层区,布置在所述突出外侧段对中的一个上。第三覆层区布置在所述突出外侧段对中的另一个上。第二覆层区和第三覆层区与布置在半导体鳍状物的中心突出段上的覆层区分离但相邻。
在一个实施例中,半导体鳍状物和覆层区共同提供顺从性的衬底。
在一个实施例中,所述中心突出段由隔离层与所述突出外侧段对隔开。
在一个实施例中,半导体鳍状物实质上由硅组成,覆层区实质上由锗组成。
在一个实施例中,半导体器件是PMOS器件。
在一个实施例中,所述半导体鳍状物实质上由硅组成,所述覆层区由III-V族材料组成。
在一个实施例中,所述半导体器件是NMOS器件。
在一个实施例中,一种半导体器件包括半导体鳍状物,布置在半导体衬底上。半导体鳍状物具有中心凹陷段,沿半导体鳍状物的长度与突出外侧段对间隔开。覆层区布置在半导体鳍状物的中心凹陷段上。栅极叠置体布置在覆层区上。源极区/漏极区布置在半导体鳍状物的所述突出外侧段对中。
在一个实施例中,半导体器件进一步包括第二覆层区,布置在所述突出外侧段对中的一个上。第三覆层区布置在所述突出外侧段对中的另一个上。第二覆层区和第三覆层区与布置在半导体鳍状物的中心凹陷段上的覆层区分离但相邻。
在一个实施例中,半导体鳍状物和覆层区共同提供顺从性的衬底。
在一个实施例中,所述中心凹陷段由隔离层与所述突出外侧段对隔开。
在一个实施例中,半导体鳍状物实质上由硅组成,覆层区实质上由锗组成。
在一个实施例中,半导体器件是PMOS器件。
在一个实施例中,所述半导体鳍状物实质上由硅组成,所述覆层区由III-V族材料组成。
在一个实施例中,所述半导体器件是NMOS器件。
在一个实施例中,一种制造半导体器件的方法,包括在衬底上形成半导体鳍状物。所述方法还包括蚀刻半导体鳍状物以提供中心突出段,沿半导体鳍状物的长度与突出外侧段对间隔开。所述方法还包括在中心突出段与突出外侧段对中的每一个之间形成隔离层,所述隔离层具有在中心突出段的顶部表面下的顶部表面。所述方法还包括在形成所述隔离层后,在所述半导体鳍状物的暴露出的表面上形成覆层。所述方法还包括在所述覆层上形成栅极叠置体。所述方法还包括在所述半导体鳍状物的所述突出外侧段对中形成源极区/漏极区。
在一个实施例中,权利要求的方法进一步包括在形成隔离区后,且在形成所述覆层前,使得所述中心突出段大约凹陷到所述隔离区的顶部表面。
在一个实施例中,形成覆层区包括在所述中心突出段上形成第一覆层区,在所述突出外侧段对中的一个上形成第二覆层区,在所述突出外侧段对中的另一个上形成第三覆层区。第二覆层区和第三覆层区与第一覆层区分离但相邻。
在一个实施例中,形成覆层区包括在中心凹陷段上形成第一覆层区,在所述突出外侧段对中的一个上形成第二覆层区,在所述突出外侧段对中的另一个上形成第三覆层区。第二覆层区和第三覆层区与第一覆层区分离但相邻。
在一个实施例中,在所述半导体鳍状物的暴露出的表面上形成覆层提供了顺从性的衬底。
Claims (21)
1.一种半导体器件,包括:
半导体鳍状物,所述半导体鳍状物布置在半导体衬底上方,所述半导体鳍状物具有中心突出段,所述中心突出段沿所述半导体鳍状物的长度与突出外侧段对间隔开;
覆层区,所述覆层区布置在所述半导体鳍状物的所述中心突出段上;
栅极叠置体,所述栅极叠置体布置在所述覆层区上;以及
源极区/漏极区,所述源极区/漏极区布置在所述半导体鳍状物的所述突出外侧段对中。
2.根据权利要求1所述的半导体器件,进一步包括:
第二覆层区,所述第二覆层区布置在所述突出外侧段对中的一个突出外侧段上;以及
第三覆层区,所述第三覆层区布置在所述突出外侧段对中的另一个突出外侧段上,其中,所述第二覆层区和所述第三覆层区与布置在所述半导体鳍状物的所述中心突出段上的所述覆层区分离但相邻。
3.根据权利要求1所述的半导体器件,其中,所述半导体鳍状物和所述覆层区共同提供顺从性的衬底。
4.根据权利要求1所述的半导体器件,其中,所述中心突出段通过隔离层与所述突出外侧段对间隔开。
5.根据权利要求1所述的半导体器件,其中,所述半导体鳍状物实质上由硅组成,并且所述覆层区实质上由锗组成。
6.根据权利要求4所述的半导体器件,其中,所述半导体器件是PMOS器件。
7.根据权利要求1所述的半导体器件,其中,所述半导体鳍状物实质上由硅组成,并且所述覆层区实质上由III-V族材料组成。
8.根据权利要求7所述的半导体器件,其中,所述半导体器件是NMOS器件。
9.一种半导体器件,包括:
半导体鳍状物,所述半导体鳍状物布置在半导体衬底上方,所述半导体鳍状物具有中心凹陷段,所述中心凹陷段沿所述半导体鳍状物的长度与突出外侧段对间隔开;
覆层区,所述覆层区布置在所述半导体鳍状物的所述中心凹陷段上;
栅极叠置体,所述栅极叠置体布置在所述覆层区上;以及
源极区/漏极区,所述源极区/漏极区布置在所述半导体鳍状物的所述突出外侧段对中。
10.根据权利要求9所述的半导体器件,进一步包括:
第二覆层区,所述第二覆层区布置在所述突出外侧段对中的一个突出外侧段上;以及
第三覆层区,所述第三覆层区布置在所述突出外侧段对中的另一个突出外侧段上,其中,所述第二覆层区和所述第三覆层区与布置在所述半导体鳍状物的所述中心凹陷段上的所述覆层区分离但相邻。
11.根据权利要求9所述的半导体器件,其中,所述半导体鳍状物和所述覆层区共同提供顺从性的衬底。
12.根据权利要求9所述的半导体器件,其中,所述中心凹陷段通过隔离层与所述突出外侧段对间隔开。
13.根据权利要求9所述的半导体器件,其中,所述半导体鳍状物实质上由硅组成,并且所述覆层区实质上由锗组成。
14.根据权利要求13所述的半导体器件,其中,所述半导体器件是PMOS器件。
15.根据权利要求14所述的半导体器件,其中,所述半导体鳍状物实质上由硅组成,并且所述覆层区由III-V族材料组成。
16.根据权利要求15所述的半导体器件,其中,所述半导体器件是NMOS器件。
17.一种制造半导体器件的方法,所述方法包括:
在衬底上方形成半导体鳍状物;
蚀刻所述半导体鳍状物以提供中心突出段,所述中心突出段沿所述半导体鳍状物的长度与突出外侧段对间隔开;
在所述中心突出段与所述突出外侧段对中的每个突出外侧段之间形成隔离层,所述隔离层具有位于所述中心突出段的顶部表面下方的顶部表面;以及
在形成所述隔离层之后,在所述半导体鳍状物的暴露出的表面上形成覆层;
在所述覆层上形成栅极叠置体;以及
在所述半导体鳍状物的所述突出外侧段对中形成源极区/漏极区。
18.根据权利要求17所述的方法,进一步包括:
在形成所述隔离区之后并且在形成所述覆层之前,使所述中心突出段大约凹陷至所述隔离区的所述顶部表面。
19.根据权利要求17所述的方法,其中,形成所述覆层区包括:在所述中心突出段上形成第一覆层区;在所述突出外侧段对中的一个突出外侧段上形成第二覆层区;以及在所述突出外侧段对中的另一个突出外侧段上形成第三覆层区,并且其中,所述第二覆层区和所述第三覆层区与所述第一覆层区分离但相邻。
20.根据权利要求18所述的方法,其中,形成所述覆层区包括:在所述中心凹陷段上形成第一覆层区;在所述突出外侧段对中的一个突出外侧段上形成第二覆层区;以及在所述突出外侧段对中的另一个突出外侧段上形成第三覆层区,并且其中,所述第二覆层区和所述第三覆层区与所述第一覆层区分离但相邻。
21.根据权利要求17所述的方法,其中,在所述半导体鳍状物的暴露出的表面上形成所述覆层提供了顺从性的衬底。
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