SG11201601319QA - Ge and iii-v channel semiconductor devices having maximized compliance and free surface relaxation - Google Patents

Ge and iii-v channel semiconductor devices having maximized compliance and free surface relaxation

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Publication number
SG11201601319QA
SG11201601319QA SG11201601319QA SG11201601319QA SG11201601319QA SG 11201601319Q A SG11201601319Q A SG 11201601319QA SG 11201601319Q A SG11201601319Q A SG 11201601319QA SG 11201601319Q A SG11201601319Q A SG 11201601319QA SG 11201601319Q A SG11201601319Q A SG 11201601319QA
Authority
SG
Singapore
Prior art keywords
iii
semiconductor devices
free surface
channel semiconductor
surface relaxation
Prior art date
Application number
SG11201601319QA
Inventor
Ravi Pillarisetty
Sansaptak Dasgupta
Niti Goel
Van H Le
Marko Radosavljevic
Gilbert Dewey
Niloy Mukherjee
Matthew V Metz
Willy Rachmady
Jack T Kavalieros
Benjamin Chu-Kung
Harold W Kennel
Stephen M Cea
Robert S Chau
Original Assignee
Intel Corp
Ravi Pillarisetty
Sansaptak Dasgupta
Niti Goel
Van H Le
Marko Radosavljevic
Gilbert Dewey
Niloy Mukherjee
Matthew V Metz
Willy Rachmady
Jack T Kavalieros
Benjamin Chu-Kung
Harold W Kennel
Stephen M Cea
Robert S Chau
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp, Ravi Pillarisetty, Sansaptak Dasgupta, Niti Goel, Van H Le, Marko Radosavljevic, Gilbert Dewey, Niloy Mukherjee, Matthew V Metz, Willy Rachmady, Jack T Kavalieros, Benjamin Chu-Kung, Harold W Kennel, Stephen M Cea, Robert S Chau filed Critical Intel Corp
Publication of SG11201601319QA publication Critical patent/SG11201601319QA/en

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    • H01L29/165Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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SG11201601319QA 2013-09-27 2013-09-27 Ge and iii-v channel semiconductor devices having maximized compliance and free surface relaxation SG11201601319QA (en)

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PCT/US2013/062447 WO2015047342A1 (en) 2013-09-27 2013-09-27 Ge and iii-v channel semiconductor devices having maximized compliance and free surface relaxation

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US (2) US9570614B2 (en)
EP (1) EP3050091B1 (en)
KR (1) KR102135306B1 (en)
CN (2) CN110071168B (en)
SG (1) SG11201601319QA (en)
TW (2) TWI600152B (en)
WO (1) WO2015047342A1 (en)

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US20170125524A1 (en) 2017-05-04
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US9905651B2 (en) 2018-02-27
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