CN105789158A - 一种免塑封体开孔的pop封装件及其制作工艺 - Google Patents

一种免塑封体开孔的pop封装件及其制作工艺 Download PDF

Info

Publication number
CN105789158A
CN105789158A CN201610190611.6A CN201610190611A CN105789158A CN 105789158 A CN105789158 A CN 105789158A CN 201610190611 A CN201610190611 A CN 201610190611A CN 105789158 A CN105789158 A CN 105789158A
Authority
CN
China
Prior art keywords
stannum
plastic
post
substrate
sealed body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610190611.6A
Other languages
English (en)
Inventor
于大全
王虎
刘卫东
梁天胜
王奎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huatian Technology Xian Co Ltd
Original Assignee
Huatian Technology Xian Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huatian Technology Xian Co Ltd filed Critical Huatian Technology Xian Co Ltd
Priority to CN201610190611.6A priority Critical patent/CN105789158A/zh
Publication of CN105789158A publication Critical patent/CN105789158A/zh
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)

Abstract

本发明公开了一种免塑封体开孔的POP封装件及其制作工艺,所述封装件主要由基板、焊盘、锡柱围墙、锡柱、凸点、倒装芯片、锡球、塑封体、上层器件成品和上层器件锡球组成;所述倒装芯片通过凸点与基板上的焊盘连接;所述锡柱围墙在基板上的焊盘周围,锡柱注满锡柱围墙;塑封体包围锡柱围墙、倒装芯片及其底部和基板上部;基板下部植锡球;锡柱上部植上层器件锡球,并与上层器件成品连接。所述制作工艺为:晶圆减薄—划片—倒装上芯—底部填充—锡柱围墙开口处植球—回流—塑封—研磨—植球—上层器件贴装。本发明避免在塑封体上进行开孔,节省了设备开支,极大的缩小封装成本。

Description

一种免塑封体开孔的POP封装件及其制作工艺
技术领域
本发明涉及集成电路领域,具体是一种免塑封体开孔的POP封装件及其制作工艺。
背景技术
传统POP封装过程中的TMV(塑封体穿孔技术)的使用,是通过激光实现,成本很高。
发明内容
对于上述现有技术存在的问题,本发明提供了一种免塑封体开孔的POP封装件及其制作工艺,其避免在塑封体上进行开孔,节省了设备开支,极大的缩小封装成本。
一种免塑封体开孔的POP封装件,所述封装件主要由基板、焊盘、锡柱围墙、锡柱、凸点、倒装芯片、锡球、塑封体、上层器件成品和上层器件锡球组成;所述倒装芯片通过凸点与基板上的焊盘连接;所述锡柱围墙在基板上的焊盘周围,锡柱注满锡柱围墙;塑封体包围锡柱围墙、倒装芯片及其底部和基板上部;基板下部植锡球;锡柱上部植上层器件锡球,并与上层器件成品连接。
所述锡柱围墙采用光刻胶或者绿油等非导电材质制成。
所述制作工艺主要工艺流程为:晶圆减薄——划片——倒装上芯——底部填充——锡柱围墙开口处植球——回流——塑封——研磨——植球——上层器件贴装。
一种免塑封体开孔的POP封装件的制作工艺,具体按照以下步骤进行:
第一步:晶圆减薄,减薄范围为50um—250um;
第二步:划片,形成单颗倒装芯片;
第三步:准备基板,基板上有焊盘;
第四步:在基板焊盘上制作锡柱围墙;
第五步:植球,将锡柱成型前锡球置于基板的锡柱围墙上并进行回流,形成锡柱;
第六步:倒装焊接并底部填充胶水,将芯片通过凸点与基板上的焊盘连接;
第七步:塑封;
第八步:研磨,塑封体减薄达到要求厚度,将锡柱漏出;
第九步:植球,基板下部植锡球;
第十步:锡柱上部植上层器件锡球,并与上层器件成品连接。
所述第五步可代替为:用成型的锡柱直插入锡柱围墙。
所述第六步不用底部填充胶水。
所述第八步可代替为:采用切割代替研磨减薄,切割方式包括刀具切割和激光切割。
附图说明
图1为基板图;
图2为基板焊盘上进行锡柱围墙制作图;
图3为锡柱围墙上植球图;
图4为锡球回流形成锡柱图;
图5为倒装焊接图;
图6为塑封图;
图7为研磨图;
图8为植球图;
图9为上层成品器件连接图。
图中,1为基板,2为焊盘,3为锡柱围墙,4为锡柱,5为凸点,6为倒装芯片,7为锡球,8为塑封体,9为上层器件成品,10为上层器件锡球,11为锡柱成型前锡球。
具体实施方式
一种免塑封体开孔的POP封装件,所述封装件主要由基板1、焊盘2、锡柱围墙3、锡柱4、凸点5、倒装芯片6、锡球7、塑封体8、上层器件成品9和上层器件锡球10组成;所述倒装芯片6通过凸点5与基板1上的焊盘2连接;所述锡柱围墙3在基板1上的焊盘2周围,锡柱4注满锡柱围墙3;塑封体8包围锡柱围墙3、倒装芯片6及其底部和基板1上部;基板1下部植锡球7;锡柱4上部植上层器件锡球10,并与上层器件成品9连接。
所述锡柱围墙3采用光刻胶或者绿油等非导电材质制成。
所述制作工艺主要流程为:晶圆减薄——划片——倒装上芯——底部填充——锡柱围墙开口处植球——回流——塑封——研磨——植球——上层器件贴装。
一种免塑封体开孔的POP封装件的制作工艺,具体按照以下步骤进行:
第一步:晶圆减薄,减薄范围为50um—250um;
第二步:划片,形成单颗倒装芯片6;
第三步:准备基板1,基板1上有焊盘2,如图1所示;
第四步:在基板1焊盘2上制作锡柱围墙3,如图2所示;
第五步:植球,将锡柱成型前锡球11置于基板1的锡柱围墙3上并进行回流,形成锡柱4,如图3和图4所示;
第六步:倒装焊接并底部填充胶水,将芯片6通过凸点5与基板1上的焊盘2连接,如图5所示;
第七步:塑封,如图6所示;
第八步:研磨,塑封体8减薄达到要求厚度,将锡柱4漏出,如图7所示;
第九步:植球,基板1下部植锡球7,如图8所示;
第十步:锡柱4上部植上层器件锡球10,并与上层器件成品9连接,如图9所示。
所述第五步可代替为:用成型的锡柱直插入锡柱围墙3。
所述第六步不用底部填充胶水。
所述第八步可代替为:采用切割代替研磨减薄,切割方式包括刀具切割和激光切割。

Claims (6)

1.一种免塑封体开孔的POP封装件,其特征在于,所述封装件主要由基板(1)、焊盘(2)、锡柱围墙(3)、锡柱(4)、凸点(5)、倒装芯片(6)、锡球(7)、塑封体(8)、上层器件成品(9)和上层器件锡球(10)组成;所述倒装芯片(6)通过凸点(5)与基板(1)上的焊盘(2)连接;所述锡柱围墙(3)在基板(1)上的焊盘(2)周围,锡柱(4)注满锡柱围墙(3);塑封体(8)包围锡柱围墙(3)、倒装芯片(6)及其底部和基板(1)上部;基板(1)下部植锡球(7);锡柱(4)上部植上层器件锡球(10),并与上层器件成品(9)连接。
2.根据权利要求1所述的一种免塑封体开孔的POP封装件,其特征在于,所述锡柱围墙(3)采用光刻胶或者绿油等非导电材质制成。
3.一种免塑封体开孔的POP封装件的制作工艺,其特征在于,具体按照以下步骤进行:
第一步:晶圆减薄,减薄范围为50um—250um;
第二步:划片,形成单颗倒装芯片(6);
第三步:准备基板(1),基板(1)上有焊盘(2);
第四步:在基板(1)焊盘(2)上制作锡柱围墙(3);
第五步:植球,将锡柱成型前锡球(11)置于基板(1)的锡柱围墙(3)上并进行回流,形成锡柱(4);
第六步:倒装焊接并底部填充胶水,将芯片(6)通过凸点(5)与基板(1)上的焊盘(2)连接;
第七步:塑封;
第八步:研磨,塑封体(8)减薄达到要求厚度,将锡柱(4)漏出;
第九步:植球,基板(1)下部植锡球(7);
第十步:锡柱(4)上部植上层器件锡球(10),并与上层器件成品(9)连接。
4.根据权利要求3所述的一种免塑封体开孔的POP封装件的制作工艺,其特征在于,所述第五步代替为:用成型的锡柱(4)直插入锡柱围墙(3)。
5.根据权利要求3所述的一种免塑封体开孔的POP封装件的制作工艺,其特征在于,所述第六步不用底部填充胶水。
6.根据权利要求3所述的一种免塑封体开孔的POP封装件的制作工艺,其特征在于,所述第八步代替为:采用切割代替研磨减薄,切割方式包括刀具切割和激光切割。
CN201610190611.6A 2016-03-30 2016-03-30 一种免塑封体开孔的pop封装件及其制作工艺 Pending CN105789158A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610190611.6A CN105789158A (zh) 2016-03-30 2016-03-30 一种免塑封体开孔的pop封装件及其制作工艺

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610190611.6A CN105789158A (zh) 2016-03-30 2016-03-30 一种免塑封体开孔的pop封装件及其制作工艺

Publications (1)

Publication Number Publication Date
CN105789158A true CN105789158A (zh) 2016-07-20

Family

ID=56391024

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610190611.6A Pending CN105789158A (zh) 2016-03-30 2016-03-30 一种免塑封体开孔的pop封装件及其制作工艺

Country Status (1)

Country Link
CN (1) CN105789158A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110335824A (zh) * 2019-05-24 2019-10-15 江苏长电科技股份有限公司 一种双面封装的工艺方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100258932A1 (en) * 2009-04-08 2010-10-14 Elpida Memory, Inc. Supporting substrate before cutting, semiconductor device, and method of forming semiconductor device
CN102456968A (zh) * 2010-11-01 2012-05-16 富士康(昆山)电脑接插件有限公司 电连接器组合及制造方法
CN104078435A (zh) * 2014-07-15 2014-10-01 南通富士通微电子股份有限公司 Pop封装结构
US20150187741A1 (en) * 2014-01-02 2015-07-02 Siliconware Precision Industries Co., Ltd Package on package structure and fabrication method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100258932A1 (en) * 2009-04-08 2010-10-14 Elpida Memory, Inc. Supporting substrate before cutting, semiconductor device, and method of forming semiconductor device
CN102456968A (zh) * 2010-11-01 2012-05-16 富士康(昆山)电脑接插件有限公司 电连接器组合及制造方法
US20150187741A1 (en) * 2014-01-02 2015-07-02 Siliconware Precision Industries Co., Ltd Package on package structure and fabrication method thereof
CN104078435A (zh) * 2014-07-15 2014-10-01 南通富士通微电子股份有限公司 Pop封装结构

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110335824A (zh) * 2019-05-24 2019-10-15 江苏长电科技股份有限公司 一种双面封装的工艺方法

Similar Documents

Publication Publication Date Title
US9196534B2 (en) Method for preparing semiconductor devices applied in flip chip technology
WO2006035321A3 (en) Structurally-enhanced integrated circuit package and method of manufacture
US20020173074A1 (en) Method for underfilling bonding gap between flip-chip and circuit substrate
KR20070076846A (ko) 수지 봉합부를 갖는 웨이퍼 레벨 패키지 및 그의 제조 방법
TW200729445A (en) Flip chip on leadframe package and method of making the same
MY139752A (en) Encapsulated chip scale package having flip-chip on lead frame structure and method
TWI267172B (en) IC chip solder bump structure and method of manufacturing same
US20060001114A1 (en) Apparatus and method of wafer level package
CN105789158A (zh) 一种免塑封体开孔的pop封装件及其制作工艺
CN103996666A (zh) 功率半导体器件及其制造方法
KR20190000267U (ko) 예비성형된 범용 리드 프레임 장치
TW200605304A (en) Flip-chip semiconductor package with lead frame and method for fabricating the same
CN104064532A (zh) 一种带有散热结构的器件封装结构及制造方法
CN104979224B (zh) 一种器件封装互联方法
KR20150046117A (ko) 장치 및 그 제조 방법
CN104465548A (zh) 一种三维柔性封装结构及其注塑成型方法
CN201421840Y (zh) 低应力芯片凸点封装结构
CN106098569A (zh) 用于半导体封装件的模制层的形成方法
CN105006458A (zh) 一种带包封的芯片封装结构与实现工艺
CN101976662B (zh) 一种无基板的输出端扇出型倒装芯片封装结构
CN106340496A (zh) 芯片封装结构及其制造方法
CN108922853A (zh) 一种基于Fan-out工艺的三维结构制作方法
CN104347542A (zh) 五面包封的csp结构及制造工艺
CN104064557B (zh) 一种芯片背面裸露的重构晶圆结构及制造方法
CN205141022U (zh) 芯片封装结构

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20160720