CN105760785B - A kind of unclonable chip circuit of physics based on time-domain difference current measurement - Google Patents

A kind of unclonable chip circuit of physics based on time-domain difference current measurement Download PDF

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CN105760785B
CN105760785B CN201610045830.5A CN201610045830A CN105760785B CN 105760785 B CN105760785 B CN 105760785B CN 201610045830 A CN201610045830 A CN 201610045830A CN 105760785 B CN105760785 B CN 105760785B
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nmos
row
drain electrode
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CN105760785A (en
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赵晓锦
林仕傍
梁德健
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Shenzhen University
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    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/73—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by creating or determining hardware identification, e.g. serial numbers

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Abstract

The invention discloses a kind of unclonable chip circuits of the physics based on time-domain difference current measurement, including two current lens array circuits, two current mirroring circuits and current comparator circuit, the output current of two current lens array circuits inputs the first current mirroring circuit and the second current mirroring circuit respectively；The first electron current that the first electron current and the second current mirroring circuit that first current mirroring circuit generates generate is separately input to current comparator circuit, after two electron currents of current comparator circuit pair are compared, exports binary system ID；After repeatedly selecting the element circuit of current lens array circuit to be exported and being handled, an ID sequence, the identity identification information as chip are obtained.The present invention has the characteristics that small chip area, low-power consumption, high reliability and low cost, can be widely applied on the circuit industry that reliability requirement is high, power budget is low.

Description

A kind of unclonable chip circuit of physics based on time-domain difference current measurement
[technical field]
The present invention relates to information security field more particularly to a kind of physics based on time-domain difference current measurement are unclonable Chip circuit.
[background technology]
Physics unclonable function (Physical Unclonable Function：PUF it) refers to a physics reality Body inputs an excitation, and using the random difference of its inevitable inherent physique, output one is uncertain random Respond such a function.The most basic application of PUF is to realize certification with the unique mark of entity, later with people To its deep understanding, it is proposed that the PUF implementation methods of more and more new types, PUF, butterfly PUF such as based on moderator, Ring oscillator PUF etc..Based on these implementation methods, PUF circuits have gradually been applied to more security fields, such as public close The key generation of key encryption system, secrete key of smart card identifying system, radio-frequency recognition system (Radio Frequency Identification, RFID) and relevant knowledge property right protection etc..Meanwhile classifying in such a way that integrated circuit is realized, it The unclonable chip of pure digi-tal physics (digital PUF chips) and the unclonable chip of numerical model analysis physics (number can be divided into again Mould mixing PUF chips).
Document [6] proposes a kind of PUF circuits based on arbitration mechanism, and obtaining output by comparing the delay of two paths rings It answers.The circuit is made of two parts of delay circuit and arbitration determining device, and delay circuit has 64 inputs, is inputted by every " 0 " or " 1 " determines the trend of upper and lower two paths, shares 264 kinds of different combination of paths, and moderator is for judging up and down two The priority that road strength signal reaches, corresponding output " 1 " or " 0 ".Such as a rising signals are passed by upper and lower two paths respectively It broadcasts, if upper path first travels to arbitration, it is " 1 " to export response, otherwise output response is " 0 ".Connect in this way by input one The rise and fall signal of string can obtain a string of corresponding response binary sequences.Since moderator needs settling time, institute To cause the stability of the circuit not high, although the stability of circuit can be improved by introducing complicated correcting circuit, It is but so that the power consumption of circuit and the area of chip increase significantly.
Document [7] proposes a PUF circuit based on cross-coupled circuit that can be applied to FPGA.The PUF circuits utilize Cross-coupled circuit due to positive feedback circle presence and existing " 0 " or " 1 " two stable states and one it is unstable and easy In the characteristic of the intermediate state changed to one of two stable states.Two latch cross-couplings form a positive feedback loop, open When the beginning, by the pumping signal for controlling additional circuit is played pendulum, then made by changing the pumping signal Circuit turns to one of " 0 " or " 1 " two stable states from unstable state, to obtain the two of one " 0 " or " 1 " into Position processed.An array is formed using multiple such cross-coupled circuits, finally obtains the output of a string of binary sequences.Due to When cross-coupled circuit changes from unstable state to stable state, it is easy to not by some circuits or device Determine that factor influences, so the process of this transformation is uncertain, so finally obtained a string of binary sequences are also It is unpredictable, unique.But circuit the problem of equally existing stability, it needs to improve stabilization by aided algorithm circuit Property.
It offers [9] and proposes that a PUF based on thyristor realizes circuit.The circuit is by thyristor sensor circuit, time difference Divide amplifier circuit, time difference comparator circuit, voting mechanism circuit, broadcast algorithm circuit composition.Using multiple in circuit Same thyristor sensor, since production process makes a variation, each sensor generates two works for having subtle different length of delay Make electric current, operating current is postponed to be amplified by time difference amplifier circuit；Time difference has compared circuit reality An arbiter circuit, the circuit by comparing the priority that two current signals reach accordingly export response for " 1 " or "0"；Voting mechanism circuit carries out sampling statistics to the output response of time differential comparator, and output is determined according to sampled result ID is " 1 " or " 0 ", and when the number of sampling is sufficiently large, (sampling number is 1000 in document) can obtain a stable ID； Broadcast algorithm circuit converts obtained ID according to a determining algorithm, it is made to meet the requirement of unified statistical distribution, Improve the uniqueness of PUF circuits.The problem of circuit, is the bit error rate for having larger, and even if increases power consumption and chip face Product, it is also difficult to obtain the low bit error rate of ideal.
Document [1] K.Lofstrom, W.R.Daasch and D.Taylor, " IC identification circuit using device mismatch,”IEEE International Solid-State Circuits Conf.(ISSCC), pp.372-373,2000.
Document [2] J.Zhang, Y.Lin, Y.Lyu and G.Qu, " A PUF-FSM Binding Scheme for FPGA IP Protection and Pay-Per-Device Licensing,”IEEE Transactions on Information Forensics and Security,vol.10,no.6,pp.1137-1150,2015.
Document [3] W.Liu, Z.Zhang, M.Li and Z.Liu, " A Trustworthy key Generation Prototype based on DDR3 PUF for Wireless Sensor Networks,”IEEE International Symposium on Computer,Consumer and Control,pp.706-709,2014.
Document [4] Y.Cao, S.S.Z., L.Zhang, C.H.Chang and S.Chen, " CMOS Image Sensor Based Physical Unclonable Function for Smart Phone Security Applications,” IEEE International Symposium on Integrated Circuits,pp.392-395,2014.
Document [5] G.Qu and L.Yuan, " Design THINGS for the Internet of Things-An EDA Perspective,”IEEE International Conference on Computer-Aided Design, pp.411-416,2014.
Document [6] Lang Lin, S.Srivathsa, D.K.Krishnappa, P.Shabadi and W.Burleson, “Design and validation of Arbiter-Based PUFs for Sub-45-nm Low-Power Security Applications,”IEEE Transactions on Information Forensics and Security,vol.7, no.4,pp.1394-1403,2012.
Document [7] S.S.Kumar, J.Guajardo, R.Maesyz, G.-J.Schrijen and P.Tuyls, " The butterfl y PUF protecting IP on every FPGA,”IEEE Sym.on Hardware-Oriented Security and Trust(HOST),pp.67-70,2008.
Document [8] Y.Su, J.Holleman and B.Otis, " A 1.6pJ/bit 96%Stable Chip-ID Generating Circuit using Process Variation,”IEEE International Solid-State Circuits Conf.(ISSCC),pp.406-611,2007.
Document [9] C.Bai, X.Zou and K.Dai, " A Novel Thyristor-Based Silicon Physical Unclonable Function,”IEEE Transactions on Very Large Scale Integartion(VLSI)Systems,in press,2015.
Document [10] S.Stanzione, D.Puntin and G.Iannaccone, " CMOS Silicon Physical Unclonable Functions Based on Intrinsic Process Variability,”IEEE J.Solid- State Circuits,vol.46,no.6,pp.1456-1463,2011.
Document [11] K.Yang, Q.Dong, D.Blaauw and D.Sylvester, " A Physically Un- clonable Function with BER<10-8 for Robust Chip Authentication Using Oscillator Collapse in 40nm CMOS,”IEEE International Solid-State Circuits Conf.(ISSCC),pp.254-256,2015.
Document [12] Jason H.Anderson, " A PUF Design for Secure FPGA-Based Embedded Systems,”IEEE Asia and South Paci fi c Design Automation Conference,pp.1-6, 2010.
These PUF proposed in document above realize circuit, generally existing is larger such as chip area, power consumption is higher Problem, if the PUF circuit chip areas in document [9] are 21750um2, power consumption 380uw, these disadvantages limit to a certain extent The application of PUF chips in practice.
[invention content]
It is small, low in energy consumption based on the survey of time-domain difference electric current that the technical problem to be solved in the present invention is to provide a kind of chip areas The unclonable chip circuit of physics of amount.
In order to solve the above-mentioned technical problem, the technical solution adopted by the present invention is that one kind being based on time-domain difference current measurement The unclonable chip circuit of physics, including two current lens array circuits, two current mirroring circuits and current comparator circuit, The output current of two current lens array circuits inputs the first current mirroring circuit and the second current mirroring circuit respectively；First current mirror The first electron current that the first electron current and the second current mirroring circuit that circuit generates generate is separately input to current comparator circuit, After two electron currents of current comparator circuit pair are compared, binary system ID is exported；By repeatedly selecting current mirror battle array After the element circuit of column circuits is exported and handled, an ID sequence, the identity identification information as chip are obtained.
The above-described unclonable chip circuit of physics, including time-domain difference measuring circuit, the production of the first current mirroring circuit The second electron current that the second raw electron current and the second current mirroring circuit generate is separately input to time-domain difference measuring circuit, time domain The second electron current that the second electron current and the second current mirroring circuit that the first current mirroring circuit of difference measurement circuit pair generates generate Absolute value of the difference measures, and the size of the absolute value is calculated by controllable counter, by the absolute value and setting Threshold value comparison exports a binary identification position；By repeatedly selecting the element circuit of current lens array circuit to be exported simultaneously After being handled, a mark sequence corresponding with the ID sequences is obtained, for characterizing the reliable of the identity identification information Property.
The above-described unclonable chip circuit of physics, current lens array circuit include M root row address lines, N roots row ground Location line, M row N row NMOS tube, row identical with NMOS tube quantity switch and M row switch, the whole of current lens array circuit The grid of NMOS tube is connected, and connects additional control voltage；The source electrode of whole NMOS tubes is connected and is grounded；The drain electrode of each NMOS tube is logical Cross the input terminal that corresponding row switch connects every trade switch；The control of same row row switch terminates the column address conductor of the row, and row is opened The control of pass terminates the row address line of the row, and the output end of all row switches is connected, the output end as current lens array circuit.
The above-described unclonable chip circuit of physics, row switch and row switch are all NMOS, arrange the source electrode of switch with The drain electrode of corresponding NMOS tube is connected, and the grid for arranging switch connects the column address conductor of the row, and the drain electrode with all row switches of a line connects this The grid of the source electrode of every trade switch, row switch connects the row address line of the row, and the drain electrode of all row switches is connected, as current mirror battle array The output end of column circuits.
The above-described unclonable chip circuit of physics, current mirroring circuit include three PMOS tube, three PMOS tube Source electrode external power supply；The grid of three PMOS tube links together, and connects the drain electrode of the first PMOS tube；First current mirroring circuit The drain electrode of first PMOS tube connects the output end of the first current lens array circuit, and the drain electrode of the second PMOS tube connects current comparator circuit First input end, the drain electrode of third PMOS tube connects the first input end of time-domain difference measuring circuit；Second current mirroring circuit The drain electrode of first PMOS tube connects the output end of the second current lens array circuit, and the drain electrode of the second PMOS tube connects current comparator circuit The second input terminal, the drain electrode of third PMOS tube connects the second input terminal of time-domain difference measuring circuit.
The above-described unclonable chip circuit of physics, current comparator circuit include two and reset NMOS and two friendship The NMOS of coupling is pitched, the source electrode ground connection of NMOS and cross-couplings NMOS is resetted, first, which resets the drain electrode of NMOS and second, intersects coupling The grid for closing NMOS connects the drain electrode of the first cross-couplings NMOS, and second resets the drain electrode of NMOS and the grid of the first cross-couplings NMOS Pole connects the drain electrode of the second cross-couplings NMOS；The drain electrode of two cross-couplings NMOS connects the first current mirroring circuit and the second electricity respectively The electron current of current mirror circuit output, the drain electrode of the first cross-couplings NMOS are the output end of current comparator circuit.
Above-described physics unclonable chip circuit when current comparator circuit works, first resets two The grid input high level of NMOS makes reset NMOS be connected, and so that two cross-couplings NMOS is passed through drain electrode and carries out discharge reduction；So Afterwards to the grid input low level of two reset NMOS, reset NMOS is made to turn off；Hereafter, the drain electrode of two cross-couplings NMOS point The electron current of the first current mirroring circuit and the output of the second current mirroring circuit is not inputted, if the son electricity of the first current mirroring circuit output Stream is more than the electron current of the second current mirroring circuit output, and the drain electrode of the first cross-couplings NMOS exports high level, obtains a value For the positions ID of " 1 "；If the first current mirroring circuit output electron current be less than the second current mirroring circuit output electron current, first The drain electrode of cross-couplings NMOS exports low level, obtains the positions ID that a value is " 0 ".
The above-described unclonable chip circuit of physics, time-domain difference measuring circuit include controllable counter and two ratios Compared with device circuit, comparator circuit includes capacitance, resets NMOS tube and voltage comparator, and the drain electrode for resetting NMOS tube connects the of capacitance One end, the source electrode for resetting NMOS tube connect the second end ground connection of capacitance；The inverting input of first termination voltage comparator of capacitance, The homophase input of voltage comparator terminates reference voltage；The first electricity of anti-phase input termination of first comparator circuit voltage comparator The second output terminal of current mirror circuit, the first input end of output termination controllable counter；Second comparator circuit voltage comparator Anti-phase input terminate the second current mirroring circuit second output terminal, output termination controllable counter the second input terminal.
Above-described physics unclonable chip circuit when time-domain difference measuring circuit is started to work, resets NMOS tube Conducting, to capacitance discharge reduction；After the completion of reset, NMOS tube shutdown is resetted；Second electron current of the first current mirroring circuit and Second electron current of two current mirroring circuits is not input to the reverse side of two voltage comparators, while being two capacitor chargings；When When capacitance voltage rises to the reference voltage given more than voltage comparator in-phase end, the output voltage saltus step of voltage comparator is 0；If respectively t at the time of two voltage comparator output end voltage saltus stepsaAnd tb, controllable counter is in first jumping moment taIt starts counting up, in second jumping moment tbStop counting；The counting between two jumping moments is read on controllable counter Difference exports the flag that a value is " 1 " when this difference is more than preset threshold value from controllable counter；It is on the contrary then One value of output is the flag of " 0 ".
The present invention, which has the unclonable chip circuit of physics based on time-domain difference current measurement, that chip area is small, low work( Consumption, the feature of high reliability and low cost, can be widely applied on the circuit industry that reliability requirement is high, power budget is low.
[description of the drawings]
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
Fig. 1 is the principle frame of the unclonable chip circuit of physics of the embodiment of the present invention based on time-domain difference current measurement Figure.
Fig. 2 is the basic principle figure of current lens array of the embodiment of the present invention.
Fig. 3 is the circuit structure diagram of current lens array of the embodiment of the present invention.
Fig. 4 is the circuit diagram of current mirror of embodiment of the present invention A.
Fig. 5 is the circuit diagram of current mirror of embodiment of the present invention B.
Fig. 6 is the circuit diagram of current comparator circuit of the embodiment of the present invention.
Fig. 7 is the circuit diagram of time-domain difference current measurement circuit of the embodiment of the present invention.
Fig. 8 is the fundamental diagram of time-domain difference current measurement circuit of the embodiment of the present invention.
Fig. 9 is that the unclonable chip circuit of physics of the embodiment of the present invention based on time-domain difference current measurement emulates The statistical chart of the bit error rate under different temperatures and operating voltage.
Figure 10 is the unclonable chip circuit intersymbol Hamming of physics of the embodiment of the present invention based on time-domain difference current measurement The histogram of distance.
[specific implementation mode]
System structure such as Fig. 1 of the unclonable chip circuit of physics of the embodiment of the present invention based on time-domain difference current measurement Shown, the PUF circuits are by two identical current lens array circuits, two identical current mirroring circuits, a current comparator Circuit and a time-domain difference measuring circuit composition.The operation principle of circuit totality is as follows：Two current lens array circuit difference Output current IAAnd IB, the two electric currents respectively pass through current mirroring circuit A and current mirroring circuit B, respectively generate two electron current IA1、 IA2And IB1、IB2。IA1And IB1It is input to current comparator circuit, after current comparator is compared the two electric currents, output One binary system I D (" 1 " or " 0 ")；IA2And IB2It is input in time-domain difference measuring circuit, the measuring circuit is to IA2And IB2 Absolute value of the difference Δ I=| IA2-IB2| it measures, the size of Δ I is calculated by a controllable counter, then passes through this again A counter exports a binary identification position (" 1 " or " 0 ").By repeatedly from two electric currents of current lens array circuit output into As row relatively and after measurement, an ID sequence and a corresponding mark sequence can be obtained.Obtained ID sequences can be used as The identity identification information of one chip, mark sequence then are used to characterize the reliability of the identity identification information.
The basic principle of current lens array circuit is as illustrated in fig. 2, it is assumed that three metal-oxide-semiconductor M1、M2、M3Technological parameter (such as： Electron mobility μn, unit area gate oxide capacitance Cox, channel width-over-length ratio W/L, threshold voltage VTHDeng) identical (do not examine Consider channel modulation effect), theoretically the two output currents I1And I2It is essentially equal, but due to the deviation in manufacturing process, this Two electric currents are actually not fully equal, such a pair of of electric current can be called mismatch current.In fig. 2, IREFIt is given Input current, VBIt is electric current IREFIn transistor M1The voltage of upper generation.
Current lens array circuit shown in Fig. 3 is to be extended to obtain on the basis of circuit shown in Fig. 2.Current mirror battle array Row are made of the identical NMOS tube of M rows N row, and the grid of all NMOS tubes of current lens array circuit links together；All The source electrode of NMOS tube is connected and is grounded, and a row switch (and a NMOS tube) is connected in the drain electrode of each NMOS tube.Row are opened Source electrode is closed with the drain electrode of NMOS tube in array to be connected, in the same current lens array circuit, the row switch control terminal of same row (grid) is connected.External N root address wires are connected on the grid of N number of row switch, control the row switch of same row simultaneously Turn-on and turn-off, this N root address wire are known as the bit line (BL of the array1-BLN)；Drain electrode with all row switches of a line is connected, together The NMOS tube of a line shares a row switch (and a NMOS tube), and the source electrode connection of row switch is the same as all row switches of a line Drain electrode.External M root address wires are connected on the grid of M row switch, control the turn-on and turn-off of row switch, this M root Address wire is known as the wordline (WL of the array1-WLM)；The drain electrode of all row switches is connected, the output end as entire array.
The output current I of array circuit shown in Fig. 3OUTIt is respectively the output current I of array 1 and array 2 in Fig. 1AAnd IB。 IAAnd IBIt is separately input to the input terminal of current mirroring circuit A and current mirroring circuit B.VBIt is additional control voltage, controls in array NMOS tube is in normal working condition (conducting).The groundwork process of current lens array is：Additional control voltage VBSo that All NMOS tubes are in the conduction state in array, and external address wire (bit line and wordline of array) is switched by controlling ranks, A NMOS tube is respectively selected in array 1 and array 2, exports two mismatch currents.The two mismatch currents are input to current mirror In circuit A and current mirroring circuit B.
The circuit structure of current mirroring circuit A and current mirroring circuit B distinguish as shown in Figure 4 and Figure 5, PMOS tube M4-M6Composition electricity The circuit of current mirror circuit A, M7-M9Form the circuit of current mirroring circuit B, M4-M9This six PMOS tube are identical.Current mirror electricity The basic function of road A and current mirroring circuit B are to generate two output currents essentially equal with input current.Such as Fig. 4 and Fig. 5 institutes Show, the input of two current mirroring circuits is respectively IAAnd IB, it is respectively I to obtain outputA1、IA2And IB1、IB2.Due to process deviation, IAWith IA1、IA2, IBWith IB1、IB2It is not completely equivalent, but by increasing the size of PMOS tube in the two current mirroring circuits, it can The error between input and output electric current is narrowed down in a negligible range；Similarly, by reducing current lens array The size of NMOS tube in circuit 1 and current lens array circuit 2 can increase the difference between the mismatch current of two arrays generation Value improves the reliability of PUF circuits.
The circuit structure of current comparator circuit is as shown in Figure 6.The circuit resets NMOS tube M by two10And M13With two Cross-linked NMOS tube M11And M12Composition, the two input ports difference input current mirror circuit A and current mirroring circuit of circuit The output current I of BA1And IB1, in M11Drain electrode export ID.When circuit works, input reset signal first (is to NOMS pipes High level) circuit is resetted.Reset NMOS tube M10And M13Conducting, to two cross-couplings NMOS tube M11And M12Drain electrode It discharges, its voltage is made to be reduced to zero.After the completion of reset, make M10And M13It turns off (reset signal becomes low level).Respectively from friendship Fork coupling NMOS tube M11And M12Drain electrode input current IA1And IB1, two cross-linked NMOS tube M at this time11And M12In not The state of conducting, IA1And IB1Respectively to M11And M12Drain charge, due to two electric current IA1And IB1Size be not completely equivalent, So M11And M12The rate that drain voltage rises is different, if IA1>IB1, then M11Drain voltage climbing speed be more than M12Leakage Pole tension climbing speed, so M12First be connected.M12Conducting the result is that its drain voltage be pulled low to ground or electricity closely Pressure, so M11The state of shutdown, last M will be always maintained at11The drain voltage of pipe can rise to a stable value, at this time In M11Drain electrode end can export high level, you can obtain a value be " 1 " the positions ID.Similarly, work as IA1<IB1When, circuit will obtain One value is the positions ID of " 0 ".
In order to ensure that the reliability of integrated circuit work, the present invention propose time-domain difference current measurement shown in Fig. 7 (Time-Domain Current Difference Measurement：TDCDM circuit).The structure is by two identical electricity Hold C1、C2, two reset NMOS tube M14、M15, two voltage comparator D1、D2It is formed with 9 controllable counter.D1And D2 Reverse side be separately connected capacitance C1And C2Upper end, reset transistor M14And M15Respectively with C1And C2In parallel and lower end is grounded.Electricity Press comparator D1、D2In-phase end meet given reference voltage VREF, reverse side meets capacitance C respectively1And C2Upper end, output end connect The control terminal of controllable counter is connect, control counter starts counting up and stops counting respectively.When beginning, due to voltage comparator D1、D2Reverse phase terminal voltage is less than in-phase end voltage, D1、D2Output voltage be Vdd(supply voltage)；It is multiple when circuit is started to work Bit transistor M14、M15Conducting, to capacitance C1And C2Execute reset (electric discharge) operation.After the completion of reset, reset transistor M14、M15 Shutdown.Then electric current IA2And IB2It is separately input to D1、D2Reverse side, while be two capacitor chargings.As capacitance C1And C2Both ends Voltage rise to more than D1、D2The reference voltage V of in-phase endREFWhen, D1、D2Output voltage from VddSaltus step is 0.Due to IA2With IB2It is not completely equivalent, so capacitance C1And C2The climbing speed of both end voltage is different, so two comparator D1、D2Output end Voltage occurs different at the time of saltus step.Assuming that respectively t at the time of two voltage comparator output end voltage saltus stepsaAnd tb, controllably Counter is in first jumping moment taIt starts counting up, in second jumping moment tbStop counting.It can be read on this hour counter Go out the count difference between two moment, when this difference is more than a preset threshold value, a value is exported from counter For the flag of " 1 ", on the contrary then one flag being worth for " 0 " of output.
Fig. 8 is the operation principle of time-domain difference current measurement (TDCDM) circuit, and curve X, curve Y are respectively two in figure Capacitance C1And C2The change curve of both end voltage；taAnd tbRespectively comparator D1、D2Output end voltage occur saltus step at the time of, At the time of i.e. counter starts counting up and stops counting；The numerical value that CLK is counted by fixed cycle counter, electric current IA2And IB2It Between difference it is directly proportional to the numerical value that counter is counted, the numerical value that counter is counted is bigger, illustrates electric current IA2And IB2Between difference Value is bigger, and generated PUF of reliability is also higher.
Above example of the present invention has the advantages that：
PUF implementation methods proposed by the invention are greatly reduced without complicated error correction circuit needed for circuit Chip area and power consumption.PUF circuits proposed by the present invention are using the transistor of identical parameters in process of production because technique is inclined The parameter error that difference band comes generates mismatch current, so need not be designed using large-sized element in circuit inclined to buffer technique The circuit problem that difference band comes, can use smaller size of transistor in current lens array instead, so that current lens array is produced The mismatch current of raw bigger improves the reliability of circuit to reduce the bit error rate of circuit.Meanwhile it can be to all moulds Quasi- circuit optimizes and it is made to be operated in subthreshold region, this also very big overall power for reducing circuit.
Further it is proposed that PUF chip circuits that 0.18 μm of standard CMOS process of UMC can be used to carry out circuit is imitative The chip area of true and layout design, entire circuit is 13310 μm2, 40% left side is reduced compared to the PUF circuits in document [9] It is right.Fig. 9 gives the simulation result of the PUF circuit bit error rates proposed by the invention, it can be seen that the PUF circuits are in ordinary temp With can reach the superior function that the bit error rate is zero under the conditions of supply voltage, error code under the conditions of worst temperature and supply voltage Rate also only has 1.56%.
Moreover, the unclonable practical circuit of the novel physical proposed in the present invention is tested, by input with Machine selection signal (addresses) for current lens array, can obtain the output (response vector) that length is 128, the code of the output Between Hamming distance (Hamming distance) frequency distribution it is as shown in Figure 10, by graphic calculation obtain PUF chip circuits output return One changes mean value as μ=0.5018, and corresponding standard deviation is σ=0.0182, and it is excellent that this indicates that PUF circuits proposed by the present invention have Circuit performance more.
PUF of embodiment of the present invention circuits and other PUF circuit performance comparison sheets：
Upper table gives the embodiment of the present invention compared with the performance of some other homogeneous circuits, it can be seen that object of the invention PUF circuits that unclonable chip circuit is invented than before are managed in performances such as power consumption, chip area, circuit reliabilities (bit error rate) Aspect has larger promotion.
It can be seen that the PUF circuits proposed by the present invention measured based on difference current are had, chip area is small, low-power consumption, The feature of high reliability and low cost can be widely applied on the circuit industry that reliability requirement is high, power budget is low.

Claims (8)

1. a kind of unclonable chip circuit of physics based on time-domain difference current measurement, which is characterized in that including two electric currents Lens array circuit, two current mirroring circuits, current comparator circuit and time-domain difference measuring circuit, two current lens array circuits Output current input the first current mirroring circuit and the second current mirroring circuit respectively；The first son electricity that first current mirroring circuit generates The first electron current that stream and the second current mirroring circuit generate is separately input to current comparator circuit, current comparator circuit pair two After a electron current is compared, binary system ID is exported；By repeatedly select the element circuit of current lens array circuit into After row is exported and handled, an ID sequence, the identity identification information as chip are obtained；The second of first current mirroring circuit generation The second electron current that electron current and the second current mirroring circuit generate is separately input to time-domain difference measuring circuit, and time-domain difference measures The first current mirroring circuit of circuit pair generate the second electron current and the second current mirroring circuit generate the second electron current difference it is absolute Value measures, and the size of the absolute value is calculated by controllable counter, by the threshold value comparison of the absolute value and setting, Export a binary identification position；After repeatedly selecting the element circuit of current lens array circuit to be exported and being handled, obtain To a mark sequence corresponding with the ID sequences, the reliability for characterizing the identity identification information.
2. the unclonable chip circuit of physics according to claim 1, which is characterized in that current lens array circuit includes M Root row address line, N roots column address conductor, M row N row NMOS tube, row identical with NMOS tube quantity switch and M row switch, electric current The grid of whole NMOS tubes of lens array circuit is connected, and connects additional control voltage；The source electrode of whole NMOS tubes is connected and is grounded； The drain electrode of NMOS tube connects the input terminal of every trade switch by arranging switch；The control of same row row switch terminates the column address of the row The control of line, row switch terminates the row address line of the row, and the output end of all row switches is connected, as current lens array circuit Output end.
3. the unclonable chip circuit of physics according to claim 2, which is characterized in that row switch and row switch are all NMOS tube, the source electrode for arranging switch are connected with the drain electrode of corresponding NMOS tube, and the grid for arranging switch connects the column address conductor of the row, same The drain electrode of all row switches of row connects the source electrode of every trade switch, and the grid of row switch connects the row address line of the row, all row switches Drain electrode be connected, the output end as current lens array circuit.
4. the unclonable chip circuit of physics according to claim 1, which is characterized in that current mirroring circuit includes three PMOS tube, the source electrode external power supply of three PMOS tube；The grid of three PMOS tube links together, and connects the leakage of the first PMOS tube Pole；The drain electrode of first PMOS tube of the first current mirroring circuit connects the output end of the first current lens array circuit, the second PMOS tube Drain electrode connects the first input end of current comparator circuit, and the drain electrode of third PMOS tube connects the first input of time-domain difference measuring circuit End；The drain electrode of first PMOS tube of the second current mirroring circuit connects the output end of the second current lens array circuit, the second PMOS tube Drain electrode connects the second input terminal of current comparator circuit, and the drain electrode of third PMOS tube connects the second input of time-domain difference measuring circuit End.
5. the unclonable chip circuit of physics according to claim 1, which is characterized in that current comparator circuit includes two NMOS and two cross-linked NMOS of a reset, reset NMOS and NMOS source electrode ground connection, first reset NMOS drain electrode and The grid of 2nd NMOS connects the drain electrode of the first NMOS, and the drain electrode of the second reset NMOS and the grid of the first NMOS connect the 2nd NMOS's Drain electrode；The drain electrode of two NMOS meets the electron current of the first current mirroring circuit and the output of the second current mirroring circuit, the first NMOS respectively Drain electrode be current comparator circuit output end.
6. the unclonable chip circuit of physics according to claim 5, which is characterized in that current comparator circuit works When, the grid input high level for resetting NMOS to two first makes reset NMOS be connected, two cross-couplings NMOS is made to pass through leakage Pole carries out discharge reduction；Then to the grid input low level of two reset NMOS, reset NMOS is made to turn off；Hereafter, two The drain electrode of NMOS inputs the electron current of the first current mirroring circuit and the output of the second current mirroring circuit respectively, if the first current mirror is electric The electron current of road output is more than the electron current of the second current mirroring circuit output, and the drain electrode of the first NMOS exports high level, obtains one A value is the positions ID of " 1 "；If the electron current of the first current mirroring circuit output is less than the electron current of the second current mirroring circuit output, The drain electrode of first NMOS exports low level, obtains the positions ID that a value is " 0 ".
7. the unclonable chip circuit of physics according to claim 1, which is characterized in that time-domain difference measuring circuit includes Controllable counter and two comparator circuits, comparator circuit include capacitance, reset NMOS tube and voltage comparator, reset NMOS The drain electrode of pipe connects the first end of capacitance, and the source electrode for resetting NMOS tube connects the second end ground connection of capacitance；First termination voltage of capacitance The homophase input of the inverting input of comparator, voltage comparator terminates reference voltage；First comparator circuit voltage comparator Anti-phase input terminate the first current mirroring circuit second output terminal, output termination controllable counter first input end；Second The anti-phase input of comparator circuit voltage comparator terminates the second output terminal of the second current mirroring circuit, and output termination is controllable to be counted Second input terminal of device.
8. the unclonable chip circuit of physics according to claim 7, which is characterized in that time-domain difference measuring circuit starts When work, NMOS tube conducting is resetted, to capacitance discharge reduction；After the completion of reset, NMOS tube shutdown is resetted；First current mirroring circuit The second electron current and the second electron current of the second current mirroring circuit be not input to two capacitances, while being filled for the two capacitances Electricity；When capacitance voltage rises to the reference voltage more than voltage comparator in-phase end, the output voltage saltus step of voltage comparator It is 0；If respectively ta and tb at the time of two voltage comparator output end voltage saltus steps, controllable counter is in first saltus step It carves ta to start counting up, stops counting in second jumping moment tb；The meter between two jumping moments is read on controllable counter Number is poor, and when this difference is more than preset threshold value, the flag that a value is " 1 " is exported from controllable counter；It is on the contrary Then export the flag that a value is " 0 ".
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CN107491704A (en) * 2017-08-23 2017-12-19 大家传承网络科技（深圳）有限公司 It is related to false proof, certification, the unclonable circuit of the physics of key and implementation method
CN107766750B (en) * 2017-11-22 2023-05-09 河海大学常州校区 PUF circuit based on threshold voltage reference
CN108694336B (en) * 2018-04-28 2022-02-11 深圳大学 Low-code-rate low-energy-consumption physical unclonable technology based on current comparator
CN109697376B (en) * 2019-01-18 2022-10-04 河海大学常州校区 PUF circuit based on differential charging capacitor
CN114487762B (en) * 2020-11-12 2024-09-24 北京昂瑞微电子技术股份有限公司 Chip and userID detection circuit thereof
CZ2021146A3 (en) * 2021-03-24 2022-01-05 České vysoké učení technické v Praze Connection with current mirrors, method of impedance measurement and current to voltage conversion in this connection
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