CN105760785B - A kind of unclonable chip circuit of physics based on time-domain difference current measurement - Google Patents

Abstract

The invention discloses a physically unclonable chip circuit based on time-domain differential current measurement, which comprises two current mirror array circuits, two current mirror circuits and a current comparator circuit, and the output currents of the two current mirror array circuits are respectively input into the first A current mirror circuit and a second current mirror circuit; the first sub-current produced by the first current mirror circuit and the first sub-current produced by the second current mirror circuit are respectively input to the current comparator circuit, and the current comparator circuit is used for the two sub-currents After comparison, a binary ID bit is output; after multiple selection of the unit circuit of the current mirror array circuit for output and processing, an ID sequence is obtained as the identification information of the chip. The invention has the characteristics of small chip area, low power consumption, high reliability and low cost, and can be widely used in the circuit industry with high reliability requirements and low power budget.

Description

A physically unclonable chip circuit based on time-domain differential current measurement

[technical field]

The invention relates to the field of information security, in particular to a physically unclonable chip circuit based on time-domain differential current measurement.

[Background technique]

Physical Unclonable Function (Physical Unclonable Function: PUF) refers to a function that inputs a stimulus to a physical entity, uses the random difference in its inevitable internal physical structure, and outputs an unpredictable random response. The most basic application of PUF is to use the entity's unique identifier to achieve authentication. Later, with people's in-depth understanding of it, more and more new types of PUF implementation methods have been proposed, such as arbiter-based PUF, butterfly PUF, Ring oscillator PUF, etc. Based on these implementation methods, PUF circuits have gradually been applied to more security fields, such as key generation of public key encryption systems, smart card key identification systems, radio frequency identification systems (Radio Frequency Identification, RFID) and related intellectual property protection. At the same time, according to the way integrated circuits are implemented, it can be divided into pure digital physical unclonable chips (digital PUF chips) and digital-analog hybrid physical unclonable chips (digital-analog hybrid PUF chips).

Literature [6] proposes a PUF circuit based on an arbitration mechanism, and the output response is obtained by comparing the delays of the two paths. The circuit is composed of two parts: a delay circuit and an arbitration judger. The delay circuit has 64-bit input, and the direction of the upper and lower paths is determined by inputting "0" or "1" per bit. There are 264 different path combinations in total. , the arbiter is used to judge the arrival sequence of the upper and lower road signals, and outputs "1" or "0" correspondingly. For example, a rising signal propagates through the upper and lower paths respectively. If the upper path propagates to the arbitration first, the output response is "1", otherwise the output response is "0". In this way, a series of corresponding response binary sequences can be obtained by inputting a series of rising and falling signals. Since the arbiter needs a settling time, the stability of the circuit is not high. Although the stability of the circuit can be improved by introducing a complex correction circuit, the power consumption of the circuit and the area of the chip are greatly increased.

Literature [7] proposes a PUF circuit based on a cross-coupling circuit that can be applied to FPGA. The PUF circuit utilizes the characteristics of two stable states of "0" or "1" in the cross-coupling circuit due to the existence of positive feedback loops, and an unstable intermediate state that is easy to transition to one of the two stable states. The two latches are cross-coupled to form a positive feedback loop. At the beginning, the circuit is in an unstable state by controlling the external excitation signal, and then the circuit is turned from an unstable state to "0" or "1" by changing the excitation signal. One of the stable states, thus obtaining a binary bit of "0" or "1". A plurality of such cross-coupling circuits are used to form an array, and finally a series of binary sequence outputs are obtained. Because when the cross-coupled circuit transitions from an unstable state to a stable state, it is easily affected by uncertain factors of some circuits or devices, so the transition process is unpredictable, so the final string of binary sequences is also unpredictable. ,only. However, this circuit also has stability problems, and an auxiliary algorithm circuit is needed to improve stability.

Reference [9] proposed a thyristor-based PUF implementation circuit. The circuit is composed of a thyristor sensor circuit, a time differential amplifier circuit, a time differential comparator circuit, a voting mechanism circuit and a diffusion algorithm circuit. Multiple identical thyristor sensors are used in the circuit. Due to the variation of the production process, each sensor generates two working currents with slightly different delay values. The working current is amplified by the delay through the time differential amplifier circuit; It is an arbiter circuit, which outputs a response of "1" or "0" correspondingly by comparing the arrival of two current signals; the voting mechanism circuit samples and counts the output response of the time difference comparator, and determines the output according to the sampling result The ID of the ID is "1" or "0". When the number of samples is large enough (the number of samples in the literature is 1000), a stable ID can be obtained; the diffusion algorithm circuit converts the obtained ID according to a certain algorithm, so that Meet the requirements of uniform statistical distribution and improve the uniqueness of the PUF circuit. The problem with this circuit is that it has a relatively high bit error rate, and it is difficult to obtain an ideally low bit error rate even if the power consumption and the chip area are increased.

Literature [1] K.Lofstrom, W.R.Daasch and D.Taylor, "IC identification circuitry using device mismatch," IEEE International Solid-State Circuits Conf. (ISSCC), pp.372-373, 2000.

Literature [2] J.Zhang, Y.Lin, Y.Lyu and G.Qu, "A PUF-FSM Binding Scheme for FPGA IP Protection and Pay-Per-Device Licensing," IEEE Transactions on Information Forensics and Security, vol.10, no.6, pp.1137-1150, 2015.

Literature [3] W.Liu, Z.Zhang, M.Li and Z.Liu, "A Trustworthy key Generation Prototype based on DDR3 PUF for Wireless Sensor Networks," IEEE International Symposium on Computer, Consumer and Control, pp.706-709, 2014.

Literature [4] Y.Cao, S.S.Z., L.Zhang, C.H.Chang and S.Chen, "CMOS Image SensorBased Physical Unclonable Function for Smart Phone Security Applications," IEEE International Symposium on Integrated Circuits, pp.392-395, 2014.

Literature [5] G.Qu and L.Yuan, "Design THINGS for the Internet of Things -AnEDA Perspective," IEEE International Conference on Computer-Aided Design, pp.411-416, 2014.

Literature [6] Lang Lin, S.Srivathsa, D.K.Krishnappa, P.Shabadi and W.Burleson, "Design and validation of Arbiter-Based PUFs for Sub-45-nm Low-Power Security Applications," IEEE Transactions on Information Forensics and Security , vol.7, no.4, pp.1394-1403, 2012.

Literature [7] S.S.Kumar, J.Guajardo, R.Maesyz, G.-J.Schrijen and P.Tuyls, "Thebutterfly PUF protecting IP on every FPGA," IEEE Sym.on Hardware-OrientedSecurity and Trust(HOST), pp.67-70, 2008.

Literature [8] Y.Su, J.Holleman and B.Otis, "A 1.6pJ/bit 96% Stable Chip-ID Generating Circuit using Process Variation," IEEE International Solid-State Circuits Conf. (ISSCC), pp.406-611 ,2007.

Literature [9] C.Bai, X.Zou and K.Dai, "A Novel Thyristor-Based SiliconPhysical Unclonable Function," IEEE Transactions on Very Large Scale Integartion (VLSI) Systems, in press, 2015.

Literature [10] S.Stanzione, D.Puntin and G.Iannaccone, "CMOS Silicon Physical Unclonable Functions Based on Intrinsic Process Variability," IEEE J.Solid-State Circuits, vol.46, no.6, pp.1456-1463, 2011.

Literature [11] K.Yang, Q.Dong, D.Blaauw and D.Sylvester, "A Physically Un-clonable Function with BER<10-8 for Robust Chip Authentication Using Oscillator Collapse in 40nm CMOS," IEEE International Solid-State CircuitsConf .(ISSCC),pp.254-256,2015.

Literature [12] Jason H.Anderson, "A PUF Design for Secure FPGA-Based Embedded Systems," IEEE Asia and South Pacific Design Automation Conference, pp.1-6, 2010.

The PUF implementation circuits proposed in the above literature generally have problems such as large chip area and relatively high power consumption. For example, the PUF circuit in the literature [9] has a chip area of 21750um ² and a power consumption of 380uw. These shortcomings limit the The practical application of PUF chips.

[Content of the invention]

The technical problem to be solved by the present invention is to provide a physically unclonable chip circuit based on time-domain differential current measurement with small chip area and low power consumption.

In order to solve the above technical problems, the technical solution adopted by the present invention is, a physical unclonable chip circuit based on time domain differential current measurement, including two current mirror array circuits, two current mirror circuits and current comparator circuits, two The output current of the current mirror array circuit is respectively input into the first current mirror circuit and the second current mirror circuit; the first sub-current generated by the first current mirror circuit and the first sub-current generated by the second current mirror circuit are respectively input into the current comparator circuit, the current comparator circuit compares the two sub-currents, and outputs a binary ID bit; after multiple selection of the unit circuit of the current mirror array circuit for output and processing, an ID sequence is obtained as the identification information of the chip.

The physical non-clonable chip circuit described above includes a time-domain differential measurement circuit, and the second sub-current generated by the first current mirror circuit and the second sub-current generated by the second current mirror circuit are respectively input to the time-domain differential measurement circuit. The domain difference measurement circuit measures the absolute value of the difference between the second sub-current generated by the first current mirror circuit and the second sub-current generated by the second current mirror circuit, calculates the magnitude of the absolute value through a controllable counter, and converts the Compare the absolute value of the absolute value with the set threshold, and output a binary identification bit; after multiple selection of the unit circuit of the current mirror array circuit for output and processing, an identification sequence corresponding to the ID sequence is obtained, which is used to characterize the ID sequence. The reliability of the above identification information.

The physical non-clonable chip circuit described above, the current mirror array circuit includes M row address lines, N column address lines, M rows and N columns of NMOS transistors, column switches and M row switches with the same number of NMOS transistors, and the current mirror The gates of all NMOS transistors in the array circuit are connected to the external control voltage; the sources of all NMOS transistors are connected to ground; the drain of each NMOS transistor is connected to the input terminal of the row switch through the corresponding column switch; The control terminal of the switch is connected to the column address line of the column, the control terminal of the row switch is connected to the row address line of the row, and the output terminals of all the row switches are connected together as the output terminal of the current mirror array circuit.

In the physical non-clonable chip circuit described above, both the column switch and the row switch are NMOS, the source of the column switch is connected to the drain of the corresponding NMOS transistor, the gate of the column switch is connected to the column address line of the column, and all columns in the same row The drain of the switch is connected to the source of the row switch, the gate of the row switch is connected to the row address line of the row, and the drains of all the row switches are connected to each other as the output terminal of the current mirror array circuit.

In the physical non-clonable chip circuit described above, the current mirror circuit includes three PMOS transistors, the sources of the three PMOS transistors are connected to an external power supply; the gates of the three PMOS transistors are connected together and connected to the drain of the first PMOS transistor; The drain of the first PMOS transistor of the first current mirror circuit is connected to the output end of the first current mirror array circuit, the drain of the second PMOS transistor is connected to the first input end of the current comparator circuit, and the drain of the third PMOS transistor is connected to The first input end of the time-domain differential measurement circuit; the drain of the first PMOS transistor of the second current mirror circuit is connected to the output end of the second current mirror array circuit, and the drain of the second PMOS transistor is connected to the second current comparator circuit The input end, the drain of the third PMOS transistor is connected to the second input end of the time domain difference measurement circuit.

The physical non-clonable chip circuit described above, the current comparator circuit includes two reset NMOS and two cross-coupled NMOS, the source of the reset NMOS and the cross-coupled NMOS is grounded, the drain of the first reset NMOS and the second cross-coupled The gate of the NMOS is connected to the drain of the first cross-coupled NMOS, the drain of the second reset NMOS and the gate of the first cross-coupled NMOS are connected to the drain of the second cross-coupled NMOS; the drains of the two cross-coupled NMOSs are respectively connected to The sub-current output by the first current mirror circuit and the second current mirror circuit, the drain of the first cross-coupled NMOS is the output terminal of the current comparator circuit.

In the physical non-clonable chip circuit described above, when the current comparator circuit is working, first input a high level to the gates of the two reset NMOSs, so that the reset NMOSs are turned on, and the two cross-coupled NMOSs are discharged and reset through the drains; Then input a low level to the gates of the two reset NMOSs to turn off the reset NMOSs; after that, the drains of the two cross-coupled NMOSs respectively input the sub-currents output by the first current mirror circuit and the second current mirror circuit, if the first The sub-current output by a current mirror circuit is greater than the sub-current output by the second current mirror circuit, the drain of the first cross-coupled NMOS outputs a high level, and an ID bit with a value of "1" is obtained; if the output of the first current mirror circuit The sub-current is smaller than the sub-current output by the second current mirror circuit, the drain of the first cross-coupled NMOS outputs a low level, and an ID bit with a value of "0" is obtained.

The physical non-clonable chip circuit described above, the time-domain differential measurement circuit includes a controllable counter and two comparator circuits, the comparator circuit includes a capacitor, a reset NMOS transistor and a voltage comparator, and the drain of the reset NMOS transistor is connected to the first capacitor of the capacitor. At one end, the source of the reset NMOS transistor is connected to the second end of the capacitor to ground; the first end of the capacitor is connected to the inverting input end of the voltage comparator, and the non-inverting input end of the voltage comparator is connected to the reference voltage; the first comparator circuit voltage comparison The inverting input terminal of the device is connected to the second output terminal of the first current mirror circuit, and the output terminal is connected to the first input terminal of the controllable counter; the inverting input terminal of the second comparator circuit voltage comparator is connected to the second current mirror circuit The second output terminal is connected to the second input terminal of the controllable counter.

In the physical non-clonable chip circuit described above, when the time domain difference measurement circuit starts to work, the reset NMOS tube is turned on, and the capacitor discharge is reset; after the reset is completed, the reset NMOS tube is turned off; the second sub-current of the first current mirror circuit and the second sub-current of the second current mirror circuit are input to the inverting terminals of the two voltage comparators, and charge the two capacitors at the same time; The output voltage of the comparator jumps to 0; the moment when the voltage jumps at the output terminals of the two voltage comparators is respectively t _a and t _b , the controllable counter starts counting at the first jumping moment t _a , and at the second Stop counting at the jump moment t _b ; read the count difference between the two jump moments on the controllable counter, when the difference is greater than the preset threshold value, output a flag with a value of "1" from the controllable counter bit; otherwise, an identification bit with a value of "0" is output.

The physical unclonable chip circuit based on time domain differential current measurement of the present invention has the characteristics of small chip area, low power consumption, high reliability and low cost, and can be widely used in the circuit industry with high reliability requirements and low power budget.

[Description of drawings]

The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

FIG. 1 is a functional block diagram of a physically unclonable chip circuit based on time-domain differential current measurement according to an embodiment of the present invention.

Fig. 2 is a basic schematic diagram of a current mirror array according to an embodiment of the present invention.

Fig. 3 is a circuit structure diagram of a current mirror array according to an embodiment of the present invention.

FIG. 4 is a circuit diagram of a current mirror A according to an embodiment of the present invention.

FIG. 5 is a circuit diagram of a current mirror B according to an embodiment of the present invention.

FIG. 6 is a circuit diagram of a current comparator circuit according to an embodiment of the present invention.

FIG. 7 is a circuit diagram of a time-domain differential current measurement circuit according to an embodiment of the present invention.

FIG. 8 is a working principle diagram of a time-domain differential current measurement circuit according to an embodiment of the present invention.

FIG. 9 is a statistical diagram of bit error rates under different temperatures and operating voltages obtained from physical unclonable chip circuit simulation based on time-domain differential current measurement according to an embodiment of the present invention.

FIG. 10 is a frequency distribution diagram of the Hamming distance between codes of physically unclonable chip circuits based on time-domain differential current measurement according to an embodiment of the present invention.

[Detailed ways]

The system structure of the physical unclonable chip circuit based on time domain differential current measurement in the embodiment of the present invention is shown in Figure 1. The PUF circuit consists of two identical current mirror array circuits, two identical current mirror circuits, and a current comparator circuit and a time-domain differential measurement circuit. The overall working principle of the circuit is as follows: two current mirror array circuits respectively output currents I _A and I _B , and these two currents respectively pass through current mirror circuit A and current mirror circuit B to generate two sub-currents I _A1 , I _A2 and I _B1 , I _B2 . I _A1 and I _B1 are input to the current comparator circuit, and the current comparator outputs a binary ID bit (“1” or “0” after comparing the two currents); I _A2 and I _B2 are input to the time-domain differential measurement In the circuit, the measurement circuit measures the absolute value ΔI=|I _A2 -I _B2 | of the difference between I _A2 and I _B2 , calculates the size of ΔI through a controllable counter, and then outputs a binary flag through this counter ("1" or "0"). After multiple times of comparing and measuring two currents output from the current mirror array circuit, an ID sequence and a corresponding identification sequence can be obtained. The obtained ID sequence can be used as the identification information of a chip, and the identification sequence is used to characterize the reliability of the identification information.

The basic principle of the current mirror array circuit is shown in Figure 2, assuming the process parameters of the three MOS transistors M ₁ , M ₂ , and M ₃ (such as: electron mobility μ _n , gate oxide capacitance per unit area C _ox , channel width The length ratio W/L, threshold voltage V _TH , etc.) are exactly the same (regardless of the channel modulation effect), theoretically the two output currents I ₁ and I ₂ are completely equal, but due to the deviation in the manufacturing process, the two currents In fact, they are not exactly equal, and such a pair of currents can be called a mismatch current. In Figure 2, I _REF is a given input current and V _B is the voltage generated by current _{I REF} across transistor M1.

The current mirror array circuit shown in Figure 3 is obtained by expanding the circuit shown in Figure 2 . The current mirror array is composed of the same NMOS transistors in M rows and N columns. The gates of all NMOS transistors in the current mirror array circuit are connected together; the sources of all NMOS transistors are connected and grounded, and the drain of each NMOS transistor is connected to a column switch (also an NMOS tube). The source of the column switch is connected to the drain of the NMOS transistor in the array, and in the same current mirror array circuit, the column switch control terminal (gate) of the same column is connected. The external N address lines are respectively connected to the gates of N column switches, and the column switches of the same column are controlled to be turned on and off at the same time. These N address lines are called the bit lines of the array (BL ₁ -BL _N ) ; The drains of all the column switches in the same row are connected, the NMOS transistors in the same row share a row switch (also an NMOS transistor), and the source of the row switch is connected to the drains of all the column switches in the same row. The external M address lines are respectively connected to the gates of the M row switches to control the turn-on and turn-off of the row switches. These M address lines are called the word lines (WL ₁ -WL _M ) of the array; all row The drains of the switches are connected as the output of the entire array.

The output current I _OUT of the array circuit shown in FIG. 3 is respectively the output currents I _A and I _B of array 1 and array 2 in FIG. 1 . I _A and I _B are respectively input to the input ends of the current mirror circuit A and the current mirror circuit B. V _B is an external control voltage, which controls the NMOS transistors in the array to be in a normal working state (conduction). The basic working process of the current mirror array is as follows: the external control voltage V _B makes all the NMOS transistors in the array in the conduction state, and the external address lines (bit lines and word lines of the array) control the row and column switches, and in array 1 and array 2 Each selects one NMOS transistor to output two mismatch currents. These two mismatched currents are input into the current mirror circuit A and the current mirror circuit B.

The circuit structures of the current mirror circuit A and the current mirror circuit B are shown in Figure 4 and Figure 5 respectively, the PMOS tubes M ₄ -M ₆ form the circuit of the current mirror circuit A, and M ₇ -M ₉ form the circuit of the current mirror circuit B, The six PMOS transistors M ₄ -M ₉ are identical. The basic function of current mirror circuit A and current mirror circuit B is to generate two output currents that are exactly equal to the input current. As shown in Figure 4 and Figure 5, the inputs of the two current mirror circuits are I _A and I _B , and the outputs are I _A1 , I _A2 and I _B1 , I _B2 respectively. Due to process deviation, I _A is not exactly equal to I _A1 , I _A2 , and I _B is not completely equal to I _B1 , I _B2 , but by increasing the size of the PMOS transistor in the two current mirror circuits, the error between the input and output currents can be reduced Reduced to a negligible range; similarly, by reducing the size of the NMOS transistors in the current mirror array circuit 1 and the current mirror array circuit 2, the difference between the mismatch currents generated by the two arrays can be increased to improve The reliability of the PUF circuit.

The circuit structure of the current comparator circuit is shown in Figure 6. The circuit consists of two reset NMOS transistors M ₁₀ and M ₁₃ and two cross-coupled NMOS transistors M ₁₁ and M _12. The two input ports of the circuit input the output current I _A1 of the current mirror circuit A and the current mirror circuit B respectively. and I _B1 , the output ID bit at the drain of M ₁₁ . When the circuit is working, first input the reset signal (high level for the NOMS tube) to reset the circuit. The reset NMOS transistors M ₁₀ and M ₁₃ are turned on, and the drains of the two cross-coupled NMOS transistors M ₁₁ and M ₁₂ are discharged to reduce their voltage to zero. After the reset is completed, _M10 and _M13 are turned off (reset signal becomes low level). The currents I _A1 and I _B1 are input from the _{drains of the cross-coupled NMOS transistors M 11 and M 12 respectively .} The drain charging of M ₁₁ and M ₁₂ , because the magnitudes of the two currents I _A1 and I _B1 are not exactly equal, so the rate of rise of the drain voltage of M ₁₁ and M ₁₂ is different, if I _A1 > I _B1 , then M ₁₁ ’s The rising rate _of the drain voltage is greater than that of M12, so M12 is turned _on first. As a result of the conduction of M ₁₂ , its drain voltage is pulled down to ground or close to the ground voltage, so M ₁₁ will always remain off, and finally the drain voltage of M ₁₁ will rise to a stable value. At this time, the drain terminal of M ₁₁ will output a high level, and an ID bit with a value of "1" can be obtained. Similarly, when I _A1 <I _B1 , the circuit will get an ID bit with a value of "0".

In order to ensure the reliability of the overall circuit operation, the present invention proposes a Time-Domain Current Difference Measurement (TDCDM) circuit as shown in FIG. 7 . The structure consists of two identical capacitors C ₁ , C ₂ , two reset NMOS transistors M ₁₄ , M ₁₅ , two voltage comparators D ₁ , D ₂ and a 9-bit controllable counter. The inverting terminals of D ₁ and D ₂ are respectively connected to the upper terminals of capacitors C ₁ and C ₂ , the reset transistors M ₁₄ and M ₁₅ are respectively connected in parallel with C ₁ and C ₂ and the lower terminals are grounded. The non-inverting terminals of the voltage comparators D ₁ and D ₂ are connected to a given reference voltage V _REF , the inverting terminals are respectively connected to the upper terminals of capacitors C ₁ and C ₂ , and the output terminals are connected to the control terminal of the controllable counter to control the counter to start counting and Stop counting. At the beginning, since the voltage at the inverting terminal of the voltage comparator D ₁ and D ₂ is smaller than the voltage at the non-inverting terminal, the output voltage of D ₁ and D ₂ is V _dd (power supply voltage); when the circuit starts to work, the reset transistors M ₁₄ and M ₁₅ conduct Through, the reset (discharge) operation is performed on the capacitors C ₁ and C ₂ . After the reset is completed, the reset transistors M ₁₄ and M ₁₅ are turned off. Then the currents I _A2 and I _B2 are respectively input to the inverting terminals of D ₁ and D ₂ to charge the two capacitors at the same time. When the voltage across capacitors C ₁ and C ₂ rises higher than the reference voltage V _REF at the non-inverting terminals of D ₁ and D ₂ , the output voltages of D ₁ and D ₂ jump from V _dd to 0. Since I _A2 and I _B2 are not completely equal, the rising rates of the voltages at both ends of the capacitors C ₁ and C ₂ are different, so the timings at which the output voltages of the two comparators D ₁ and D ₂ jump are different. Assuming that the voltage jumps at the output terminals of the two voltage comparators are t _a and t _b respectively, the controllable counter starts counting at the first jumping time t _a and stops counting at the second jumping time t _b . At this time, the count difference between the two moments can be read from the counter. When the difference is greater than a preset threshold, a flag with a value of "1" is output from the counter, otherwise a value of "0" is output. " flag.

Figure 8 is the working principle of the time-domain differential current measurement (TDCDM) circuit, the curve X and curve Y in the figure are the change curves of the voltages at both ends of the two capacitors C ₁ and C ₂ respectively; t _a and t _b are the comparator D _{1. The} moment when the output terminal voltage of D2 jumps, that is, the moment when the counter starts counting and stops counting; CLK is the value counted by the fixed-cycle counter, and the difference between the current I _A2 and I _B2 is equal to the value counted by the counter The values are proportional, and the larger the value counted by the counter, the larger the difference between the currents I _A2 and I _B2 , and the higher the reliability of the generated PUF bits.

The above embodiments of the present invention have the following beneficial effects:

The PUF implementation method proposed by the present invention does not require a complex error correction circuit, and greatly reduces the chip area and power consumption required by the circuit. The PUF circuit proposed by the present invention uses transistors with the same parameters to generate mismatch current due to parameter deviation caused by process deviation in the production process, so there is no need to use large-sized component design in the circuit to buffer circuit problems caused by process deviation, Instead, transistors with smaller sizes can be used in the current mirror array, so that the current mirror array generates a larger mismatch current, thereby reducing the bit error rate of the circuit and improving the reliability of the circuit. At the same time, all analog circuits can be optimized and made to work in the sub-threshold region, which also greatly reduces the overall power consumption of the circuit.

In addition, the PUF chip circuit proposed by the present invention can use the UMC 0.18μm standard CMOS process for circuit simulation and layout design. The chip area of the entire circuit is 13310μm ² , which is about 40% lower than that of the PUF circuit in literature [9]. Fig. 9 has provided the simulation result of bit error rate of the PUF circuit that the present invention proposes, can see that this PUF circuit can reach the superior performance of bit error rate zero under common temperature and power supply voltage condition, under worst temperature and power supply The bit error rate under voltage conditions is only 1.56%.

Not only that, the novel physical unclonable circuit example proposed in the present invention is tested, by inputting random selection signal (for current mirror array addressing), can obtain the output (response vector) that length is 128 bits, the code interval of this output The frequency distribution of the Hamming distance (Hamming distance) is shown in Figure 10, and the normalized mean value of the PUF chip circuit output calculated from the figure is μ=0.5018, and the corresponding standard deviation is σ=0.0182, which means that the PUF circuit proposed by the present invention Has superior circuit performance.

Performance comparison table between the PUF circuit of the embodiment of the present invention and other PUF circuits:

The above table shows the performance comparison between the embodiment of the present invention and some other similar circuits. It can be seen that the physically unclonable chip circuit of the present invention is better than the PUF circuit invented before in terms of power consumption, chip area, and circuit reliability (bit error rate). Performance has been greatly improved.

It can be seen that the PUF circuit based on differential current measurement proposed by the present invention has the characteristics of small chip area, low power consumption, high reliability and low cost, and can be widely used in the circuit industry with high reliability requirements and low power budget.

Claims (8)

1. A physical unclonable chip circuit based on time-domain differential current measurement, characterized in that it comprises two current mirror array circuits, two current mirror circuits, a current comparator circuit and a time-domain differential measurement circuit, two current mirrors The output current of the array circuit is respectively input into the first current mirror circuit and the second current mirror circuit; the first sub-current generated by the first current mirror circuit and the first sub-current generated by the second current mirror circuit are respectively input into the current comparator circuit, After the current comparator circuit compares the two sub-currents, it outputs a binary ID bit; after multiple selection of the unit circuit of the current mirror array circuit for output and processing, an ID sequence is obtained as the identification information of the chip; the first current The second sub-current generated by the mirror circuit and the second sub-current generated by the second current mirror circuit are respectively input to the time-domain differential measurement circuit, and the time-domain differential measurement circuit is used for the second sub-current and the second current generated by the first current mirror circuit. The absolute value of the second sub-current difference generated by the mirror circuit is measured, the size of the absolute value is calculated by a controllable counter, the absolute value is compared with the set threshold, and a binary flag is output; after multiple selections After the unit circuit of the current mirror array circuit outputs and processes, an identification sequence corresponding to the ID sequence is obtained, which is used to represent the reliability of the identification information. 2. The physical non-clonable chip circuit according to claim 1, wherein the current mirror array circuit comprises M row address lines, N column address lines, M rows and N columns of NMOS transistors, and the columns identical to the number of NMOS transistors The switch is connected to M row switches, and the gates of all NMOS transistors in the current mirror array circuit are connected to an external control voltage; the sources of all NMOS transistors are connected and grounded; the drains of the NMOS transistors are connected to the input of the row switch through the column switch terminal; the control terminal of the column switch of the same column is connected to the column address line of the column, the control terminal of the row switch is connected to the row address line of the row, and the output terminals of all the row switches are connected as the output terminal of the current mirror array circuit. 3. The physical non-clonable chip circuit according to claim 2, wherein both the column switch and the row switch are NMOS tubes, the source of the column switch is connected to the drain of the corresponding NMOS tube, and the gate of the column switch is connected to the drain of the corresponding NMOS tube. The column address line of the column, the drains of all the column switches in the same row are connected to the source of the row switch, the gate of the row switch is connected to the row address line of the row, and the drains of all the row switches are connected, as a current mirror array circuit output terminal. 4. The physical non-clonable chip circuit according to claim 1, wherein the current mirror circuit comprises three PMOS transistors, the source electrodes of the three PMOS transistors are connected to an external power supply; the gates of the three PMOS transistors are connected together, and Connect the drain of the first PMOS tube; the drain of the first PMOS tube of the first current mirror circuit is connected to the output terminal of the first current mirror array circuit, and the drain of the second PMOS tube is connected to the first input terminal of the current comparator circuit , the drain of the third PMOS transistor is connected to the first input end of the time-domain differential measurement circuit; the drain of the first PMOS transistor of the second current mirror circuit is connected to the output end of the second current mirror array circuit, and the drain of the second PMOS transistor is The electrode is connected to the second input end of the current comparator circuit, and the drain of the third PMOS transistor is connected to the second input end of the time domain difference measurement circuit. 5. The physical non-clonable chip circuit according to claim 1, wherein the current comparator circuit includes two reset NMOSs and two cross-coupled NMOSs, the source of the reset NMOS and the NMOS is grounded, and the source of the first reset NMOS is grounded. The drain and the gate of the second NMOS are connected to the drain of the first NMOS, the drain of the second reset NMOS and the gate of the first NMOS are connected to the drain of the second NMOS; the drains of the two NMOSs are respectively connected to the first current The sub-current output by the mirror circuit and the second current mirror circuit, the drain of the first NMOS is the output terminal of the current comparator circuit. 6. The physical non-clonable chip circuit according to claim 5, characterized in that, when the current comparator circuit is working, first input a high level to the gates of the two reset NMOSs, so that the reset NMOSs are turned on, and the two crossed The coupled NMOS is discharged and reset through the drain; then a low level is input to the gates of the two reset NMOSs, so that the reset NMOSs are turned off; after that, the drains of the two NMOSs are respectively input into the first current mirror circuit and the second current mirror circuit The output sub-current, if the sub-current output by the first current mirror circuit is greater than the sub-current output by the second current mirror circuit, the drain of the first NMOS outputs a high level, and an ID bit with a value of "1" is obtained; if the first The sub-current output by the first current mirror circuit is smaller than the sub-current output by the second current mirror circuit, the drain of the first NMOS outputs a low level, and an ID bit with a value of "0" is obtained. 7. The physical non-clonable chip circuit according to claim 1, wherein the time-domain differential measurement circuit includes a controllable counter and two comparator circuits, and the comparator circuit includes a capacitor, a reset NMOS transistor and a voltage comparator, and the reset The drain of the NMOS tube is connected to the first terminal of the capacitor, and the source of the reset NMOS tube is connected to the second terminal of the capacitor to ground; the first terminal of the capacitor is connected to the inverting input terminal of the voltage comparator, and the non-inverting input terminal of the voltage comparator is connected to the reference Voltage; the inverting input terminal of the first comparator circuit voltage comparator is connected to the second output terminal of the first current mirror circuit, and the output terminal is connected to the first input terminal of the controllable counter; the inverting phase of the second comparator circuit voltage comparator The input terminal is connected to the second output terminal of the second current mirror circuit, and the output terminal is connected to the second input terminal of the controllable counter. 8. The physical non-clonable chip circuit according to claim 7, characterized in that, when the time-domain differential measurement circuit starts to work, the reset NMOS tube is turned on, and the capacitor discharge is reset; after the reset is completed, the reset NMOS tube is turned off; the second The second sub-current of the first current mirror circuit and the second sub-current of the second current mirror circuit are respectively input to two capacitors, and the two capacitors are charged at the same time; when the capacitor voltage rises to a reference voltage greater than the non-inverting terminal of the voltage comparator, The output voltage of the voltage comparator jumps to 0; set the moment of the voltage jump of the output terminals of the two voltage comparators as ta and tb respectively, the controllable counter starts counting at the first jump time ta, and at the second jump time Stop counting at time tb; read the count difference between two jumping moments on the controllable counter, when the difference is greater than the preset threshold, output a flag value "1" from the controllable counter; otherwise Then output an identification bit whose value is "0".