CN115130152B - Method and device for generating physical unclonable function - Google Patents
Method and device for generating physical unclonable function Download PDFInfo
- Publication number
- CN115130152B CN115130152B CN202211064981.7A CN202211064981A CN115130152B CN 115130152 B CN115130152 B CN 115130152B CN 202211064981 A CN202211064981 A CN 202211064981A CN 115130152 B CN115130152 B CN 115130152B
- Authority
- CN
- China
- Prior art keywords
- differential
- memory
- puf
- data
- determining
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/73—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by creating or determining hardware identification, e.g. serial numbers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
- G06F7/588—Random number generators, i.e. based on natural stochastic processes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
- H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
- H04L9/0866—Generation of secret information including derivation or calculation of cryptographic keys or passwords involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computer Security & Cryptography (AREA)
- General Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Mathematical Physics (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Read Only Memory (AREA)
Abstract
The invention discloses a method and a device for generating a physical unclonable function, wherein the method is applied to a differential storage module, the differential storage module comprises a plurality of differential units, and each differential unit comprises a first differential memory and a second differential memory which are matched; the method comprises the following steps: performing an erase operation on the first differential memory and the second differential memory in each of the differential units; determining a comparison value of the first differential memory and the second differential memory after the erasing operation by using a comparator corresponding to the differential unit; and determining PUF data according to the comparison value corresponding to each difference unit. The PUF data is generated based on the inherent physical structure of the differential unit, so that any additional circuit structure or timing control structure does not need to be introduced.
Description
Technical Field
The present invention relates to the field of data processing technologies, and in particular, to a method and an apparatus for generating a physical unclonable function.
Background
A physically Unclonable Function (i.e. a physically Unclonable Function, PUF for short) is considered a "digital fingerprint" in an integrated circuit. The generation of PUFs depends on the uniqueness of the microstructures in the integrated circuit, and thus PUFs have unpredictable and uncontrollable characteristics. In other words, a PUF can be considered as a kind of truly random data in the semiconductor field.
In the prior art, PUFs are usually generated using some special timing or special design rules. For example, the memory cell may suffer from different tendencies due to microstructural effects when transitioning from an unstable state to a stable state. Based on this tendency, a PUF can be generated. Alternatively, the digital signal may have random delay due to the influence of the microstructure during propagation. PUFs can also be generated using this delay.
However, the prior art has the disadvantage that the PUF generation with a special timing or special design rules requires the introduction of additional circuit structures or timing control structures. Therefore, each introduces a large additional circuit overhead, and the data length of the generated PUF is limited.
Disclosure of Invention
The invention provides a method and a device for generating a physical unclonable function, which can generate a PUF by using a differential storage unit in a differential structure.
In a first aspect, the present invention provides a PUF generation method, where the method is applied to a differential storage module, where the differential storage module includes a plurality of differential units, and each of the differential units includes a first differential memory and a second differential memory that are matched with each other; the method comprises the following steps:
performing an erase operation on the first differential memory and the second differential memory in each of the differential units;
determining a comparison value of the first differential memory and the second differential memory after the erasing operation by using a comparator corresponding to the differential unit;
and determining PUF data according to the comparison value corresponding to each difference unit.
Preferably, the differential memory module includes:
the obtained specific memory area is divided in the nonvolatile memory having the differential structure.
Preferably, the differential unit including the first differential memory and the second differential memory matched with each other includes:
the drain end of the first differential memory is connected with a first PMOS tube;
the drain end of the second differential memory is connected with a second PMOS tube;
the first differential memory is connected with the first input end of the comparator corresponding to the differential unit;
and the second differential memory is connected with the second input end of the comparator corresponding to the differential unit.
Preferably, the determining, by using the comparator corresponding to the differential unit, the comparison value of the first differential memory and the second differential memory after the erase operation includes:
the comparator outputs a random number value based on the microstructure difference of the first differential memory and the second differential memory;
determining the random number value as the comparison number value.
Preferably, the determining PUF data according to the comparison value corresponding to each of the differential units includes:
arranging the comparison numerical values corresponding to the differential units into random number sequences;
determining the random number sequence as the PUF data.
Preferably, the method further comprises the following steps:
and backing up the PUF data to a local storage medium and an external storage medium.
Preferably, the method further comprises the following steps:
performing encryption calculation on original data in the local storage medium by using the PUF data to determine encrypted data;
and transmitting the encrypted data to the external storage medium so that the external storage medium performs decryption calculation on the encrypted data by using the PUF data.
In a second aspect, the present invention provides a PUF generation apparatus, where the apparatus is disposed in a differential memory module, where the differential memory module includes a plurality of differential units, and each of the differential units includes a first differential memory and a second differential memory that are matched with each other; the device comprises:
an erasing module, configured to perform an erasing operation on the first differential memory and the second differential memory in each differential unit;
the comparison data determining module is used for determining a comparison value of the first differential memory and the second differential memory after the erasing operation by using the comparator corresponding to the differential unit;
and the PUF data determining module is used for determining the PUF data according to the comparison numerical value corresponding to each difference unit.
Preferably, the method further comprises the following steps:
the backup module is used for backing up the PUF data to a local storage medium and an external storage medium;
and the encryption module is used for carrying out encryption calculation on the original data in the local storage medium by utilizing the PUF data so as to determine encrypted data.
In a third aspect, the invention provides a readable medium comprising executable instructions, which when executed by a processor of an electronic device, perform the method according to any of the first aspect.
In a fourth aspect, the present invention provides an electronic device, comprising a processor and a memory storing execution instructions, wherein when the processor executes the execution instructions stored in the memory, the processor performs the method according to any one of the first aspect.
The invention provides a method and a device for generating a physical unclonable function, which are used for generating PUF data based on the inherent physical structure of a differential unit, so that any additional circuit structure or time sequence control structure is not required to be introduced, the hardware design process is simplified, and the hardware cost is also reduced; meanwhile, the memory resources in the differential memory module are not required to be occupied permanently, so that the circuit overhead is greatly reduced; and the PUF data with enough data volume can be generated to meet the current use requirement.
Further effects of the above-mentioned unconventional preferred modes will be described below in conjunction with specific embodiments.
Drawings
In order to more clearly illustrate the embodiments or the prior art solutions of the present invention, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments described in the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive labor.
Fig. 1 is a schematic flowchart of a PUF generation method according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a differential unit in a PUF generation method according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an apparatus for generating a PUF according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to specific embodiments and corresponding drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the field of semiconductor/integrated circuits, identical circuit structures are macroscopically uniform, but each circuit structure is microscopically distinct. This uniqueness arises from random factors in the fabrication of the integrated circuit. It can therefore be theoretically assumed that absolutely identical circuit configurations do not exist. PUFs are generated by exploiting the uniqueness of the integrated circuit microstructure.
Therefore, PUFs are unpredictable and uncontrollable and are truly random data. Unlike the common 'pseudo random data' generated by using a preset random number table, the PUF as the true random data has the characteristics of almost no cloning and no reproducibility, and has special application value in some fields.
In the prior art, PUFs are usually generated using some special timing or special design rules. For example, the memory cell may suffer from different tendencies due to microstructural effects when transitioning from an unstable state to a stable state. Based on this tendency, a PUF can be generated. Currently applied SRAM PUFs, flip-flop PUFs are based on this principle. Alternatively, the digital signal is also influenced by microstructures such as a channel length, a channel width, a threshold voltage, an oxide layer thickness, and a shape of a metal line during propagation, and random delay occurs. PUFs can also be generated using this delay. It is based on this principle that currently applied arbiter-based PUFs, ring oscillator-based PUFs are.
However, the prior art has the disadvantage that the PUF generation using a special timing or special design rules requires the introduction of additional circuit structures or timing control structures. Therefore, a large additional circuit overhead is incurred, and the data length of the generated PUF is limited.
In view of this, the present invention provides a PUF generation method. Referring to fig. 1, a specific embodiment of a PUF generation method provided in the present invention is shown.
In this embodiment, the method is applied to a differential memory module. The differential memory block may be a specific memory area divided in a nonvolatile memory having a differential structure. This storage area is not used for conventional data storage for the time being during implementation of the method in this embodiment.
The differential memory module comprises a plurality of differential units, and each differential unit comprises a first differential memory S205 and a second differential memory S206 which are matched. The specific structure of the differential unit is shown in fig. 2. The drain of the first differential memory S205 is connected to the first PMOS transistor S201, that is, the first PMOS transistor S201 constitutes a load of the first differential memory S205, and the first differential memory S205 is connected to the first drain bias S203. The drain of the second differential memory S206 is connected to the second PMOS transistor S202, that is, the second PMOS transistor S202 constitutes a load of the second differential memory S206, and the second differential memory S206 is connected to the second drain bias S204. The first drain bias S203 is the same as the second drain bias S204. The first differential memory S205 is connected to the first input terminal of the comparator S207 corresponding to the differential unit; the second differential memory S206 is connected to the second input terminal of the comparator S207 corresponding to the differential unit.
The differential cell can be considered as a basic memory cell in a conventional differential nonvolatile memory. Generally, one differential cell as described above can store 1 bit of data, i.e., one bit "0" or "1" in binary data. In this embodiment, the PUF data is generated using the differential unit of this structure.
In this embodiment, the method includes the steps of:
During normal storage, the first differential memory S205 and the second differential memory S206 in one differential cell must be in opposite states; i.e. one is high, the other is low. Therefore, the comparator S207 can compare the potentials of the two and output binary data "0" or "1" according to the comparison result. Thereby realizing recording of data of 1 bit.
In the present embodiment, the first differential memory S205 and the second differential memory S206 are first subjected to an erase operation. An erase operation is a conventional data erase operation for a memory. By the erase operation, charges in the floating gates of the first and second differential memories S205 and S206 can be swept.
And step 102, determining a comparison numerical value of the first differential memory and the second differential memory after the erasing operation by using the comparator corresponding to the differential unit.
After the erasing operation is completed, the states (potentials) of the first differential memory S205 and the second differential memory S206 should be theoretically uniform. But the integrated circuits of the two have differences in microstructure. In practice this difference in microstructure will result in the potentials of the two remaining inconsistent. The comparator S207 may capture the potential mismatch, and compare the potentials to output a comparison value. The comparison value is also binary data "0" or "1".
It should be noted that, since the difference in the microstructures of the first differential memory S205 and the second differential memory S206 is uncertain, it is not possible to determine in advance which potential will be relatively higher after the erasing operation is performed between the two. That is, whether the comparison value is "0" or "1" cannot be determined in advance. This means that the comparison value is a random number generated based on a true random mechanism.
That is, in this embodiment, the comparator will output a random number value based on the microstructure difference between the first differential memory S205 and the second differential memory S206; and determining the random number value as the comparison number value.
And 103, determining the PUF data according to the comparison value corresponding to each difference unit.
A plurality of differential cells as shown in fig. 2 are included in a differential memory block. Each differential cell has the same or similar structure. And a random comparison value can be generated according to the modes in the steps 101 to 102. Further, the comparison values corresponding to each difference unit are arranged in sequence, so that a binary random number sequence can be obtained. Each bit of data of the random number sequence is a randomly generated binary value. The random number sequence is therefore characterized by being almost unclonable and irreproducible. The random number sequence may be determined as the PUF data in this embodiment.
Further preferably, the PUF data may be backed up to a local storage medium and an external storage medium. For subsequent use.
For example, in some cases, encryption of the raw data may be implemented using the PUF data. The original data is various types of data originally stored in the local storage medium. Specifically, the PUF data may be used to perform a cryptographic calculation on raw data in the local storage medium to determine cryptographic data. The encrypted data is then transmitted to the external storage medium. The external storage medium can decrypt and calculate the encrypted data by utilizing the pre-stored PUF data.
In the method described in this embodiment, the PUF data is generated by means of the inherent physical structure of the difference cells. Therefore, any additional circuit structure or time sequence control structure is not required to be introduced, the hardware design process is simplified, and the hardware cost is also reduced. In addition, the storage resources in the differential storage module can be used for other purposes after the PUF data is generated, permanent occupation is not needed, and circuit overhead is greatly reduced. The differential memory block comprises a large number of differential cells and corresponding comparators S207. Theoretically, each comparator S207 can generate one bit of binary data in the PUF data. Therefore, in this embodiment, PUF data of sufficient length can be generated to make the data amount sufficient for the current application.
According to the technical scheme, the beneficial effects of the embodiment are as follows: the PUF data is generated based on the inherent physical structure of the differential unit, so that any additional circuit structure or time sequence control structure is not required to be introduced, the hardware design process is simplified, and the hardware cost is also reduced; meanwhile, the memory resources in the differential memory module are not required to be occupied permanently, so that the circuit overhead is greatly reduced; and the PUF data with enough data volume can be generated to meet the current use requirement.
Fig. 3 shows a specific embodiment of a PUF generation apparatus according to the present invention. The apparatus of this embodiment, i.e. the physical apparatus for performing the method of 1~2 in fig. 5363. The technical solution is essentially the same as that in the above embodiment, and the corresponding description in the above embodiment is also applicable to this embodiment. The device in the embodiment is arranged in a differential storage module, the differential storage module comprises a plurality of differential units, and each differential unit comprises a first differential memory and a second differential memory which are matched; the device comprises:
an erasing module 301, configured to perform an erasing operation on the first differential memory and the second differential memory in each differential unit.
A comparison data determining module 302, configured to determine, by using the comparator corresponding to the differential unit, a comparison value of the first differential memory and the second differential memory after the erase operation.
A PUF data determining module 303, configured to determine PUF data according to the comparison value corresponding to each difference unit.
In addition, on the basis of the embodiment shown in fig. 3, it is preferable that:
a backup module 304, configured to backup the PUF data to a local storage medium and an external storage medium.
An encryption module 305, configured to perform an encryption calculation on the raw data in the local storage medium by using the PUF data to determine encrypted data.
Fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present invention. On the hardware level, the electronic device comprises a processor and optionally an internal bus, a network interface and a memory. The Memory may include a nonvolatile Memory, such as a Random-Access Memory (RAM), and may also include a non-volatile Memory, such as at least 1 disk Memory. Of course, the electronic device may also include hardware required for other services.
The processor, the network interface, and the memory may be connected to each other via an internal bus, which may be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, an EISA (Extended Industry Standard Architecture) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one double-headed arrow is shown in FIG. 4, but that does not indicate only one bus or one type of bus.
And the memory is used for storing the execution instruction. In particular, a computer program can be executed by executing instructions. The memory may include non-volatile memory and provide execution instructions and data to the processor.
In a possible implementation manner, the processor reads corresponding execution instructions from the non-volatile memory into the memory and then executes the execution instructions, and corresponding execution instructions can also be obtained from other devices, so as to form the PUF generation device on a logic level. The processor executes the execution instructions stored in the memory to implement the PUF generation method provided in any embodiment of the present invention by executing the execution instructions.
The method performed by the PUF generation device according to the embodiment of the present invention shown in fig. 3 may be applied to or implemented by a processor. The processor may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or instructions in the form of software. The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also Digital Signal Processors (DSPs), application Specific Integrated Circuits (ASICs), field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components. The various methods, steps and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The steps of the method disclosed in connection with the embodiments of the present invention may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in a memory, and a processor reads information in the memory and completes the steps of the method in combination with hardware of the processor.
An embodiment of the present invention further provides a readable storage medium, where the readable storage medium stores an execution instruction, and when the stored execution instruction is executed by a processor of an electronic device, the electronic device can be caused to perform the PUF generation method provided in any embodiment of the present invention, and is specifically configured to perform the method shown in fig. 1.
The electronic device described in the foregoing embodiments may be a computer.
It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as a method or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects.
All the embodiments in the invention are described in a progressive manner, and the same and similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, as for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
The above description is only an example of the present invention, and is not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.
Claims (11)
1. A PUF generation method is applied to a differential storage module, the differential storage module comprises a plurality of differential units, and each differential unit comprises a first differential storage and a second differential storage which are matched; the method comprises the following steps:
performing an erase operation on the first differential memory and the second differential memory in each of the differential units;
determining a comparison value of the first differential memory and the second differential memory after the erasing operation by using a comparator corresponding to the differential unit; the comparison value is based on a potential inconsistency caused by a microstructure difference between the first differential memory and the second differential memory after the erase operation;
and determining PUF data according to the comparison value corresponding to each difference unit.
2. The method of claim 1, wherein the differential storage module comprises:
the obtained specific memory area is divided in the nonvolatile memory having the differential structure.
3. The method of claim 1, wherein including the first and second matched differential memories in the differential cell comprises:
the drain end of the first differential memory is connected with a first PMOS tube;
the drain end of the second differential memory is connected with a second PMOS tube;
the first differential memory is connected with the first input end of the comparator corresponding to the differential unit;
and the second differential memory is connected with the second input end of the comparator corresponding to the differential unit.
4. The method of claim 3, wherein determining the comparison value of the first differential memory and the second differential memory after the erase operation by using the comparator corresponding to the differential cell comprises:
the comparator outputs a random number value based on the microstructure difference of the first differential memory and the second differential memory;
determining the random number value as the comparison number value.
5. The method of claim 1, wherein determining PUF data based on the comparison value for each of the difference cells comprises:
arranging the comparison numerical values corresponding to the differential units into random number sequences;
determining the random number sequence as the PUF data.
6. The method of claim 1~5, further comprising:
and backing up the PUF data to a local storage medium and an external storage medium.
7. The method of claim 6, further comprising:
performing encryption calculation on the original data in the local storage medium by utilizing the PUF data to determine encrypted data;
and transmitting the encrypted data to the external storage medium so that the external storage medium performs decryption calculation on the encrypted data by using the PUF data.
8. An apparatus for generating PUF, wherein the apparatus is disposed in a differential storage module, the differential storage module comprises a plurality of differential units, each of the differential units comprises a first differential memory and a second differential memory which are matched; the device comprises:
an erasing module, configured to perform an erasing operation on the first differential memory and the second differential memory in each differential unit;
the comparison data determining module is used for determining a comparison value of the first differential memory and the second differential memory after the erasing operation by using the comparator corresponding to the differential unit; the comparison value is based on a potential inconsistency caused by a microstructure difference between the first differential memory and the second differential memory after the erase operation;
and the PUF data determining module is used for determining the PUF data according to the comparison numerical value corresponding to each difference unit.
9. The apparatus of claim 8, further comprising:
the backup module is used for backing up the PUF data to a local storage medium and an external storage medium;
and the encryption module is used for carrying out encryption calculation on the original data in the local storage medium by utilizing the PUF data so as to determine encrypted data.
10. A computer-readable storage medium, in which a computer program is stored, the computer program being adapted to perform the method of generating a PUF according to any one of claims 1 to 7.
11. An electronic device, the electronic device comprising:
a processor;
a memory for storing the processor-executable instructions;
the processor is configured to read the executable instructions from the memory and execute the instructions to implement the PUF generation method according to any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211064981.7A CN115130152B (en) | 2022-09-01 | 2022-09-01 | Method and device for generating physical unclonable function |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211064981.7A CN115130152B (en) | 2022-09-01 | 2022-09-01 | Method and device for generating physical unclonable function |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115130152A CN115130152A (en) | 2022-09-30 |
| CN115130152B true CN115130152B (en) | 2022-11-18 |
Family
ID=83386940
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211064981.7A Active CN115130152B (en) | 2022-09-01 | 2022-09-01 | Method and device for generating physical unclonable function |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115130152B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105760785A (en) * | 2016-01-24 | 2016-07-13 | 深圳大学 | Physical no-cloning chip circuit based on time domain differential current measurement |
| CN106295408A (en) * | 2011-02-15 | 2017-01-04 | Ictk有限公司 | Integrated circuit and encryption method |
| CN111613255A (en) * | 2019-02-22 | 2020-09-01 | 意法半导体(鲁塞)公司 | Device with physical unclonable function of floating gate transistor and manufacturing method thereof |
| US11366604B1 (en) * | 2021-02-19 | 2022-06-21 | United Microelectronics Corp. | Method of operating physically unclonable function circuit, physically unclonable function circuit and semiconductor chip |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109472169A (en) * | 2017-09-08 | 2019-03-15 | 中电海康集团有限公司 | A kind of the physics unclonable function generation method and device of MRAM chip |
| US10534554B2 (en) * | 2017-10-13 | 2020-01-14 | Silicon Storage Technology, Inc. | Anti-hacking mechanisms for flash memory device |
| US11416416B2 (en) * | 2019-01-13 | 2022-08-16 | Ememory Technology Inc. | Random code generator with non-volatile memory |
-
2022
- 2022-09-01 CN CN202211064981.7A patent/CN115130152B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106295408A (en) * | 2011-02-15 | 2017-01-04 | Ictk有限公司 | Integrated circuit and encryption method |
| CN105760785A (en) * | 2016-01-24 | 2016-07-13 | 深圳大学 | Physical no-cloning chip circuit based on time domain differential current measurement |
| CN111613255A (en) * | 2019-02-22 | 2020-09-01 | 意法半导体(鲁塞)公司 | Device with physical unclonable function of floating gate transistor and manufacturing method thereof |
| US11366604B1 (en) * | 2021-02-19 | 2022-06-21 | United Microelectronics Corp. | Method of operating physically unclonable function circuit, physically unclonable function circuit and semiconductor chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115130152A (en) | 2022-09-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US12068038B2 (en) | Method and apparatus for PUF generator characterization | |
| US11190365B2 (en) | Method and apparatus for PUF generator characterization | |
| US7945791B2 (en) | Protected storage of a datum in an integrated circuit | |
| Maes et al. | Intrinsic PUFs from flip-flops on reconfigurable devices | |
| Tehranipoor et al. | Robust hardware true random number generators using DRAM remanence effects | |
| US10574469B1 (en) | Physically unclonable function and method for generating a digital code | |
| CN110928522B (en) | Random bit circuit and method of operating a random bit circuit | |
| CN110366838B (en) | Random number generator including physically unclonable circuit | |
| KR102010454B1 (en) | Scan flip-flop, method thereof and device including the same | |
| Barbareschi et al. | Testing 90 nm microcontroller SRAM PUF quality | |
| US11321459B2 (en) | Method, system and apparatus for error correction coding embedded in physically unclonable function arrays | |
| US11294639B2 (en) | Native ternary random numbers generation | |
| Cao et al. | An energy-efficient current-starved inverter based strong physical unclonable function with enhanced temperature stability | |
| US9276609B2 (en) | Systems and methods for soft decision generation in a solid state memory system | |
| US20200052893A1 (en) | System to generate a signature key and method of operating the same | |
| CN115130152B (en) | Method and device for generating physical unclonable function | |
| Serrano et al. | A unified NVRAM and TRNG in standard CMOS technology | |
| Shamsoshoara | Ring oscillator and its application as physical unclonable function (puf) for password management | |
| JP2017191627A (en) | Nonvolatile memory device and integrated circuit card | |
| CN117010032B (en) | SRAM physical unclonable function circuit capable of automatically reading and clearing and equipment | |
| US9385696B1 (en) | Generating a pulse clock signal based on a first clock signal and a second clock signal | |
| KR101580196B1 (en) | Flash memory apparatus for physical unclonable function and embodying method of the same | |
| US11568114B2 (en) | All-digital camouflage circuit | |
| US20070220074A1 (en) | Sharing of a logic operator having a work register | |
| US7499342B2 (en) | Dynamic module output device and method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |