CN103838546A - Chaos true random number generation circuit and method - Google Patents
Chaos true random number generation circuit and method Download PDFInfo
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- CN103838546A CN103838546A CN201410058843.7A CN201410058843A CN103838546A CN 103838546 A CN103838546 A CN 103838546A CN 201410058843 A CN201410058843 A CN 201410058843A CN 103838546 A CN103838546 A CN 103838546A
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Abstract
The invention provides a chaos true random number generation circuit and method. The chaos true random number generation circuit comprises a first / second subtracter; the first / second subtracter is used for outputting an input difference between a first / second loop current value and a reference current value to a second / first chaos loop; the first chaos loop multiplies the difference between the second loop current value and the reference current value by k, and the product serves as the first loop current value; the first loop current value is output to the first subtracter when the first loop current value is larger than the reference current value, the difference between the reference current value and the first loop current value is multiplied by k when the first loop current value is not larger than the reference current value, and the product serves as a new first loop current value; the second chaos loop multiplies the difference between the first loop current value and the reference current value by k and changes a current direction into an opposite direction, and the product serves as the second loop current value; the second loop current value is output to the second subtracter when the second loop current value is larger than the reference current value, the difference between the reference current value and the second loop current value is multiplied by k when the second loop current value is not larger than the reference current value, and the product serves as a new second loop current value after the current direction is changed into the opposite direction.
Description
Technical field
The present invention relates to electronic applications, relate in particular to a kind of chaos true random number circuit for generating and method for generation.
Background technology
Chaos is a kind of definite similar random phenomenon of nonlinear dynamic system, due to the extreme sensitivity of Chaos dynamic system to starting condition and chaotic parameter, and can produce a large amount of continuous wide band frequency spectrums non-periodic, similar noise and determine reproducible chaotic signal, thereby be specially adapted to real random number generator.
Real random number generator has a wide range of applications in fields such as information security, remote measuring and controlling, digital communication and cryptographies, it is an extremely important fundamental research that concerns information security strategy, in recent years the demand of the high performance real random number generator of high-quality is grown with each passing day, this research field is subject to domestic and international research institution and scholar's extensive concern.
The prior art scheme that realizes chaos random number has a lot, mainly comprises and utilizes switched capacitor technique, analog to digital conversion circuit technology and switched current technique etc.
Utilize switching current to realize chaos random number circuit than other technology, easier circuit is realized, also more outstanding in the advantage that reduces the aspect switched current techniques such as imbalance, mismatch, non-ideal factor in addition, switched current technique is often realized by fully differential structure, so all larger on circuit scale, current drain.
Summary of the invention
The technical problem to be solved in the present invention is how in the situation that circuit scale is relatively little, to reduce the current drain of chaos true random number circuit for generating, promotes randomness and reliability.
In order to address the above problem, the invention provides a kind of chaos true random number circuit for generating, comprising:
The first chaos loop, the second chaos loop, the first subtracter, the second subtracter;
Described the first subtracter is for exporting to described the second chaos loop by the first loop current value of input and the difference of reference current value;
Described the second subtracter is for exporting to described the first chaos loop by the second loop current value of input and the difference of described reference current value;
Described the first chaos loop is in the time receiving the difference of described the second loop current value and described reference current value, after this difference is multiplied by k as described the first loop current value; In the time that described the first loop current value is greater than described reference current value, described the first loop current value is exported to described the first subtracter; In the time that described the first loop current value is not more than described reference current value, after the difference of described reference current value and described the first loop current value is multiplied by k as new described the first loop current value;
Described the second chaos loop for when receive the difference of described the first loop current value and described reference current value, is multiplied by k by this difference, and using direction of current change into and originally on the contrary after as described the second loop current; In the time that described the second loop current value is greater than described reference current value, described the second loop current value is exported to described the second subtracter; In the time that described the second loop current value is not more than described reference current value, the difference of described reference current value and described the second loop current value is multiplied by k, and using direction of current change into and original contrary after as new described the second loop current value;
Wherein, k is current ratio coefficient.
Alternatively, k, between 1.75 to 2, does not comprise 1.75 and 2.
Alternatively, described the first chaos loop comprises:
The first comparer, the 3rd subtracter and the first multiplier;
Described the first multiplier for exporting to described the first comparer as described the first loop current value after the current value of input is multiplied by k;
Described the first comparer is used for judging whether described the first loop current value is greater than described reference current value; If be greater than, described the first loop current value is exported to described the first subtracter; If be not more than, described the first loop current value is exported to described the 3rd subtracter;
Described the 3rd subtracter is for exporting to described the first multiplier by described reference current and the difference of described the first loop current value of inputting;
Described the second chaos loop comprises:
The second comparer, the 4th subtracter and the second multiplier;
Described the second multiplier is for being multiplied by k by the current value of input, and direction of current is changed into and originally exports to described the second comparer as described the second loop current value after contrary;
Described the second comparer is used for judging whether described the second loop current value is greater than described reference current value; If be greater than, described the second loop current value is exported to described the first subtracter; If be not more than, described the second loop current value is exported to described the 4th subtracter;
Described the 4th subtracter is for exporting to described the second multiplier by described reference current and the difference of described the second loop current value of inputting.
Alternatively, described circuit also comprises:
For exporting the first not overlapping clock signal and the control module of second clock signal;
Described the first subtracter is N-type metal-oxide-semiconductor, and source electrode connects low level; Described the second subtracter is P type metal-oxide-semiconductor, and source electrode connects high level, and drain electrode connects the drain electrode of described the first subtracter;
Described the first chaos circuit comprises:
The first metal-oxide-semiconductor and the second metal-oxide-semiconductor, be P type metal-oxide-semiconductor, and source electrode all connects high level, and grid connects respectively described the first clock signal; The drain and gate of the second metal-oxide-semiconductor is connected;
The 3rd metal-oxide-semiconductor and the 4th metal-oxide-semiconductor, be N-type metal-oxide-semiconductor, and source electrode all connects low level, and grid connects respectively described second clock signal; The grid of the 4th metal-oxide-semiconductor connects the grid of described the first subtracter; The grid of the 3rd metal-oxide-semiconductor is connected with drain electrode, and connects the drain electrode of described the first metal-oxide-semiconductor;
The first switch, comprises first end and the second end;
Second switch, comprises first end and the second end;
For generation of the first current source of reference current, one end connects high level, and one end connects the first end of described the first switch and described second switch;
The second end of described second switch is connected with the grid of described the second metal-oxide-semiconductor; First end is also connected with the drain electrode of described the 4th metal-oxide-semiconductor;
Described the second chaos circuit comprises:
The 5th metal-oxide-semiconductor and the 6th metal-oxide-semiconductor, be P type metal-oxide-semiconductor, and source electrode all connects high level, and grid connects respectively described the first clock signal; The grid of described the 6th metal-oxide-semiconductor is connected with drain electrode, and the grid of described the 5th metal-oxide-semiconductor is connected with the grid of described the second subtracter;
The 7th metal-oxide-semiconductor and the 8th metal-oxide-semiconductor, be N-type metal-oxide-semiconductor, and source electrode all connects low level, and grid connects respectively described second clock signal; The drain electrode of described the 7th metal-oxide-semiconductor is connected with grid; The drain electrode of described the 8th metal-oxide-semiconductor is connected with the drain electrode of described the 6th metal-oxide-semiconductor;
The 3rd switch, comprises first end and the second end;
The 4th switch, comprises first end and the second end;
For generation of the second current source of reference current, one end connects low level, and one end connects the first end of described the 3rd switch and described the 4th switch;
The second end of described the 4th switch is connected with the second end of second switch; First end is also connected with the drain electrode of described the 5th metal-oxide-semiconductor;
The second end of described the 3rd switch is connected with the second end of described the first switch, and is connected on the grid of described the 7th metal-oxide-semiconductor.
Alternatively, described control module also, in the time that the drain current value of described the 4th metal-oxide-semiconductor is less than reference current value, by described the first switch conduction, opens circuit described second switch; In the time that the drain current value of described the 4th metal-oxide-semiconductor is greater than reference current value, described the first switch is opened circuit, by described second switch conducting; In the time that the drain current value of described the 5th metal-oxide-semiconductor is less than reference current value, by described the 4th switch conduction, described the 3rd switch is opened circuit; In the time that the drain current value of described the 5th metal-oxide-semiconductor is greater than reference current value, described the 4th switch is opened circuit, by described the 3rd switch conduction.
The present invention also provides a kind of chaos true random number method for generation, is applied in the circuit as described in claim 1～5 any one, comprising:
Relatively the first loop current value and reference current value in the first chaos loop; If described the first loop current value is greater than described reference current value, the difference of described the first loop current value and described reference current value is inputed to the second chaos loop; If described the first loop current value is not more than described reference current value, after the difference of described reference current value and described the first loop current value is multiplied by k as new described the first loop current value; K is current ratio coefficient;
Described the second chaos loop, in the time receiving the difference of described the first loop current value and described reference current value, is multiplied by k by this difference, and using direction of current change into and original contrary after as described the second loop current;
More described the second loop current value and described reference current value, if described the second loop current value is greater than described reference current value, input to the first chaos loop by the difference of described the second loop current value and described reference current value; If described the first loop current value is not more than described reference current value, the difference of described reference current value and described the second loop current value is multiplied by k, and using direction of current change into and original contrary after as new described the second loop current value;
Described the first chaos loop, in the time receiving the difference of described the second loop current value and described reference current value, is multiplied by k by this difference, and using direction of current change into and original contrary after as described the first loop current.
Alternatively, k, between 1.75 to 2, does not comprise 1.75 and 2.
The present invention adopts a kind of novel topological structure to realize chaos true random number circuit for generating, and it is two independent chaos loops that fully differential structure is disassembled, and precisely realizes separately difference and the multiply operation of electric current by circuit structure optimization; Compare existing structure, structure is more simple, but reliability gets a promotion.Because the each branch road of whole circuit does not have current offset, current drain only has dynamic consumption, and therefore current drain is effectively reduced.
Brief description of the drawings
Fig. 1 is the principle schematic of the chaos true random number circuit for generating of embodiment mono-;
Fig. 2 is the circuit diagram in a kind of embodiment of embodiment mono-;
Fig. 3 is the sequential schematic diagram that drives clock and switch on and off in embodiment mono-.
Embodiment
Below in conjunction with drawings and Examples, technical scheme of the present invention is described in detail.
It should be noted that, if do not conflicted, each feature in the embodiment of the present invention and embodiment can mutually combine, all within protection scope of the present invention.In addition, although there is shown logical order in flow process, in some cases, can carry out shown or described step with the order being different from herein.
Embodiment mono-, a kind of chaos true random number circuit for generating, comprising:
The first chaos loop, the second chaos loop, the first subtracter, the second subtracter;
Described the first subtracter is for exporting to described the second chaos loop by the first loop current value of input and the difference of reference current value;
Described the second subtracter is for exporting to described the first chaos loop by the second loop current value of input and the difference of described reference current value;
Described the first chaos loop is in the time receiving the difference of described the second loop current value and described reference current value, after this difference is multiplied by k as described the first loop current value; In the time that described the first loop current value is greater than described reference current value, described the first loop current value is exported to described the first subtracter; In the time that described the first loop current value is not more than described reference current value, after the difference of described reference current value and described the first loop current value is multiplied by k as new described the first loop current value;
Described the second chaos loop for when receive the difference of described the first loop current value and described reference current value, is multiplied by k by this difference, and using direction of current change into and originally on the contrary after as described the second loop current; In the time that described the second loop current value is greater than described reference current value, described the second loop current value is exported to described the second subtracter; In the time that described the second loop current value is not more than described reference current value, the difference of described reference current value and described the second loop current value is multiplied by k, and using direction of current change into and original contrary after as new described the second loop current value;
Wherein, k is current ratio coefficient.
In the present embodiment, described reference current value and current ratio coefficient can be based on experience value or test findings arrange.
The chaos math equation of piecewise linear function is as follows:
x[n+1]=k*x[n]+b,if?x[n]<0
x[n+1]=k*x[n]－b,if?x[n]>=0
In an embodiment of the present embodiment, wherein x[] be variable, n is the serial number for representing this variable, such as x[n+1] be x[n] after variable once, represent in the present embodiment the described first or second loop current value; B is constant, represents in the present embodiment described reference current value; The span of k is 1～2, does not comprise 1,2; X[n in this embodiment] to initial value x[0] be very responsive, x[0] thus ring decided by border temperature, noise, technique device aging, various interference. x[0] be highstrung. slope k is for the height impact of randomness significantly, k value more approaches 2, random quality is higher, but designing requirement is higher, and difficulty is larger, k value more approaches 1, random quality is lower, but designing requirement is lower, and difficulty is less.
In a kind of alternatives of present embodiment, k, between 1.75 to 2, does not comprise 1.75 and 2.In other alternatives, k also can be taken as other value as required.
Fig. 1 is the schematic flow sheet of the chaos true random number circuit for generating work of the present embodiment, can find out from this flow process, whole circulation comprises the first chaos loop LOOPA and two loops of the second chaos loop LOOPB, they do not exist separately initial and finish, only have in loop when electric current is greater than reference current, just can spill into another loop.It is emphasized that, for avoiding interfering with each other, two loops can not be worked simultaneously, along with the moment of the action that powers on, circuit random start is in the possible any stage of this flow process, this randomness is decided by the enchancement factors such as environment temperature, noise, technique device aging, the extreme sensitivity to starting condition and chaotic parameter according to chaos structure in addition, for example, even if determine that any action that powers on for twice exists very faint difference (: skin ampere) also can occur in the least irregular non-periodic of chaos after iteration repeatedly.
In an embodiment of the present embodiment, described the first chaos loop comprises:
The first comparer, the 3rd subtracter and the first multiplier;
Described the first multiplier for exporting to described the first comparer as described the first loop current value after the current value of input is multiplied by k;
Described the first comparer is used for judging whether described the first loop current value is greater than described reference current value; If be greater than, described the first loop current value is exported to described the first subtracter; If be not more than, described the first loop current value is exported to described the 3rd subtracter;
Described the 3rd subtracter is for exporting to described the first multiplier by described reference current value and the difference of described the first loop current value of inputting.
In present embodiment, described the second chaos loop comprises:
The second comparer, the 4th subtracter and the second multiplier;
Described the second multiplier is for being multiplied by k by the current value of input, and direction of current is changed into and originally exports to described the second comparer as described the second loop current value after contrary;
Described the second comparer is used for judging whether described the second loop current value is greater than described reference current value; If be greater than, described the second loop current value is exported to described the first subtracter; If be not more than, described the second loop current value is exported to described the 4th subtracter;
Described the 4th subtracter is for exporting to described the second multiplier by described reference current value and the difference of described the second loop current value of inputting.
In an embodiment of the present embodiment, as shown in Figure 2, described circuit can also comprise:
For exporting the control module of not overlapping the first clock signal pai1 and second clock signal pai2;
Described the first subtracter is N-type metal-oxide-semiconductor N0, and source electrode connects low level; Described the second subtracter is P type metal-oxide-semiconductor P0, and source electrode connects high level, and drain electrode connects the drain electrode of N0, as the port out of output true random number;
Described the first chaos circuit specifically can comprise:
The first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2; M1, M2 is P type metal-oxide-semiconductor, and source electrode all connects high level, and grid connects respectively described the first clock signal pai1; The drain and gate of M2 is connected;
The 3rd metal-oxide-semiconductor M3 and the 4th metal-oxide-semiconductor M4; M3, M4 are N-type metal-oxide-semiconductor, and source electrode all connects low level, and grid connects respectively described second clock signal pai2; The grid of M4 connects the grid of described N0; The grid of M3 is connected with drain electrode, and connects the drain electrode of described M1;
The first switch S 1, comprises first end and the second end;
Second switch S2, comprises first end and the second end;
For generation of the first current source I1 of reference current, one end connects high level, and one end connects the first end of described the first switch S 1 and described second switch S2;
The second end of described second switch S2 is connected with the grid of described M2; First end is also connected with the drain electrode of described M4;
Described the second chaos circuit specifically can comprise:
The 5th metal-oxide-semiconductor M5 and the 6th metal-oxide-semiconductor M6; M5, M6 is P type metal-oxide-semiconductor, and source electrode all connects high level, and grid connects respectively described the first clock signal pai1; The grid of M6 is connected with drain electrode, and the grid of M5 is connected with the grid of described P0;
The 7th metal-oxide-semiconductor M7 and the 8th metal-oxide-semiconductor M8; M7, M8 are N-type metal-oxide-semiconductor, and source electrode all connects low level, and grid connects respectively described second clock signal pai2; The drain electrode of M7 is connected with grid; The drain electrode of M8 is connected with the drain electrode of M6;
The 3rd switch S 3, comprises first end and the second end;
The 4th switch S 4, comprises first end and the second end;
For generation of the second current source I2 of reference current, one end connects low level, and one end connects the first end of described the 3rd switch S 3 and described the 4th switch S 4;
The second end of described the 4th switch S 4 is connected with the second end of second switch S2; First end is also connected with the drain electrode of described M5;
The second end of described the 3rd switch S 3 is connected with the second end of described the first switch S 1, and is connected on the grid of described M7.
Described control module is also for controlling the break-make of S1, S2, S3, S4.
In present embodiment, powering on of circuit makes this circuit enter at random a certain link, may be any loop of LOOPA or LOOPB.
Analyze as an example of LOOPA example, under the driving of not overlapping clock signal pai1 and pai2, if pai1 is high level, pai2 is low level, M1 and M2(or M5 and M6) the P type current mirror circuit that forms opens circuit, and the gate capacitance current potential of the drain current value of M1 when opening circuit determines, M3 and M4(or M7 and M8) form N-type current mirror circuit can normally work, the drain current of M4 is k times of M3, and the drain current value of M4 and reference current Iref do subtraction operation simultaneously, has two kinds of possibilities:
A, M4 drain current value I(M4) be greater than reference current value Iref, now described control module is by S1 conducting, and S2 opens circuit, and electric current difference Iref-I (M4) overflows, and enters LOOPB loop;
B, M4 drain current are not more than Iref, and now described control module opens circuit S1, S2 conducting, and electric current difference I (M4)-Iref continues at LOOPA loop.
When pai1 is low level, pai2 is high level, M1 and M2(or M5 and M6) form P type current mirror circuit normal, the drain current value of M1 is determined by M2, M3 and M4(or M7 and M8) form N-type current mirror circuit open circuit, the gate capacitance current potential when drain current of M4 is opened circuit by switch determines.
That is to say LOOPA(or LOOPB) by S1(or S4) realize and overflowing, S2(or S3) realize self-loopa.
For LOOPB, principle is identical with LOOPA, forms mutual symmetry loop; Accordingly, described control module, according to the drain current value of M5 and the magnitude relationship of reference current value, is controlled the break-make of S3 and S4; Two loops under the driving of not overlapping clock signal pai1 and pai2, alternation.So far, the principle of work of chaos true random source is explained complete.
Work schedule and S1 and S2(or S3 and the S4 of neither overlapping clock pai1 and pai2 below) switch conduction and the sequencing of cut-off, as shown in Figure 3:
(P type current mirror and N-type current mirror joint conference cause that current value is uncertain in the current mirror while conducting forming for fear of the current mirror of M1 and M2 composition and M3 and M4, cause randomness to reduce), adopt not overlapping clock pai1 and pai2 to control difference conducting and the cut-off of N-type and P type current mirror; Described N-type and P type current mirror circuit can be realized ratio multiplication and subtraction.
For S1 and S2(or S3 and S4), for avoiding two switches to occur the situation of conducting simultaneously, while needing S1 to be opened circuit by conducting change, S2 must be again by the change conducting of opening circuit after S1 action, same is also like this for S2, when S2 is opened circuit by conducting change, S1 must be again by the change conducting of opening circuit after S2 action.Switch S 1 and S2, under the pai1 of overlapping clock not and pai2 drive, control in the mode of short circuit after first opening circuit.
The present embodiment is not limited to adopt the circuit in Fig. 2 to realize, and can realize the present embodiment as long as possess circuit or the chip of identical function.
Embodiment bis-, a kind of chaos true random number method for generation, is applied in the circuit as described in claim 1～5 any one, comprising:
Relatively the first loop current value and reference current value in the first chaos loop; If described the first loop current value is greater than described reference current value, the difference of described the first loop current value and described reference current value is inputed to the second chaos loop; If described the first loop current value is not more than described reference current value, after the difference of described reference current value and described the first loop current value is multiplied by k as new described the first loop current value; K is current ratio coefficient;
Described the second chaos loop, in the time receiving the difference of described the first loop current value and described reference current value, is multiplied by k by this difference, and using direction of current change into and original contrary after as described the second loop current;
More described the second loop current value and described reference current value, if described the second loop current value is greater than described reference current value, input to the first chaos loop by the difference of described the second loop current value and described reference current value; If described the first loop current value is not more than described reference current value, the difference of described reference current value and described the second loop current value is multiplied by k, and using direction of current change into and original contrary after as new described the second loop current value;
Described the first chaos loop, in the time receiving the difference of described the second loop current value and described reference current value, is multiplied by k by this difference, and using direction of current change into and original contrary after as described the first loop current.
In an embodiment of the present embodiment, k, between 1.75 to 2, does not comprise 1.75 and 2.
Certainly; the present invention also can have other various embodiments; in the situation that not deviating from spirit of the present invention and essence thereof; those of ordinary skill in the art are when making according to the present invention various corresponding changes and distortion, but these corresponding changes and distortion all should belong to the protection domain of claim of the present invention.
Claims (7)
1. a chaos true random number circuit for generating, is characterized in that, comprising:
The first chaos loop, the second chaos loop, the first subtracter, the second subtracter;
Described the first subtracter is for exporting to described the second chaos loop by the first loop current value of input and the difference of reference current value;
Described the second subtracter is for exporting to described the first chaos loop by the second loop current value of input and the difference of described reference current value;
Described the first chaos loop is in the time receiving the difference of described the second loop current value and described reference current value, after this difference is multiplied by k as described the first loop current value; In the time that described the first loop current value is greater than described reference current value, described the first loop current value is exported to described the first subtracter; In the time that described the first loop current value is not more than described reference current value, after the difference of described reference current value and described the first loop current value is multiplied by k as new described the first loop current value;
Described the second chaos loop for when receive the difference of described the first loop current value and described reference current value, is multiplied by k by this difference, and using direction of current change into and originally on the contrary after as described the second loop current; In the time that described the second loop current value is greater than described reference current value, described the second loop current value is exported to described the second subtracter; In the time that described the second loop current value is not more than described reference current value, the difference of described reference current value and described the second loop current value is multiplied by k, and using direction of current change into and original contrary after as new described the second loop current value;
Wherein, k is current ratio coefficient.
2. circuit as claimed in claim 1, is characterized in that:
K, between 1.75 to 2, does not comprise 1.75 and 2.
3. circuit as claimed in claim 1 or 2, is characterized in that, described the first chaos loop comprises:
The first comparer, the 3rd subtracter and the first multiplier;
Described the first multiplier for exporting to described the first comparer as described the first loop current value after the current value of input is multiplied by k;
Described the first comparer is used for judging whether described the first loop current value is greater than described reference current value; If be greater than, described the first loop current value is exported to described the first subtracter; If be not more than, described the first loop current value is exported to described the 3rd subtracter;
Described the 3rd subtracter is for exporting to described the first multiplier by described reference current and the difference of described the first loop current value of inputting;
Described the second chaos loop comprises:
The second comparer, the 4th subtracter and the second multiplier;
Described the second multiplier is for being multiplied by k by the current value of input, and direction of current is changed into and originally exports to described the second comparer as described the second loop current value after contrary;
Described the second comparer is used for judging whether described the second loop current value is greater than described reference current value; If be greater than, described the second loop current value is exported to described the first subtracter; If be not more than, described the second loop current value is exported to described the 4th subtracter;
Described the 4th subtracter is for exporting to described the second multiplier by described reference current and the difference of described the second loop current value of inputting.
4. circuit as claimed in claim 1 or 2, is characterized in that, also comprises:
For exporting the first not overlapping clock signal and the control module of second clock signal;
Described the first subtracter is N-type metal-oxide-semiconductor, and source electrode connects low level; Described the second subtracter is P type metal-oxide-semiconductor, and source electrode connects high level, and drain electrode connects the drain electrode of described the first subtracter;
Described the first chaos circuit comprises:
The first metal-oxide-semiconductor and the second metal-oxide-semiconductor, be P type metal-oxide-semiconductor, and source electrode all connects high level, and grid connects respectively described the first clock signal; The drain and gate of the second metal-oxide-semiconductor is connected;
The 3rd metal-oxide-semiconductor and the 4th metal-oxide-semiconductor, be N-type metal-oxide-semiconductor, and source electrode all connects low level, and grid connects respectively described second clock signal; The grid of the 4th metal-oxide-semiconductor connects the grid of described the first subtracter; The grid of the 3rd metal-oxide-semiconductor is connected with drain electrode, and connects the drain electrode of described the first metal-oxide-semiconductor;
The first switch, comprises first end and the second end;
Second switch, comprises first end and the second end;
For generation of the first current source of reference current, one end connects high level, and one end connects the first end of described the first switch and described second switch;
The second end of described second switch is connected with the grid of described the second metal-oxide-semiconductor; First end is also connected with the drain electrode of described the 4th metal-oxide-semiconductor;
Described the second chaos circuit comprises:
The 5th metal-oxide-semiconductor and the 6th metal-oxide-semiconductor, be P type metal-oxide-semiconductor, and source electrode all connects high level, and grid connects respectively described the first clock signal; The grid of described the 6th metal-oxide-semiconductor is connected with drain electrode, and the grid of described the 5th metal-oxide-semiconductor is connected with the grid of described the second subtracter;
The 7th metal-oxide-semiconductor and the 8th metal-oxide-semiconductor, be N-type metal-oxide-semiconductor, and source electrode all connects low level, and grid connects respectively described second clock signal; The drain electrode of described the 7th metal-oxide-semiconductor is connected with grid; The drain electrode of described the 8th metal-oxide-semiconductor is connected with the drain electrode of described the 6th metal-oxide-semiconductor;
The 3rd switch, comprises first end and the second end;
The 4th switch, comprises first end and the second end;
For generation of the second current source of reference current, one end connects low level, and one end connects the first end of described the 3rd switch and described the 4th switch;
The second end of described the 4th switch is connected with the second end of second switch; First end is also connected with the drain electrode of described the 5th metal-oxide-semiconductor;
The second end of described the 3rd switch is connected with the second end of described the first switch, and is connected on the grid of described the 7th metal-oxide-semiconductor.
5. circuit as claimed in claim 4, is characterized in that:
Described control module also, in the time that the drain current value of described the 4th metal-oxide-semiconductor is less than reference current value, by described the first switch conduction, opens circuit described second switch; In the time that the drain current value of described the 4th metal-oxide-semiconductor is greater than reference current value, described the first switch is opened circuit, by described second switch conducting; In the time that the drain current value of described the 5th metal-oxide-semiconductor is less than reference current value, by described the 4th switch conduction, described the 3rd switch is opened circuit; In the time that the drain current value of described the 5th metal-oxide-semiconductor is greater than reference current value, described the 4th switch is opened circuit, by described the 3rd switch conduction.
6. a chaos true random number method for generation, is applied in the circuit as described in claim 1～5 any one, comprising:
Relatively the first loop current value and reference current value in the first chaos loop; If described the first loop current value is greater than described reference current value, the difference of described the first loop current value and described reference current value is inputed to the second chaos loop; If described the first loop current value is not more than described reference current value, after the difference of described reference current value and described the first loop current value is multiplied by k as new described the first loop current value; K is current ratio coefficient;
Described the second chaos loop, in the time receiving the difference of described the first loop current value and described reference current value, is multiplied by k by this difference, and using direction of current change into and original contrary after as described the second loop current;
More described the second loop current value and described reference current value, if described the second loop current value is greater than described reference current value, input to the first chaos loop by the difference of described the second loop current value and described reference current value; If described the first loop current value is not more than described reference current value, the difference of described reference current value and described the second loop current value is multiplied by k, and using direction of current change into and original contrary after as new described the second loop current value;
Described the first chaos loop, in the time receiving the difference of described the second loop current value and described reference current value, is multiplied by k by this difference, and using direction of current change into and original contrary after as described the first loop current.
7. method as claimed in claim 6, is characterized in that:
K, between 1.75 to 2, does not comprise 1.75 and 2.
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