CN105760785A - Physical no-cloning chip circuit based on time domain differential current measurement - Google Patents

Physical no-cloning chip circuit based on time domain differential current measurement Download PDF

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CN105760785A
CN105760785A CN201610045830.5A CN201610045830A CN105760785A CN 105760785 A CN105760785 A CN 105760785A CN 201610045830 A CN201610045830 A CN 201610045830A CN 105760785 A CN105760785 A CN 105760785A
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circuit
current
drain electrode
nmos
row
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CN105760785B (en
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赵晓锦
林仕傍
梁德健
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Shenzhen University
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/73—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by creating or determining hardware identification, e.g. serial numbers

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  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
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Abstract

The invention discloses a physical no-cloning chip circuit based on time domain differential current measurement.The physical no-cloning chip circuit comprises two current mirror array circuits, two current mirror circuits and a current comparator circuit.The output currents of the two current mirror array circuits are input into the first current mirror circuit and the second current mirror circuit respectively.A first sub-current generated by the first current mirror circuit and a first sub-current generated by the second current mirror circuit are input into the current comparator circuit, and the current comparator circuit compares the two sub-currents and then outputs a binary ID digit; an ID sequence is obtained after the binary ID digit is output and processed by selecting unit circuits of the current mirror array circuits many times, and the ID sequence serves as identity recognition information of a chip.The physical no-cloning chip circuit has the advantages that the chip is small in area, low in power consumption, high in reliability and low in cost, and the physical no-cloning chip circuit can be widely applied to the circuit industry with high reliability requirements and low power budget.

Description

A kind of unclonable chip circuit of the physics based on time-domain difference current measurement
[technical field]
The present invention relates to information security field, particularly relate to a kind of unclonable chip circuit of the physics based on time-domain difference current measurement.
[background technology]
The unclonable function of physics (PhysicalUnclonableFunction:PUF) refers to and a physical entity is inputted an excitation, utilize the random difference of its inevitable inherent physique, export a such a function of uncertain random response.The most basic application of PUF is to realize certification by unique mark of entity, later along with people are to its deep understanding, it is proposed that the PUF of increasing new type realizes method, as based on the PUF of moderator, butterfly PUF, ring oscillator PUF etc..Method is realized based on these; PUF circuit has been applied to more security fields gradually; key such as public key encryption system generates, secrete key of smart card identification system, radio-frequency recognition system (RadioFrequencyIdentification, RFID) and relevant knowledge property right protection etc..Meanwhile, the mode realized according to integrated circuit is classified, and it can be divided into again the unclonable chip of pure digi-tal physics (numeral PUF chip) and the unclonable chip of numerical model analysis physics (numerical model analysis PUF chip).
Document [6] proposes a kind of PUF circuit based on arbitration mechanism, obtains output response by comparing the delay of two paths.This circuit is made up of delay circuit and arbitration two parts of diagnosis apparatus, delay circuit has 64 inputs, the trend of upper and lower two paths is determined by every input " 0 " or " 1 ", have combination of paths 264 kinds different, moderator is for judging the priority that upper and lower Liang Tiao road strength signal arrives, and correspondence exports " 1 " or " 0 ".Such as a rising signals is propagated respectively through upper and lower two paths, if upper path first propagates arbitration, then output response is " 1 ", otherwise output response is " 0 ".So through inputting a series of rise and fall signal, a string corresponding response binary sequence just can be obtained.Owing to moderator needs the time of setting up, so causing the stability of this circuit not high, although the stability of circuit can be improved by introducing the correcting circuit of complexity, but but make the power consumption of circuit and the area of chip significantly increase.
Document [7] proposes a PUF circuit based on cross-coupled circuit that can be applicable to FPGA.This PUF circuit make use of cross-coupled circuit to there are " 0 " or " 1 " two steady statues due to the existence of positive feedback circle, and an instability and be prone to the characteristic of intermediate state changed to one of two stable states.Two latch cross-couplings form a positive feedback loop, during beginning, by controlling additional pumping signal, circuit is played pendulum, then passing through this pumping signal of change makes circuit turn to one of them of " 0 " or " 1 " two steady statues from labile state, thus obtaining the binary digit of " 0 " or " 1 ".Utilize multiple such cross-coupled circuit one array of composition, finally give the output of a string binary sequence.In changing from labile state to steady statue at cross-coupled circuit, it is highly susceptible to the uncertain factor impact of some circuits or device, so the process of this transformation is uncertain, so a string binary sequence finally given also is unpredictable, unique.But the problem that this circuit equally exists stability, it is necessary to improve stability by aided algorithm circuit.
Offer one PUF based on IGCT of [9] proposition and realize circuit.This circuit is made up of IGCT sensor circuit, time difference amplifier circuit, time difference comparator circuit, voting mechanism circuit, broadcast algorithm circuit.Adopting multiple same IGCT sensor in circuit, owing to production process makes a variation, each sensor produces two operating currents having trickle different length of delay, and operating current elapsed time differential amplifier circuit is postponed to be amplified；Time difference has compared circuit and has been really an arbiter circuit, and the priority that this circuit arrives by comparing two current signals exports response accordingly for " 1 " or " 0 "；The output of time difference comparator is responded and carries out sampling statistics by voting mechanism circuit, determining that according to sampled result the ID of output is " 1 " or " 0 ", when the number of times of sampling is sufficiently large, (in document, sampling number is 1000) can obtain a stable ID；The ID obtained is changed by broadcast algorithm circuit according to an algorithm determined so that it is meets the requirement of unified statistical distribution, improves the uniqueness of PUF circuit.This circuit has a problem in that have the bigger bit error rate, even and if increase power consumption and chip area, it is also difficult to obtain the low bit error rate of ideal.
Document [1] K.Lofstrom, W.R.DaaschandD.Taylor, " ICidentificationcircuitusingdevicemismatch, " IEEEInternationalSolid-StateCircuitsConf. (ISSCC), pp.372-373,2000.
Document [2] J.Zhang, Y.Lin, Y.LyuandG.Qu, " APUF-FSMBindingSchemeforFPGAIPProtectionandPay-Per-Devic eLicensing; " IEEETransactionsonInformationForensicsandSecurity, vol.10, no.6, pp.1137-1150,2015.
Document [3] W.Liu, Z.Zhang, M.LiandZ.Liu, " ATrustworthykeyGenerationPrototypebasedonDDR3PUFforWirel essSensorNetworks; " IEEEInternationalSymposiumonComputer, ConsumerandControl, pp.706-709,2014.
Document [4] Y.Cao, S.S.Z., L.Zhang, C.H.ChangandS.Chen, " CMOSImageSensorBasedPhysicalUnclonableFunctionforSmartPh oneSecurityApplications; " IEEEInternationalSymposiumonIntegratedCircuits, pp.392-395,2014.
Document [5] G.QuandL.Yuan, " DesignTHINGSfortheInternetofThings-AnEDAPerspective, " IEEEInternationalConferenceonComputer-AidedDesign, pp.411-416,2014.
Document [6] LangLin, S.Srivathsa, D.K.Krishnappa, P.ShabadiandW.Burleson, " DesignandvalidationofArbiter-BasedPUFsforSub-45-nmLow-Po werSecurityApplications, " IEEETransactionsonInformationForensicsandSecurity, vol.7, no.4, pp.1394-1403,2012.
Document [7] S.S.Kumar, J.Guajardo, R.Maesyz, G.-J.SchrijenandP.Tuyls, " ThebutterflyPUFprotectingIPoneveryFPGA; " IEEESym.onHardware-OrientedSecurityandTrust (HOST), pp.67-70,2008.
Document [8] Y.Su, J.HollemanandB.Otis, " A1.6pJ/bit96%StableChip-IDGeneratingCircuitusingProcessV ariation; " IEEEInternationalSolid-StateCircuitsConf. (ISSCC), pp.406-611,2007.
Document [9] C.Bai, X.ZouandK.Dai, " ANovelThyristor-BasedSiliconPhysicalUnclonableFunction, " IEEETransactionsonVeryLargeScaleIntegartion (VLSI) Systems, inpress, 2015.
Document [10] S.Stanzione, D.PuntinandG.Iannaccone, " CMOSSiliconPhysicalUnclonableFunctionsBasedonIntrinsicPr ocessVariability; " IEEEJ.Solid-StateCircuits, vol.46, no.6, pp.1456-1463,2011.
Document [11] K.Yang, Q.Dong, D.BlaauwandD.Sylvester, " APhysicallyUn-clonableFunctionwithBER < 10-8forRobustChipAuthenticationUsingOscillatorCollapsein 40nmCMOS; " IEEEInternationalSolid-StateCircuitsConf. (ISSCC), pp.254-256,2015.
Document [12] JasonH.Anderson, " APUFDesignforSecureFPGA-BasedEmbeddedSystems, " IEEEAsiaandSouthPacificDesignAutomationConference, pp.1-6,2010.
These PUF proposed in document above realize circuit, it is common to there is the such as problems such as chip area is relatively big, power dissipation ratio is higher, the PUF circuit chip area in document [9] is 21750um2, power consumption 380uw, these shortcomings limit the application in practice of PUF chip to a certain extent.
[summary of the invention]
The technical problem to be solved in the present invention is to provide the unclonable chip circuit of the physics based on time-domain difference current measurement that a kind of chip area is little, low in energy consumption.
In order to solve above-mentioned technical problem, the technical solution used in the present invention is, a kind of unclonable chip circuit of the physics based on time-domain difference current measurement, including two current lens array circuit, two current mirroring circuits and current comparator circuit, the output electric current of two current lens array circuit inputs the first current mirroring circuit and the second current mirroring circuit respectively；The first electron current and the first electron current of the second current mirroring circuit generation that first current mirroring circuit produces are separately input to current comparator circuit, after two electron currents are compared by current comparator circuit, export a binary system ID position；After repeatedly selecting the element circuit of current lens array circuit to carry out and exporting and process, obtain an ID sequence, as the identity identification information of chip.
The unclonable chip circuit of above-described physics, including time-domain difference measuring circuit, the second electron current and the second electron current of the second current mirroring circuit generation that first current mirroring circuit produces are separately input to time-domain difference measuring circuit, the second electron current and the absolute value of the second electron current difference of the second current mirroring circuit generation that first current mirroring circuit is produced by time-domain difference measuring circuit measure, the size of described absolute value is calculated by controllable counter, by the threshold ratio of described absolute value and setting relatively, a binary identification position is exported；After repeatedly selecting the element circuit of current lens array circuit to carry out and exporting and process, obtain an identifier answered with described ID sequence pair, for characterizing the reliability of described identity identification information.
The unclonable chip circuit of above-described physics, current lens array circuit includes M root row address line, row switch and M row that N root column address conductor, M row N row NMOS tube are identical with NMOS tube quantity switch, and the grid of whole NMOS tube of current lens array circuit is connected, and connects additional control voltage；The source electrode of whole NMOS tube is connected and ground connection；The drain electrode of each NMOS tube connects the input of this every trade switch by corresponding row switch；With the column address conductor controlling these row of termination of rows of switches, the control of row switch terminates the row address line of this row, and the outfan that all row switch is connected, as the outfan of current lens array circuit.
The unclonable chip circuit of above-described physics, row switch and row switch are all NMOS, the source electrode of row switch is connected with the drain electrode of corresponding NMOS tube, the grid of row switch connects the column address conductor of these row, the source electrode of this every trade switch is connect with the drain electrode of all row switches of a line, the grid of row switch connects the row address line of this row, and the drain electrode of all row switch is connected, as the outfan of current lens array circuit.
The unclonable chip circuit of above-described physics, current mirroring circuit includes three PMOS, the source electrode external power supply of three PMOS；The grid of three PMOS links together, and connects the drain electrode of the first PMOS；The drain electrode of the first PMOS of the first current mirroring circuit connects the outfan of the first current lens array circuit, and the drain electrode of the second PMOS connects the first input end of current comparator circuit, and the drain electrode of the 3rd PMOS connects the first input end of time-domain difference measuring circuit；The drain electrode of the first PMOS of the second current mirroring circuit connects the outfan of the second current lens array circuit, and the drain electrode of the second PMOS connects the second input of current comparator circuit, and the drain electrode of the 3rd PMOS connects the second input of time-domain difference measuring circuit.
The unclonable chip circuit of above-described physics, current comparator circuit includes two reset NMOS and two cross-linked NMOS, the source ground of reset NMOS and cross-couplings NMOS, the drain electrode of the first reset NMOS and the grid of the second cross-couplings NMOS connect the drain electrode of the first cross-couplings NMOS, the drain electrode of the second reset NMOS and the grid of the first cross-couplings NMOS and connect the drain electrode of the second cross-couplings NMOS；The drain electrode of two cross-couplings NMOS connects the first current mirroring circuit and the electron current of the second current mirroring circuit output respectively, the outfan that drain electrode is current comparator circuit of the first cross-couplings NMOS.
The unclonable chip circuit of above-described physics, during current comparator circuit work, the first grid input high level to two reset NMOS, make reset NMOS turn on, make two cross-couplings NMOS carry out discharge reduction by drain electrode；Then the grid input low level to two reset NMOS, makes reset NMOS turn off；Hereafter, the drain electrode of two cross-couplings NMOS inputs the first current mirroring circuit and the electron current of the second current mirroring circuit output respectively, if the electron current that the electron current of the first current mirroring circuit output exports more than the second current mirroring circuit, the drain electrode output high level of the first cross-couplings NMOS, obtains the ID position that value is " 1 "；If the electron current that exports less than the second current mirroring circuit of electron current of the first current mirroring circuit output, the drain electrode output low level of the first cross-couplings NMOS, obtain the ID position that value is " 0 ".
The unclonable chip circuit of above-described physics, time-domain difference measuring circuit includes controllable counter and two comparator circuits, comparator circuit includes electric capacity, reset NMOS tube and voltage comparator, the drain electrode of reset NMOS tube connects the first end of electric capacity, and the source electrode of reset NMOS tube connects the second end ground connection of electric capacity；The inverting input of the first termination voltage comparator of electric capacity, the in-phase input end of voltage comparator connects reference voltage；The anti-phase input of the first comparator circuit voltage comparator terminates the second outfan of the first current mirroring circuit, the first input end of output termination controllable counter；The anti-phase input of the second comparator circuit voltage comparator terminates the second outfan of the second current mirroring circuit, the second input of output termination controllable counter.
The unclonable chip circuit of above-described physics, when time-domain difference measuring circuit is started working, reset NMOS tube turns on, to electric capacity discharge reduction；After reset completes, reset NMOS tube turns off；Second electron current of the first current mirroring circuit and the second electron current of the second current mirroring circuit are not input to the end of oppisite phase of two voltage comparators, are two electric capacity chargings simultaneously；When capacitance voltage rises to more than the reference voltage that voltage comparator in-phase end is given, the output voltage saltus step of voltage comparator is 0；If the moment respectively t of two voltage comparator output end voltage saltus stepsaAnd tb, controllable counter is at first jumping moment taStart counting up, at second jumping moment tbStop counting；Controllable counter reads the count difference between two jumping moments, when this difference is more than threshold value set in advance, exports a flag being worth for " 1 " from controllable counter；Otherwise then output one value is the flag of " 0 ".
Based on the unclonable chip circuit of physics of time-domain difference current measurement, present invention tool has that chip area is little, low-power consumption, high reliability and low cost feature, can be widely applied on the circuit industry that reliability requirement height, power budget are low.
[accompanying drawing explanation]
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
Fig. 1 is the embodiment of the present invention theory diagram based on the unclonable chip circuit of physics of time-domain difference current measurement.
Fig. 2 is the ultimate principle figure of embodiment of the present invention current lens array.
Fig. 3 is the circuit structure diagram of embodiment of the present invention current lens array.
Fig. 4 is the circuit diagram of embodiment of the present invention current mirror A.
Fig. 5 is the circuit diagram of embodiment of the present invention current mirror B.
Fig. 6 is the circuit diagram of embodiment of the present invention current comparator circuit.
Fig. 7 is the circuit diagram of embodiment of the present invention time-domain difference current measurement circuit.
Fig. 8 is the fundamental diagram of embodiment of the present invention time-domain difference current measurement circuit.
The cartogram of the bit error rate under different temperatures that Fig. 9 is the embodiment of the present invention to be obtained based on the unclonable chip circuit emulation of physics of time-domain difference current measurement and running voltage.
Figure 10 is the embodiment of the present invention histogram based on the unclonable chip circuit intersymbol Hamming distance of physics of time-domain difference current measurement.
[detailed description of the invention]
The embodiment of the present invention based on the system structure of the unclonable chip circuit of physics of time-domain difference current measurement as it is shown in figure 1, this PUF circuit is made up of two identical current lens array circuit, two identical current mirroring circuits, a current comparator circuit and a time-domain difference measuring circuit.The operation principle of circuit overall is as follows: two current lens array circuit export electric current I respectivelyAAnd IB, the two electric current, respectively through current mirroring circuit A and current mirroring circuit B, respectively produces two electron current IA1、IA2And IB1、IB2。IA1And IB1It is input to current comparator circuit, after the two electric current is compared by current comparator, exports a binary system ID position (" 1 " or " 0 ")；IA2And IB2Being input in time-domain difference measuring circuit, this measuring circuit is to IA2And IB2The absolute value delta I=of difference | IA2-IB2| measurement, calculated the size of Δ I by a controllable counter, then export a binary identification position (" 1 " or " 0 ") again through this enumerator.Through repeatedly export from current lens array circuit two electric currents carry out such compare and measure after, an ID sequence identifier corresponding with can be obtained.The ID sequence obtained can as the identity identification information of a chip, and identifier is then for characterizing the reliability of this identity identification information.
The ultimate principle of current lens array circuit is as illustrated in fig. 2, it is assumed that three metal-oxide-semiconductor M1、M2、M3Technological parameter (such as electron mobility μn, unit are gate oxide capacitance Cox, channel width-over-length ratio W/L, threshold voltage VTHDeng) identical (being left out channel modulation effect), in theory the two output electric current I1And I2Essentially equal, but due to the deviation in manufacturing process, the two electric current actually and is not completely equivalent, it is possible to such a pair electric current is called mismatch current.In fig. 2, IREFIt is given input current, VBIt is electric current IREFAt transistor M1The voltage of upper generation.
Current lens array circuit shown in Fig. 3 is to be extended obtaining on the basis of circuit shown in Fig. 2.The identical NMOS tube that current lens array is arranged by M row N is constituted, and the grid of all NMOS tube of current lens array circuit links together；The source electrode of whole NMOS tube is connected and ground connection, and the drain electrode of each NMOS tube connects row switch (being also a NMOS tube).Row switch source is connected with the drain electrode of NMOS tube in array, in same current lens array circuit, is connected with the row switch control terminal (grid) of string.External N root address wire is connected on the grid of N number of row switch, controls to switch with the row of string to simultaneously turn on and turn off, and this N root address wire is called the bit line (BL of this array1-BLN)；Being connected with the drain electrode of all row switches of a line, share row switch (being also a NMOS tube) with the NMOS tube of a line, the source electrode of row switch connects the drain electrode with all row switches of a line.External M root address wire is connected on the grid of M row switch, controls the turn-on and turn-off of row switch, and this M root address wire is called the wordline (WL of this array1-WLM)；The drain electrode of all row switch is connected, as the outfan of whole array.
The output electric current I of array circuit shown in Fig. 3OUTThe output electric current I of respectively array 1 and array 2 in FIGAAnd IB。IAAnd IBIt is separately input to current mirroring circuit A and the input of current mirroring circuit B.VBIt is additional control voltage, controls NMOS tube in array and be in normal duty (conducting).The groundwork process of current lens array is: additional control voltage VBMaking all NMOS tube in array in the conduction state, external address wire (bit line of array and wordline) is by controlling ranks switch, and in array 1 and array 2, one NMOS tube of each selection, exports two mismatch current.The two mismatch current is input in current mirroring circuit A and current mirroring circuit B.
The circuit structure of current mirroring circuit A and current mirroring circuit B is distinguished as shown in Figure 4 and Figure 5, PMOS M4-M6The circuit of composition current mirroring circuit A, M7-M9The circuit of composition current mirroring circuit B, M4-M9These six PMOS are identical.The basic function of current mirroring circuit A and current mirroring circuit B is to produce two output electric currents essentially equal with input current.As shown in Figure 4 and Figure 5, the input of two current mirroring circuits respectively IAAnd IB, obtain exporting respectively IA1、IA2And IB1、IB2.Due to process deviation, IAWith IA1、IA2, IBWith IB1、IB2It is not completely equivalent, but by increasing the size of PMOS in the two current mirroring circuit, it is possible to the error between input and output electric current is narrowed down in a negligible scope；In like manner, by reducing the size of NMOS tube in current lens array circuit 1 and current lens array circuit 2, it is possible to increase the difference between the mismatch current that two arrays produce, the reliability of PUF circuit is improved.
The circuit structure of current comparator circuit is as shown in Figure 6.This circuit is by two reset NMOS tube M10And M13With two cross-linked NMOS tube M11And M12Composition, the output electric current I of two input ports of circuit input current mirror circuit A and current mirroring circuit B respectivelyA1And IB1, at M11Drain electrode output ID position.During circuit work, first input reset signal (being high level to NOMS pipe) and circuit is resetted.Reset NMOS tube M10And M13Conducting, to two cross-couplings NMOS tube M11And M12Drain electrode discharge so that it is voltage reduces to zero.After reset completes, make M10And M13Turn off (reset signal becomes low level).Respectively from cross-couplings NMOS tube M11And M12Drain electrode input current IA1And IB1, now two cross-linked NMOS tube M11And M12It is in the state being not turned on, IA1And IB1Respectively to M11And M12Drain charge, due to two electric current IA1And IB1Size be not completely equivalent, so M11And M12The speed that drain voltage rises is different, if IA1>IB1, then M11Drain voltage climbing speed more than M12Drain voltage climbing speed, so M12First turn on.M12The result of conducting is that its drain voltage is pulled low to ground or voltage closely, so M11The state turned off, last M will be always maintained at11The drain voltage of pipe can rise to a stable value, now at M11Drain electrode end can export high level, the ID position that value is " 1 " can be obtained.In like manner, I is worked asA1<IB1Time, circuit will obtain the ID position that value is " 0 ".
In order to ensure the reliability that integrated circuit works, the present invention proposes the circuit of the time-domain difference current measurement (Time-DomainCurrentDifferenceMeasurement:TDCDM) shown in Fig. 7.This structure is by two identical electric capacity C1、C2, two reset NMOS tube M14、M15, two voltage comparator D1、D2Form with 9 controllable counter.D1And D2End of oppisite phase connect electric capacity C respectively1And C2Upper end, reset transistor M14And M15Respectively with C1And C2Parallel connection and lower end ground connection.Voltage comparator D1、D2The given reference voltage V of homophase terminationREF, end of oppisite phase meets electric capacity C respectively1And C2Upper end, outfan connect controllable counter control end, respectively control counter start counting up and stop counting.During beginning, due to voltage comparator D1、D2End of oppisite phase voltage is less than in-phase end voltage, D1、D2Output voltage be Vdd(supply voltage)；When circuit is started working, reset transistor M14、M15Conducting, to electric capacity C1And C2Perform reset (electric discharge) operation.After reset completes, reset transistor M14、M15Turn off.Then electric current IA2And IB2It is separately input to D1、D2End of oppisite phase, be the chargings of two electric capacity simultaneously.As electric capacity C1And C2The voltage at two ends rises to more than D1、D2The reference voltage V of in-phase endREFTime, D1、D2Output voltage from VddSaltus step is 0.Due to IA2And IB2It is not completely equivalent, so electric capacity C1And C2The climbing speed of both end voltage is different, so two comparator D1、D2Moment of output end voltage generation saltus step different.Assume the moment respectively t of two voltage comparator output end voltage saltus stepsaAnd tb, controllable counter is at first jumping moment taStart counting up, at second jumping moment tbStop counting.This hour counter can read the count difference between two moment, when this difference is more than a threshold value set in advance, exports one from enumerator and be worth the flag for " 1 ", otherwise then output one is worth the flag for " 0 ".
Fig. 8 is the operation principle of time-domain difference current measurement (TDCDM) circuit, curve X, curve Y respectively two electric capacity C in figure1And C2The change curve of both end voltage；taAnd tbRespectively comparator D1、D2Moment of output end voltage generation saltus step, namely enumerator starts counting up and stops the moment of counting；CLK is the numerical value that fixed cycle enumerator is counted, electric current IA2And IB2Between the numerical value counted to enumerator of difference be directly proportional, the numerical value that enumerator is counted is more big, and electric current I is describedA2And IB2Between difference more big, the reliability of generated PUF position is also more high.
Above example of the present invention has the advantages that
PUF proposed by the invention realizes method without complicated error correction circuit, greatly reduces the chip area needed for circuit and power consumption.The PUF circuit that the present invention proposes utilizes the transistor of identical parameters in process of production because the parameter error that process deviation brings produces mismatch current, so circuit need not use the design of large-sized element cushion the circuit problem that process deviation brings, smaller size of transistor can be used on the contrary in current lens array, so that the bigger mismatch current that current lens array produces, thus reducing the bit error rate of circuit, improve the reliability of circuit.Simultaneously, it is possible to be optimized and make it to be operated in subthreshold region all analog circuits, this is the very big overall power that must reduce circuit also.
Further it is proposed that PUF chip circuit UMC0.18 μm of standard CMOS process can be used to carry out circuit simulation and layout design, the chip area of whole circuit is 13310 μm2, the PUF circuit compared in document [9] reduces about 40%.Fig. 9 gives the simulation result of the PUF circuit bit error rate proposed by the invention, it can be seen that this PUF circuit can reach the superior function that the bit error rate is zero when ordinary temp and supply voltage, the bit error rate when worst temperature and supply voltage also only has 1.56%.
Moreover, the unclonable practical circuit of Novel physical proposed in the present invention is tested, signal (addressing for current lens array) is randomly choosed by inputting, the output (response vector) that length is 128 can be obtained, the frequency distribution of the intersymbol Hamming distance (Hammingdistance) of this output is as shown in Figure 10, the normalization average value being obtained the output of PUF chip circuit by graphic calculation is μ=0.5018, corresponding standard deviation is σ=0.0182, and this represents that the PUF circuit that the present invention proposes has superior circuit performance.
Embodiment of the present invention PUF circuit and other PUF circuit performance comparison sheets:
Upper table gives the Performance comparision of the embodiment of the present invention and some other homogeneous circuits, it can be seen that the PUF circuit of the unclonable chip circuit of physics of present invention invention relatively before has had bigger lifting at aspect of performances such as power consumption, chip area, circuit reliabilities (bit error rate).
As can be seen here, the PUF circuit measured based on difference current that the present invention proposes has that chip area is little, low-power consumption, high reliability and low cost feature, can be widely applied on the circuit industry that reliability requirement height, power budget are low.

Claims (9)

1. the unclonable chip circuit of the physics based on time-domain difference current measurement, it is characterized in that, including two current lens array circuit, two current mirroring circuits and current comparator circuit, the output electric current of two current lens array circuit inputs the first current mirroring circuit and the second current mirroring circuit respectively；The first electron current and the first electron current of the second current mirroring circuit generation that first current mirroring circuit produces are separately input to current comparator circuit, after two electron currents are compared by current comparator circuit, export a binary system ID position；After repeatedly selecting the element circuit of current lens array circuit to carry out and exporting and process, obtain an ID sequence, as the identity identification information of chip.
2. the unclonable chip circuit of physics according to claim 1, it is characterized in that, including time-domain difference measuring circuit, the second electron current and the second electron current of the second current mirroring circuit generation that first current mirroring circuit produces are separately input to time-domain difference measuring circuit, the second electron current and the absolute value of the second electron current difference of the second current mirroring circuit generation that first current mirroring circuit is produced by time-domain difference measuring circuit measure, the size of described absolute value is calculated by controllable counter, by the threshold ratio of described absolute value and setting relatively, export a binary identification position；After repeatedly selecting the element circuit of current lens array circuit to carry out and exporting and process, obtain an identifier answered with described ID sequence pair, for characterizing the reliability of described identity identification information.
3. the unclonable chip circuit of physics according to claim 1, it is characterized in that, current lens array circuit includes M root row address line, row switch and M row that N root column address conductor, M row N row NMOS tube are identical with NMOS tube quantity switch, the grid of whole NMOS tube of current lens array circuit is connected, and connects additional control voltage；The source electrode of whole NMOS tube is connected and ground connection；The drain electrode of NMOS tube connects the input of this every trade switch by arranging switch；With the column address conductor controlling these row of termination of rows of switches, the control of row switch terminates the row address line of this row, and the outfan that all row switch is connected, as the outfan of current lens array circuit.
4. the unclonable chip circuit of physics according to claim 3, it is characterized in that, row switch and row switch are all NMOS tube, the source electrode of row switch is connected with the drain electrode of corresponding NMOS tube, the grid of row switch connects the column address conductor of these row, connects the source electrode of this every trade switch with the drain electrode of all row switches of a line, and the grid of row switch connects the row address line of this row, the drain electrode of all row switch is connected, as the outfan of current lens array circuit.
5. the unclonable chip circuit of physics according to claim 2, it is characterised in that current mirroring circuit includes three PMOS, the source electrode external power supply of three PMOS；The grid of three PMOS links together, and connects the drain electrode of the first PMOS；The drain electrode of the first PMOS of the first current mirroring circuit connects the outfan of the first current lens array circuit, and the drain electrode of the second PMOS connects the first input end of current comparator circuit, and the drain electrode of the 3rd PMOS connects the first input end of time-domain difference measuring circuit；The drain electrode of the first PMOS of the second current mirroring circuit connects the outfan of the second current lens array circuit, and the drain electrode of the second PMOS connects the second input of current comparator circuit, and the drain electrode of the 3rd PMOS connects the second input of time-domain difference measuring circuit.
6. the unclonable chip circuit of physics according to claim 1, it is characterized in that, current comparator circuit includes two reset NMOS and two cross-linked NMOS, the source ground of reset NMOS and NMOS, the drain electrode of the first reset NMOS and the grid of the 2nd NMOS connect the drain electrode of a NMOS, the drain electrode of the second reset NMOS and the grid of a NMOS and connect the drain electrode of the 2nd NMOS；The drain electrode of two NMOS connects the first current mirroring circuit and the electron current of the second current mirroring circuit output respectively, the outfan that drain electrode is current comparator circuit of a NMOS.
7. the unclonable chip circuit of physics according to claim 6, it is characterized in that, during current comparator circuit work, the first grid input high level to two reset NMOS, make reset NMOS turn on, make two cross-couplings NMOS carry out discharge reduction by drain electrode；Then the grid input low level to two reset NMOS, makes reset NMOS turn off；Hereafter, the drain electrode of two NMOS inputs the first current mirroring circuit and the electron current of the second current mirroring circuit output respectively, if the electron current that export more than the second current mirroring circuit of electron current of the first current mirroring circuit output, the drain electrode of a NMOS exports high level, obtains the ID position that value is " 1 "；If the electron current that exports less than the second current mirroring circuit of electron current of the first current mirroring circuit output, the drain electrode output low level of a NMOS, obtain the ID position that value is " 0 ".
8. the unclonable chip circuit of physics according to claim 2, it is characterized in that, time-domain difference measuring circuit includes controllable counter and two comparator circuits, comparator circuit includes electric capacity, reset NMOS tube and voltage comparator, the drain electrode of reset NMOS tube connects the first end of electric capacity, and the source electrode of reset NMOS tube connects the second end ground connection of electric capacity；The inverting input of the first termination voltage comparator of electric capacity, the in-phase input end of voltage comparator connects reference voltage；The anti-phase input of the first comparator circuit voltage comparator terminates the second outfan of the first current mirroring circuit, the first input end of output termination controllable counter；The anti-phase input of the second comparator circuit voltage comparator terminates the second outfan of the second current mirroring circuit, the second input of output termination controllable counter.
9. the unclonable chip circuit of physics according to claim 8, it is characterised in that when time-domain difference measuring circuit is started working, reset NMOS tube turns on, to electric capacity discharge reduction；After reset completes, reset NMOS tube turns off；Second electron current of the first current mirroring circuit and the second electron current of the second current mirroring circuit are not input to two electric capacity, charge for the two electric capacity simultaneously；When capacitance voltage rises to the reference voltage more than voltage comparator in-phase end, the output voltage saltus step of voltage comparator is 0；If moment respectively ta and the tb of two voltage comparator output end voltage saltus steps, controllable counter starts counting up at first jumping moment ta, stops counting at second jumping moment tb；Controllable counter reads the count difference between two jumping moments, when this difference is more than threshold value set in advance, exports a flag being worth for " 1 " from controllable counter；Otherwise then output one value is the flag of " 0 ".
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CN106919216A (en) * 2017-03-01 2017-07-04 深圳大学 A kind of unclonable circuit of physics based on Cascode current-mirror structures
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CN107766750A (en) * 2017-11-22 2018-03-06 河海大学常州校区 A kind of PUF circuits based on threshold voltage benchmark
CN108694336A (en) * 2018-04-28 2018-10-23 深圳大学 A kind of unclonable technology of low bit- rate low energy consumption physics based on current comparator
CN108983866A (en) * 2017-06-01 2018-12-11 新唐科技股份有限公司 The electronic circuit and method of current lens array
CN109697376A (en) * 2019-01-18 2019-04-30 河海大学常州校区 A kind of PUF circuit based on difference charging capacitor
CN112994445A (en) * 2021-04-25 2021-06-18 四川蕊源集成电路科技有限公司 Apparatus and method for reducing electromagnetic interference of DC-DC power supply
CZ309064B6 (en) * 2021-03-24 2022-01-05 České vysoké učení technické v Praze Connection with current mirrors, method of impedance measurement and method of current to voltage conversion in this connection
CN115130152A (en) * 2022-09-01 2022-09-30 北京紫光青藤微系统有限公司 Method and device for generating physical unclonable function

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CN105245220A (en) * 2015-09-25 2016-01-13 深圳大学 Physical unclonable chip circuit

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Publication number Priority date Publication date Assignee Title
CN106919216A (en) * 2017-03-01 2017-07-04 深圳大学 A kind of unclonable circuit of physics based on Cascode current-mirror structures
CN108983866A (en) * 2017-06-01 2018-12-11 新唐科技股份有限公司 The electronic circuit and method of current lens array
CN107491704A (en) * 2017-08-23 2017-12-19 大家传承网络科技（深圳）有限公司 It is related to false proof, certification, the unclonable circuit of the physics of key and implementation method
CN107766750A (en) * 2017-11-22 2018-03-06 河海大学常州校区 A kind of PUF circuits based on threshold voltage benchmark
CN107766750B (en) * 2017-11-22 2023-05-09 河海大学常州校区 PUF circuit based on threshold voltage reference
CN108694336A (en) * 2018-04-28 2018-10-23 深圳大学 A kind of unclonable technology of low bit- rate low energy consumption physics based on current comparator
CN108694336B (en) * 2018-04-28 2022-02-11 深圳大学 Low-code-rate low-energy-consumption physical unclonable technology based on current comparator
CN109697376B (en) * 2019-01-18 2022-10-04 河海大学常州校区 PUF circuit based on differential charging capacitor
CN109697376A (en) * 2019-01-18 2019-04-30 河海大学常州校区 A kind of PUF circuit based on difference charging capacitor
CZ309064B6 (en) * 2021-03-24 2022-01-05 České vysoké učení technické v Praze Connection with current mirrors, method of impedance measurement and method of current to voltage conversion in this connection
CN112994445A (en) * 2021-04-25 2021-06-18 四川蕊源集成电路科技有限公司 Apparatus and method for reducing electromagnetic interference of DC-DC power supply
CN115130152B (en) * 2022-09-01 2022-11-18 北京紫光青藤微系统有限公司 Method and device for generating physical unclonable function
CN115130152A (en) * 2022-09-01 2022-09-30 北京紫光青藤微系统有限公司 Method and device for generating physical unclonable function

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