CN105742465A - Semiconductor light emitting chip - Google Patents
Semiconductor light emitting chip Download PDFInfo
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- CN105742465A CN105742465A CN201610235309.8A CN201610235309A CN105742465A CN 105742465 A CN105742465 A CN 105742465A CN 201610235309 A CN201610235309 A CN 201610235309A CN 105742465 A CN105742465 A CN 105742465A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
Abstract
The invention provides a semiconductor light emitting chip. The semiconductor light emitting chip comprises a substrate, wherein a semiconductor stacked layer at least comprising an n type conductive layer, a light emitting layer and a p type conductive layer is formed on the first surface of the substrate; at least an n type electrode slot position is formed in the surface of the semiconductor stacked layer; the partial or total exposed and conductive surface and side faces of the semiconductor light emitting chip are coated with at least an insulating layer; at least an n type welding pad conductively connected with the n type conductive layer and at least a p type welding pad conductively connected with the p type conductive layer are arranged on the surface of the insulating layer; an n type metal filling-leveling layer is arranged between the surface of the n type conductive layer and the n type welding pad, and/or a p type metal filling-leveling layer is arranged between the surface of the p type conductive layer and the p type welding pad. According to the semiconductor light emitting chip provided by the invention, the filling-leveling layer is filled and leveled between the corresponding conductive layer and the corresponding welding pad, so that the surface of the welding pads are flattened, and the welding quality and yield are improved as well; and in addition, the semiconductor light emitting chip is simple in structure, convenient to use, and low in manufacturing cost.
Description
Technical field
The present invention relates to a kind of semiconductor luminous chip, further to a kind of semiconductor luminous chip promoting welding quality and yield.
Background technology
Along with the decline of the lifting of semiconductor luminous chip luminous efficiency and manufacturing cost, semiconductor luminous chip has been widely used in the fields such as backlight, display and illumination.
In existing semiconductor luminous chip structure, owing to conductive layer surface and surface of insulating layer are not in same level, cause n-type weld pad surface and p-type weld pad uneven surface, have the depression that the depth is different.Depression can affect the welding quality of metal lead wire and weld pad surface, during especially with eutectic weldering and Reflow Soldering, it may appear that cavity, causes that welding yield is not high, the low inferior problem of welding quality.
Summary of the invention
The technical problem to be solved in the present invention is in that, it is provided that a kind of to weld pad surface planarisation, promotes the semiconductor luminous chip of welding quality and yield.
The technical solution adopted for the present invention to solve the technical problems is: provide a kind of semiconductor luminous chip, including the substrate with first surface and second surface, have at described substrate first surface and at least include the semiconductor laminated of n-type conductive layer, luminescent layer and p-type electric-conducting layer, have at least a n-type electrode groove position exposing partially n-type conductive layer on described semiconductor laminated surface；The surface that is partly or entirely exposed, that have electric conductivity of described semiconductor luminous chip and side are wrapped up by least one insulating barrier；
At described surface of insulating layer, it is provided with at least one n-type weld pad being conductively connected with n-type conductive layer and at least one p-type weld pad being conductively connected with p-type electric-conducting layer, insulated from each other between described p-type weld pad and n-type weld pad；
It is provided with n-type metal between at least one described n-type conductive layer surface and described n-type weld pad and fills and leads up layer, and/or, it is provided with p-type metal between at least one described p-type electric-conducting layer surface and described p-type weld pad and fills and leads up layer.
Preferably, the described insulating barrier position of corresponding described n-type conductive layer is provided with the first groove, and described first groove is positioned at described n-type electrode groove position through to described n-type conductive layer；Described n-type metal is filled and led up layer and is positioned at described n-type electrode groove position and fills described first groove；
The described insulating barrier position of corresponding described p-type electric-conducting layer is provided with the second groove, described second through to the described p-type electric-conducting layer of groove；Described p-type metal is filled and led up layer and is filled in described second groove.
Preferably, described n-type metal is filled and led up layer and is included being filled in described first groove and the first n-type metal of being conductively connected with described n-type conductive layer fills and leads up layer and the second n-type metal of being filled in described n-type electrode groove position fills and leads up layer；
Described second n-type metal is filled and led up layer and is filled and led up between layer and described n-type weld pad at described first n-type metal, and fills and leads up layer with described first n-type metal and described n-type weld pad is conductively connected.
Preferably, described n-type metal is filled and led up layer and is included metal and fill and lead up layer, and this metal is filled and led up layer and is arranged in described n-type electrode groove position and is conductively connected by described first groove and described n-type conductive layer.
Preferably, described n-type metal is filled and led up layer and is also included being wrapped in the centre that described metal fills and leads up layer peripheral and fill and lead up layer；
Described centre fills and leads up layer and described metal fills and leads up layer and n-type weld pad is conductively connected.
Preferably, described centre is filled and led up layer and is adopted a kind of or several metal in chromium, nickel, titanium, tungsten, platinum, molybdenum, palladium and/or their alloy to make.
Preferably, a p-type current extending it is provided with between described p-type electric-conducting layer surface and described insulating barrier；Described p-type metal is filled and led up layer and is conductively connected with described p-type current extending；And/or,
A n-type current extending it is provided with between described bottom surface, n-type electrode groove position and described insulating barrier；Described n-type metal is filled and led up layer and is conductively connected with described n-type current extending.
Preferably, described p-type current extending includes one or more in p-type electric-conducting extension layer, p-type reflecting layer, P type contact layer；Described n-type current extending includes one or more in n-type conductive extension layer, n-type reflecting layer, n-contact layer.
Preferably, described p-type current extending includes p-type reflecting layer, and described n-type current extending includes n-type reflecting layer, and described semiconductor luminous chip is front and/or side goes out light；Or, described p-type current extending includes p-type electric-conducting extension layer and/or P type contact layer；Described n-type current extending includes n-type conductive extension layer and/or n-contact layer, and described semiconductor luminous chip is that front, the back side and/or side go out light.
Preferably, this semiconductor luminous chip also includes at least one n-type electrode and at least one p-type electrode, insulated from each other between described n-type electrode and p-type electrode, and runs through described insulating barrier and be conductively connected with described n-type conductive layer and p-type electric-conducting layer respectively；
Described n-type electrode is positioned at described n-type electrode groove position, described n-type metal is filled and led up layer and is wrapped in described n-type electrode periphery, and be conductively connected with described n-type weld pad, described n-type weld pad fills and leads up layer and n-type electrode by described n-type metal and described n-type conductive layer is conductively connected；
Described p-type metal is filled and led up layer and is wrapped in described p-type electrode periphery, and is conductively connected with described p-type weld pad, and described p-type weld pad is filled and led up layer and p-type electrode by described p-type metal and is conductively connected with described p-type electric-conducting layer.
Preferably, a p-type current extending it is provided with between described p-type electric-conducting layer surface and described insulating barrier；Described p-type electrode and described p-type current extending are conductively connected；And/or,
A n-type current extending it is provided with between described bottom surface, n-type electrode groove position and described insulating barrier；Described n-type electrode and described n-type current extending are conductively connected.
Preferably, described p-type current extending includes one or more in p-type electric-conducting extension layer, p-type reflecting layer, P type contact layer；Described n-type current extending includes one or more in n-type conductive extension layer, n-type reflecting layer, n-contact layer.
Preferably, between described n-type electrode and described p-type electrode, it is provided with the Metal Substrate heat conduction weld pad being at least close to described surface of insulating layer, insulated from each other between described Metal Substrate heat conduction weld pad and described n-type electrode and p-type electrode.
Preferably, at least one described p-type weld pad and/or at least one described n-type weld pad extend to the outside side surface of described semiconductor luminous chip, part or all of side surface in described outside forms corresponding side weld pad, has at least one described insulating barrier between described side weld pad and described side surface.
Preferably, between described n-type weld pad and p-type weld pad, it is provided with the Metal Substrate heat conduction weld pad being at least close to described surface of insulating layer, insulated from each other between described Metal Substrate heat conduction weld pad and described n-type weld pad and p-type weld pad.
Preferably, described n-type electrode groove position includes step and/or through hole.
Preferably, this semiconductor luminous chip surrounding has an indent；Described indent is positioned at described semiconductor laminated side, and the bottom surface of described indent is positioned at described substrate first surface or described substrate, described indent side and bottom surface and is wrapped up by least one described insulating barrier.
Preferably, described insulating barrier is part or all of containing a reflection layer；Described reflection layer is positioned at the centre of described insulating barrier or is positioned at the exposed surface of described insulating barrier.
Preferably, described substrate is light-transmissive substrates；Described substrate first surface and/or second surface are smooth finished surfaces or patterned surface；Described patterned surface includes one or more in taper rough surface, convex-concave surface, pyramid shape surface；And/or,
Described side of substrate and/or described semiconductor laminated side is vertical with described substrate first surface or the smooth flat of oblique, smooth surface, structuring plane or structuring curved surface；Described structuring includes one or more in concavo-convex, sawtooth.
The semiconductor luminous chip of the present invention, fills and leads up arranging filling and filling and leading up between conductive layer and weld pad of layer by metal, makes weld pad surface planarisation, reaches to promote the purpose of welding quality and yield.This semiconductor luminous chip simple in construction, easy to use, low cost of manufacture.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the invention will be further described, in accompanying drawing:
Fig. 1 is the structural representation of the semiconductor luminous chip of one embodiment of the invention；
Fig. 2 is the structural representation of the semiconductor luminous chip of another embodiment of the present invention.
Detailed description of the invention
As it is shown in figure 1, the semiconductor luminous chip of one embodiment of the invention, including substrate 10, semiconductor laminated 11, at least one n-type weld pad 12 and at least one p-type weld pad 13.Wherein, substrate 10 has first surface and second surface；Semiconductor laminated 11 are arranged on the first surface, and it includes folding the n-type conductive layer 111, luminescent layer 112 and the p-type electric-conducting layer 113 that set successively.The surface that is partly or entirely exposed, that have electric conductivity of this semiconductor luminous chip and side are wrapped up by least one insulating barrier 16.
N-type weld pad 12 is arranged on insulating barrier 16 surface and is conductively connected with n-type conductive layer 111；P-type weld pad 13 is arranged on insulating barrier 16 surface and is conductively connected with p-type electric-conducting layer 113.Between this p-type weld pad 13 and n-type weld pad 12 insulated from each other.
Being provided with n-type metal between at least one n-type conductive layer 111 surface and n-type weld pad 12 and fill and lead up layer 14, n-type metal is filled and led up layer 14 and is filled and led up in space between n-type conductive layer 111 surface and n-type weld pad 12, facilitates the setting of n-type weld pad 12 so that weld pad surface planarisation.Also can be provided with p-type metal between at least one p-type electric-conducting layer 113 surface and p-type weld pad 13 and fill and lead up layer 15, p-type metal is filled and led up layer 15 and is filled and led up in space between p-type electric-conducting layer 113 surface and p-type weld pad 13, facilitate the setting of p-type weld pad 13 so that weld pad surface planarisation.Certainly, according to actual needs, n-type metal fills and leads up layer 14 and p-type metal is filled and led up layer 15 and also can only be arranged one of which.
Specifically, in the present embodiment, semiconductor laminated 11 are arranged on the first surface of substrate 10, and the second surface of substrate 10 can as light output surface, and semiconductor laminated 11 light produced are sent by second surface.Substrate 10 is light-transmissive substrates, it is preferred to Sapphire Substrate.It is to be appreciated that substrate 10 can also adopt the light-transmissive substrates that other materials are made.
The first surface of this substrate 10 and/or second surface are smooth finished surfaces or patterned surface；Patterned surface includes one or more in taper rough surface, convex-concave surface, pyramid shape surface.
The side of this substrate 10 and/or semiconductor laminated 11 sides are vertical with the first surface of substrate 10 or the smooth flat of oblique, smooth surface, structuring plane or structuring curved surface；Structuring includes one or more in concavo-convex, sawtooth.
Semiconductor laminated 11 surfaces have at least a n-type electrode groove position 110 exposing partially n-type conductive layer 111.N-type electrode groove position 110 includes step and/or through hole.The bottom surface of n-type electrode groove position 110 is used for making counter electrode, metal fills and leads up layer and/or n-type current extending, and this bottom surface can be located on n-type conductive layer 111, or is positioned at n-type conductive layer 111.The side of n-type electrode groove position 110 can be vertical with the first surface of substrate 10 or the smooth flat of oblique, smooth surface, structuring plane or structuring curved surface；Structuring includes one or more in concavo-convex, sawtooth.
For reducing the minimizing of luminescent layer 113 area to greatest extent, it is narrow to try one's best in making n-type electrode groove position 110, it may be preferable to through hole replaces step.
In the present embodiment, it has been formed around an indent 100 at semiconductor luminous chip.Indent 100 is shunk to semiconductor laminated 11 sides relative to the edge of substrate 10, thus indent 100 is positioned at semiconductor laminated 11 sides.The bottom surface of this indent 100 is positioned on substrate 10 first surface or substrate 10.
Indent 100 side and bottom surface are wrapped up by least one insulating barrier, and this insulating barrier can be extended to form by above-mentioned insulating barrier 16.The setting of indent 100, forms substrate level over the substrate 10.Insulating barrier wraps up indent 100 and fills up whole substrate level, such that it is able to more easily by the conduction side wrap of whole semiconductor luminous chip, form insulation.Insulating barrier 16 material can include silicon dioxide, aluminium sesquioxide, aluminium nitride and silicon nitride etc..
The surface all exposed, that have electric conductivity of semiconductor luminous chip and side include surface all exposed, that have electric conductivity and the side of semiconductor laminated 11, do not filled and led up the exposed surface of the n-type conductive layer 111 that layer 14 covers and exposed sides by n-type metal, are not filled and led up exposed surface and exposed sides, the exposed sides of luminescent layer 112, n-type electrode groove side, position 110 and indent 100 side and the bottom surface etc. thereof of the p-type electric-conducting layer 113 that layer 15 covers by p-type metal.The thickness of the thinnest part of insulating barrier 16 is typically larger than 150 nanometers.Whole semiconductor luminous chip is due to fully wrapped around by insulating barrier 16, so can use too even without casting glue protection.
On semiconductor laminated 11, insulating barrier 13 position of corresponding n-type conductive layer 111 is provided with the first groove 161, and the first groove 161 is positioned at n-type electrode groove position 110, and through to n-type conductive layer 111.N-type metal is filled and led up layer 14 and is positioned at n-type electrode groove position 110 and fills the first groove 161.
In the present embodiment, n-type metal is filled and led up layer 14 and is included being filled in the first groove 161 and the first n-type metal of being conductively connected with n-type conductive layer 111 fills and leads up layer 141 and the second n-type metal of being filled in n-type electrode groove position 110 fills and leads up layer 142.Second n-type metal is filled and led up layer 142 and is filled and led up n-type electrode groove position 110, fills and leads up between layer 141 and n-type weld pad 12 at the first n-type metal, and fills and leads up layer 141 with the first n-type metal and n-type weld pad 12 is conductively connected.
First n-type metal is filled and led up layer the 141, second n-type metal and is filled and led up layer 142 a kind of the or several metal in chromium, nickel, titanium, tungsten, platinum, molybdenum, palladium and/or their alloy all can be adopted to make.First n-type metal is filled and led up the material that layer the 141, second n-type metal fill and lead up between layer 142 and be may be the same or different.
Insulating barrier 16 position of corresponding p-type electric-conducting layer 113 is provided with the second groove 162, and the second groove 162 is through to p-type electric-conducting layer 113；P-type metal is filled and led up layer 15 and is filled in the second groove 162, is filled and led up by this second groove 162.P-type weld pad is arranged on p-type metal and fills and leads up on layer 15, fills and leads up layer 15 by p-type metal and is conductively connected with p-type electric-conducting layer 113.P-type metal is filled and led up layer 15 and a kind of or several metal in chromium, nickel, titanium, tungsten, platinum, molybdenum, palladium and/or their alloy can be adopted to make.
At least one p-type weld pad 13 and/or at least one n-type weld pad 12 can extend to the outside side surface of semiconductor luminous chip, and the part or all of side surface in outside forms corresponding side weld pad, has at least one insulating barrier 16 between side weld pad and side surface.The convenient welding of the formation of side weld pad, welding cohesiveness is good, and resistance thermal resistance is low, low cost of manufacture, it is adaptable to manufacture the semiconductor luminous chip of the big current type of small size.
Additionally, arranged by the formation of side weld pad, weld pad can be greatly reduced and take the area in chip light-emitting face, for need two-sided go out light semiconductor luminous chip for, the setting of this side weld pad does not affect the luminescence on two sides.So that chip have two-sided go out light feasibility, expanded the application scenario of chip.
Further, the semiconductor luminous chip of the present embodiment may also include p-type current extending.
N-type conductive layer 111 generally thicker than p-type electric-conducting layer 113 5-15 times, and there is conductive characteristic more preferably, so its electric current can be distributed to whole n-type conductive layer 111 preferably.Conversely, because p-type electric-conducting layer 113 is very thin, electric conductivity is poor again, in order to ensure electric current energy uniform vertical by luminescent layer 112, it is preferable that at p-type electric-conducting layer 113 surface blanket p-type current extending.
P-type current extending has good conductive characteristic on the one hand, can form low resistance contacts or low-resistance Ohm contact with p-type electric-conducting layer 113 on the other hand, additionally, for improving the amount of light from substrate 10 second surface, p-type current extending comprises p-type reflecting layer.So, p-type current extending generally forms by having the p-type electric-conducting extension layer of good conductive characteristic, P type contact layer and p-type reflecting layer；Certainly, p-type current extending can also be arranged as required to into one or more that include in p-type electric-conducting extension layer, p-type reflecting layer and P type contact layer.
Wherein, the material that p-type electric-conducting extension layer uses includes one or more in ITO, Ag, Au, Al, Cr, Ti, Pt, Pd, Ni, W, ZnO, the material that P type contact layer uses includes one or more in ITO, Ag, Al, Cr, Ti, Pt, Pd, Ni, NiO, ZnO, heavily doped producing a low resistance p-type conductive layer, and the material that p-type reflecting layer uses includes one or more in Ag, Al, Prague total reflection film (DBR).Starting to be arranged in order order from p-type electric-conducting layer 113 is P type contact layer, p-type reflecting layer, p-type electric-conducting extension layer, and when p-type electric-conducting extension layer is transparent, being arranged in order order can also be P type contact layer, p-type electric-conducting extension layer, p-type reflecting layer.
P-type current extending is arranged between p-type electric-conducting layer 113 surface and insulating barrier 16, and fills and leads up layer 15 with p-type metal and be conductively connected.
As required, the semiconductor luminous chip of the present embodiment also includes n-type current extending, has identical effect and function with p-type current extending.N-type current extending is arranged between n-type electrode groove bottom surface, position 110 and insulating barrier 16, and fills and leads up layer 14 with n-type metal and be conductively connected.
N-type current extending can also include one or more in n-type conductive extension layer, n-type reflecting layer, n-contact layer.The material that n-type conductive extension layer uses includes one or more in ITO, Ag, Au, Al, Cr, Ti, Pt, Pd, Ni, W, ZnO, the material that n-contact layer uses includes one or more in ITO, Ag, Al, Cr, Ti, Pt, Pd, Ni, NiO, ZnO, heavily doped low-resistance n-type conductive layer, and the material that n-type reflecting layer uses includes one or more in Ag, Al, Prague total reflection film (DBR).
In above-mentioned p-type current extending and n-type current extending, when p-type current extending includes p-type reflecting layer, and n-type current extending includes n-type reflecting layer, semiconductor luminous chip front and/or side can go out light；When p-type current extending does not include p-type reflecting layer, as included P type contact layer and/or p-type electric-conducting extension layer, n-type current extending does not include n-type reflecting layer, and during as included n-contact layer and/or n-type conductive extension layer, semiconductor luminous chip front, side and/or the back side can go out light.
Certainly, as required, n-type current extending and p-type current extending also optional one is configured, or is all not provided with.
Further, the semiconductor luminous chip of the present embodiment may also include at least Metal Substrate heat conduction weld pad (not shown).Metal Substrate heat conduction weld pad may be provided between n-type weld pad 12 and p-type weld pad 13, and is close to insulating barrier 16 surface.Between Metal Substrate heat conduction weld pad and n-type weld pad 12 and p-type weld pad 13 insulated from each other.
Metal Substrate heat conduction weld pad can directly be connected with heat abstractor, improving heat radiation efficiency.Metal Substrate heat conduction weld pad generally adopts good thermal conductive metallic material, including silver, aluminum, gold.
Semiconductor luminous chip can pass through the backflow of Metal Substrate heat conduction weld pad and be soldered on the pad of LED support, whole technique is simple, and the solder reflow device of the cheap and simple compatible with other electronic devices and components and technology generations can be adopted for the LED die bond routing device of normally used complex and expensive and technique, it is greatly saved equipment investment, reduces manufacturing cost and reduce process procedure.
The semiconductor luminous chip of another embodiment of the present invention, with reference to Fig. 1, n-type metal is filled and led up layer 14 and is partly or entirely alternatively arranged as n-type electrode use, plays the function of n-type electrode.Or, this semiconductor luminous chip may also include at least one n-type electrode (not shown), and n-type electrode is arranged on insulating barrier 16 and runs through insulating barrier and is conductively connected with n-type conductive layer 111 respectively.N-type electrode is positioned at n-type electrode groove position 110, n-type metal is filled and led up layer 14 and is wrapped in n-type electrode periphery, filling and leading up n-type electrode groove position 110, and be conductively connected with n-type weld pad 12, n-type weld pad 12 fills and leads up layer 14 and n-type electrode by n-type metal and n-type conductive layer 111 is conductively connected.
Accordingly, p-type metal is filled and led up layer 15 and also can partly or entirely be used as p-type electrode, plays the function of p-type electrode.Or, this semiconductor luminous chip may also include at least one p-type electrode (not shown), and p-type electrode is arranged on insulating barrier 16 and runs through insulating barrier and is conductively connected with p-type electric-conducting layer 113 respectively.P-type metal is filled and led up layer 15 and is wrapped in p-type electrode periphery and carries out filling and leading up effect, and is conductively connected with p-type weld pad 13, and p-type weld pad 13 is filled and led up layer 15 and p-type electrode by p-type metal and is conductively connected with p-type electric-conducting layer 113.
Setting according to n-type electrode and p-type electrode, can require to be correspondingly arranged n-type current extending (not shown) and p-type current extending (not shown) according to CURRENT DISTRIBUTION equally.P-type current extending is arranged between p-type electric-conducting layer 113 surface and insulating barrier 16, and p-type electrode and p-type current extending are conductively connected；N-type current extending is arranged between bottom surface, n-type electrode groove position and insulating barrier, and n-type electrode and n-type current extending are conductively connected.
P-type current extending and n-type current extending concrete structure and material etc. are with reference to above-mentioned.
Further, the semiconductor luminous chip of the present embodiment may also include at least Metal Substrate heat conduction weld pad (not shown), is arranged between n-type electrode and p-type electrode and is close to insulating barrier 16 surface.Between Metal Substrate heat conduction weld pad and n-type electrode and p-type electrode insulated from each other.
Metal Substrate heat conduction weld pad can directly be connected with heat abstractor, improving heat radiation efficiency.Metal Substrate heat conduction weld pad generally adopts good thermal conductive metallic material, including silver, aluminum, gold.
Semiconductor luminous chip can pass through the backflow of Metal Substrate heat conduction weld pad and be soldered on the pad of LED support, whole technique is simple, and the solder reflow device of the cheap and simple compatible with other electronic devices and components and technology generations can be adopted for the LED die bond routing device of normally used complex and expensive and technique, it is greatly saved equipment investment, reduces manufacturing cost and reduce process procedure.
As in figure 2 it is shown, the semiconductor luminous chip of another embodiment of the present invention, including substrate 10, semiconductor laminated 11, at least one n-type weld pad 12 and at least one p-type weld pad 13.Wherein, substrate 10 has first surface and second surface；Semiconductor laminated 11 are arranged on the first surface, and it includes folding the n-type conductive layer 111, luminescent layer 112 and the p-type electric-conducting layer 113 that set successively.The surface that is partly or entirely exposed, that have electric conductivity of this semiconductor luminous chip and side are wrapped up by least one insulating barrier 16.
N-type weld pad 12 is arranged on insulating barrier 16 surface and is conductively connected with n-type conductive layer 111；P-type weld pad 13 is arranged on insulating barrier 16 surface and is conductively connected with p-type electric-conducting layer 113.Between this p-type weld pad 13 and n-type weld pad 12 insulated from each other.
Being provided with n-type metal between at least one n-type conductive layer 111 surface and n-type weld pad 12 and fill and lead up layer 14, n-type metal is filled and led up layer 14 and is filled and led up in space between n-type conductive layer 111 surface and n-type weld pad 12, facilitates the setting of n-type weld pad 12 so that weld pad surface planarisation.Also can be provided with p-type metal between at least one p-type electric-conducting layer 113 surface and p-type weld pad 13 and fill and lead up layer 15, p-type metal is filled and led up layer 15 and is filled and led up in space between p-type electric-conducting layer 113 surface and p-type weld pad 13, facilitate the setting of p-type weld pad 13 so that weld pad surface planarisation.Certainly, according to actual needs, n-type metal fills and leads up layer 14 and p-type metal is filled and led up layer 15 and also can only be arranged one of which.
The present embodiment is unlike the embodiments above: n-type metal is filled and led up layer 14 and included being arranged on the metal being conductively connected in n-type electrode groove position 110 and by the first groove 161 and n-type conductive layer 111 and fill and lead up layer 143 and be wrapped in metal and fill and lead up the centre of layer 143 periphery and fill and lead up layer 144；Centre is filled and led up layer 144 and is filled and led up n-type electrode groove position 110.Centre fills and leads up layer 144 and metal fills and leads up layer 143 and n-type weld pad 12 is conductively connected.
Centre is filled and led up layer 144 and is adopted a kind of or several metal in chromium, nickel, titanium, tungsten, platinum, molybdenum, palladium and/or their alloy to make.Metal fills and leads up layer 143 can fill and lead up the identical or different setting of layer 144 with centre.
P-type metal fill and lead up the set-up mode of layer 15 can refer to relevant in above-mentioned embodiment illustrated in fig. 1 described in.
In other embodiments, n-type metal is filled and led up layer 14 and also be may not include centre and fill and lead up layer 144, fill and lead up layer 143 by metal and be filled in n-type electrode groove position 110 and the first groove 161, and fill and lead up n-type electrode groove position 110, can reach to facilitate the setting of n-type weld pad 12 equally so that the purpose of weld pad surface planarisation.
It addition, in other embodiments, in the semiconductor luminous chip of the present invention, with reference to above-mentioned Fig. 1,2, insulating barrier 16 partly or entirely containing a reflection layer；Reflection layer is positioned at the centre of insulating barrier 16 or is positioned at the exposed surface of insulating barrier 16.
Due to insulating barrier 16 usually printing opacity thin layer, the setting of reflection layer prevents light from passing through to penetrate outside insulating barrier 16 well.Reflection layer includes one or more in silver layer, aluminium lamination, Prague total reflection film (DBR).
It should be understood that above-mentioned each technical characteristic can use and unrestricted in any combination.
The foregoing is only embodiments of the invention; not thereby the scope of the claims of the present invention is limited; every equivalent structure utilizing description of the present invention and accompanying drawing content to make or equivalence flow process conversion; or directly or indirectly it is used in other relevant technical fields, all in like manner include in the scope of patent protection of the present invention.
Claims (13)
1. a semiconductor luminous chip, including the substrate with first surface and second surface, have at described substrate first surface and at least include the semiconductor laminated of n-type conductive layer, luminescent layer and p-type electric-conducting layer, have at least a n-type electrode groove position exposing partially n-type conductive layer on described semiconductor laminated surface；It is characterized in that, the surface that is partly or entirely exposed, that have electric conductivity of described semiconductor luminous chip and side are wrapped up by least one insulating barrier；
At described surface of insulating layer, it is provided with at least one n-type weld pad being conductively connected with n-type conductive layer and at least one p-type weld pad being conductively connected with p-type electric-conducting layer, insulated from each other between described p-type weld pad and n-type weld pad；
It is provided with n-type metal between at least one described n-type conductive layer surface and described n-type weld pad and fills and leads up layer, and/or, it is provided with p-type metal between at least one described p-type electric-conducting layer surface and described p-type weld pad and fills and leads up layer.
2. semiconductor luminous chip according to claim 1, it is characterised in that the described insulating barrier position of corresponding described n-type conductive layer is provided with the first groove, described first groove is positioned at described n-type electrode groove position through to described n-type conductive layer；Described n-type metal is filled and led up layer and is positioned at described n-type electrode groove position and fills described first groove；
The described insulating barrier position of corresponding described p-type electric-conducting layer is provided with the second groove, described second through to the described p-type electric-conducting layer of groove；Described p-type metal is filled and led up layer and is filled in described second groove.
3. semiconductor luminous chip according to claim 2, it is characterized in that, described n-type metal is filled and led up layer and is included being filled in described first groove and the first n-type metal of being conductively connected with described n-type conductive layer fills and leads up layer and the second n-type metal of being filled in described n-type electrode groove position fills and leads up layer；
Described second n-type metal is filled and led up layer and is filled and led up between layer and described n-type weld pad at described first n-type metal, and fills and leads up layer with described first n-type metal and described n-type weld pad is conductively connected.
4. semiconductor luminous chip according to claim 2, it is characterised in that described n-type metal is filled and led up layer and included metal and fill and lead up layer, this metal is filled and led up layer and is arranged in described n-type electrode groove position and is conductively connected by described first groove and described n-type conductive layer.
5. semiconductor luminous chip according to claim 4, it is characterised in that described n-type metal is filled and led up layer and also included being wrapped in the centre that described metal fills and leads up layer peripheral and fill and lead up layer；
Described centre fills and leads up layer and described metal fills and leads up layer and n-type weld pad is conductively connected.
6. semiconductor luminous chip according to claim 5, it is characterised in that described centre is filled and led up layer and adopted a kind of or several metal in chromium, nickel, titanium, tungsten, platinum, molybdenum, palladium and/or their alloy to make.
7. semiconductor luminous chip according to claim 2, it is characterised in that be provided with a p-type current extending between described p-type electric-conducting layer surface and described insulating barrier；Described p-type metal is filled and led up layer and is conductively connected with described p-type current extending；And/or,
A n-type current extending it is provided with between described bottom surface, n-type electrode groove position and described insulating barrier；Described n-type metal is filled and led up layer and is conductively connected with described n-type current extending；
Described p-type current extending includes one or more in p-type electric-conducting extension layer, p-type reflecting layer, P type contact layer；Described n-type current extending includes one or more in n-type conductive extension layer, n-type reflecting layer, n-contact layer；Or,
Described p-type current extending includes p-type reflecting layer, and described n-type current extending includes n-type reflecting layer, and described semiconductor luminous chip is front and/or side goes out light；Or, described p-type current extending includes p-type electric-conducting extension layer and/or P type contact layer；Described n-type current extending includes n-type conductive extension layer and/or n-contact layer, and described semiconductor luminous chip is that front, the back side and/or side go out light.
8. semiconductor luminous chip according to claim 1, it is characterized in that, this semiconductor luminous chip also includes at least one n-type electrode and at least one p-type electrode, between described n-type electrode and p-type electrode insulated from each other, and run through described insulating barrier and be conductively connected with described n-type conductive layer and p-type electric-conducting layer respectively；
Described n-type electrode is positioned at described n-type electrode groove position, described n-type metal is filled and led up layer and is wrapped in described n-type electrode periphery, and be conductively connected with described n-type weld pad, described n-type weld pad fills and leads up layer and n-type electrode by described n-type metal and described n-type conductive layer is conductively connected；
Described p-type metal is filled and led up layer and is wrapped in described p-type electrode periphery, and is conductively connected with described p-type weld pad, and described p-type weld pad is filled and led up layer and p-type electrode by described p-type metal and is conductively connected with described p-type electric-conducting layer.
9. semiconductor luminous chip according to claim 8, it is characterised in that be provided with a p-type current extending between described p-type electric-conducting layer surface and described insulating barrier；Described p-type electrode and described p-type current extending are conductively connected；And/or,
A n-type current extending it is provided with between described bottom surface, n-type electrode groove position and described insulating barrier；Described n-type electrode and described n-type current extending are conductively connected；
Described p-type current extending includes one or more in p-type electric-conducting extension layer, p-type reflecting layer, P type contact layer；Described n-type current extending includes one or more in n-type conductive extension layer, n-type reflecting layer, n-contact layer.
10. semiconductor luminous chip according to claim 8, it is characterized in that, the Metal Substrate heat conduction weld pad being at least close to described surface of insulating layer it is provided with between described n-type electrode and described p-type electrode, insulated from each other between described Metal Substrate heat conduction weld pad and described n-type electrode and p-type electrode.
11. according to the semiconductor luminous chip described in any one of claim 1-10, it is characterized in that, at least one described p-type weld pad and/or at least one described n-type weld pad extend to the outside side surface of described semiconductor luminous chip, part or all of side surface in described outside forms corresponding side weld pad, has at least one described insulating barrier between described side weld pad and described side surface；And/or,
The Metal Substrate heat conduction weld pad being at least close to described surface of insulating layer it is provided with between described n-type weld pad and p-type weld pad, insulated from each other between described Metal Substrate heat conduction weld pad and described n-type weld pad and p-type weld pad；And/or,
This semiconductor luminous chip surrounding has an indent；Described indent is positioned at described semiconductor laminated side, and the bottom surface of described indent is positioned at described substrate first surface or described substrate, described indent side and bottom surface and is wrapped up by least one described insulating barrier.
12. according to the semiconductor luminous chip described in any one of claim 1-10, it is characterised in that the part or all of of described insulating barrier contains a reflection layer；Described reflection layer is positioned at the centre of described insulating barrier or is positioned at the exposed surface of described insulating barrier.
13. according to the semiconductor luminous chip described in any one of claim 1-10, it is characterised in that described substrate is light-transmissive substrates；Described substrate first surface and/or second surface are smooth finished surfaces or patterned surface；Described patterned surface includes one or more in taper rough surface, convex-concave surface, pyramid shape surface；And/or,
Described side of substrate and/or described semiconductor laminated side is vertical with described substrate first surface or the smooth flat of oblique, smooth surface, structuring plane or structuring curved surface；Described structuring includes one or more in concavo-convex, sawtooth.
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