CN105742453A - Led chip and preparation method thereof - Google Patents
Led chip and preparation method thereof Download PDFInfo
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- CN105742453A CN105742453A CN201410738682.6A CN201410738682A CN105742453A CN 105742453 A CN105742453 A CN 105742453A CN 201410738682 A CN201410738682 A CN 201410738682A CN 105742453 A CN105742453 A CN 105742453A
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Abstract
The present invention provides a LED chip. The LED chip comprises a substrate, and a buffer layer, N-type semiconductor layer, a luminescent layer, a P-type semiconductor layer and a transparent conducting layer arranged on the substrate. The transparent conducting layer is a stair-step transparent conducting layer; a P-type electrode is located at the uppermost end of the stair-step transparent conducting layer and is electrically connected with the transparent conducting layer; and a N-type electrode is located at the side of the lowermost end of the stair-step transparent conducting layer and is electrically connected with the N-type semiconductor layer. Through arrangement of a stair-step transparent conducting layer, the LED chip is able to effectively reduce the current congestion to improve the luminescence efficiency of the chip, prolong the service life and enhance the stability. The present invention further provides the preparation method of the LED chip.
Description
Technical field
The invention belongs to semiconductor applications, particularly relate to a kind of LED chip and preparation method.
Background technology
LED(LightingEmittingDiode, light emitting diode) chip is the core texture of LED, at present, LED chip adopts sapphire as substrate mostly, as it is shown in figure 1, chip structure includes: (1), difference deposit epitaxial layers on saphire substrate material, it is followed successively by cushion, N-type GaN layer from top to bottom, MQW(MultipleQuantumWells, MQW) luminescent layer, P type GaN layer.(2), chip is etched to N-type GaN layer from P type GaN layer, etch areas is prepared N electrode and negative pole.(3), in P type GaN layer, ITO(Indiumtinoxide, tin indium oxide are deposited) layer, prepare P electrode and positive pole on the ito layer, wherein, on ITO layer, include silicon dioxide passivation layer.
But, LED chip for horizontal structure as shown in Figure 1, current spread is very uneven, producing the uneven reason of current spread, to be primarily due to the resistivity difference of P type GaN and N-type GaN very big, when electric current flows through P type GaN layer, it is substantially free of horizontal proliferation, the problem therefore solving current spread on P type GaN surface by transparent conductive layer.But, as shown in Figure 2, when electric current spreads through P type GaN layer, owing to the resistivity of ITO layer is relatively low, electric current can be collected at the region near negative pole in a large number through ITO horizontal proliferation, and get congestion phenomenon, causes this portion of electrical current density excessive, and then affect the stability of chip, reduce its light efficiency and service life.
Specifically, as it is shown on figure 3, be the path model of LED chip current direction in correlation technique.Occurring that the region of electric current horizontal proliferation only has ITO layer and N-type GaN layer, wherein, ITO layer resistance is set to dt, and N-type GaN layer resistance is set to dx, P type GaN layer resistance and is set to R1, and PN junction step resistance is set to R2.Due to resistivity less than N-type GaN of the resistivity of conventional ITO material, wherein, the resistivity of ITO is at the 10-4 order of magnitude, and the resistivity of N-type GaN layer is 10-2-10-3The order of magnitude, therefore electric current preferentially by ITO horizontal proliferation to the L path in region such as Fig. 3 of negative pole, can cause electric current to block up in the region near negative pole.
Electric current for the LED chip of horizontal structure can block up in the shortcoming in the region near electrode, discloses the scheme of a kind of improvement in the related.As shown in Figure 4, in the related, based on said chip structure, complete hole on the ito layer, density distribution is there is in hole from positive to negative pole, the making of hole enables current to be uniformly injected into whole LED chip as far as possible so that it is works in the state of uniformly light-emitting, improves the luminous efficiency of LED chip.
Although make hole on ITO layer surface, alleviate electric current preferentially to the non-uniform phenomenon of negative regions diffusion, but, equally exist some problems, for instance, the local diffusion of ITO layer surface current is uneven, electric current can preferentially flow to the region not having ITO hole, that is: on ITO, imperforate zone current density is big, and pertusate zone current density is little, thus will also result in the inhomogeneities of current spread.
Summary of the invention
It is contemplated that solve one of above-mentioned technical problem at least to a certain extent.For this, the present invention proposes a kind of LED chip, and this LED chip can effectively reduce electric current and block up so that current spread is more uniform, and luminous efficiency is improved, and life-span length, stability are strengthened.
The preparation method that the present invention also proposes this LED chip a kind of.
For solving the problems referred to above, one aspect of the present invention embodiment proposes a kind of LED chip, including: substrate；Including cushion, n type semiconductor layer, luminescent layer, p type semiconductor layer and transparency conducting layer successively in described substrate, wherein, described transparency conducting layer is stepped transparency conducting layer；P-type electrode, is positioned at the top of described stepped transparency conducting layer and electrically connects with transparency conducting layer；N-type electrode, is positioned at the side of the bottom of described stepped transparency conducting layer and electrically connects with described n type semiconductor layer.
Structure based on the LED chip of above-mentioned aspect embodiment, another aspect of the present invention embodiment propose a kind of LED chip preparation method, this preparation method comprises the following steps: on substrate successively epitaxial growth buffer, n type semiconductor layer, luminescent layer and p type semiconductor layer to obtain epitaxial wafer；Described epitaxial wafer is produced PN junction step；Preparing transparency conducting layer on epitaxial wafer after producing described PN junction step, described transparency conducting layer is stepped transparency conducting layer；P electrode is formed in the top of described stepped transparency conducting layer；PN junction step is formed N electrode.
LED chip according to embodiments of the present invention, by arranging stair-stepping transparency conducting layer, it is possible to effectively reducing electric current and block up, and then the luminous efficiency of chip is improved, life-span length, stability are strengthened.
The additional aspect of the present invention and advantage will part provide in the following description, and part will become apparent from the description below, or is recognized by the practice of the present invention.
Accompanying drawing explanation
The present invention above-mentioned and/or that add aspect and advantage will be apparent from easy to understand from the following description of the accompanying drawings of embodiments, wherein:
Fig. 1 is the structural representation of a kind of LED chip of prior art；
Fig. 2 is that the electric current of the LED chip of prior art blocks up schematic diagram；
Fig. 3 is the current spread schematic equivalent circuit of the LED chip of prior art；
Fig. 4 is the pore space structure schematic diagram in the ITO layer of the LED chip of prior art；
Fig. 5 is the structural representation of LED chip according to an embodiment of the invention；
Fig. 6 is the sectional view of the transparency conducting layer of the LED chip of a specific embodiment according to the present invention；
Fig. 7 is the top view on the transparency conducting layer of the LED chip of a specific embodiment according to the present invention；
Fig. 8 is the structural representation of LED chip according to another embodiment of the invention.
Detailed description of the invention
In order to make technical problem solved by the invention, technical scheme and beneficial effect clearly understand, below in conjunction with embodiment, the present invention is further elaborated.Should be appreciated that specific embodiment described herein is only in order to explain the present invention, is not intended to limit the present invention.
In describing the invention, it will be appreciated that, term " " center ", " longitudinal direction ", " transverse direction ", " length ", " width ", " thickness ", " on ", D score, " front ", " afterwards ", " left side ", " right side ", " vertically ", " level ", " top ", " end " " interior ", " outward ", " clockwise ", orientation or the position relationship of the instruction such as " counterclockwise " are based on orientation shown in the drawings or position relationship, it is for only for ease of the description present invention and simplifies description, rather than the device of instruction or hint indication or element must have specific orientation, with specific azimuth configuration and operation, therefore it is not considered as limiting the invention.
Additionally, term " first ", " second " are only for descriptive purposes, and it is not intended that indicate or imply relative importance or the implicit quantity indicating indicated technical characteristic.Thus, define " first ", the feature of " second " can express or implicitly include one or more these features.In describing the invention, " multiple " are meant that two or more, unless otherwise expressly limited specifically.
The preparation method describing LEDN chip and the LED chip proposed according to embodiments of the present invention with reference to the accompanying drawings.
Fig. 5 is the structural representation of LED chip according to an embodiment of the invention.As shown in Figure 5, the LED chip 100 of the embodiment of the present invention includes substrate 10 such as Sapphire Substrate, includes cushion 20, n type semiconductor layer 30 such as N-type GaN layer on substrate 10 successively, luminescent layer 40 such as mqw layer, p type semiconductor layer 50 such as P type GaN layer and transparency conducting layer 60 such as ITO layer, ITO layer plays the effect increasing current spread, wherein, described transparency conducting layer 60 is stepped transparency conducting layer；And, P-type electrode 70 and N-type electrode 80, described P-type electrode 70 is positioned at the top of described stepped transparency conducting layer and electrically connects with transparency conducting layer 60, and described N-type electrode 80 is positioned at the side of the bottom of described stepped transparency conducting layer and electrically connects with described n type semiconductor layer 30.Specifically, in present example, electrode and P-type electrode 70 and N-type electrode 80 can include one or both in Cr/Ti/Au electrode, Cr/Pt/Au electrode and Ti/Al/Ti/Au electrode.
Existing LED chip, owing to the resistivity of transparency conducting layer is relatively low, electric current can be collected at the region near N-type electrode in a large number through transparency conducting layer horizontal proliferation, get congestion phenomenon, cause this portion of electrical current density excessive, and then affect the stability of chip, reduce its light efficiency and service life.For this kind of problem, in one embodiment of the invention, by arranging stair-stepping transparency conducting layer on p type semiconductor layer 50 so that the thickness of transparency conducting layer 60 is along P-type electrode 70(positive pole) to N-type electrode 80(negative pole) direction be gradually reduced.Specifically, owing to material resistance and cross-sectional area are inversely proportional to, the thickness of transparency conducting layer 60 is more little, and namely cross-sectional area is more little, then the resistance of transparency conducting layer 60 is more big.As shown in Figure 3, electric current when transparency conducting layer 60 is from P-type electrode region to the horizontal proliferation of N-type electrode region by more and more difficult, will not preferentially through transparency conducting layer 60 horizontal proliferation to N-type electrode region, thus reaching the purpose preventing electric current at N-type electrode region clustering.
The thickness of described transparency conducting layer 60 is 100-300nm, as shown in Figure 6, transparency conducting layer 60 includes multiple step 61, the height of each step 61 can be consistent with width, different adjustment can also be done according to the resistance of transparency conducting layer 60, the number of step 61 is relevant to the surface area of LED chip, can arrange according to actual needs, and the parameter of concrete step 61 should with the resistors match of the resistance of transparency conducting layer 60 such as ITO layer and epitaxial layer n type semiconductor layer 30 such as N-type GaN layer.In one embodiment of the invention, the height of described step 61 is 8-25 μm, and the width of step 61 is 3-10 μm.
Preferably, for instance shown in Fig. 7, the edge of described step 61 is circular arc, then electric current from P-type electrode 70 to the process of N-type electrode 80 horizontal mobility, can whole transparency conducting layer 60 be diffused into more uniformly.It is further preferred that the plurality of step 61 is axisymmetricly, axis of symmetry is P-type electrode 70 and the line at N-type electrode 80 center, and the electrode of conventional LED chips is circular, the Ji Shiqi center, the center of circle of electrode, and certain electrode is not limited merely to the situation of circle.It should be noted that, the conducting layer figure of rule symmetry, advantageously in the diffusion of electric current, can further enhance electric current and uniformly be diffused into the effect of whole transparency conducting layer 60.
Further, as shown in Figure 8, above-mentioned LED chip 100 also includes passivation layer 90, and described passivation layer 90 covers transparency conducting layer 60 and the exposed region of N-type electrode layer 30.Described passivation layer 90 is silicon dioxide layer, and passivation layer 90 can play the effect of protection transparency conducting layer 60, it is also possible to reduce the total reflection of light.
In sum, the LED chip of the embodiment of the present invention, by arranging stair-stepping transparency conducting layer, it is possible to effectively reducing electric current and block up, and then the luminous efficiency of LED chip is improved, life-span length, stability are strengthened.
Based on the structure of the LED chip of above-mentioned aspect embodiment, the preparation method describing the LED chip that embodiment proposes according to a further aspect in the invention with reference to the accompanying drawings.
The preparation method of the LED chip of the embodiment of the present invention comprises the following steps:
S1, over the substrate 10 successively epitaxial growth buffer 20, n type semiconductor layer 30, luminescent layer 40 and p type semiconductor layer 50 to obtain epitaxial wafer.
Specifically, with sapphire for substrate, adopting MOCVD(metal organic chemical vapor deposition) equipment prepares the epitaxial layer of LED, upwards include successively from Sapphire Substrate 10: cushion 20 such as gallium nitride, n type semiconductor layer 30 is N-GaN(n type gallium nitride such as), luminescent layer 40 is MQW(Multiple-quantum hydrazine layer such as) structure, p type semiconductor layer 50 is P-GaN(p type gallium nitride such as).
S2, produces PN junction step on epitaxial wafer, and prepares transparency conducting layer on the epitaxial wafer after producing PN junction step.
Specifically, epitaxial wafer is produced PN junction step to specifically include: on epitaxial wafer, prepare mask by photoetching method, for instance, adopt positive photoresist epitaxial wafer surface to carry out photoetching to make mask, expose the position needing etching.And then the epitaxial wafer with mask is performed etching until n type semiconductor layer 30 is to obtain PN junction step, such as, utilize ICP(InductiveCoupledPlasmaEmissionSpectrometer, inductively coupled plasma) epitaxial wafer with mask carries out dry etching by etching machine, etch period is such as 10-14 minute, and etching depth reaches 1.2-1.6um, after having etched, remove residual photoresist, namely obtain PN junction step.
S3, the epitaxial wafer after producing described PN junction step is prepared transparency conducting layer 60, and described transparency conducting layer 60 is stepped transparency conducting layer；
Epitaxial wafer after producing PN junction step is prepared transparency conducting layer 60, specifically include: adopt evaporation coating method to be deposited with transparency conducting layer 60 on the epitaxial wafer producing after PN junction step, such as, the epitaxial wafer having made PN junction step is carried out chemical solution surface treatment, it is then placed in evaporator and carries out being deposited with to form transparency conducting layer such as ito thin film, the final thickness 100-300nm of transparency conducting layer and thin film, and then be annealed processing in nitrogen atmosphere to transparency conducting layer, such as, annealing is in pure nitrogen gas atmosphere, annealing temperature is 450-540 DEG C, annealing time is 20-40 minute.Finally, the epitaxial wafer after annealing is performed etching, for instance, need the region retained in yellow light area with positive photoresist protection, remove the region that need not protect with ITO etching liquid, complete ITO and prepare, it is thus achieved that transparency conducting layer.
Further, transparency conducting layer 60 is fabricated to stair-stepping transparency conducting layer.Specifically, for instance, utilize yellow light area photoetching technique, transparency conducting layer such as ITO layer make mask, to expose the region of first step needing making, and then use ITO etching liquid that the part exposed is performed etching, control etching liquid concentration, temperature and soak time, to control height and the width of step, the shape of step can be square or circular arc, in one embodiment of the invention, the height of step is 8-25 μm, and the width of step is 3-10 μm.Repeating said process, prepare second, the 3rd ... n-th step, concrete step parameter should be mated with transparency conducting layer resistance sizes and n type semiconductor layer resistance sizes.After having etched, get rid of the photoresist of remnants.
S4, forms P-type electrode 70 in the top of described stepped transparency conducting layer.
S5, forms N-type electrode 80 on PN junction step.
Specifically, first, photoetching method is adopted to obtain electrode mask on epitaxial wafer, such as, in yellow light area, negative photoresist is utilized epitaxial wafer to carry out photoetching to prepare electrode mask, to expose the region needing to prepare electrode, namely prepare P electrode in the region of the top of stepped transparency conducting layer, PN junction step is prepared N electrode.Then, evaporation coating method is adopted to prepare P-type electrode and N-type electrode respectively, the epitaxial wafer preparing mask being put into metal evaporation machine be deposited with, wherein, electrode material can be one or both in Cr Ti Au, Cr Pt Au and Ti Al Ti Au.
After evaporation completes, remove electrode mask, and after removing described electrode mask, in nitrogen atmosphere, epitaxial wafer being carried out heat treatment, wherein, heat treatment temperature is 280-350 DEG C, time is 15-25 minute, after carrying out alloy heat treatment, complete the preparation of electrode, prepare P-type electrode and N-type electrode as shown in Figure 5.
It addition, after preparation P-type electrode 70 and N-type electrode 80, in order to protect LED chip and reduce the total reflection of emergent light, above-mentioned preparation method can also include:
S6, the exposed region at transparency conducting layer 60 and n type semiconductor layer 30 forms passivation layer 90.
Specifically, passivation layer 90 can be silicon dioxide layer.Making the epitaxial wafer surface PECVD(PlasmaEnhancedChemicalVaporDeposition of electrode, plasma enhanced chemical vapor deposition) equipment one layer of SiO of deposition2, the thickness of silicon dioxide layer is 50-100nm.And then adopt photoetching, lithographic method to process passivation layer to obtain electrode part, for instance, make mask to expose electrode part by photoetching technique, use HF-NH4F cushions etching liquid and gets rid of the SiO of expose portion2, after having etched, get rid of the photoresist of remnants, namely obtain the LED chip of deposit passivation layer as shown in Figure 8, then complete the preparation of whole LED chip.
The preparation method of LED chip according to embodiments of the present invention, on LED chip, stair-stepping transparency conducting layer is formed by photoetching, lithographic method, the electric current that can reduce LED chip blocks up, and compared with the chip that hole is set, current spread is more uniform, and then the luminous efficiency of raising chip, extend the life-span of LED chip, strengthen the stability of chip.
In the description of this specification, specific features, structure, material or feature that the description of reference term " embodiment ", " some embodiments ", " example ", " concrete example " or " some examples " etc. means in conjunction with this embodiment or example describe are contained at least one embodiment or the example of the present invention.And, the specific features of description, structure, material or feature can combine in an appropriate manner in any one or more embodiments or example.Although above it has been shown and described that embodiments of the invention, but above-described embodiment is not considered as limiting the invention, above-described embodiment can be changed when without departing from principles of the invention and objective, revises, replace and modification by those of ordinary skill in the art within the scope of the invention.
Claims (10)
1. a LED chip, it is characterised in that including:
Substrate；
Including cushion, n type semiconductor layer, luminescent layer, p type semiconductor layer and transparency conducting layer successively in described substrate, wherein, described transparency conducting layer is stepped transparency conducting layer；
P-type electrode, is positioned at the top of described stepped transparency conducting layer and electrically connects with transparency conducting layer；
N-type electrode, is positioned at the side of the bottom of described stepped transparency conducting layer and electrically connects with described n type semiconductor layer.
2. LED chip as claimed in claim 1, it is characterised in that described transparency conducting layer includes multiple step, and the edge of the plurality of step is circular arc.
3. LED chip as claimed in claim 2, it is characterised in that axisymmetricly, axis of symmetry is P-type electrode and the line at N-type electrode center to the plurality of step.
4. LED chip as claimed in claim 1, it is characterised in that described transparency conducting layer includes multiple step, and the height of described step is 8-25 μm, and the width of described step is 3-10 μm.
5. LED chip as claimed in claim 1, it is characterised in that also include:
Passivation layer, described passivation layer covers transparency conducting layer and the exposed region of N-type electrode layer.
6. the preparation method of a LED chip, it is characterised in that comprise the following steps:
On substrate successively epitaxial growth buffer, n type semiconductor layer, luminescent layer and p type semiconductor layer to obtain epitaxial wafer；
Described epitaxial wafer is produced PN junction step；
Preparing transparency conducting layer on epitaxial wafer after producing described PN junction step, described transparency conducting layer is stepped transparency conducting layer；
P electrode is formed in the top of described stepped transparency conducting layer；
PN junction step is formed N electrode.
7. the preparation method of LED chip as claimed in claim 6, it is characterised in that described transparency conducting layer includes multiple step, and the edge of the plurality of step is circular arc type.
8. the preparation method of LED chip as claimed in claim 7, it is characterised in that axisymmetricly, axis of symmetry is P-type electrode and the line at N-type electrode center to the plurality of step.
9. the preparation method of LED chip as claimed in claim 6, it is characterised in that described transparency conducting layer includes multiple step, and the height of described step is 8-25 μm, and the width of described step is 3-10 μm.
10. the preparation method of LED chip as claimed in claim 6, it is characterised in that also include:
Exposed region at transparency conducting layer and N-type electrode layer forms passivation layer.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109065688A (en) * | 2018-06-29 | 2018-12-21 | 苏州新纳晶光电有限公司 | A kind of high light efficiency LED chip and preparation method thereof |
| CN109962130A (en) * | 2019-04-15 | 2019-07-02 | 扬州乾照光电有限公司 | A kind of the infrared LED chip and production method of the roughening of six faces |
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| JP2008227109A (en) * | 2007-03-12 | 2008-09-25 | Mitsubishi Chemicals Corp | GaN-BASED LED ELEMENT AND LIGHT-EMITTING DEVICE |
| CN101834247A (en) * | 2009-03-03 | 2010-09-15 | Lg伊诺特有限公司 | Light emitting device, light emitting device package and lighting system including the same |
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| JP2008227109A (en) * | 2007-03-12 | 2008-09-25 | Mitsubishi Chemicals Corp | GaN-BASED LED ELEMENT AND LIGHT-EMITTING DEVICE |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109065688A (en) * | 2018-06-29 | 2018-12-21 | 苏州新纳晶光电有限公司 | A kind of high light efficiency LED chip and preparation method thereof |
| CN109962130A (en) * | 2019-04-15 | 2019-07-02 | 扬州乾照光电有限公司 | A kind of the infrared LED chip and production method of the roughening of six faces |
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Application publication date: 20160706 |