CN105742352A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN105742352A CN105742352A CN201410759094.0A CN201410759094A CN105742352A CN 105742352 A CN105742352 A CN 105742352A CN 201410759094 A CN201410759094 A CN 201410759094A CN 105742352 A CN105742352 A CN 105742352A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 title claims description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 230000001105 regulatory effect Effects 0.000 claims description 46
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 230000000694 effects Effects 0.000 abstract description 12
- 239000000969 carrier Substances 0.000 abstract 1
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- 239000010410 layer Substances 0.000 description 33
- 239000000463 material Substances 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 229910052747 lanthanoid Inorganic materials 0.000 description 6
- 150000002602 lanthanoids Chemical class 0.000 description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- -1 titanium aluminum carbon Chemical compound 0.000 description 5
- 229910000838 Al alloy Inorganic materials 0.000 description 4
- 229910001339 C alloy Inorganic materials 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000010276 construction Methods 0.000 description 3
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 3
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
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- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
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- 239000002019 doping agent Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
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- 239000005297 pyrex Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides a semiconductor device, including: a semiconductor substrate; a gate dielectric layer on the substrate; a gate structure on the gate dielectric layer; source and drain regions on both sides of the gate structure; the grid structure comprises a first grid and a second grid, the first grid is positioned on a grid dielectric layer on the inner side of the source drain region, the second grid is positioned on a grid dielectric layer between the first grids, the effective work function of the first grid is smaller than that of the second grid for NMOS, and the effective work function of the first grid is larger than that of the second grid for PMOS. In the invention, before the device of the second grid is conducted, a region with more carriers is induced in the substrate under the first grid, which is equivalent to a source drain extension region, and the junction depth of the source drain extension region is shallow, so that the short channel effect can be effectively inhibited, the static power consumption of the device is reduced, and the performance of the device is improved.
Description
Technical field
The present invention relates to field of semiconductor devices, particularly to a kind of semiconductor device and manufacture method thereof.
Background technology
Highly integrated along with semiconductor device, MOSFET channel length constantly shortens, a series of in MOSFET long raceway groove model negligible effect become more notable, even become the leading factor affecting device performance and power consumption, this phenomenon is referred to as short-channel effect.Short-channel effect can worsen the electrology characteristic of device, has a strong impact on performance and the power consumption of device.
In order to control short-channel effect, it is necessary to take to improve to some aspects of traditional devices, in theory, can pass through to reduce the degree of depth of source drain junction, reduce threshold voltage shorten with raceway groove and the amplitude that drops, reduce the drain electric impact on groove potential, thus alleviating short-channel effect.
Summary of the invention
The purpose of the present invention aims to solve the problem that above-mentioned technological deficiency, it is provided that a kind of semiconductor device and manufacture method thereof, it is suppressed that short-channel effect.
The invention provides a kind of semiconductor device, including:
Semiconductor substrate；
Gate dielectric layer on substrate；
Grid structure on gate dielectric layer；
The source-drain area of grid structure both sides；
Wherein, grid structure includes first grid and second grid, first grid is positioned on the gate dielectric layer inside source-drain area, on second grid gate dielectric layer between first grid, for NMOS, the effective work function of first grid is less than the effective work function of second grid, and for PMOS, the effective work function of first grid is more than the effective work function of second grid.
Optionally, the long scope of the grid of described first grid is respectively 2-40nm.
Optionally, described first grid is the first work function regulating course, and described second grid includes the second work function regulating course and the 3rd metal level thereon.
Optionally, for nmos device, the effective work function of the first work function regulating course is less than 4.6eV, and for PMOS device, the effective work function of the first work function regulating course is more than 4.6eV.
Optionally, the second work function regulating course is formed on the gate dielectric layer on the sidewall of the first work function regulating course and between the first work function regulating course.
Additionally, present invention also offers the manufacture method of a kind of semiconductor device, including:
Semiconductor substrate is provided, substrate is formed pseudo-grid region and the source-drain area of pseudo-both sides, grid region；
Remove pseudo-grid region, to form opening；
The sidewall of described opening is formed first grid；
Fill opening, to form second grid in the opening；
Wherein, for NMOS, the effective work function of first grid is less than the effective work function of second grid, and for PMOS, the effective work function of first grid is more than the effective work function of second grid.
Optionally, the long scope of the grid of described first grid is respectively 2-40nm.
Optionally, described first grid is the first work function regulating course.
Optionally, the step forming second grid includes: forms the second work function regulating course on the inner surface of opening, and fills opening with the 3rd metal level, to form second grid.
Optionally, for nmos device, the effective work function of the first work function regulating course is less than 4.6eV, and for PMOS device, the effective work function of the first work function regulating course is more than 4.6eV.
The semiconductor device of embodiment of the present invention offer and manufacture method thereof, gate dielectric layer inside source-drain area defines first grid, and the gate dielectric layer between first grid defines second grid, owing to first grid and second grid have different effective work functions, after device powers on, the threshold voltage of first grid is less than the threshold voltage of second grid, before the break-over of device of second grid, the region that carrier becomes many can be induced in the substrate under first grid, be equivalent to define source drain extension district, the junction depth in this source drain extension district is very shallow, can effectively suppress short-channel effect, reduce the quiescent dissipation of device, improve the performance of device.
Accompanying drawing explanation
The present invention above-mentioned and/or that add aspect and advantage will be apparent from easy to understand from the following description of the accompanying drawings of embodiments, wherein:
Fig. 1 illustrates the structural representation of semiconductor device according to embodiments of the present invention；
Fig. 2 illustrates structural representation when semiconductor device according to embodiments of the present invention powers on；
Fig. 3 illustrates the flow chart of the manufacture method of semiconductor device according to embodiments of the present invention；
Fig. 4-12 illustrates the structural representation of each formation stages of semiconductor device according to embodiments of the present invention.
Detailed description of the invention
Being described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has the element of same or like function from start to finish.The embodiment described below with reference to accompanying drawing is illustrative of, and is only used for explaining the present invention, and is not construed as limiting the claims.
It is desirable to provide a kind of semiconductor device, effectively to suppress short-channel effect.With reference to shown in Fig. 1, this device includes: Semiconductor substrate 100；Gate dielectric layer 104 on substrate 100；Grid structure on gate dielectric layer 104；The source-drain area 140 of grid structure both sides；Wherein, grid structure includes first grid 120 and second grid 130, first grid 120 is positioned on the gate dielectric layer 104 inside source-drain area 140, on the second grid 130 gate dielectric layer 104 between first grid 120, for NMOS, the effective work function of first grid 120 is less than the effective work function of second grid 130, and for PMOS, the effective work function of first grid 120 is more than the effective work function of second grid 130.
In the present invention, first grid 120 can be one or more layers structure, and it is positioned on the gate dielectric layer 104 of substrate inside source-drain area 140, is equivalent on the region in source drain extension district of usual device, and width (i.e. grid length) can be 2-40 nanometer.Second grid 130 can be one or more layers structure, on its gate dielectric layer 104 between first grid 120, is equivalent on the channel region of usual device.In the particular embodiment, first grid can surround second grid, or is positioned at the both sides of second grid, is clipped in by second grid wherein, and the width (grid length) of this first grid refers to the width d of the first grid 120 of the every side of second grid 130.
Wherein, first grid and second grid have different effective work functions, and for NMOS, the effective work function of first grid is less than the effective work function of second grid, and for PMOS, the effective work function of first grid is more than the effective work function of second grid.
In the particular embodiment, the effective work function of first grid and second grid can be mainly regulated by work function regulating course, in the present embodiment, with reference to shown in Figure 12, first grid 120 is single layer structure, it is the first work function regulating course 120-1, second grid 130 includes the second work function regulating course 130-1 and the 3rd metal level 130-2 thereon, wherein, first and second work function regulating courses adopt the gate material with work function adjustment effect, and the 3rd metal level adopts other grid material to complete to fill.
In the present embodiment, for nmos device, first work function regulating course 120-1 can adopt the effective work function metal gate material less than 4.6eV, the metal gate material less than 4.6eV such as can select aluminum (Al), titanium-aluminium alloy (TiAl), titanium aluminum carbon alloy (TiAlC), lanthanide series nitride, mixed with the titanium nitride (TiN) etc. of phosphorus (P) or lanthanide series or their combination；Second work function regulating course 130-1 adopts effective work function more than the metal gate material of the first work function regulating course, for instance can select titanium nitride (TiN) etc. or their combination of aluminum (Al), titanium-aluminium alloy (TiAl), titanium aluminum carbon alloy (TiAlC), the nitride of lanthanide series, p-doped (P) or lanthanide series.
In the present embodiment, for PMOS device, first work function regulating course 120-1 can adopt the effective work function metal gate material more than 4.6eV, metal gate material more than 4.6eV such as can select molybdenum (Mo), titanium nitride (TiN), the nitride of lanthanide series, mixed with boron (B), indium (In), platinum (Pt), the titanium nitride (TiN) of hafnium (Hf) or aluminum (Al) etc. and their combination thereof, second work function regulating course can adopt the effective work function metal gate material less than the first work function regulating course, such as can select molybdenum (Mo), titanium nitride (TiN), the nitride of lanthanide series, mixed with boron (B), indium (In), platinum (Pt), the titanium nitride (TiN) of hafnium (Hf) or aluminum (Al) and other combination.
In a specific embodiment, pseudo-grid technique is adopted to form grid structure, as shown in figure 12, first grid 120 is the first work function regulating course 120-1, second grid 130 includes the 3rd metal level 130-2 of the second work function regulating course 130-1 and upper filling thereof, second work function regulating course 130-1 is formed on the gate dielectric layer 104 on the sidewall of the first work function regulating course 120-1 and between the first work function regulating course 120-1, in this specific embodiment, first work function regulating course can be titanium-aluminium alloy (TiAl), second work function regulating course can be titanium aluminum carbon alloy (TiAlC).
In the present invention, owing to first grid and second grid have employed different effective work function, make the threshold voltage threshold voltage less than second grid of first grid, after device powers on, with reference to shown in Fig. 2, owing to the threshold voltage of first grid is less than the threshold voltage of second grid, before the break-over of device of second grid, substrate under first grid 120 can induce the region 150 that carrier becomes many, be equivalent to source drain extension district, the junction depth in this source drain extension district is very shallow, can effectively suppress short-channel effect, reduce the quiescent dissipation of device, improve the performance of device.
Above the semiconductor device structure of the present invention is described, additionally, present invention also offers the manufacture method of above-mentioned semiconductor device, with reference to shown in Fig. 3, the method includes: provide Semiconductor substrate, and substrate is formed pseudo-grid region and the source-drain area of pseudo-both sides, grid region；Remove pseudo-grid region, to form opening；The sidewall of described opening is formed first grid；Fill opening, to form second grid in the opening；Wherein, for NMOS, the effective work function of first grid is less than the effective work function of second grid, and for PMOS, the effective work function of first grid is more than the effective work function of second grid.
In order to be better understood from technical scheme and technique effect, below with reference to specific embodiment and manufacture method flow chart Fig. 3, the manufacture method of above-mentioned semiconductor device is described in detail.
First, in step S01, it is provided that Semiconductor substrate 100, substrate is formed with pseudo-grid region and the source-drain area 140 of pseudo-both sides, grid region, with reference to shown in Fig. 5.
In embodiments of the present invention, described Semiconductor substrate 100 can be Si substrate, Ge substrate, SiGe substrate, SOI (silicon-on-insulator, SiliconOnInsulator) or GOI (germanium on insulator, GermaniumOnInsulator) etc..Described Semiconductor substrate can also be the substrate including other elemental semiconductors or compound semiconductor, such as GaAs, InP or SiC etc., it can also be laminated construction, such as Si/SiGe etc., can also be other epitaxial structures, such as SGOI (silicon germanium on insulator), it is also possible to for three-dimensional silicon architecture, for instance silicon fin (Fin) or nano thread structure etc..In the present embodiment, described Semiconductor substrate is body silicon substrate, has been formed with the isolation 102 separated by active area in substrate, as shallow trench isolates (STI) structure.
In the present embodiment, pseudo-grid region can be the laminated construction including pseudo-gate dielectric layer 103 and dummy grid 106, and pseudo-grid region can also be other monolayer or laminated construction in other embodiments, as only included dummy grid, it is sacrifice layer, after its formation after continuous structure, remove it.Concrete, it is possible to form pseudo-grid region and the source-drain area of pseudo-both sides, grid region as follows.
First, the lamination of the pseudo-gate dielectric layer 103 of deposit and dummy grid 106 successively, pseudo-gate dielectric layer 103 can be thermal oxide layer or other suitable dielectric materials, for instance silicon oxide, silicon nitride etc., dummy grid 106 can be non-crystalline silicon, polysilicon, or amorphous carbon etc., and utilize lithographic technique, it is patterned, form pseudo-grid region, as shown in Figure 4, it is different from the device of routine, the grid length that grid length is device of these puppet grid and the long sum of grid for sensing generation source drain extension district.Then, deposit spacer material, side wall can have single or multiple lift structure, can by silicon nitride, silicon oxide, silicon oxynitride, carborundum, boron or phosphorous doped silicon glass, low k dielectric material and combination thereof, and/or other suitable materials are formed, and by after anisotropic etching, the sidewall in pseudo-grid region forms side wall 108, as shown in Figure 4.Then, can pass through according to desired transistor arrangement, implanted with p-type or n-type dopant or impurity are in the substrate of pseudo-both sides, grid region, and activate doping by thermal annealing, to form source-drain area 140, as it is shown in figure 5, with conventional device technique the difference is that, in the present invention, do not carry out the doping in source drain extension district.Certainly, in other embodiments, it would however also be possible to employ the mode of extension forms source-drain area.
Then, in step S02, pseudo-grid region is removed, to form opening 114, with reference to shown in Fig. 8.
In the present embodiment, after forming interlayer dielectric layer, remove pseudo-grid region, form opening.Concrete, first, as shown in Figure 6, it is possible on above-mentioned device can the material of the first contact etching stop layer such as deposit silicon nitride or silicon oxynitride, form contact etching stop layer 110 (CESL, ContactEtchingStopLayer)；Then, the material 112 of interlayer dielectric layer is covered, for instance unadulterated silicon oxide (SiO2), doping silicon oxide (such as Pyrex, boron-phosphorosilicate glass etc.) or other low k dielectric materials；Then, planarize, for instance cmp, until exposing dummy grid 106, thus, source-drain area 104 defines contact etching stop layer 110, and covers interlayer dielectric layer 112 thereon, as shown in Figure 7.
Then, lithographic technique can be used, remove the dummy grid 106 of non-crystalline silicon, in the particular embodiment, such as use the etching solution wet etching including Tetramethylammonium hydroxide (TMAH) to remove the dummy grid of polysilicon, and further puppet gate dielectric layer 103 is removed, until exposing substrate, thus forming opening 114, as shown in Figure 8.Certainly, in other embodiments, this puppet grid region can only include dummy grid, and the gate dielectric layer under it can not also be removed, and directly again forms replacement gate on the gate dielectric layers.
Then, in step S03, the sidewall of described opening forms the first grid 120 with the first work-function layer, with reference to shown in Figure 10.
In the present embodiment, concrete, first, the substrate of opening 114 first passes through aoxidize and form boundary layer 105, and carry out the deposit of gate dielectric material 104, as shown in Figure 9, gate dielectric material be such as high K medium material (such as, compare with silicon oxide, there is the material of high-k) or other suitable dielectric materials, high K medium material is hafnio oxide, zirconio oxide, aluminium oxide, lanthanide oxide etc. such as；Then, carrying out the deposit of the first work function regulating course 120-1, this first work function regulating course can be titanium-aluminium alloy (TiAl), and thickness can be 2-40 nanometer.The grid that this thickness determines first grid are long, and device formed after sense the length in source drain extension district of formation, then, carry out anisotropic etching, such as RIE, thus only defining the first grid of the first work function regulating course 120-1 on the sidewall of opening, as shown in Figure 10.
Then, in step S04, fill opening, form second grid 130, wherein, for NMOS, the effective work function of first grid is less than the effective work function of second grid, for PMOS, the effective work function of first grid is more than the effective work function of second grid, with reference to shown in Figure 12.
In the present embodiment, concrete, first, as shown in figure 11, deposit the second work function regulating course 130-1, this second work function regulating course 130-1 can be titanium aluminum carbon alloy (TiAlC), and thickness can be 1-10 nanometer.Then, fill the 3rd metal level 130-2, and carry out planarization process, such as CMP, until exposing interlayer dielectric layer 112, as shown in figure 12, thus, form the second grid including the second work function regulating course 130-1 and the three metal level 130-2.
So far, the semiconductor device of the embodiment of the present invention is defined.Then, it is possible to as required, other structures of device are formed, such as source and drain contact, gate contact etc..
The above, be only presently preferred embodiments of the present invention, and the present invention not does any pro forma restriction.
Although the present invention discloses as above with preferred embodiment, but is not limited to the present invention.Any those of ordinary skill in the art, without departing from, under technical solution of the present invention ambit, may utilize the method for the disclosure above and technology contents and technical solution of the present invention is made many possible variations and modification, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content without departing from technical solution of the present invention, the technical spirit of the foundation present invention, to any simple modification made for any of the above embodiments, equivalent variations and modification, all still falls within the scope of technical solution of the present invention protection.
Claims (10)
1. a semiconductor device, it is characterised in that including:
Semiconductor substrate；
Gate dielectric layer on substrate；
Grid structure on gate dielectric layer；
The source-drain area of grid structure both sides；
Wherein, grid structure includes first grid and second grid, first grid is positioned on the gate dielectric layer inside source-drain area, on second grid gate dielectric layer between first grid, for NMOS, the effective work function of first grid is less than the effective work function of second grid, and for PMOS, the effective work function of first grid is more than the effective work function of second grid.
2. semiconductor device according to claim 1, it is characterised in that the long scope of grid of described first grid is respectively 2-40nm.
3. semiconductor device according to claim 1, it is characterised in that described first grid is the first work function regulating course, described second grid includes the second work function regulating course and the 3rd metal level thereon.
4. semiconductor device according to claim 3, it is characterised in that for nmos device, the effective work function of the first work function regulating course is less than 4.6eV, and for PMOS device, the effective work function of the first work function regulating course is more than 4.6eV.
5. semiconductor device according to claim 3, it is characterised in that the second work function regulating course is formed on the gate dielectric layer on the sidewall of the first work function regulating course and between the first work function regulating course.
6. the manufacture method of a semiconductor device, it is characterised in that including:
Semiconductor substrate is provided, substrate is formed pseudo-grid region and the source-drain area of pseudo-both sides, grid region；
Remove pseudo-grid region, to form opening；
The sidewall of described opening is formed first grid；
Fill opening, to form second grid in the opening；
Wherein, for NMOS, the effective work function of first grid is less than the effective work function of second grid, and for PMOS, the effective work function of first grid is more than the effective work function of second grid.
7. manufacture method according to claim 6, it is characterised in that the long scope of grid of described first grid is respectively 2-40nm.
8. manufacture method according to claim 6, it is characterised in that described first grid is the first work function regulating course.
9. manufacture method according to claim 6, it is characterised in that the step forming second grid includes: form the second work function regulating course on the inner surface of opening, and fill opening with the 3rd metal level, to form second grid.
10. manufacture method according to claim 9, it is characterised in that for nmos device, the effective work function of the first work function regulating course is less than 4.6eV, and for PMOS device, the effective work function of the first work function regulating course is more than 4.6eV.
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| US20210351041A1 (en) * | 2018-10-31 | 2021-11-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing semiconductor devices and semiconductor devices |
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| CN1938858A (en) * | 2004-03-31 | 2007-03-28 | 英特尔公司 | Semiconductor device having a laterally modulated gate workfunction and method of fabrication |
| US20120223387A1 (en) * | 2011-03-01 | 2012-09-06 | Tsinghua University | Tunneling device and method for forming the same |
| CN104022035A (en) * | 2013-02-28 | 2014-09-03 | 中芯国际集成电路制造(上海)有限公司 | Transistor and forming method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20210351041A1 (en) * | 2018-10-31 | 2021-11-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing semiconductor devices and semiconductor devices |
| US12020947B2 (en) * | 2018-10-31 | 2024-06-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing semiconductor devices and semiconductor devices |
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