US20150270348A1 - Semiconductor device including superlattice sige/si fin structure - Google Patents
Semiconductor device including superlattice sige/si fin structure Download PDFInfo
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- US20150270348A1 US20150270348A1 US14/732,931 US201514732931A US2015270348A1 US 20150270348 A1 US20150270348 A1 US 20150270348A1 US 201514732931 A US201514732931 A US 201514732931A US 2015270348 A1 US2015270348 A1 US 2015270348A1
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- semiconductor device
- sige
- layer
- fin
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 69
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 59
- 125000006850 spacer group Chemical group 0.000 claims abstract description 35
- 239000012212 insulator Substances 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 30
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims description 28
- 239000002184 metal Substances 0.000 claims description 28
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 239000003989 dielectric material Substances 0.000 claims description 5
- MTPVUVINMAGMJL-UHFFFAOYSA-N trimethyl(1,1,2,2,2-pentafluoroethyl)silane Chemical compound C[Si](C)(C)C(F)(F)C(F)(F)F MTPVUVINMAGMJL-UHFFFAOYSA-N 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 claims 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims 1
- 238000000034 method Methods 0.000 description 30
- 150000002500 ions Chemical class 0.000 description 12
- 239000000463 material Substances 0.000 description 11
- 238000000137 annealing Methods 0.000 description 9
- 238000005530 etching Methods 0.000 description 9
- 238000009413 insulation Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- -1 silicon germanium ions Chemical class 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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Definitions
- the present invention relates to finFET semiconductor devices, and more specifically, to a finFET including a superlattice silicon germanium/silicon (SiGe/Si) fin structure.
- Conventional finFET semiconductor devices include a gate that fully wraps one or more semiconductor fins formed from Si.
- the wrapped gate can improve carrier depletion in the channel defined by the Si fin. Accordingly, electrostatic control of the channel defined by the Si fin may be improved.
- Recent semiconductor fabrication methods have been developed to replace pure Si fins with SiGe fins.
- Forming the fins from SiGe reduces the threshold voltage (Vt) of the semiconductor device, thereby increasing the drive current that flows through the channel.
- SiGe material provides higher carrier mobility than Si. Accordingly, SiGe fins may have improve electron hole mobility performance with respect to Si fins
- Conventional methods use an ion implantation process that drives SiGe ions into the fin to form a SiGe fin. However, these conventional methods may damage the fin and reduce overall performance of the finFET device.
- a method of fabricating a semiconductor device includes forming a semiconductor fin on an insulator layer of a semiconductor-on-insulator (SOI) substrate and forming a gate stack on the semiconductor fin.
- the method further includes etching the SOI substrate to expose an insulator layer to define at least one source/drain region and to expose sidewalls of the semiconductor fin.
- the method further includes growing a silicon germanium (SiGe) layer on the etched sidewalls of the fin.
- the method further includes annealing the semiconductor device to diffuse SiGe ions of the SiGe layer into the fin such that a SiGe fin having a superlattice structure is formed beneath the gate stack.
- a semiconductor device comprises a semiconductor-on-insulator substrate including an insulator layer, and at least one fin having a superlattice silicon germanium/silicon structure.
- the fin is formed on an upper surface of the insulator layer.
- a gate stack is formed on an upper surface of the at least one fin.
- the gate stack includes first and second opposing spacers defining a gate length therebetween.
- First and second epitaxial source/drain structures are formed on the insulator layer. The first and second epitaxial source/drain structures extend beneath the spacer to define a superlattice silicon germanium/silicon gate channel beneath the gate stack.
- FIGS. 1-19 illustrate a process flow of fabricating a semiconductor device according to at least one exemplary embodiment in which:
- FIG. 1 illustrates a semiconductor-on-insulator (SOI) substrate including a semiconductor fin formed on a buried insulation layer and a gate stack formed on the fin;
- SOI semiconductor-on-insulator
- FIG. 2 illustrates the SOI substrate of FIG. 1 following deposition of a hardmask block layer that covers the fin and the gate stack;
- FIG. 3 illustrates the SOI substrate of FIG. 2 after etching the hardmask block layer to form a spacer that covers the gate stack;
- FIG. 4 illustrates the SOI substrate of FIG. 3 after etching the source/drain regions of the fin to expose the underlying buried insulator layer and sidewalls of the fin;
- FIG. 5 illustrates the SOI substrate of FIG. 4 following epitaxial growth of a silicon germanium layer at the etched sidewalls of the fin;
- FIG. 6 illustrates the SOI substrate of FIG. 5 undergoing an annealing process that induces diffusion of silicon germanium ions into the fin;
- FIG. 7 illustrates the SOI substrate of FIG. 6 showing a superlattice silicon germanium/silicon fin extending beneath the gate stack following the diffusion of silicon germanium ions into the fin;
- FIG. 8 illustrates the SOI substrate of FIG. 7 following epitaxially grown source/drain regions
- FIG. 9 illustrates the SOI substrate of FIG. 8 following deposition of a nitride block layer on exposed surfaces of the epitaxially grown source/drain regions and spacer;
- FIG. 10 illustrates the SOI substrate of FIG. 9 after etching the nitride block layer to form spacer extensions on a portion of the spacer;
- FIG. 11 illustrates the SOI substrate of FIG. 10 undergoing a second annealing process to diffuse doped ions of the epitaxially grown source/drain regions into the fin;
- FIG. 12 illustrates the SOI substrate of FIG. 11 following deposition of dielectric layer on upper surfaces of the epitaxially grown source/drain regions, the spacer extensions, and the exposed portion of the spacer;
- FIG. 13 illustrates the SOI substrate of FIG. 12 after etching the dielectric layer and spacer to expose a dummy gate of the gate stack;
- FIG. 14 illustrates the SOI substrate of FIG. 13 following removal of the dummy gate to form a trench in the gate stack
- FIG. 15 illustrates the SOI substrate of FIG. 14 following deposition of a dielectric block layer on an upper surface of the etched dielectric layer and in the trench;
- FIG. 16 illustrates the SOI substrate of FIG. 15 following patterning of the dielectric block layer to form a gate insulation layer in the trench;
- FIG. 17 illustrates the SOI substrate of FIG. 16 following deposition of a metal contact layer on an upper surface of the gate insulation layer;
- FIG. 18 illustrates the SOI substrate of FIG. 17 following deposition of a metal block layer on an upper surface of the metal contact layer and in the trench;
- FIG. 19 illustrates the SOI substrate of FIG. 18 after etching portions of the metal block layer, metal contact layer, gate insulation layer and dielectric layer to expose the epitaxially grown source/drain regions and to form a metal gate above a superlattice silicon germanium/silicon gate channel.
- FIG. 20 is a flow diagram illustrating a method of fabricating a semiconductor device according to an exemplary embodiment.
- the semiconductor device 100 includes a semiconductor-on-insulator (SOI) substrate 102 .
- the SOI substrate 102 may include a bulk substrate layer 103 and a buried insulator layer 104 .
- the bulk substrate layer 103 may be formed from a semiconductor material such as silicon (Si), for example.
- the buried insulator layer 104 may be formed from, for example, an oxide material to form a buried oxide (BOX) layer as understood by those ordinarily skilled in the art.
- One or more semiconductor fins 106 are formed on the buried insulator layer 104 .
- the semiconductor fins 106 may be formed by etching an active semiconductor block layer (not shown) formed on the buried insulator layer 104 using a sidewall image transfer (SIT) process as understood by those ordinarily skilled in the art.
- an active silicon (Si) layer (not shown) may be formed on the buried insulator layer 104 to form a semiconductor fin 106 made from Si.
- a dummy gate stack 108 is formed to wrap around the upper surface and sides of the semiconductor fins 106 . Accordingly, a portion of the fin formed beneath the dummy gate stack 108 defines a gate channel interposed between exposed portions of the semiconductor fin 106 .
- the exposed portions of the semiconductor fin 106 define a first source/drain (S/D) region 112 and a second source/drain (S/D) region 112 ′.
- the dummy gate stack 108 further includes a gate insulator 110 interposed between a dummy gate 113 and the semiconductor fin 106 .
- the gate insulator 110 may be formed from silicon oxide (SiO 2 ), for example.
- the dummy gate 113 may be formed from a polysilicon material, which may be replaced according to a replacement metal gate (RMG) process as understood by those ordinarily skilled in the art.
- RMG replacement metal gate
- a hardmask block layer 114 is deposited on the semiconductor device 100 .
- the hardmask block layer 114 covers the semiconductor fin 106 and the dummy gate stack 108 .
- the hardmask block layer 114 may be formed from various masking materials including, but not limited to, silicon nitride (Si 3 N 4 ).
- the hardmask block layer 114 may be deposited using, for example, chemical vapor deposition (CVD).
- the hardmask block layer 114 is etched to form a spacer 116 that covers the dummy gate stack 108 and a portion of the semiconductor fin 106 .
- the hardmask block layer 114 may be etched using, for example, a reactive ion etching (RIE) technique.
- RIE reactive ion etching
- the thickness of the spacer 116 sidewalls defines an effective offset distance between the exposed surface of the first and second S/D regions 112 / 112 ′, and the dummy gate stack 108 .
- first S/D region 112 and second S/D region 112 ′ are etched below the spacer 116 to expose the underlying buried insulator layer 104 and Si sidewalls 118 of the semiconductor fin 106 .
- Various etching techniques may be used to etch the first S/D region 112 and second S/D region 112 ′ including, but not limited to, an SIT process.
- a SiGe layer 120 is epitaxially grown at the etched fin sidewalls 118 of the semiconductor fin 106 .
- the exposed Si material of the semiconductor fin 106 provides an epitaxial template.
- the SiGe layer 120 may be grown by introducing a gas containing SiGe ions to the exposed Si fin sidewalls 118 of the semiconductor fin 106 .
- the SiGe ions attached to the exposed Si and are epitaxially grown from the fin sidewalls 118 of the semiconductor fin 106 as understood by those ordinarily skilled in the art.
- the SiGe layer 120 is shown as having a faceted triangular shape extending outwardly from the sidewalls 118 , the shape of the SiGe layer 120 is not limited thereto.
- an annealing operation is applied to the semiconductor device 100 to heat the SiGe layer 120 .
- a temperature applied during the annealing operation may range, for example, from approximately 1025 degrees Celsius (° C.) to approximately 1050° C.
- the SiGe ions of the SiGe layer 120 diffuse into the Si semiconductor fin 106 and beneath the dummy gate stack 108 .
- a superlattice SiGe/Si fin 122 is formed as illustrated in FIG. 7 .
- the SiGe/Si fin 122 may provide a reduced threshold voltage (Vt) and may improve electron hole mobility therethrough.
- a first epitaxially grown (epi) structure 124 and second epi structure 126 are formed following an epitaxial growth process as understood by those skilled in the art.
- the first epi structure 124 and second epi structure 126 form elevated S/D regions of the semiconductor device 100 .
- the first epi structure 124 and second epi structure 126 may be doped with p-type ions to form a PFET, for example.
- the p-type ions may include, but are not limited to, boron.
- the first epi structure 124 and second epi structure 126 are doped in-situ during the epitaxially growth process. Accordingly, a p-type finFET semiconductor device may be formed, for example.
- a second hardmask block layer 128 is deposited on exposed surfaces of the first epi structure 124 and second epi structure 126 (i.e., the elevated S/D regions) and the spacer 116 .
- the second hardmask block layer 128 may be formed from various materials including, but not limited to, Si 3 N 4 .
- the second hardmask block layer 128 may be deposited using, for example, chemical vapor deposition (CVD).
- the second hardmask block layer 128 is etched to form spacer extensions 130 on sidewalls of the spacer 116 .
- the spacer extensions 130 are configured to further protect dummy gate stack 108 during subsequent fabrication processes applied to the semiconductor device 100 .
- a second annealing operation is applied to the semiconductor device 100 .
- the second annealing operation causes the doped ions of the first epi structure 124 and second epi structure 126 to diffuse into SiGe/Si fin 122 .
- the diffusion of the doped ions is controlled such that the first epi structure 124 and second epi structure 126 extend beneath the spacer 116 , while maintaining a superlattice gate channel 132 beneath the dummy gate stack 108 .
- the gate channel 132 is a superlattice SiGe/Si gate channel 132 .
- a dielectric layer 134 is deposited on upper surfaces of the first epi structure 124 , the second epi structure 126 , the spacer extensions 130 , and the exposed portion of the spacer 116 .
- the dielectric layer 134 may be formed from flowable low dielectric material.
- the low dielectric material may include, but is not limited to, silicon oxide (SiO 2 ), SiO 2 doped with carbon (C), and SiO 2 doped with hydrogen (H).
- the dielectric layer 134 and spacer are recessed to expose the dummy gate 113 of the dummy gate stack 108 .
- a chemical-mechanical planarization (CMP) process may be used to recess the dielectric layer 134 and spacer 116 .
- an RMG process is described to form a metal gate stack having a metal gate formed over a SiGe gate channel 132 .
- the dummy gate stack 108 (including the dummy gate 113 ) is removed to form a trench 136
- the dummy gate stack 108 may be removed according to various known RMG processes understood by those ordinarily skilled in the art.
- the spacer 116 may further be etched using a STI process, for example, to increase the length (iGATE) of the trench 136 (i.e., the distance between the opposing sidewalls of the spacer 116 ) as further illustrated in FIG. 14 .
- an S/D overlap region 138 may be formed that is offset with respect to the sidewalls of the spacer 116 and that overlaps (i.e., extend) beneath the trench 136 .
- a second dielectric block layer 140 is deposited on an upper surface of the dielectric layer 134 , the spacer extensions 130 , the spacer 116 , and in the trench 136 .
- the second dielectric block layer 140 may be a high-k material including, but not limited to, hafnium oxide (HfO 2 ).
- the second dielectric block layer 140 may be deposited according to various process including, for example, CVD.
- the second dielectric block layer 140 is patterned to form a high-k gate insulation layer 142 formed over the sidewalls and bottom surfaces of the trench 136 .
- Various etching process may be used to etch the second dielectric block layer 140 including, but not limited to, a reactive ion etching (RIE) process.
- RIE reactive ion etching
- a metal contact layer 144 is formed on an upper surface of the gate insulation layer 142 .
- the metal contact layer 114 may be formed from, for example, titanium nitride (TiN), or titanium carbide (TiC). Accordingly, the gate insulation layer 142 is interposed between a metal contact layer 144 , the S/D extension portions 138 , and the SiGe gate channel 132 .
- a metal block layer 146 is deposited on an upper surface of the metal contact layer 144 and in the trench 136 .
- the metal block layer 146 may be formed from various metal gate materials as understood by those ordinarily skilled in the art.
- the metal gate is formed from tungsten (W).
- portions of the metal block layer 146 , metal contact layer 144 , gate insulation layer 142 , and dielectric layer 134 are recessed using, for example, a CMP process to expose the epitaxially grown source/drain regions.
- the remaining portions of the metal block layer 146 , metal contact layer 144 , gate insulation layer 142 , and dielectric layer 134 are planarized to form a metal gate 148 .
- the process flow described above provides a semiconductor device including a superlattice SiGe/Si semiconductor fin that forms a SiGe gate channel beneath the gate stack.
- the semiconductor device further includes one or more S/D extension portions that overlap the gate stack, while providing a SiGe gate channel. Therefore, a semiconductor device having a reduced threshold voltage (Vt) and improved electron hole mobility performance may be provided.
- Vt threshold voltage
- a flow diagram illustrates a method of fabricating a semiconductor device according to an exemplary embodiment.
- the method begins at operation 200 , and at operation 202 a semiconductor structure is formed on a semiconductor-on-insulator (SOI) substrate.
- the semiconductor structure includes, for example, a semiconductor fin formed on an insulator layer of the SW substrate, and a gate stack formed on the semiconductor fin.
- the semiconductor fin may be formed from, for example, Si.
- the semiconductor fin is etched to expose the insulator layer defining first and second source/drain regions, and sidewalls of the semiconductor fin.
- a SiGe layer is grown on the sidewalls of the Si fin.
- SiGe gas may be introduced to the semiconductor device. Silicon germanium ions included with the gas attach to the exposed sidewalls of Si fin to form the SiGe layer.
- the semiconductor device is annealed such that the SiGe ions of the SiGe layer diffuse into the fin. As a result, a fin having a superlattice structure comprising SiGe/Si is formed beneath the gate stack.
- source/drain structures are epitaxially grown on the exposed insulator layer of the source/drain region.
- a second annealing process is applied to the semiconductor device.
- the second annealing process causes the ions of the epitaxially source/drain structures to diffuse into the SiGe/Si fin to form source/drain extension portions.
- the source/drain extension portions define a SiGe gate channel beneath the gate stack.
- spacers of the gate stack are etched to increase the gate stack length stack such that the extension portions overlap the spacers, and the method ends at operation 216 .
Abstract
A semiconductor device includes a semiconductor-on-insulator substrate having an insulator layer, and at least one silicon germanium (SiGe) fin having a superlattice structure. The SiGe fin is formed on an upper surface of the insulator layer. A gate stack is formed on an upper surface of the at least one silicon germanium fin. The gate stack includes first and second opposing spacers defining a gate length therebetween. First and second epitaxial source/drain structures are formed on the insulator layer. The first and second epitaxial source/drain structures extend beneath the spacer to define a silicon germanium gate channel beneath the gate stack.
Description
- This application is a division of U.S. patent application Ser. No. 14/167,110, filed Jan. 29, 2014, the disclosure of which is incorporated by reference herein in its entirety.
- The present invention relates to finFET semiconductor devices, and more specifically, to a finFET including a superlattice silicon germanium/silicon (SiGe/Si) fin structure.
- Conventional finFET semiconductor devices include a gate that fully wraps one or more semiconductor fins formed from Si. The wrapped gate can improve carrier depletion in the channel defined by the Si fin. Accordingly, electrostatic control of the channel defined by the Si fin may be improved.
- Recent semiconductor fabrication methods have been developed to replace pure Si fins with SiGe fins. Forming the fins from SiGe reduces the threshold voltage (Vt) of the semiconductor device, thereby increasing the drive current that flows through the channel. Further, SiGe material provides higher carrier mobility than Si. Accordingly, SiGe fins may have improve electron hole mobility performance with respect to Si fins Conventional methods use an ion implantation process that drives SiGe ions into the fin to form a SiGe fin. However, these conventional methods may damage the fin and reduce overall performance of the finFET device.
- According to at least one exemplary embodiment, a method of fabricating a semiconductor device includes forming a semiconductor fin on an insulator layer of a semiconductor-on-insulator (SOI) substrate and forming a gate stack on the semiconductor fin. The method further includes etching the SOI substrate to expose an insulator layer to define at least one source/drain region and to expose sidewalls of the semiconductor fin. The method further includes growing a silicon germanium (SiGe) layer on the etched sidewalls of the fin. The method further includes annealing the semiconductor device to diffuse SiGe ions of the SiGe layer into the fin such that a SiGe fin having a superlattice structure is formed beneath the gate stack.
- According to another exemplary embodiment, a semiconductor device comprises a semiconductor-on-insulator substrate including an insulator layer, and at least one fin having a superlattice silicon germanium/silicon structure. The fin is formed on an upper surface of the insulator layer. A gate stack is formed on an upper surface of the at least one fin. The gate stack includes first and second opposing spacers defining a gate length therebetween. First and second epitaxial source/drain structures are formed on the insulator layer. The first and second epitaxial source/drain structures extend beneath the spacer to define a superlattice silicon germanium/silicon gate channel beneath the gate stack.
- Additional features are realized through the techniques of the present invention. Other embodiments are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention and related features, refer to the description and to the drawings.
- The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification.
- The forgoing and other features of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings.
FIGS. 1-19 illustrate a process flow of fabricating a semiconductor device according to at least one exemplary embodiment in which: -
FIG. 1 illustrates a semiconductor-on-insulator (SOI) substrate including a semiconductor fin formed on a buried insulation layer and a gate stack formed on the fin; -
FIG. 2 illustrates the SOI substrate ofFIG. 1 following deposition of a hardmask block layer that covers the fin and the gate stack; -
FIG. 3 illustrates the SOI substrate ofFIG. 2 after etching the hardmask block layer to form a spacer that covers the gate stack; -
FIG. 4 illustrates the SOI substrate ofFIG. 3 after etching the source/drain regions of the fin to expose the underlying buried insulator layer and sidewalls of the fin; -
FIG. 5 illustrates the SOI substrate ofFIG. 4 following epitaxial growth of a silicon germanium layer at the etched sidewalls of the fin; -
FIG. 6 illustrates the SOI substrate ofFIG. 5 undergoing an annealing process that induces diffusion of silicon germanium ions into the fin; -
FIG. 7 illustrates the SOI substrate ofFIG. 6 showing a superlattice silicon germanium/silicon fin extending beneath the gate stack following the diffusion of silicon germanium ions into the fin; -
FIG. 8 illustrates the SOI substrate ofFIG. 7 following epitaxially grown source/drain regions; -
FIG. 9 illustrates the SOI substrate ofFIG. 8 following deposition of a nitride block layer on exposed surfaces of the epitaxially grown source/drain regions and spacer; -
FIG. 10 illustrates the SOI substrate ofFIG. 9 after etching the nitride block layer to form spacer extensions on a portion of the spacer; -
FIG. 11 illustrates the SOI substrate ofFIG. 10 undergoing a second annealing process to diffuse doped ions of the epitaxially grown source/drain regions into the fin; -
FIG. 12 illustrates the SOI substrate ofFIG. 11 following deposition of dielectric layer on upper surfaces of the epitaxially grown source/drain regions, the spacer extensions, and the exposed portion of the spacer; -
FIG. 13 illustrates the SOI substrate ofFIG. 12 after etching the dielectric layer and spacer to expose a dummy gate of the gate stack; -
FIG. 14 illustrates the SOI substrate ofFIG. 13 following removal of the dummy gate to form a trench in the gate stack; -
FIG. 15 illustrates the SOI substrate ofFIG. 14 following deposition of a dielectric block layer on an upper surface of the etched dielectric layer and in the trench; -
FIG. 16 illustrates the SOI substrate ofFIG. 15 following patterning of the dielectric block layer to form a gate insulation layer in the trench; -
FIG. 17 illustrates the SOI substrate ofFIG. 16 following deposition of a metal contact layer on an upper surface of the gate insulation layer; -
FIG. 18 illustrates the SOI substrate ofFIG. 17 following deposition of a metal block layer on an upper surface of the metal contact layer and in the trench; and -
FIG. 19 illustrates the SOI substrate ofFIG. 18 after etching portions of the metal block layer, metal contact layer, gate insulation layer and dielectric layer to expose the epitaxially grown source/drain regions and to form a metal gate above a superlattice silicon germanium/silicon gate channel. -
FIG. 20 is a flow diagram illustrating a method of fabricating a semiconductor device according to an exemplary embodiment. - With reference now to
FIG. 1 , asemiconductor device 100 is illustrated according to an exemplary embodiment. Thesemiconductor device 100 includes a semiconductor-on-insulator (SOI)substrate 102. TheSOI substrate 102 may include abulk substrate layer 103 and a buriedinsulator layer 104. Thebulk substrate layer 103 may be formed from a semiconductor material such as silicon (Si), for example. The buriedinsulator layer 104 may be formed from, for example, an oxide material to form a buried oxide (BOX) layer as understood by those ordinarily skilled in the art. One ormore semiconductor fins 106 are formed on the buriedinsulator layer 104. Thesemiconductor fins 106 may be formed by etching an active semiconductor block layer (not shown) formed on the buriedinsulator layer 104 using a sidewall image transfer (SIT) process as understood by those ordinarily skilled in the art. According to at least one embodiment, an active silicon (Si) layer (not shown) may be formed on the buriedinsulator layer 104 to form asemiconductor fin 106 made from Si. - A
dummy gate stack 108 is formed to wrap around the upper surface and sides of thesemiconductor fins 106. Accordingly, a portion of the fin formed beneath thedummy gate stack 108 defines a gate channel interposed between exposed portions of thesemiconductor fin 106. The exposed portions of thesemiconductor fin 106 define a first source/drain (S/D)region 112 and a second source/drain (S/D)region 112′. Thedummy gate stack 108 further includes a gate insulator 110 interposed between adummy gate 113 and thesemiconductor fin 106. The gate insulator 110 may be formed from silicon oxide (SiO2), for example. Thedummy gate 113 may be formed from a polysilicon material, which may be replaced according to a replacement metal gate (RMG) process as understood by those ordinarily skilled in the art. - Turning to
FIG. 2 , ahardmask block layer 114 is deposited on thesemiconductor device 100. Thehardmask block layer 114 covers thesemiconductor fin 106 and thedummy gate stack 108. Thehardmask block layer 114 may be formed from various masking materials including, but not limited to, silicon nitride (Si3N4). Thehardmask block layer 114 may be deposited using, for example, chemical vapor deposition (CVD). - Referring to
FIG. 3 , thehardmask block layer 114 is etched to form aspacer 116 that covers thedummy gate stack 108 and a portion of thesemiconductor fin 106. Thehardmask block layer 114 may be etched using, for example, a reactive ion etching (RIE) technique. The thickness of thespacer 116 sidewalls defines an effective offset distance between the exposed surface of the first and second S/D regions 112/112′, and thedummy gate stack 108. - Turning now to
FIG. 4 , the first S/D region 112 and second S/D region 112′ are etched below thespacer 116 to expose the underlying buriedinsulator layer 104 and Si sidewalls 118 of thesemiconductor fin 106. Various etching techniques may be used to etch the first S/D region 112 and second S/D region 112′ including, but not limited to, an SIT process. - Referring now to
FIG. 5 aSiGe layer 120 is epitaxially grown at the etchedfin sidewalls 118 of thesemiconductor fin 106. The exposed Si material of thesemiconductor fin 106 provides an epitaxial template. Accordingly, theSiGe layer 120 may be grown by introducing a gas containing SiGe ions to the exposed Si fin sidewalls 118 of thesemiconductor fin 106. The SiGe ions attached to the exposed Si, and are epitaxially grown from the fin sidewalls 118 of thesemiconductor fin 106 as understood by those ordinarily skilled in the art. Although theSiGe layer 120 is shown as having a faceted triangular shape extending outwardly from thesidewalls 118, the shape of theSiGe layer 120 is not limited thereto. - With reference now to
FIGS. 6-7 , an annealing operation is applied to thesemiconductor device 100 to heat theSiGe layer 120. A temperature applied during the annealing operation may range, for example, from approximately 1025 degrees Celsius (° C.) to approximately 1050° C. In response to the heat, the SiGe ions of theSiGe layer 120 diffuse into theSi semiconductor fin 106 and beneath thedummy gate stack 108. Accordingly, a superlattice SiGe/Si fin 122 is formed as illustrated inFIG. 7 . The SiGe/Si fin 122 may provide a reduced threshold voltage (Vt) and may improve electron hole mobility therethrough. - Turning now to
FIG. 8 , a first epitaxially grown (epi)structure 124 andsecond epi structure 126 are formed following an epitaxial growth process as understood by those skilled in the art. Thefirst epi structure 124 andsecond epi structure 126 form elevated S/D regions of thesemiconductor device 100. Thefirst epi structure 124 andsecond epi structure 126 may be doped with p-type ions to form a PFET, for example. The p-type ions may include, but are not limited to, boron. In at least one exemplary embodiment, thefirst epi structure 124 andsecond epi structure 126 are doped in-situ during the epitaxially growth process. Accordingly, a p-type finFET semiconductor device may be formed, for example. - Turning to
FIG. 9 , a secondhardmask block layer 128 is deposited on exposed surfaces of thefirst epi structure 124 and second epi structure 126 (i.e., the elevated S/D regions) and thespacer 116. The secondhardmask block layer 128 may be formed from various materials including, but not limited to, Si3N4. The secondhardmask block layer 128 may be deposited using, for example, chemical vapor deposition (CVD). - Referring now to
FIG. 10 , the secondhardmask block layer 128 is etched to formspacer extensions 130 on sidewalls of thespacer 116. Thespacer extensions 130 are configured to further protectdummy gate stack 108 during subsequent fabrication processes applied to thesemiconductor device 100. - Turning to
FIG. 11 , a second annealing operation is applied to thesemiconductor device 100. The second annealing operation causes the doped ions of thefirst epi structure 124 andsecond epi structure 126 to diffuse into SiGe/Si fin 122. The diffusion of the doped ions is controlled such that thefirst epi structure 124 andsecond epi structure 126 extend beneath thespacer 116, while maintaining asuperlattice gate channel 132 beneath thedummy gate stack 108. According to at least one exemplary embodiment, since a superlattice SiGe/Si fin 122 is formed, thegate channel 132 is a superlattice SiGe/Si gate channel 132. - Turning now to
FIG. 12 , adielectric layer 134 is deposited on upper surfaces of thefirst epi structure 124, thesecond epi structure 126, thespacer extensions 130, and the exposed portion of thespacer 116. Thedielectric layer 134 may be formed from flowable low dielectric material. The low dielectric material may include, but is not limited to, silicon oxide (SiO2), SiO2 doped with carbon (C), and SiO2 doped with hydrogen (H). - Referring to
FIG. 13 , thedielectric layer 134 and spacer are recessed to expose thedummy gate 113 of thedummy gate stack 108. According to at least one exemplary embodiment, a chemical-mechanical planarization (CMP) process may be used to recess thedielectric layer 134 andspacer 116. - With reference now to
FIGS. 14-19 , an RMG process is described to form a metal gate stack having a metal gate formed over aSiGe gate channel 132. Referring toFIG. 14 , the dummy gate stack 108 (including the dummy gate 113) is removed to form atrench 136 Thedummy gate stack 108 may be removed according to various known RMG processes understood by those ordinarily skilled in the art. Thespacer 116 may further be etched using a STI process, for example, to increase the length (iGATE) of the trench 136 (i.e., the distance between the opposing sidewalls of the spacer 116) as further illustrated inFIG. 14 . Accordingly, an S/D overlap region 138 may be formed that is offset with respect to the sidewalls of thespacer 116 and that overlaps (i.e., extend) beneath thetrench 136. - Referring now to
FIG. 15 , a seconddielectric block layer 140 is deposited on an upper surface of thedielectric layer 134, thespacer extensions 130, thespacer 116, and in thetrench 136. The seconddielectric block layer 140 may be a high-k material including, but not limited to, hafnium oxide (HfO2). The seconddielectric block layer 140 may be deposited according to various process including, for example, CVD. - Turning to
FIG. 16 , the seconddielectric block layer 140 is patterned to form a high-kgate insulation layer 142 formed over the sidewalls and bottom surfaces of thetrench 136. Various etching process may be used to etch the seconddielectric block layer 140 including, but not limited to, a reactive ion etching (RIE) process. - Turning now to
FIG. 17 , ametal contact layer 144 is formed on an upper surface of thegate insulation layer 142. Themetal contact layer 114 may be formed from, for example, titanium nitride (TiN), or titanium carbide (TiC). Accordingly, thegate insulation layer 142 is interposed between ametal contact layer 144, the S/D extension portions 138, and theSiGe gate channel 132. - Referring to
FIG. 18 , ametal block layer 146 is deposited on an upper surface of themetal contact layer 144 and in thetrench 136. Themetal block layer 146 may be formed from various metal gate materials as understood by those ordinarily skilled in the art. In at least one exemplary embodiment, the metal gate is formed from tungsten (W). - Turning now to
FIG. 19 , portions of themetal block layer 146,metal contact layer 144,gate insulation layer 142, anddielectric layer 134 are recessed using, for example, a CMP process to expose the epitaxially grown source/drain regions. The remaining portions of themetal block layer 146,metal contact layer 144,gate insulation layer 142, anddielectric layer 134 are planarized to form ametal gate 148. - The process flow described above provides a semiconductor device including a superlattice SiGe/Si semiconductor fin that forms a SiGe gate channel beneath the gate stack. The semiconductor device further includes one or more S/D extension portions that overlap the gate stack, while providing a SiGe gate channel. Therefore, a semiconductor device having a reduced threshold voltage (Vt) and improved electron hole mobility performance may be provided.
- Referring now to
FIG. 20 , a flow diagram illustrates a method of fabricating a semiconductor device according to an exemplary embodiment. The method begins atoperation 200, and at operation 202 a semiconductor structure is formed on a semiconductor-on-insulator (SOI) substrate. The semiconductor structure includes, for example, a semiconductor fin formed on an insulator layer of the SW substrate, and a gate stack formed on the semiconductor fin. According to at least one exemplary embodiment, the semiconductor fin may be formed from, for example, Si. Atoperation 204, the semiconductor fin is etched to expose the insulator layer defining first and second source/drain regions, and sidewalls of the semiconductor fin. Atoperation 206, a SiGe layer is grown on the sidewalls of the Si fin. According to at least one embodiment, SiGe gas may be introduced to the semiconductor device. Silicon germanium ions included with the gas attach to the exposed sidewalls of Si fin to form the SiGe layer. Atoperation 208, the semiconductor device is annealed such that the SiGe ions of the SiGe layer diffuse into the fin. As a result, a fin having a superlattice structure comprising SiGe/Si is formed beneath the gate stack. Atoperation 210, source/drain structures are epitaxially grown on the exposed insulator layer of the source/drain region. Atoperation 212, a second annealing process is applied to the semiconductor device. The second annealing process causes the ions of the epitaxially source/drain structures to diffuse into the SiGe/Si fin to form source/drain extension portions. The source/drain extension portions define a SiGe gate channel beneath the gate stack. Atoperation 214, spacers of the gate stack are etched to increase the gate stack length stack such that the extension portions overlap the spacers, and the method ends atoperation 216. - The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one more other features, integers, steps, operations, element components, and/or groups thereof.
- The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated
- The flow diagrams depicted herein are just one example. There may be many variations to this diagram or the operations described therein without departing from the spirit of the invention. For instance, the operations may be performed in a differing order, or operations may be added, deleted or modified. All of these variations are considered a part of the claimed invention.
- While a preferred embodiment has been described, it will be understood that those skilled in the art, both now and in the future, may make various modifications which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.
Claims (13)
1. A semiconductor device, comprising:
a semiconductor-on-insulator substrate including an insulator layer;
at least one fin having a superlattice structure, the at least one fin formed on an upper surface of the insulator layer;
a gate stack formed on an upper surface of the at least one fin, the gate stack including first and second opposing spacers defining a gate length therebetween; and
first and second epitaxial source/drain structures formed on the insulator layer and extending beneath the spacer to define a superlattice gate channel beneath the gate stack.
2. The semiconductor device of claim 1 , wherein the superlattice structure is a superlattice silicon germanium/silicon (SiGe/Si) structure, and wherein the superlattice gate channel is a superlattice SiGe/Si gate channel beneath the gate stack.
3. The semiconductor device of claim 2 , wherein the spacers are offset with respect to the first and second epitaxial source/drain structures.
4. The semiconductor device of claim 3 , wherein the first and second epitaxial source/drain structures include respective source/drain extension portions overlapping the spacer and extending beneath the gate stack.
5. The semiconductor device of claim 4 , wherein the SiGe/Si gate channel is interposed between the source/drain extension portions.
6. The semiconductor device of claim 5 , wherein the gate stack includes a metal gate interposed between the spacer.
7. The semiconductor device of claim 6 , further comprising at least one gate layer interposed between the metal gate, the source/drain extension portions, and the SiGe/Si gate channel.
8. The semiconductor device of claim 6 , wherein the at least one gate layer is interposed between the metal gate and the SiGe/Si gate channel.
9. The semiconductor device of claim 8 , wherein the at least one gate layer includes a high dielectric material atop the silicon germanium gate channel.
10. The semiconductor device of claim 9 , wherein the at least one gate layer includes a metal contact layer formed on the high dielectric material.
11. The semiconductor device of claim 10 , wherein the metal gate is formed from tungsten.
12. The semiconductor device of claim 11 , wherein high dielectric material is formed from hafnium oxide.
13. The semiconductor device of claim 12 , wherein the metal contact layer is formed from one of titanium nitride or titanium carbide.
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US20150214351A1 (en) | 2015-07-30 |
WO2015114482A1 (en) | 2015-08-06 |
US9660035B2 (en) | 2017-05-23 |
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