CN105742298B - A kind of display base plate and preparation method thereof, display device - Google Patents
A kind of display base plate and preparation method thereof, display device Download PDFInfo
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- CN105742298B CN105742298B CN201610245440.2A CN201610245440A CN105742298B CN 105742298 B CN105742298 B CN 105742298B CN 201610245440 A CN201610245440 A CN 201610245440A CN 105742298 B CN105742298 B CN 105742298B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Abstract
The embodiment of the invention provides a kind of display base plates and preparation method thereof, display device, are related to field of display technology, can reduce etching cabling using this method and the larger problem of key size deviation occur, reduce wiring open circuit, guarantee the normal output capacity of product.The preparation method includes: the metal layer that covering underlay substrate is formed above underlay substrate；Metal layer includes the metal layer second portion corresponding to the metal layer first part of peripheral circuit area and corresponding to effective display area domain；To metal layer carry out the processing of first time patterning processes so that metal layer first part etch to form the first pattern, metal layer second portion etches to form the second pattern；Second of patterning processes processing is carried out to first pattern and the second pattern, forms the third pattern being located in peripheral circuit area, the 4th pattern in effective display area domain.For display base plate and the preparation of the display device including the display base plate.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of display base plate and preparation method thereof, display device.
Background technique
With the development of LCD technology, to semiconductor in TFT (Thin Film Transistor, thin film transistor (TFT))
The electron mobility of layer requires higher and higher, low temperature polycrystalline silicon (Low Temperature Poly Silicon, LTPS) technology
It comes into being.Semiconductor in TFT using after LTPS semiconductor, due to LTPS semiconductor material carrier mobility very
Height, pixel writing speed have obtained display and have been promoted, so as to which the area of TFT is configured smaller and will be in array substrate
The structure settings such as cabling it is thinner, to obtain the higher display panel of aperture opening ratio.
In order to enable the array substrate integrated level with LTPS TFT structure is higher, the array base of LTPS TFT structure at present
Plate generallys use CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor)
Structure, i.e., in the peripheral circuit except the effective display area domain of array substrate (Active Area, referred to as AA) formed by
NMOS (N-Metal-Oxide-Semiconductor, i.e. N-type Metal-oxide-semicondutor) and PMOS (P-Metal-
Oxide-Semiconductor, i.e. p-type Metal-oxide-semicondutor) composition complementary structure, so as to by GOA
(Gate Driver on Array, the driving of array substrate row) circuit integration is in array substrate.
Wherein, peripheral circuit is positioned only at corresponding to the grid metal pattern of PMOS TFT (hereinafter referred to as P gate)
In the region GOA, and the grid metal pattern (hereinafter referred to as N gate) corresponding to NMOS TFT is not only formed in effective display area
In domain, it is additionally arranged in the region GOA of peripheral circuit.In current CMOS manufacturing process, due to PMOS TFT and NMOS
Active layer Doped ions in TFT are different, need to carry out different doping process as exposure mask using respective grid metal pattern,
Therefore after depositing one layer of barrier metal layer on undoped LTPS, P gate and N corresponding to PMOS TFT and NMOS TFT
Gate needs to be formed by twice etching technique.
So, as shown in Figure 1, due to etching small area region only when barrier metal layer etches for the first time to form GOA
(shown in such as Fig. 2 (a), the region AA is only formed with light blocking layer 11 and undoped low temperature polycrystalline silicon to P gate in region at this time
Active layer 13)；And what N gate to be formed in the region GOA and N gate same layer were arranged is fanned out to (fan- positioned at peripheral circuit
Out) data cable lead wire in region, large area the region AA in the region N gate and AA in N gate same layer be arranged
Public electrode wire be covered by photoresist protection without etching；And when barrier metal layer etches for the second time, due in the region AA
N gate 27 (as shown in Fig. 2 (b)) and public electrode wire be being formed by etching the barrier metal layer of large area, and to be located at
Data cable lead wire 23 (shown in such as Fig. 2 (c)) in the region N gate and fan-out in the region GOA except the region AA is logical
What the barrier metal layer of over etching small area was formed.This is resulted in second of etching technics of barrier metal layer, by etching work
(load effect, i.e., under same etching technics, the etch rate of large area is less than the quarter of small area to the Loading effect of skill
Lose rate) it influences, the CD bias of N gate and public electrode wire in the region AA (Critical Dimension bias, i.e.,
Key size deviation) it is 1.5 μm or so, and the data cable lead wire CD bias meeting in N gate, the region fan-out in the area GOA
More than 2.0 μm, since N gate in the area GOA, the data cable lead wire line width in the region fan-out are natively relatively narrow, line and line
Between only 5.5 μm of the sum of spacing.It results in the metal wire CD bias of etching small area larger in this way, etching is caused to be formed
The width that designs more originally of line width it is smaller, it is bad to be easy to produce broken string, influences to show the normal output capacity of product.
Summary of the invention
In consideration of it, to solve problem of the prior art, the embodiment of the present invention provides a kind of display base plate and its preparation side
Method, display device, the display base plate obtained using the preparation method can reduce etching cabling, and key size deviation occur larger
The problem of, reduce the generation of wiring open circuit, guarantees the normal output capacity of product.
In order to achieve the above objectives, the embodiment of the present invention adopts the following technical scheme that
First aspect, the embodiment of the invention provides a kind of preparation methods of display base plate, and the display base plate is including all
Side circuit region and effective display area domain；The preparation method includes: to be formed to cover the underlay substrate above underlay substrate
Metal layer；Wherein, the metal layer includes corresponding to the metal layer first part of the peripheral circuit area and corresponding to institute
State the metal layer second portion of effective display area domain；The processing of first time patterning processes is carried out to the metal layer, so that described
Metal layer first part etches and to form the first pattern, the metal layer second portion etches to form the second pattern；Wherein, the gold
The region area that the region area and the metal layer second portion that Shu Ceng first part is etched away are etched away has first
Preset difference value；Second of patterning processes processing is carried out to first pattern and second pattern, is formed and is located at the periphery
Third pattern in circuit region, the 4th pattern in the effective display area domain；Wherein, first pattern is etched
The region area that the region area and second pattern fallen is etched away has the second preset difference value.
Preferably, the display base plate is specially array substrate；The peripheral circuit area includes: GOA gate driving electricity
Road region and fan-out area；The gate driving circuit region GOA include: corresponding to P-type TFT the first sub-district and
The second sub-district corresponding to N-type TFT；The effective display area domain includes: the third corresponding to N-type TFT
Sub-district, corresponding to the 4th sub-district of public electrode wire and other regions.
As a kind of optional mode, the preparation method includes: to be formed to cover the substrate base above underlay substrate
The barrier metal layer of plate；The processing of first time patterning processes is carried out to the barrier metal layer, corresponds to the week in the barrier metal layer
The barrier metal layer first part of side circuit region etches and to form the first pattern, corresponds to effective display in the barrier metal layer
The barrier metal layer second part in region etches to form the second pattern；Wherein, the area that the barrier metal layer first part is etched away
The region area that domain area and the barrier metal layer second part are etched away has the first preset difference value；The first pattern packet
Include: first of the first gate pattern, covering second sub-district in first sub-district retains pattern and is located at the fan
The pattern of the data cable lead wire in region out；Second pattern includes: the second reservation pattern of the covering third sub-district, is located at
The pattern of public electrode wire in 4th sub-district and bar paten positioned at other regions；First sub-district,
The data cable lead wire, the public electrode wire, second sub-district correspond to the second gate pattern to be formed region and
The third sub-district, which corresponds to, forms photoetching compound protective layer on the region of third grid line to be formed, and to first pattern and
The part that second pattern is not covered by the photoetching compound protective layer carries out second of patterning processes processing, is formed described in being located at
Third pattern in second sub-district, the 4th pattern in the third sub-district；Wherein, first pattern is etched away
The region area that region area and second pattern are etched away has the second preset difference value；The third pattern corresponds to institute
State the second gate pattern；4th pattern corresponds to the pattern of the third grid line.
As a kind of optional mode, the preparation method includes: to be formed to cover the substrate base above underlay substrate
The barrier metal layer of plate；The processing of first time patterning processes is carried out to the barrier metal layer, corresponds to the week in the barrier metal layer
The barrier metal layer first part of side circuit region etches and to form the first pattern, corresponds to effective display in the barrier metal layer
Region
Barrier metal layer second part etches to form the second pattern；Wherein, the area that the barrier metal layer first part etches away
The region area that domain area and the barrier metal layer second part etch away has the first preset difference value；The first pattern packet
Include: first of the first gate pattern, covering second sub-district in first sub-district retains pattern and is located at the fan
The pattern of the data cable lead wire in region out；Second pattern includes: the second reservation pattern of the covering third sub-district, covering
The third of 4th sub-district retains pattern and the bar paten positioned at other regions；In first sub-district, the number
Correspond to the region of the second gate pattern to be formed, the third sub-district corresponding to be formed according to line lead, second sub-district
Third grid line region and the 4th sub-district correspond to public electrode wire to be formed region on formed photoresist protect
Sheath, and second of structure is carried out to the part that first pattern and second pattern are not covered by the photoetching compound protective layer
Figure process forms the third pattern being located in second sub-district, the 4th pattern in the effective display area domain；
Wherein, the region area that the region area and second pattern that first pattern is etched away are etched away is pre- with second
If difference；The third pattern corresponds to second gate pattern；4th pattern includes: in the third sub-district
The pattern of the pattern of the third grid line and the public electrode wire in the 4th sub-district.
As a kind of optional mode, the preparation method includes: to be formed to cover the substrate base above underlay substrate
The barrier metal layer of plate；The processing of first time patterning processes is carried out to the barrier metal layer, corresponds to the week in the barrier metal layer
The barrier metal layer first part of side circuit region etches and to form the first pattern, corresponds to effective display in the barrier metal layer
The barrier metal layer second part in region etches to form the second pattern；Wherein, the region that the barrier metal layer first part etches away
The region area that area and the barrier metal layer second part etch away has the first preset difference value；First pattern includes:
First of the first gate pattern, covering second sub-district in first sub-district retains pattern and the covering fanout area
The second of domain retains pattern；Second pattern includes: the third reservation pattern for covering the third sub-district, covering the described 4th
The 4th of sub-district retains pattern and the bar paten positioned at other regions；In first sub-district, second sub-district pair
Should in the region of the second gate pattern to be formed, the third sub-district correspond to third grid line to be formed region, described the
Four sub-districts correspond to the region of public electrode wire to be formed and the fan-out area corresponds to data cable lead wire to be formed
Region on form photoetching compound protective layer, and first pattern and second pattern are not covered by the photoetching compound protective layer
The part of lid carries out second of patterning processes processing, forms the third pattern being located in the peripheral circuit area, positioned at described
The 4th pattern in effective display area domain；Wherein, the region area and the second pattern quilt that first pattern is etched away
The region area etched away has the second preset difference value；The third pattern includes: described in second sub-district
Two gate patterns and the data cable lead wire in the fan-out area；4th pattern includes: positioned at third
The third grid line in area and the public electrode wire in the 4th sub-district.
As a kind of optional mode, the preparation method includes: to be formed to cover the substrate base above underlay substrate
The barrier metal layer of plate；The processing of first time patterning processes is carried out to the barrier metal layer, corresponds to the week in the barrier metal layer
The barrier metal layer first part of side circuit region etches and to form the first pattern, corresponds to effective display in the barrier metal layer
The barrier metal layer second part in region etches to form the second pattern；Wherein, the region that the barrier metal layer first part etches away
The region area that area and the barrier metal layer second part etch away has the first preset difference value；First pattern includes:
First of the first gate pattern, covering second sub-district in first sub-district retains pattern and the covering fanout area
The second of domain retains pattern；Second pattern includes: the third reservation of the pattern of public electrode wire, the covering third sub-district
Pattern and bar paten positioned at other regions；In first sub-district, the public electrode wire, second sub-district pair
The region of third grid line to be formed and described should be corresponded in the region of the second gate pattern to be formed, the third sub-district
Fan-out area, which corresponds to, forms photoetching compound protective layer on the region of data cable lead wire to be formed, and to first pattern and institute
It states the part that the second pattern is not covered by the photoetching compound protective layer and carries out second of patterning processes processing, formed and be located at the week
Third pattern in the circuit region of side, the 4th pattern in the third sub-district；Wherein, first pattern is etched away
Region area and the region area that is etched away of second pattern there is the second preset difference value；The third pattern includes:
The pattern of the data cable lead wire in the fan-out area and second gate pattern in second sub-district；
4th pattern corresponds to the pattern of the third grid line.
Preferred on the basis of the above, second pattern is made of spaced multiple spirtes.
Preferred on the basis of the above, first preset difference value is the region that the metal layer first part is etched away
The 0~20% of area；And/or second preset difference value is the 0 of the region area that the metal layer first part is etched away
~20%.
Second aspect, the embodiment of the invention also provides a kind of display base plates, and the display base plate is using any of the above-described
The preparation method obtains.
The third aspect, the embodiment of the invention also provides a kind of display device, the display device includes described above
Display base plate.
Based on this, the above-mentioned preparation method provided through the embodiment of the present invention, when etch for the first time to metal layer,
The part of large area region is also performed etching when etching the region of small area, the area equation of etching or close reduces two
The etching CD bias of a region etch pattern；When etching for second, the etching and small area of large area region remainder are surplus
The etching area equation or close of remaining part point, reduces the etching CD bias of two region etch patterns.Using the preparation method
Obtained display base plate can reduce etching cabling and the larger problem of key size deviation occurs, avoid generating wiring open circuit, protect
Demonstrate,prove the normal output capacity of product.Barrier metal layer in the array substrate that above-mentioned lithographic method is applied particularly to LTPS TFT structure
When etching, it is possible to reduce the grid metal of the corresponding region NMOS TFT and PMOS TFT etches CD bias, avoids generating being routed and break
Road guarantees the normal output capacity of product.
Also, it since the CD bias in each region of entire substrate is same or similar, no longer needs to according to CD bias to each region
Pattern compensates, and improves substrate design freedom degree.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is that P gate etching and N gate etch area ratio schematic diagram in the prior art；
Fig. 2 (a) is the local pattern schematic diagram in the region AA when prior art P gate is etched；
Fig. 2 (b) is the local pattern schematic diagram in the region AA after prior art N gate etching；
Fig. 2 (c) is the local pattern schematic diagram of fan-out area after prior art N gate etching；
Fig. 3 is a kind of preparation method flow diagram of display base plate provided in an embodiment of the present invention；
Fig. 4 to Fig. 9 is followed successively by a kind of preparation method process substep of display base plate of the offer of the specific embodiment of the invention one
Schematic diagram；
Figure 10 (a) to Figure 10 (d) is followed successively by a kind of preparation method of display base plate of the offer of the specific embodiment of the invention one
Local pattern schematic diagram of the middle region AA under different patterning processes.
Appended drawing reference:
10- underlay substrate；11- light blocking layer；12- buffer layer；13- low-temperature polysilicon silicon active layer；13a-P+Source region；13b-P+
Drain region；13c-N+Source region；13d-N+Drain region；14- gate insulation layer；20- barrier metal layer；The first gate pattern of 21-；The first reserved graph of 22-
Case；23- data cable lead wire；24- second retains pattern；25- bar paten；The second gate pattern of 26-；27- third grid line (N
gate)；30- photoetching compound protective layer；40- data line.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
It should be pointed out that unless otherwise defined, all terms used in the embodiment of the present invention (including technology and section
Technics) have and identical meanings commonly understood by one of ordinary skill in the art to which the present invention belongs.It is also understood that such as existing
Term those of is defined in usual dictionary should be interpreted as having and their meaning phases one in the context of the relevant technologies
The meaning of cause is explained, unless being clearly defined herein without application idealization or the meaning of extremely formalization.
Also, each pattern dimension is very small in the array substrate as involved in the embodiment of the present invention, in order to clearly rise
See, each pattern dimension in attached drawing of the embodiment of the present invention is amplified, unless there are clearly stating, do not represent actual size with than
Example.
The embodiment of the invention provides a kind of preparation method of display base plate, the display base plate include peripheral circuit area and
Effective display area domain, the area of peripheral circuit area are less than the area of effective display area domain；As shown in figure 3, the preparation method packet
It includes:
S01, the metal layer that covering underlay substrate is formed above underlay substrate；Wherein, metal layer includes corresponding to periphery
The metal layer first part of circuit region and metal layer second portion corresponding to effective display area domain.
S02, the processing of first time patterning processes is carried out to metal layer, so that metal layer first part etches to form the first figure
Case, metal layer second portion etch to form the second pattern；Wherein, region area and metal that metal layer first part is etched away
The region area that layer second part is etched away has the first preset difference value.
S03, second of patterning processes processing is carried out to first pattern and the second pattern, is formed and is located in peripheral circuit area
Third pattern, the 4th pattern in effective display area domain；Wherein, the region area and second that the first pattern is etched away
The region area that pattern is etched away has the second preset difference value.
It should be noted that first, in above-mentioned steps S01, the description of " covering " only shows the face for the metal layer to be formed
Product, size are almost identical with underlay substrate；Metal layer specifically can directly be contacted with underlay substrate, can also be with substrate base
Other film layers above plate are in contact.
The second, the first preset difference value can require flexible setting according to the specific patterning processes of display base plate.In patterning processes
In the case where conditions permit, area surface that region area that metal layer first part etches away and metal layer second portion etch away
Product should be as same or similar as possible, for example, the first preset difference value be above-mentioned metal layer first part etch away pattern 0~
20%.
Likewise, the second preset difference value can require flexible setting according to the specific patterning processes of display base plate.In composition work
In the case where skill conditions permit, the region area that the region area that the first pattern is etched away is etched away with the second pattern is also answered
It is as same or similar as possible, for example, the second preset difference value is that the first pattern etch falls the 0~20% of pattern.
Third, in above-mentioned preparation method provided in an embodiment of the present invention, patterning processes can be arbitrarily to film layer (by one
Layer or plural layers) it is handled to form the technique with specific pattern, typical patterning processes are to apply a mask plate,
Pass through exposure, development, etching (including dry etching and/or wet etching), the technique for removing photoresist.
4th, the metal layer first part that metal layer corresponds to the peripheral circuit area of small area is formed by etching technics
While first pattern, same etching technics also corresponds to metal layer second of the effective display area domain of large area in metal layer
Divide and forms the second pattern, the area that the region area and metal layer second portion etched away due to metal layer first part is etched away
Domain area has the first preset difference value, when enabling to this etching, the etching CD bias in large area region and small area region
Difference minimizes.When the region area that region area that metal layer first part etches away and metal layer second portion etch away into
When one step is same or similar, large area region can reach consistent with the etching CD bias in small area region.
Since the partial region of the peripheral circuit area of large area in the metal layer of deposition is in a preceding etching technics
In be etched removal, when carrying out second to the first pattern and the second pattern that patterning processes before obtain at this time and etching, in week
Third pattern is formed in the circuit region of side, the 4th pattern is formed in effective display area domain；Wherein, the first pattern is etched away
The region area that region area and the second pattern are etched away has the second preset difference value, when enabling to this etching, big face
The etching CD bias difference in product region and small area region minimizes.When the region area and second that the first pattern is etched away
When the region area that pattern is etched away is further same or similar, the etching CD bias in large area region and small area region
It can reach consistent.
Here, it since the area of peripheral circuit area is less than the area of effective display area domain, when etching first time, is formed
The second pattern preferably be made of spaced multiple spirtes；Wherein, spirte for example can be bar shaped (slit),
Or circle etc..So, compared to the second pattern be complete monolith figure scheme, by the second pattern be set as by
It can make every multiple spirtes composition of arrangement when etch for the first time to metal layer, flood metal layer needs are etched
Pattern be evenly distributed, be conducive to the reduction of CD bias difference.
Based on this, the above-mentioned preparation method provided through the embodiment of the present invention, when etch for the first time to metal layer,
The part of large area region is also performed etching when etching the region of small area, the area equation of etching or close reduces two
The etching CD bias of a region etch pattern；When etching for second, the etching and small area of large area region remainder are surplus
The etching area equation or close of remaining part point, reduces the etching CD bias of two region etch patterns.Using the preparation method
Obtained display base plate can reduce etching cabling and the larger problem of key size deviation occurs, avoid generating wiring open circuit, protect
Demonstrate,prove the normal output capacity of product.Barrier metal layer in the array substrate that above-mentioned lithographic method is applied particularly to LTPS TFT structure
When etching, it is possible to reduce the grid metal of the corresponding region NMOS TFT and PMOS TFT etches CD bias, avoids generating being routed and break
Road guarantees the normal output capacity of product.
Also, it since the CD bias in each region of entire substrate is same or similar, no longer needs to according to CD bias to each region
Pattern compensates, and improves substrate design freedom degree.
By taking above-mentioned display base plate is specially the array substrate of LTPS TFT structure as an example, above-mentioned peripheral circuit area tool
Body includes: the gate driving circuit region GOA and fan-out area (the hereinafter referred to as region fan-out)；GOA gate driving circuit area
Domain further comprises: corresponding to the first sub-district (hereinafter referred to as GOA-P sub-district) of PMOS TFT and corresponding to NMOS TFT
Second sub-district (hereinafter referred to as GOA-N sub-district)；Effective display area domain (the hereinafter referred to as region AA) further comprises: corresponding to
The third sub-district (hereinafter referred to as AA-N sub-district) of NMOS TFT, corresponding to public electrode wire the 4th sub-district (hereinafter referred to as
Com sub-district) and other regions.
4 specific embodiments are given below, above-mentioned preparation method is described in detail.
It should be noted that in view of since (top gate, i.e. grid are located at active layer far from underlay substrate to top gate structure
The other side) the self-alignment structure that has of TFT itself can accurately control channel (i.e. active layer corresponds to when TFT is connected
Region between drain electrode) length so that narrow channel is designed to possibility, and TFT channel is smaller, TFT be connected when ON state electricity
It flows then bigger, TFT device performance can be significantly increased in this way and image quality that display device show, i.e., top gate structure is LTPS TFT
Mainstream structure.Therefore following specific embodiments of the present invention are illustrated using the LTPS TFT of top gate structure as example.
Also, the region AA, each regional location in the region GOA and the region fan-out and range in following Figure of description
Only illustrate, the region area that wherein four-headed arrow is illustrated does not represent actual size and ratio in array substrate.
Specific embodiment one
In the present embodiment one, first time etching technics, which is formed in array substrate, is located at corresponding in GOA-P sub-district
The gate pattern of PMOS TFT, the public electrode wire in the region AA, positioned at the region AA part bar paten and be located at
Data cable lead wire in the region fan-out；Second of etching technics forms the grid line corresponding to NMOS TFT for being located at the region AA
With the gate pattern corresponding to NMOS TFT being located in GOA-P sub-district.
Specific step is as follows for above-mentioned technique:
Step S11, as shown in figure 4, being sequentially formed on underlay substrate 10 multiple for stopping backlight to be irradiated to LTPS
On light blocking layer 11, cover light blocking layer 11 buffer layer 12, be located at the top of buffer layer 12 and one-to-one low with light blocking layer 11
Warm polysilicon active layer 13 and the gate insulation layer 14 for covering low-temperature polysilicon silicon active layer 13.
Step S12, as shown in figure 5, forming the barrier metal layer 20 of covering gate insulation layer 14 above underlay substrate 10.
Step S13, the processing of first time patterning processes is carried out to barrier metal layer 20, corresponds to peripheral circuit in barrier metal layer 20
The barrier metal layer first part in region etches to form the first pattern, correspond to the region AA in barrier metal layer barrier metal layer second
Etching is divided to form the second pattern；Wherein, the region area and barrier metal layer second part that barrier metal layer first part is etched away
The region area being etched away has the first preset difference value；As shown in Fig. 6 (a), above-mentioned first pattern includes: positioned at GOA-P
The pattern of the first gate pattern 21 (i.e. P gate) in area, the first of covering GOA-N sub-district retain pattern 22 and are located at fan-out
The pattern (not illustrated in figure) of the data cable lead wire 23 in region；Above-mentioned second pattern includes: to cover the second of AA-N sub-district to protect
It stays pattern 24, the pattern (not illustrating in figure) of public electrode wire in Com sub-district and is located at it as shown in Fig. 6 (b)
The bar paten 25 in his region.
It should be noted that first, in order to illustrate that the second reservation pattern 24 covers AA-N sub-district, with void in Fig. 6 (b)
Line illustrates the pattern of underlying low-temperature polysilicon silicon active layer 13.
The second, above-mentioned the first gate pattern 21 being located in GOA-P sub-district include PMOS TFT grid and with this
What grid was formed simultaneously is used to provide the cabling of corresponding signal to the grid.
Step S14, as shown in fig. 7, using the first gate pattern 21 formed in above-mentioned steps S13 as metal mask,
By ion implantation technology by P+(source ion implantation is, for example, BF to foreign ion3) low temperature that is doped in GOA-P sub-district is more
The two sides that crystal silicon active layer 13 is not covered by the first gate pattern 21, to be respectively formed the P being connected with source electrode+Source region 13a and with
The connected P of drain electrode+Drain region 13b.
At this point, since the low-temperature polysilicon silicon active layer 13 corresponding to NMOS TFT in the region AA and GOA-N sub-district is not had
There is the barrier metal layer etched away to be completely covered, therefore the P in above-mentioned steps S14+Impure ion injection technology does not interfere with
Active layer in NMOS TFT.
Step S15, as shown in figure 8, (not illustrating in figure in above-mentioned GOA-P sub-district, data cable lead wire 23 and public electrode wire
Out), GOA-N sub-district corresponds to the region of the second gate pattern 26 to be formed and AA-N sub-district corresponds to third grid to be formed
Photoetching compound protective layer 30 is formed on the region of line 27, and compound protective layer 30 is not photo-etched to above-mentioned first pattern and the second pattern and is covered
The part of lid carries out second of patterning processes processing, forms the third pattern being located in GOA-N sub-district, in AA-N sub-district
4th pattern；Wherein, the region area that the region area and above-mentioned second pattern that above-mentioned first pattern is etched away are etched away
With the second preset difference value；Third pattern corresponds to the pattern of the second gate pattern 26 (i.e. N gate)；4th pattern corresponds to the
The pattern of three grid lines 27 (i.e. N gate).
It should be noted that above-mentioned the second gate pattern 26 being located in GOA-N sub-district includes the grid of NMOS TFT
And it is used to provide the cabling of corresponding signal to the grid with what the grid was formed simultaneously.
Step S16, as shown in figure 9, using the second gate pattern 26 formed in above-mentioned steps S15 as metal mask,
By ion implantation technology by N+Foreign ion is doped to the low-temperature polysilicon silicon active layer 13 in GOA-N sub-district not by second
The two sides that gate pattern 26 covers, to be respectively formed the N being connected with source electrode+Source region 13c, the N being connected with drain electrode+Drain region 13d.Then
N in NMOS TFT zone respectively+Source region 13c, N+LDD region domain (the Lightly Doped of higher resistance value is formed in the 13d of drain region
Drain, low-doped drain region, label is in figure).
Likewise, passing through ion using the pattern of the third grid line 27 formed in above-mentioned steps S15 as metal mask
Injection technology is by N+Foreign ion is doped to the low-temperature polysilicon silicon active layer 13 in AA-N sub-district and is not covered by third grid line 27
The two sides of lid, to be respectively formed the N being connected with source electrode+Source region 13c, the N being connected with drain electrode+Drain region 13d.Then respectively in NMOS
N in TFT zone+Source region 13c, N+LDD region domain (Lightly Doped Drain, the low-mix of higher resistance value are formed in the 13d of drain region
Miscellaneous drain region, label is in figure).
After above-mentioned steps S16, it is subsequently formed in source electrode, drain electrode, the data line being connected with source electrode and array substrate
The isostructural step of such as pixel electrode, passivation layer can continue to use the process flow of the prior art, details are not described herein.
The schematic diagram of above each composition and etching technics successively as shown in Figure 10 (a) to Figure 10 (d), passes through work made above
Skill when being patterned to GOA-P sub-district, forms photoetching compound protective layer 30 on the region AA, in etching corresponding to PMOS TFT's
Due to foring part bar paten in the region AA, (the second of covering AA-N sub-district retains pattern 24, positioned at Com when gate pattern
The pattern of public electrode wire in area and bar paten 25 positioned at other regions) so that the region AA and periphery when this etching
The etching CD bias of circuit region is consistent and minimizes.The grid line of the NMOS TFT corresponded in the region AA is formed (i.e. in etching
Third grid line 27) when be etched away in previous step due to the part barrier metal layer in the region AA, the region AA needs to etch at this time
Barrier metal layer area and the region fan-out the barrier metal layer area that needs to etch it is essentially identical, etch in this way CD bias compared with
To be consistent, data cable lead wire wiring open (open circuit) in the region fan-out not will cause.Due to the region AA and peripheral circuit area
Etching CD bias is consistent, without carrying out additional Compensation Design, increases the design freedom of array substrate composition.
Specific embodiment two
In the present embodiment two, first time etching technics, which is formed in array substrate, is located at corresponding in GOA-P sub-district
The gate pattern of PMOS TFT, the part bar paten positioned at the region AA, the data cable lead wire in the region fan-out；Second
Secondary etching technics, which is formed, corresponds to NMOS corresponding to the grid line of NMOS TFT, in GOA-P sub-district positioned at the region AA
The gate pattern of TFT and the public electrode wire in Com sub-district.
Specific step is as follows for above-mentioned technique:
Step S21, it is sequentially formed on underlay substrate multiple for stopping backlight to be irradiated to the light blocking layer on LTPS, cover
The buffer layer of lid light blocking layer, be located at buffer layer above and with the one-to-one low-temperature polysilicon silicon active layer of light blocking layer and covering it is low
The gate insulation layer of warm polysilicon active layer.
Step S22, the barrier metal layer of covering underlay substrate is formed above underlay substrate.
Step S23, the processing of first time patterning processes is carried out to barrier metal layer, corresponds to peripheral circuit area in barrier metal layer
Barrier metal layer first part etch to be formed the first pattern, barrier metal layer correspond to the region AA barrier metal layer second part carve
Erosion forms the second pattern；Wherein, the region area that barrier metal layer first part etches away is etched away with barrier metal layer second part
Region area have the first preset difference value；Above-mentioned first pattern includes: the first gate pattern in GOA-P sub-district, covering
The first of GOA-N sub-district retains the pattern of pattern and the data cable lead wire positioned at the region fan-out；Above-mentioned second pattern includes:
It covers the second of AA-N sub-district and retains pattern, the third reservation pattern for covering Com sub-district and the bar paten positioned at other regions.
Step S24, using the first gate pattern formed in above-mentioned steps S23 as metal mask, pass through ion implanting
Technique is by P+(source ion implantation is, for example, BF to foreign ion3) it is doped to low-temperature polysilicon silicon active layer in GOA-P sub-district not
The two sides covered by the first gate pattern, to be respectively formed the P being connected with source electrode+Source region, the P being connected with drain electrode+Drain region.
At this point, since the low-temperature polysilicon silicon active layer 13 corresponding to NMOS TFT in the region AA and GOA-N sub-district is not had
There is the barrier metal layer etched away to be completely covered, therefore the P in above-mentioned steps S24+Impure ion injection technology does not interfere with
Active layer in NMOS TFT.
Step S25, the first sub-district, data cable lead wire, the second sub-district correspond to the second gate pattern to be formed region,
Third sub-district corresponds to the area of the region and the 4th sub-district of third grid line to be formed corresponding to public electrode wire to be formed
Photoetching compound protective layer is formed on domain, and is not photo-etched the part of compound protective layer covering to above-mentioned first pattern and above-mentioned second pattern
Second of patterning processes processing is carried out, the third pattern being located in GOA-N sub-district, the 4th pattern in the region AA are formed；
Wherein, the region area that the region area and above-mentioned second pattern that above-mentioned first pattern is etched away are etched away is pre- with second
If difference；Above-mentioned third pattern corresponds to the second gate pattern (i.e. N gate)；Above-mentioned 4th pattern includes: in AA-N sub-district
Third grid line (i.e. N gate) pattern and the public electrode wire in Com sub-district pattern.
Step S26, using the second gate pattern formed in above-mentioned steps S25 as metal mask, pass through ion implanting
Technique is by N+Foreign ion is doped to two that the low-temperature polysilicon silicon active layer in GOA-N sub-district is not covered by the second gate pattern
Side, to be respectively formed the N being connected with source electrode+Source region, the N being connected with drain electrode+Drain region.Then the N in NMOS TFT zone respectively+Source region, N+The LDD region domain (Lightly Doped Drain, low-doped drain region) of higher resistance value is formed in drain region.
Likewise, being infused using the pattern of the third grid line formed in above-mentioned steps S25 as metal mask by ion
Enter technique for N+Foreign ion is doped to two that the low-temperature polysilicon silicon active layer in AA-N sub-district is not covered by third grid line
Side, to be respectively formed the N being connected with source electrode+Source region, the N being connected with drain electrode+Drain region.Then the N in NMOS TFT zone respectively+Source region, N+The LDD region domain (Lightly Doped Drain, low-doped drain region) of higher resistance value is formed in drain region.
After above-mentioned steps S26, it is subsequently formed in source electrode, drain electrode, the data line being connected with source electrode and array substrate
The isostructural step of such as pixel electrode, passivation layer can continue to use the process flow of the prior art, details are not described herein.
Specific embodiment three
In the present embodiment three, first time etching technics, which is formed in array substrate, is located at corresponding in GOA-P sub-district
The gate pattern of PMOS TFT, the part bar paten positioned at the region AA；Second of etching technics forms the correspondence for being located at the region AA
In the grid line of NMOS TFT, the gate pattern, public in Com sub-district corresponding to NMOS TFT in GOA-P sub-district
Electrode wires and the data cable lead wire in the region fan-out.
Specific step is as follows for above-mentioned technique:
Step S31, it is sequentially formed on underlay substrate multiple for stopping backlight to be irradiated to the light blocking layer on LTPS, cover
The buffer layer of lid light blocking layer, be located at buffer layer above and with the one-to-one low-temperature polysilicon silicon active layer of light blocking layer and covering it is low
The gate insulation layer of warm polysilicon active layer.
Step S32, the barrier metal layer of covering underlay substrate is formed above underlay substrate.
Step S33, the processing of first time patterning processes is carried out to barrier metal layer, corresponds to peripheral circuit area in barrier metal layer
Barrier metal layer first part etch to be formed the first pattern, barrier metal layer correspond to the region AA barrier metal layer second part carve
Erosion forms the second pattern；Wherein, the region area that barrier metal layer first part etches away is etched away with barrier metal layer second part
Region area have the first preset difference value；Above-mentioned first pattern includes: the first gate pattern (i.e. P in GOA-P sub-district
Gate), the first of GOA-N sub-district is covered to retain pattern and cover the second reservation pattern in the region fan-out；Above-mentioned second pattern
It include: third reservation pattern, the 4th reservation pattern for covering Com sub-district and the bar shaped positioned at other regions for covering AA-N sub-district
Pattern.
Step S34, using the first gate pattern formed in above-mentioned steps S33 as metal mask, pass through ion implanting
Technique is by P+(source ion implantation is, for example, BF to foreign ion3) it is doped to low-temperature polysilicon silicon active layer in GOA-P sub-district not
The two sides covered by the first gate pattern, to be respectively formed the P being connected with source electrode+Source region, the P being connected with drain electrode+Drain region.
At this point, since the low-temperature polysilicon silicon active layer corresponding to NMOS TFT in the region AA and GOA-N sub-district is not had
The barrier metal layer etched away is completely covered, therefore the P in above-mentioned steps S14+Impure ion injection technology does not interfere with
Active layer in NMOS TFT.
Step S35, correspond to the region of the second gate pattern to be formed, third sub-district pair in the first sub-district, the second sub-district
It should be in the region and fan-out area of the region, the 4th sub-district of third grid line to be formed corresponding to public electrode wire to be formed
Corresponding to formation photoetching compound protective layer on the region of data cable lead wire to be formed, and to above-mentioned first pattern and above-mentioned second figure
The part that case is not photo-etched compound protective layer covering carries out second of patterning processes processing, forms the be located in peripheral circuit area
Three patterns, the 4th pattern in the region AA；Wherein, the region area and above-mentioned second figure that above-mentioned first pattern is etched away
The region area that case is etched away has the second preset difference value；Above-mentioned third pattern includes: the second gate in GOA-N sub-district
Pattern (i.e. N gate) and the data cable lead wire in the region fan-out；Above-mentioned 4th pattern includes: in AA-N sub-district
Third grid line (i.e. N gate) and the public electrode wire in Com sub-district.
Step S36, using the second gate pattern formed in above-mentioned steps S35 as metal mask, pass through ion implanting
Technique is by N+Foreign ion is doped to two that the low-temperature polysilicon silicon active layer in GOA-N sub-district is not covered by the second gate pattern
Side, to be respectively formed the N being connected with source electrode+Source region, the N being connected with drain electrode+Drain region.Then the N in NMOS TFT zone respectively+Source region, N+The LDD region domain (Lightly Doped Drain, low-doped drain region) of higher resistance value is formed in drain region.
Likewise, being infused using the pattern of the third grid line formed in above-mentioned steps S35 as metal mask by ion
Enter technique for N+Foreign ion is doped to two that the low-temperature polysilicon silicon active layer in AA-N sub-district is not covered by third grid line
Side, to be respectively formed the N being connected with source electrode+Source region, the N being connected with drain electrode+Drain region.Then the N in NMOS TFT zone respectively+Source region, N+The LDD region domain (Lightly Doped Drain, low-doped drain region) of higher resistance value is formed in drain region.
After above-mentioned steps S36, it is subsequently formed in source electrode, drain electrode, the data line being connected with source electrode and array substrate
The isostructural step of such as pixel electrode, passivation layer can continue to use the process flow of the prior art, details are not described herein.
Specific embodiment four
In the present embodiment four, first time etching technics, which is formed in array substrate, is located at corresponding in GOA-P sub-district
The gate pattern of PMOS TFT, the part bar paten positioned at the region AA and the public electrode wire in Com sub-district；Second
Etching technics, which is formed, corresponds to NMOS TFT corresponding to the grid line of NMOS TFT, in GOA-P sub-district positioned at the region AA
Gate pattern and the data cable lead wire in the region fan-out.
Specific step is as follows for above-mentioned technique:
Step S41, it is sequentially formed on underlay substrate multiple for stopping backlight to be irradiated to the light blocking layer on LTPS, cover
The buffer layer of lid light blocking layer, be located at buffer layer above and with the one-to-one low-temperature polysilicon silicon active layer of light blocking layer and covering it is low
The gate insulation layer of warm polysilicon active layer.
Step S42, the barrier metal layer of covering underlay substrate is formed above underlay substrate.
Step S43, the processing of first time patterning processes is carried out to barrier metal layer, corresponds to peripheral circuit area in barrier metal layer
Barrier metal layer first part etch to be formed the first pattern, barrier metal layer correspond to the region AA barrier metal layer second part carve
Erosion forms the second pattern；Wherein, the region area that barrier metal layer first part etches away is etched away with barrier metal layer second part
Region area have the first preset difference value；Above-mentioned first pattern includes: the first gate pattern (i.e. P in GOA-P sub-district
Gate), the first of GOA-N sub-district is covered to retain pattern and cover the second reservation pattern in the region fan-out；Above-mentioned second pattern
It include: the pattern of public electrode wire, the third reservation pattern for covering AA-N sub-district and the bar paten positioned at other regions.
Step S44, using the first gate pattern formed in above-mentioned steps S43 as metal mask, pass through ion implanting
Technique is by P+(source ion implantation is, for example, BF to foreign ion3) it is doped to low-temperature polysilicon silicon active layer in GOA-P sub-district not
The two sides covered by the first gate pattern, to be respectively formed the P being connected with source electrode+Source region, the P being connected with drain electrode+Drain region.
At this point, since the low-temperature polysilicon silicon active layer corresponding to NMOS TFT in the region AA and GOA-N sub-district is not had
The barrier metal layer etched away is completely covered, therefore the P in above-mentioned steps S14+Impure ion injection technology does not interfere with
Active layer in NMOS TFT.
Step S45, the first sub-district, public electrode wire, the second sub-district correspond to the second gate pattern to be formed region,
Third sub-district corresponds to the area of the region and fan-out area of third grid line to be formed corresponding to data cable lead wire to be formed
Photoetching compound protective layer is formed on domain, and is not photo-etched the part of compound protective layer covering to above-mentioned first pattern and above-mentioned second pattern
Second of patterning processes processing is carried out, the third pattern being located in peripheral circuit area, the in AA-N sub-district the 4th are formed
Pattern；Wherein, the region area that the region area that above-mentioned first pattern is etched away is etched away with above-mentioned second pattern has
Second preset difference value；Above-mentioned third pattern include: the data cable lead wire in the region fan-out pattern and be located at GOA-N
The pattern of the second gate pattern (i.e. N gate) in sub-district；4th pattern corresponds to the pattern of third grid line (i.e. N gate).
Step S46, using the second gate pattern formed in above-mentioned steps S45 as metal mask, pass through ion implanting
Technique is by N+Foreign ion is doped to two that the low-temperature polysilicon silicon active layer in GOA-N sub-district is not covered by the second gate pattern
Side, to be respectively formed the N being connected with source electrode+Source region, the N being connected with drain electrode+Drain region.Then the N in NMOS TFT zone respectively+Source region, N+The LDD region domain (Lightly Doped Drain, low-doped drain region) of higher resistance value is formed in drain region.
Likewise, being infused using the pattern of the third grid line formed in above-mentioned steps S45 as metal mask by ion
Enter technique for N+Foreign ion is doped to two that the low-temperature polysilicon silicon active layer in AA-N sub-district is not covered by third grid line
Side, to be respectively formed the N being connected with source electrode+Source region, the N being connected with drain electrode+Drain region.Then the N in NMOS TFT zone respectively+Source region, N+The LDD region domain (Lightly Doped Drain, low-doped drain region) of higher resistance value is formed in drain region.
After above-mentioned steps S46, it is subsequently formed in source electrode, drain electrode, the data line being connected with source electrode and array substrate
The isostructural step of such as pixel electrode, passivation layer can continue to use the process flow of the prior art, details are not described herein.Further
, the embodiment of the invention also provides a kind of display base plate, which is obtained using above-mentioned preparation method.
Further, the embodiment of the invention also provides a kind of display device, which includes above-mentioned display
Substrate.
Above-mentioned display device specifically can be liquid crystal display panel, liquid crystal display, LCD TV, ORGANIC ELECTROLUMINESCENCE DISPLAYS
(Organic Light-Emitting Display, abbreviation OLED) panel, OLED display, OLED TV, Digital Frame, hand
Machine, tablet computer etc. have the product or component of any display function.
More than, only a specific embodiment of the invention, but scope of protection of the present invention is not limited thereto, and it is any to be familiar with
Those skilled in the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all cover
Within protection scope of the present invention.Therefore, protection scope of the present invention should be subject to the protection scope in claims.
Claims (8)
1. a kind of preparation method of display base plate, the display base plate include peripheral circuit area and effective display area domain；It is special
Sign is that the preparation method includes:
The metal layer for covering the underlay substrate is formed above underlay substrate；Wherein, the metal layer includes corresponding to described
The metal layer first part of peripheral circuit area and metal layer second portion corresponding to the effective display area domain；
The processing of first time patterning processes is carried out to the metal layer, so that the metal layer first part etches to form the first figure
Case, the metal layer second portion etch to form the second pattern；Wherein, the area surface that the metal layer first part is etched away
The long-pending region area being etched away with the metal layer second portion has the first preset difference value；Wherein, described first is default poor
Value is the 0~20% of the region area that the metal layer first part is etched away；
Second of patterning processes processing is carried out to first pattern and second pattern, is formed and is located at the periphery circuit region
Third pattern in domain, the 4th pattern in the effective display area domain；Wherein, the area that first pattern is etched away
The region area that domain area and second pattern are etched away has the second preset difference value；Wherein, second preset difference value
It is the 0~20% of the region area that first pattern is etched away.
2. preparation method according to claim 1, which is characterized in that the display base plate is specially array substrate；It is described
Peripheral circuit area includes: the gate driving circuit region GOA and fan-out area；The gate driving circuit region GOA includes: pair
It should the first sub-district in P-type TFT and the second sub-district corresponding to N-type TFT；The effective display area domain packet
It includes: corresponding to the third sub-district of N-type TFT, corresponding to the 4th sub-district of public electrode wire and other regions.
3. preparation method according to claim 2, which is characterized in that the preparation method includes:
The barrier metal layer for covering the underlay substrate is formed above underlay substrate；
The processing of first time patterning processes is carried out to the barrier metal layer, corresponds to the peripheral circuit area in the barrier metal layer
Barrier metal layer first part etch to be formed the first pattern, the barrier metal layer correspond to the effective display area domain grid gold
Belong to layer second part to etch to form the second pattern；Wherein, the region area and institute that the barrier metal layer first part is etched away
Stating the region area that barrier metal layer second part is etched away has the first preset difference value；First pattern includes: positioned at institute
State the first gate pattern in the first sub-district, the first reservation pattern for covering second sub-district and the number positioned at the fan-out area
According to the pattern of line lead；Second pattern includes: the second reservation pattern of the covering third sub-district, is located at the 4th son
The pattern of public electrode wire in area and bar paten positioned at other regions；
Correspond to be formed the in first sub-district, the data cable lead wire, the public electrode wire, second sub-district
The region of two gate patterns and the third sub-district, which correspond to, forms photoetching compound protective layer on the region of third grid line to be formed,
And second of composition work is carried out to the part that first pattern and second pattern are not covered by the photoetching compound protective layer
Skill processing, forms the third pattern being located in second sub-district, the 4th pattern in the third sub-district；Wherein, institute
Stating the region area that the first pattern is etched away and the region area that second pattern is etched away has the second preset difference value；
The third pattern corresponds to second gate pattern；4th pattern corresponds to the pattern of the third grid line.
4. preparation method according to claim 2, which is characterized in that the preparation method includes:
The barrier metal layer for covering the underlay substrate is formed above underlay substrate；
The processing of first time patterning processes is carried out to the barrier metal layer, corresponds to the peripheral circuit area in the barrier metal layer
Barrier metal layer first part etch to be formed the first pattern, the barrier metal layer correspond to the effective display area domain grid gold
Belong to layer second part to etch to form the second pattern；Wherein, the region area that the barrier metal layer first part etches away with it is described
The region area that barrier metal layer second part etches away has the first preset difference value；First pattern includes: positioned at described
First of the first gate pattern, covering second sub-district in one sub-district retains pattern and the data line positioned at the fan-out area
The pattern of lead；Second pattern includes: the second reservation pattern of the covering third sub-district, covering the 4th sub-district
Third retains pattern and the bar paten positioned at other regions；
First sub-district, the data cable lead wire, second sub-district correspond to the second gate pattern to be formed region,
The third sub-district corresponds to the region of third grid line to be formed and the 4th sub-district corresponds to common electrical to be formed
Photoetching compound protective layer is formed on the region of polar curve, and first pattern and second pattern are not protected by the photoresist
The part of layer covering carries out second of patterning processes processing, formed the third pattern being located in second sub-district, be located at it is described
The 4th pattern in effective display area domain；Wherein, the region area and the second pattern quilt that first pattern is etched away
The region area etched away has the second preset difference value；The third pattern corresponds to second gate pattern；4th figure
The pattern and the common electrical in the 4th sub-district that case includes: the third grid line in the third sub-district
The pattern of polar curve.
5. preparation method according to claim 2, which is characterized in that the preparation method includes:
The barrier metal layer for covering the underlay substrate is formed above underlay substrate；
The processing of first time patterning processes is carried out to the barrier metal layer, corresponds to the peripheral circuit area in the barrier metal layer
Barrier metal layer first part etch to be formed the first pattern, the barrier metal layer correspond to the effective display area domain grid gold
Belong to layer second part to etch to form the second pattern；Wherein, the region area that the barrier metal layer first part etches away with it is described
The region area that barrier metal layer second part etches away has the first preset difference value；First pattern includes: positioned at described
First of the first gate pattern, covering second sub-district in one sub-district retains pattern and the second of the covering fan-out area and protects
Stay pattern；Second pattern includes: the third reservation pattern for covering the third sub-district, covers the 4th of the 4th sub-district
Retain pattern and the bar paten positioned at other regions；
Correspond to the region of the second gate pattern to be formed, the third sub-district pair in first sub-district, second sub-district
The region of public electrode wire to be formed and described should be corresponded in the region of third grid line to be formed, the 4th sub-district
Fan-out area, which corresponds to, forms photoetching compound protective layer on the region of data cable lead wire to be formed, and to first pattern and institute
It states the part that the second pattern is not covered by the photoetching compound protective layer and carries out second of patterning processes processing, formed and be located at the week
Third pattern in the circuit region of side, the 4th pattern in the effective display area domain；Wherein, first pattern is carved
The region area that the region area of eating away and second pattern are etched away has the second preset difference value；The third pattern packet
It includes: second gate pattern in second sub-district and the data cable lead wire in the fan-out area；Institute
It includes: the third grid line in the third sub-district and described public in the 4th sub-district for stating the 4th pattern
Electrode wires.
6. preparation method according to claim 2, which is characterized in that the preparation method includes:
The barrier metal layer for covering the underlay substrate is formed above underlay substrate；
The processing of first time patterning processes is carried out to the barrier metal layer, corresponds to the peripheral circuit area in the barrier metal layer
Barrier metal layer first part etch to be formed the first pattern, the barrier metal layer correspond to the effective display area domain grid gold
Belong to layer second part to etch to form the second pattern；Wherein, the region area that the barrier metal layer first part etches away with it is described
The region area that barrier metal layer second part etches away has the first preset difference value；First pattern includes: positioned at described
First of the first gate pattern, covering second sub-district in one sub-district retains pattern and the second of the covering fan-out area and protects
Stay pattern；Second pattern includes: the pattern of public electrode wire, covers the third reservation pattern of the third sub-district and be located at
The bar paten in other regions；
First sub-district, the public electrode wire, second sub-district correspond to the second gate pattern to be formed region,
The third sub-district corresponds to the region of third grid line to be formed and the fan-out area corresponds to data line to be formed
Photoetching compound protective layer is formed on the region of lead, and first pattern and second pattern are not protected by the photoresist
The part of layer covering carries out second of patterning processes processing, forms the third pattern being located in the peripheral circuit area, is located at
The 4th pattern in the third sub-district；Wherein, the region area and the second pattern quilt that first pattern is etched away
The region area etched away has the second preset difference value；The third pattern includes: the number in the fan-out area
According to the pattern of line lead and second gate pattern in second sub-district；4th pattern corresponds to the third
The pattern of grid line.
7. preparation method according to any one of claims 1 to 6, which is characterized in that second pattern is by being alternatively arranged
Multiple spirtes constitute.
8. a kind of display base plate, which is characterized in that the display base plate uses the described in any item systems of the claims 1 to 7
Preparation Method obtains.
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| CN108987415A (en) * | 2018-06-26 | 2018-12-11 | 武汉华星光电技术有限公司 | A kind of array substrate and preparation method thereof, touch panel |
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| US6137578A (en) * | 1998-07-28 | 2000-10-24 | International Business Machines Corporation | Segmented bar-in-bar target |
| US6566184B1 (en) * | 2002-02-21 | 2003-05-20 | Taiwan Semiconductor Manufacturing Company | Process to define N/PMOS poly patterns |
| CN1536438A (en) * | 2003-04-08 | 2004-10-13 | 旺宏电子股份有限公司 | Method for eliminating key size deviation of dense pattern and single pattern |
| CN101599430A (en) * | 2008-06-03 | 2009-12-09 | 中芯国际集成电路制造(北京)有限公司 | The formation method of grating of semiconductor element and the control system of grid etch |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6137578A (en) * | 1998-07-28 | 2000-10-24 | International Business Machines Corporation | Segmented bar-in-bar target |
| US6566184B1 (en) * | 2002-02-21 | 2003-05-20 | Taiwan Semiconductor Manufacturing Company | Process to define N/PMOS poly patterns |
| CN1536438A (en) * | 2003-04-08 | 2004-10-13 | 旺宏电子股份有限公司 | Method for eliminating key size deviation of dense pattern and single pattern |
| CN101599430A (en) * | 2008-06-03 | 2009-12-09 | 中芯国际集成电路制造(北京)有限公司 | The formation method of grating of semiconductor element and the control system of grid etch |
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