CN105742298A - Display substrate and preparation method therefor, and display apparatus - Google Patents
Display substrate and preparation method therefor, and display apparatus Download PDFInfo
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- CN105742298A CN105742298A CN201610245440.2A CN201610245440A CN105742298A CN 105742298 A CN105742298 A CN 105742298A CN 201610245440 A CN201610245440 A CN 201610245440A CN 105742298 A CN105742298 A CN 105742298A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Abstract
Embodiments of the invention provide a display substrate and a preparation method therefor, and a display apparatus, and relate to the display technical field. By adoption of the preparation method, the problem of relatively large critical dimensional deviation in etching lines can be reduced, the circuit breaking in wiring can be lowered, and the normal rate of output of products can be ensured. The preparation method comprises the steps of forming a metal layer capable of covering a substrate above the substrate, wherein the metal layer comprises a metal layer first part corresponding to a peripheral circuit region, and a metal layer second part corresponding to an effective display region; performing a patterning process for the first time on the metal layer to etch the metal layer first part to form a first pattern, and to etch the metal layer second part to form a second pattern; and performing the patterning process on the first pattern and the second pattern for the second time to form a third pattern positioned in the peripheral circuit region, and a fourth pattern positioned in the effective display region. The preparation method is used for the display substrate, and the display equipment including the display substrate.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of display base plate and preparation method thereof, display device.
Background technology
Development along with lcd technology, to TFT (ThinFilmTransistor, thin film transistor (TFT)) in semiconductor layer electron mobility require more and more higher, low temperature polycrystalline silicon (LowTemperaturePolySilicon, LTPS) technology is arisen at the historic moment.After quasiconductor in TFT adopts LTPS quasiconductor, owing to the carrier mobility of LTPS semi-conducting material is very high, pixel writing speed obtains display and promotes, such that it is able to the area of TFT be configured to less and the structures such as the cabling in array base palte be configured to thinner, the display floater higher to obtain aperture opening ratio.
nullSo that the array base palte integrated level with LTPSTFT structure is higher，The array base palte of current LTPSTFT structure generally adopts CMOS (ComplementaryMetalOxideSemiconductor，Complementary metal oxide semiconductors (CMOS)) structure，Namely at territory, the effective display area (ActiveArea of array base palte，Referred to as AA) outside peripheral circuit in formed by NMOS (N-Metal-Oxide-Semiconductor，I.e. N-type Metal-oxide-semicondutor) and PMOS (P-Metal-Oxide-Semiconductor，I.e. P type Metal-oxide-semicondutor) complementary structure that forms，It is thus possible to by GOA (GateDriveronArray，Array base palte row cutting) circuit is integrated in array base palte.
Wherein, grid metal pattern (hereinafter referred to as Pgate) corresponding to PMOSTFT is positioned only in the GOA region of peripheral circuit, and the grid metal pattern (hereinafter referred to as Ngate) corresponding to NMOSTFT is not only formed in territory, effective display area, it is additionally arranged in the GOA region of peripheral circuit.In current CMOS manufacturing process, owing to the active layer dopant ion in PMOSTFT and NMOSTFT is different, need to utilize respective grid metal pattern to carry out different doping process as mask, therefore, after depositing one layer of grid metal level on unadulterated LTPS, Pgate and the Ngate corresponding to PMOSTFT and NMOSTFT requires over the formation of twice etching technique.
So, as shown in Figure 1, the small surfaces territory Pgate (as shown in Fig. 2 (a), now AA region has only formed light blocking layer 11 and unadulterated low-temperature polysilicon silicon active layer 13) to be formed in GOA region is only etched during due to grid metal level first time etching；And not the performing etching with the Ngate public electrode wire protection covered by photoresist arranged with layer of Ngate and AA region of the data cable lead wire in fan-out (fan-out) region being positioned at peripheral circuit that Ngate and Ngate to be formed in GOA region is arranged with layer, large-area AA region；And when grid metal level second time etches, owing to the Ngate27 (as Suo Shi Fig. 2 (b)) in AA region and public electrode wire are to be formed by etching large-area grid metal level, and the data cable lead wire 23 (as Suo Shi Fig. 2 (c)) being positioned at Ngate and the fan-out region in GOA region outside AA region is by etching the formation of the grid metal level of little area.This results in the second time etching technics of grid metal level, it is subject to the Loadingeffect (load effect of etching technics, namely under same etching technics, large-area etch rate is less than the etch rate of little area) impact, Ngate in AA region and the CDbias (CriticalDimensionbias of public electrode wire, i.e. key size deviation) it is about 1.5 μm, and the Ngate in GOA district, data cable lead wire CDbias in fan-out region can more than 2.0 μm, due to the Ngate in GOA district, data cable lead wire live width in fan-out region is natively narrower, spacing sum between line and line only has 5.5 μm.Thus cause that the metal wire CDbias etching little area is relatively big, cause that the width that the live width that etching is formed designs relatively originally is less, it is easy to produce broken string bad, the impact display normal output capacity of product.
Summary of the invention
Given this, for solving problem of the prior art, embodiments of the invention provide a kind of display base plate and preparation method thereof, display device, adopt the display base plate that this preparation method obtains can reduce etching cabling and the problem that key size deviation is bigger occurs, reduce the generation of wiring open circuit, it is ensured that the normal output capacity of product.
For reaching above-mentioned purpose, embodiments of the invention adopt the following technical scheme that
First aspect, the preparation method embodiments providing a kind of display base plate, described display base plate includes peripheral circuit area and territory, effective display area；Described preparation method includes: be formed over the metal level covering described underlay substrate at underlay substrate；Wherein, described metal level includes the metal level Part I corresponding to described peripheral circuit area and the metal layer second portion corresponding to territory, described effective display area；Described metal level carries out first time patterning processes process, so that described metal level Part I etching forms the first pattern, described metal layer second portion etching forms the second pattern；Wherein, the region area that the region area that described metal level Part I is etched away and described metal layer second portion are etched away has the first preset difference value；Described first pattern and described second pattern carrying out second time patterning processes process, formation is positioned at the 3rd pattern of described peripheral circuit area, is positioned at the 4th pattern in territory, described effective display area；Wherein, the region area that the region area that described first pattern is etched away and described second pattern are etched away has the second preset difference value.
Preferably, described display base plate is specially array base palte；Described peripheral circuit area includes: GOA gate driving circuit region and fan-out area；Described GOA gate driving circuit region includes: the first sub-district corresponding to P-type TFT and the second sub-district corresponding to N-type TFT；Territory, described effective display area includes: the 3rd sub-district corresponding to N-type TFT, the 4th sub-district corresponding to public electrode wire and other regions.
As the optional mode of one, described preparation method includes: be formed over the grid metal level covering described underlay substrate at underlay substrate；Described grid metal level carrying out patterning processes for the first time process, the grid metal level Part I etching corresponding to described peripheral circuit area at described grid metal level forms the first pattern, corresponds to grid metal layer second portion etching formation second pattern in territory, described effective display area at described grid metal level；Wherein, the region area that the region area that described grid metal level Part I is etched away and described grid metal layer second portion are etched away has the first preset difference value；Described first pattern includes: the first grid pattern that is positioned at described first sub-district, cover described second sub-district first retain pattern and be positioned at the pattern of data cable lead wire of described fan-out area；Described second pattern includes: cover described 3rd sub-district second retains pattern, is positioned at the pattern of the public electrode wire in described 4th sub-district and is positioned at the bar paten in other regions described；In described first sub-district, described data cable lead wire, described public electrode wire, described second sub-district corresponding to the region of second gate pattern to be formed and described 3rd sub-district corresponding to the region of the 3rd grid line to be formed is formed photoresist protective layer; and the part that described first pattern and described second pattern do not covered by described photoresist protective layer carries out second time patterning processes and processes, formed and be positioned at the 3rd pattern in described second sub-district, be positioned at the 4th pattern in described 3rd sub-district；Wherein, the region area that the region area that described first pattern is etched away and described second pattern are etched away has the second preset difference value；Described 3rd pattern corresponds to described second gate pattern；Described 4th pattern is corresponding to the pattern of described 3rd grid line.
As the optional mode of one, described preparation method includes: be formed over the grid metal level covering described underlay substrate at underlay substrate；Described grid metal level carries out patterning processes for the first time process, form the first pattern at described grid metal level corresponding to the grid metal level Part I etching of described peripheral circuit area, correspond to territory, described effective display area at described grid metal level
Grid metal layer second portion etching forms the second pattern；Wherein, the region area that the region area that described grid metal level Part I etches away and described grid metal layer second portion etch away has the first preset difference value；Described first pattern includes: the first grid pattern that is positioned at described first sub-district, cover described second sub-district first retain pattern and be positioned at the pattern of data cable lead wire of described fan-out area；Described second pattern includes: cover described 3rd sub-district second retains pattern, covers the 3rd reservation pattern in described 4th sub-district and be positioned at the bar paten in other regions described；In described first sub-district, described data cable lead wire, described second sub-district corresponding to the region of second gate pattern to be formed, described 3rd sub-district corresponding to the region of the 3rd grid line to be formed and described 4th sub-district corresponding to the region of public electrode wire to be formed is formed photoresist protective layer; and the part that described first pattern and described second pattern do not covered by described photoresist protective layer carries out second time patterning processes and processes, formed and be positioned at the 3rd pattern in described second sub-district, be positioned at the 4th pattern in territory, described effective display area；Wherein, the region area that the region area that described first pattern is etched away and described second pattern are etched away has the second preset difference value；Described 3rd pattern corresponds to described second gate pattern；Described 4th pattern includes: the pattern of the pattern being positioned at described 3rd grid line in described 3rd sub-district and the described public electrode wire being positioned at described 4th sub-district.
As the optional mode of one, described preparation method includes: be formed over the grid metal level covering described underlay substrate at underlay substrate；Described grid metal level carrying out patterning processes for the first time process, the grid metal level Part I etching corresponding to described peripheral circuit area at described grid metal level forms the first pattern, corresponds to grid metal layer second portion etching formation second pattern in territory, described effective display area at described grid metal level；Wherein, the region area that the region area that described grid metal level Part I etches away and described grid metal layer second portion etch away has the first preset difference value；Described first pattern includes: the first grid pattern that is positioned at described first sub-district, cover described second sub-district first retain pattern and cover the second of described fan-out area and retain pattern；Described second pattern includes: cover described 3rd sub-district the 3rd retains pattern, covers the 4th reservation pattern in described 4th sub-district and be positioned at the bar paten in other regions described；In described first sub-district, described second sub-district is corresponding to the region of second gate pattern to be formed, described 3rd sub-district is corresponding to the region of the 3rd grid line to be formed, described 4th sub-district corresponds to form photoresist protective layer on the region of data cable lead wire to be formed corresponding to region and the described fan-out area of public electrode wire to be formed, and the part that described first pattern and described second pattern do not covered by described photoresist protective layer carries out second time patterning processes and processes, form the 3rd pattern being positioned at described peripheral circuit area, it is positioned at the 4th pattern in territory, described effective display area；Wherein, the region area that the region area that described first pattern is etched away and described second pattern are etched away has the second preset difference value；Described 3rd pattern includes: is positioned at the described second gate pattern in described second sub-district and is positioned at the described data cable lead wire of described fan-out area；Described 4th pattern includes: is positioned at described 3rd grid line in described 3rd sub-district and is positioned at the described public electrode wire in described 4th sub-district.
As the optional mode of one, described preparation method includes: be formed over the grid metal level covering described underlay substrate at underlay substrate；Described grid metal level carrying out patterning processes for the first time process, the grid metal level Part I etching corresponding to described peripheral circuit area at described grid metal level forms the first pattern, corresponds to grid metal layer second portion etching formation second pattern in territory, described effective display area at described grid metal level；Wherein, the region area that the region area that described grid metal level Part I etches away and described grid metal layer second portion etch away has the first preset difference value；Described first pattern includes: the first grid pattern that is positioned at described first sub-district, cover described second sub-district first retain pattern and cover the second of described fan-out area and retain pattern；Described second pattern includes: the pattern of public electrode wire, covers the 3rd of described 3rd sub-district and retains pattern and be positioned at the bar paten in other regions described；In described first sub-district, described data cable lead wire, described second sub-district corresponding to the region of second gate pattern to be formed, described 3rd sub-district corresponding to the region of the 3rd grid line to be formed and described fan-out area corresponding to the region of data cable lead wire to be formed is formed photoresist protective layer; and the part that described first pattern and described second pattern do not covered by described photoresist protective layer carries out second time patterning processes and processes, formed and be positioned at the 3rd pattern of described peripheral circuit area, be positioned at the 4th pattern in described 3rd sub-district；Wherein, the region area that the region area that described first pattern is etched away and described second pattern are etched away has the second preset difference value；Described 3rd pattern includes: is positioned at the pattern of the described data cable lead wire of described fan-out area and is positioned at the described second gate pattern in described second sub-district；Described 4th pattern is corresponding to the pattern of described 3rd grid line.
Preferred on the basis of the above, described second pattern is made up of spaced multiple spirtes.
Preferred on the basis of the above, described first preset difference value is the 0～20% of the region area that described metal level Part I is etched away；And/or, described second preset difference value is the 0～20% of the region area that described metal level Part I is etched away.
Second aspect, the embodiment of the present invention additionally provide a kind of display base plate, and described display base plate adopts the preparation method described in any of the above-described item to obtain.
The third aspect, the embodiment of the present invention additionally provide a kind of display device, and described display device includes display base plate described above.
Based on this, by the above-mentioned preparation method that the embodiment of the present invention provides, when carrying out metal level etching for the first time, when etching the region of little area, the part of large area region is also carried out etching, the area equation or close of etching, decreases the etching CDbias of two region etch patterns；When second time etches, etching and the etching area equation or close of little area remainder of large area region remainder, decrease the etching CDbias of two region etch patterns.Adopt the display base plate that this preparation method obtains can reduce etching cabling and the problem that key size deviation is bigger occurs, it is to avoid produce wiring open circuit, it is ensured that the normal output capacity of product.When above-mentioned lithographic method is applied particularly to the grid metal level etching in the array base palte of LTPSTFT structure, it is possible to reduce the grid metal etch CDbias of NMOSTFT and PMOSTFT corresponding region, it is to avoid produce wiring open circuit, it is ensured that the normal output capacity of product.
Further, owing to the CDbias in each region of whole substrate is same or like, it is not necessary to further according to CDbias, each zone map is compensated, improve substrate design degree of freedom.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, the accompanying drawing used required in embodiment or description of the prior art will be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the premise not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is that in prior art, Pgate etching and Ngate etch area ratio schematic diagram；
The local pattern schematic diagram in AA region when Fig. 2 (a) etches for prior art Pgate；
Fig. 2 (b) is the local pattern schematic diagram in AA region after prior art Ngate etching；
Fig. 2 (c) is the local pattern schematic diagram of fan-out area after prior art Ngate etching；
The preparation method schematic flow sheet of a kind of display base plate that Fig. 3 provides for the embodiment of the present invention；
Fig. 4 to Fig. 9 is followed successively by the preparation method flow process substep schematic diagram of a kind of display base plate that the specific embodiment of the invention one provides；
Figure 10 (a) to Figure 10 (d) is followed successively by the preparation method of a kind of display base plate that the specific embodiment of the invention one provides AA region local pattern schematic diagram under different patterning processes.
Accompanying drawing labelling:
10-underlay substrate；11-light blocking layer；12-cushion；13-low-temperature polysilicon silicon active layer；13a-P+Source region；13b-P+Drain region；13c-N+Source region；13d-N+Drain region；14-gate insulation layer；20-grid metal level；21-first grid pattern；22-first retains pattern；23-data cable lead wire；24-second retains pattern；25-bar paten；26-second gate pattern；27-the 3rd grid line (Ngate)；30-photoresist protective layer；40-data wire.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is only a part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art obtain under not making creative work premise, broadly fall into the scope of protection of the invention.
It is pointed out that unless otherwise defined, all terms (including technology and scientific terminology) used in the embodiment of the present invention have the identical meanings being commonly understood by with those skilled in the art.It should also be understood that, such as in usual dictionary, those terms of definition should be interpreted as having the implication consistent with they implications in the context of correlation technique, and do not apply idealization or extremely formal meaning explain, unless so defined clearly here.
Further, in the array base palte involved by the embodiment of the present invention, each pattern dimension is very small, and for the sake of clarity, each pattern dimension in embodiment of the present invention accompanying drawing is all exaggerated, unless there are clearly stating, does not represent actual size and ratio.
The preparation method embodiments providing a kind of display base plate, this display base plate includes peripheral circuit area and territory, effective display area, and the area of peripheral circuit area is less than the area in territory, effective display area；As it is shown on figure 3, this preparation method includes:
S01, underlay substrate be formed over cover underlay substrate metal level；Wherein, metal level includes the metal level Part I corresponding to peripheral circuit area and the metal layer second portion corresponding to territory, effective display area.
S02, metal level is carried out first time patterning processes process so that metal level Part I etching formed the first pattern, metal layer second portion etching formed the second pattern；Wherein, the region area that the region area that metal level Part I is etched away and metal layer second portion are etched away has the first preset difference value.
S03, the first pattern and the second pattern are carried out second time patterning processes process, formed and be positioned at the 3rd pattern of peripheral circuit area, be positioned at the 4th pattern in territory, effective display area；Wherein, the first pattern is etched away region area and the region area that the second pattern is etched away have the second preset difference value.
It should be noted that first, in above-mentioned steps S01, the description of " covering " only show formed the area of metal level, size almost identical with underlay substrate；Metal level specifically directly can contact with underlay substrate, it is also possible to contacts with other retes above underlay substrate.
The second, the first preset difference value can require to arrange flexibly according to the concrete patterning processes of display base plate.When patterning processes conditions permit, the region area that the region area that metal level Part I etches away and metal layer second portion etch away should be same or like as far as possible, such as, the metal level Part I that the first preset difference value is above-mentioned etches away the 0～20% of pattern.
Same, the second preset difference value can require to arrange flexibly according to the concrete patterning processes of display base plate.When patterning processes conditions permit, region area that the first pattern is etched away and the region area that the second pattern is etched away also should be same or like as far as possible, for instance, the second preset difference value is that the first pattern etch falls the 0～20% of pattern.
3rd, in the above-mentioned preparation method that the embodiment of the present invention provides, patterning processes can be arbitrarily process to form the technique with specific pattern to rete (by one or more layers thin film), typical patterning processes is mask plate of application, by exposing, develop, etch (including dry etching and/or wet etching), the technique removing photoresist.
4th, while metal level forms the first pattern corresponding to the metal level Part I of peripheral circuit area of little area by etching technics, the metal layer second portion that same etching technics also corresponds to territory, large-area effective display area at metal level defines the second pattern, the region area that the region area etched away due to metal level Part I and metal layer second portion etch away has the first preset difference value, when enabling to this etching, the etching CDbias difference in large area region and small surfaces territory minimizes.When the region area that the region area that metal level Part I etches away and metal layer second portion etch away further same or like time, large area region can reach consistent with the etching CDbias in small surfaces territory.
Owing in the metal level of deposition, the subregion of large-area peripheral circuit area has been etched removal in a front etching technics, when the first pattern now patterning processes before obtained and the second pattern carry out etching for the second time, in peripheral circuit area, form the 3rd pattern, in territory, effective display area, form the 4th pattern；Wherein, the first pattern is etched away region area and the region area that the second pattern is etched away have the second preset difference value, it is possible to when this is etched, the etching CDbias difference in large area region and small surfaces territory minimizes.When the region area that the first pattern is etched away and the region area that the second pattern is etched away further same or like time, large area region can reach consistent with the etching CDbias in small surfaces territory.
Here, owing to the area of peripheral circuit area is less than the area in territory, effective display area, when first time etches, the second pattern of formation is preferably made up of spaced multiple spirtes；Wherein, spirte can be such as bar shaped (slit) or circle etc..So, compared to the scheme that the second pattern is a complete monoblock figure, be set to the second pattern to be made up of spaced multiple spirtes can so that metal level is carried out first time etch time, flood metal level needs the pattern being etched to be evenly distributed, and is conducive to the minimizing of CDbias difference.
Based on this, by the above-mentioned preparation method that the embodiment of the present invention provides, when carrying out metal level etching for the first time, when etching the region of little area, the part of large area region is also carried out etching, the area equation or close of etching, decreases the etching CDbias of two region etch patterns；When second time etches, etching and the etching area equation or close of little area remainder of large area region remainder, decrease the etching CDbias of two region etch patterns.Adopt the display base plate that this preparation method obtains can reduce etching cabling and the problem that key size deviation is bigger occurs, it is to avoid produce wiring open circuit, it is ensured that the normal output capacity of product.When above-mentioned lithographic method is applied particularly to the grid metal level etching in the array base palte of LTPSTFT structure, it is possible to reduce the grid metal etch CDbias of NMOSTFT and PMOSTFT corresponding region, it is to avoid produce wiring open circuit, it is ensured that the normal output capacity of product.
Further, owing to the CDbias in each region of whole substrate is same or like, it is not necessary to further according to CDbias, each zone map is compensated, improve substrate design degree of freedom.
Be specially the array base palte of LTPSTFT structure for above-mentioned display base plate, above-mentioned peripheral circuit area specifically includes: GOA gate driving circuit region and fan-out area (hereinafter referred to as fan-out region)；GOA gate driving circuit region farther includes: the first sub-district (hereinafter referred to as the sub-district of GOA-P) corresponding to PMOSTFT and the second sub-district (hereinafter referred to as the sub-district of GOA-N) corresponding to NMOSTFT；Territory, effective display area (hereinafter referred to as AA region) farther includes: the 3rd sub-district (hereinafter referred to as the sub-district of AA-N) corresponding to NMOSTFT, the 4th sub-district (hereinafter referred to as Com district) corresponding to public electrode wire and other regions.
4 specific embodiments are given below, so that above-mentioned preparation method is described in detail.
It should be noted that, consider due to top gate structure (topgate, namely grid is positioned at the active layer opposite side away from underlay substrate) the self-alignment structure that has of TFT self can accurately control the length of raceway groove (namely during TFT conducting active layer corresponding to the region between drain electrode), narrow raceway groove is made to be designed to possibility, and TFT channel is more little, ON state current during TFT conducting is then more big, so can significantly increasing TFT device performance and image quality that display device shows, namely top gate structure is the main flow structure of LTPSTFT.Therefore specific examples below of the present invention all illustrates with the LTPSTFT of top gate structure for example.
Further, in following Figure of description, AA region, each regional location in GOA region and fan-out region and scope are only signal, and the region area that wherein four-headed arrow illustrates does not represent the actual size in array base palte and ratio.
Specific embodiment one
In the present embodiment one, first time etching technics forms the gate pattern corresponding to PMOSTFT being positioned at the sub-district of GOA-P in array base palte, is positioned at the public electrode wire in AA region, is positioned at the part bar paten in AA region and is positioned at the data cable lead wire in fan-out region；Second time etching technics forms the grid line corresponding to NMOSTFT being positioned at AA region and the gate pattern corresponding to NMOSTFT being positioned at the sub-district of GOA-P.
Specifically comprising the following steps that of above-mentioned technique
Step S11, as shown in Figure 4, underlay substrate 10 sequentially forms multiple for stopping light blocking layer 11, the cushion 12 covering light blocking layer 11 that backlight is irradiated on LTPS, be positioned at above cushion 12 and with light blocking layer 11 low-temperature polysilicon silicon active layer 13 one to one and the gate insulation layer 14 covering low-temperature polysilicon silicon active layer 13.
Step S12 as it is shown in figure 5, be formed over the grid metal level 20 covering gate insulation layer 14 at underlay substrate 10.
Step S13, grid metal level 20 is carried out first time patterning processes process, form the first pattern at grid metal level 20 corresponding to the grid metal level Part I etching of peripheral circuit area, form the second pattern at grid metal level corresponding to the grid metal layer second portion etching in AA region；Wherein, the region area that the region area that grid metal level Part I is etched away and grid metal layer second portion are etched away has the first preset difference value；As shown in Fig. 6 (a), above-mentioned first pattern includes: the pattern that is positioned at the first grid pattern 21 (i.e. Pgate) in the sub-district of GOA-P, cover the sub-district of GOA-N first retain pattern 22 and be positioned at the pattern (not shown in the figures anticipate out) of data cable lead wire 23 in fan-out region；Above-mentioned second pattern includes: cover the sub-district of AA-N second retains pattern 24, is positioned at the pattern (not shown in the figures anticipate out) of the public electrode wire in Com district and the bar paten 25 being positioned at other regions as shown in Fig. 6 (b).
It should be noted that first, in order to illustrate that sub-for AA-N district is covered by the second reservation pattern 24, Fig. 6 (b) illustrates the pattern of the low-temperature polysilicon silicon active layer 13 being positioned below with dotted line.
The second, the above-mentioned first grid pattern 21 being positioned at the sub-district of GOA-P include PMOSTFT grid and with this grid concurrently form for this grid provide corresponding signal cabling.
Step S14 is as it is shown in fig. 7, utilize the first grid pattern 21 formed in above-mentioned steps S13 as metal mask, by ion implantation technology by P+(source ion implantation is such as BF to foreign ion3) be doped to and be positioned at the both sides that the low-temperature polysilicon silicon active layer 13 in the sub-district of GOA-P is not covered by first grid pattern 21, to form the P being connected with source electrode respectively+Source region 13a and the P being connected with drain electrode+Drain region 13b.
Now, the grid metal level not etched away due to the low-temperature polysilicon silicon active layer 13 corresponding to NMOSTFT in AA region and the sub-district of GOA-N is completely covered, the therefore P in above-mentioned steps S14+Impure ion injection technology does not interfere with the active layer in NMOSTFT.
Step S15, as shown in Figure 8; in the sub-district of above-mentioned GOA-P, data cable lead wire 23 and public electrode wire (not shown in the figures anticipate out), the sub-district of GOA-N corresponding to the region of second gate pattern 26 to be formed and the sub-district of AA-N corresponding to the region of the 3rd grid line 27 to be formed is formed photoresist protective layer 30; and the part that above-mentioned first pattern and the second pattern are not photo-etched compound protective layer 30 covering carries out second time patterning processes and processes, formation is positioned at the 3rd pattern in the sub-district of GOA-N, is positioned at the 4th pattern in the sub-district of AA-N；Wherein, the region area that the region area that above-mentioned first pattern is etched away and above-mentioned second pattern are etched away has the second preset difference value；3rd pattern is corresponding to the pattern of second gate pattern 26 (i.e. Ngate)；4th pattern is corresponding to the pattern of the 3rd grid line 27 (i.e. Ngate).
It should be noted that the above-mentioned second gate pattern 26 being positioned at the sub-district of GOA-N include NMOSTFT grid and with this grid concurrently form for this grid provide corresponding signal cabling.
Step S16 is as it is shown in figure 9, utilize the second gate pattern 26 formed in above-mentioned steps S15 as metal mask, by ion implantation technology by N+Foreign ion is doped to and is positioned at the both sides that the low-temperature polysilicon silicon active layer 13 in the sub-district of GOA-N is not covered by second gate pattern 26, to form the N being connected with source electrode respectively+Source region 13c, the N being connected with drain electrode+Drain region 13d.Then the N in NMOSTFT region respectively+Source region 13c, N+The LDD region territory (LightlyDopedDrain, low-doped drain region are labeled as LDD in figure) of higher resistance value is formed in the 13d of drain region.
Same, utilize the pattern of the 3rd grid line 27 formed in above-mentioned steps S15 as metal mask, by ion implantation technology by N+Foreign ion is doped to and is positioned at the both sides that the low-temperature polysilicon silicon active layer 13 in the sub-district of AA-N is not covered by the 3rd grid line 27, to form the N being connected with source electrode respectively+Source region 13c, the N being connected with drain electrode+Drain region 13d.Then the N in NMOSTFT region respectively+Source region 13c, N+The LDD region territory (LightlyDopedDrain, low-doped drain region are labeled as LDD in figure) of higher resistance value is formed in the 13d of drain region.
After above-mentioned steps S16, the isostructural step of such as pixel electrode, passivation layer being subsequently formed on source electrode, drain electrode, the data wire being connected with source electrode and array base palte can continue to use the technological process of prior art, does not repeat them here.
The schematic diagram of each composition and etching technics is successively if Figure 10 (a) is to shown in Figure 10 (d) above; by technique made above; when the sub-district of GOA-P is patterned; AA region is formed photoresist protective layer 30; when etching is corresponding to the gate pattern of PMOSTFT owing to defining part bar paten (cover the sub-district of AA-N second retains pattern 24, be positioned at the pattern of the public electrode wire in Com district and be positioned at the bar paten 25 in other regions) in AA region so that during this etching, AA region is consistent with the etching CDbias of peripheral circuit area and minimize.When etching forms grid line (i.e. the 3rd grid line 27) corresponding to the NMOSTFT in AA region owing to the part grid metal level in AA region is etched away in previous step, now AA region needs the area of the grid metal level of etching to need the grid metal level area etched essentially identical with fan-out region, so etching CDbias is more consistent, does not result in data cable lead wire wiring open (open circuit) in fan-out region.Owing to AA region is consistent with peripheral circuit area etching CDbias, it is not necessary to carrying out extra Compensation Design, adding the design freedom of array base palte composition.
Specific embodiment two
In the present embodiment two, first time etching technics forms the gate pattern corresponding to PMOSTFT being positioned at the sub-district of GOA-P in array base palte, is positioned at the part bar paten in AA region, is positioned at the data cable lead wire in fan-out region；Second time etching technics formation is positioned at the grid line corresponding to NMOSTFT in AA region, is positioned at the gate pattern corresponding to NMOSTFT in the sub-district of GOA-P and is positioned at the public electrode wire in Com district.
Specifically comprising the following steps that of above-mentioned technique
Step S21, sequentially form on underlay substrate multiple for stopping light blocking layer that backlight is irradiated on LTPS, cover light blocking layer cushion, be positioned at above cushion and with light blocking layer low-temperature polysilicon silicon active layer one to one and the gate insulation layer covering low-temperature polysilicon silicon active layer.
Step S22, underlay substrate be formed over cover underlay substrate grid metal level.
Step S23, grid metal level is carried out first time patterning processes process, grid metal level corresponding to peripheral circuit area grid metal level Part I etching formed the first pattern, grid metal level corresponding to AA region grid metal layer second portion etching formed the second pattern；Wherein, the region area that the region area that grid metal level Part I etches away and grid metal layer second portion etch away has the first preset difference value；Above-mentioned first pattern includes: the first grid pattern that is positioned at the sub-district of GOA-P, cover the sub-district of GOA-N first retain pattern and be positioned at the pattern of data cable lead wire in fan-out region；Above-mentioned second pattern includes: covers the second of the sub-district of AA-N and retains pattern, covers the 3rd reservation pattern in Com district and be positioned at the bar paten in other regions.
The first grid pattern that step S24, utilization are formed in above-mentioned steps S23 is as metal mask, by ion implantation technology by P+(source ion implantation is such as BF to foreign ion3) it is doped to the low-temperature polysilicon silicon active layer being positioned at the sub-district of GOA-P not by the both sides of first grid pattern covers, to form the P being connected with source electrode respectively+Source region, the P being connected with drain electrode+Drain region.
Now, the grid metal level not etched away due to the low-temperature polysilicon silicon active layer 13 corresponding to NMOSTFT in AA region and the sub-district of GOA-N is completely covered, the therefore P in above-mentioned steps S24+Impure ion injection technology does not interfere with the active layer in NMOSTFT.
Step S25, in the first sub-district, data cable lead wire, the second sub-district corresponding to the region of second gate pattern to be formed, the 3rd sub-district corresponding to the region of the 3rd grid line to be formed and the 4th sub-district corresponding to the region of public electrode wire to be formed is formed photoresist protective layer; and the part that above-mentioned first pattern and above-mentioned second pattern are not photo-etched compound protective layer covering carries out second time patterning processes and processes, formation is positioned at the 3rd pattern in the sub-district of GOA-N, is positioned at the 4th pattern in AA region；Wherein, the region area that the region area that above-mentioned first pattern is etched away and above-mentioned second pattern are etched away has the second preset difference value；Above-mentioned 3rd pattern corresponds to second gate pattern (i.e. Ngate)；Above-mentioned 4th pattern includes: the pattern of the pattern being positioned at the 3rd grid line (i.e. Ngate) in the sub-district of AA-N and the public electrode wire being positioned at Com district.
The second gate pattern that step S26, utilization are formed in above-mentioned steps S25 is as metal mask, by ion implantation technology by N+Foreign ion is doped to the low-temperature polysilicon silicon active layer being positioned at the sub-district of GOA-N not by the both sides of second gate pattern covers, to form the N being connected with source electrode respectively+Source region, the N being connected with drain electrode+Drain region.Then the N in NMOSTFT region respectively+Source region, N+The LDD region territory (LightlyDopedDrain, low-doped drain region) of higher resistance value is formed in drain region.
Same, utilize the pattern of the 3rd grid line formed in above-mentioned steps S25 as metal mask, by ion implantation technology by N+Foreign ion is doped to the both sides that the low-temperature polysilicon silicon active layer being positioned at the sub-district of AA-N is not covered by the 3rd grid line, to form the N being connected with source electrode respectively+Source region, the N being connected with drain electrode+Drain region.Then the N in NMOSTFT region respectively+Source region, N+The LDD region territory (LightlyDopedDrain, low-doped drain region) of higher resistance value is formed in drain region.
After above-mentioned steps S26, the isostructural step of such as pixel electrode, passivation layer being subsequently formed on source electrode, drain electrode, the data wire being connected with source electrode and array base palte can continue to use the technological process of prior art, does not repeat them here.
Specific embodiment three
In the present embodiment three, first time etching technics forms being positioned at the gate pattern corresponding to PMOSTFT in the sub-district of GOA-P, be positioned at the part bar paten in AA region in array base palte；Second time etching technics formed be positioned at AA region corresponding to NMOSTFT grid line, be positioned at the sub-district of GOA-P corresponding to NMOSTFT gate pattern, be positioned at the public electrode wire in Com district and be positioned at the data cable lead wire in fan-out region.
Specifically comprising the following steps that of above-mentioned technique
Step S31, sequentially form on underlay substrate multiple for stopping light blocking layer that backlight is irradiated on LTPS, cover light blocking layer cushion, be positioned at above cushion and with light blocking layer low-temperature polysilicon silicon active layer one to one and the gate insulation layer covering low-temperature polysilicon silicon active layer.
Step S32, underlay substrate be formed over cover underlay substrate grid metal level.
Step S33, grid metal level is carried out first time patterning processes process, grid metal level corresponding to peripheral circuit area grid metal level Part I etching formed the first pattern, grid metal level corresponding to AA region grid metal layer second portion etching formed the second pattern；Wherein, the region area that the region area that grid metal level Part I etches away and grid metal layer second portion etch away has the first preset difference value；Above-mentioned first pattern includes: the second of the first grid pattern (i.e. Pgate) being positioned at the sub-district of GOA-P, the first reservation pattern covering the sub-district of GOA-N and covering fan-out region retains pattern；Above-mentioned second pattern includes: covers the 3rd of the sub-district of AA-N and retains pattern, covers the 4th reservation pattern in Com district and be positioned at the bar paten in other regions.
The first grid pattern that step S34, utilization are formed in above-mentioned steps S33 is as metal mask, by ion implantation technology by P+(source ion implantation is such as BF to foreign ion3) it is doped to the low-temperature polysilicon silicon active layer being positioned at the sub-district of GOA-P not by the both sides of first grid pattern covers, to form the P being connected with source electrode respectively+Source region, the P being connected with drain electrode+Drain region.
Now, the grid metal level not etched away due to the low-temperature polysilicon silicon active layer corresponding to NMOSTFT in AA region and the sub-district of GOA-N is completely covered, the therefore P in above-mentioned steps S14+Impure ion injection technology does not interfere with the active layer in NMOSTFT.
Step S35, in the first sub-district, the second sub-district corresponding to the region of second gate pattern to be formed, the 3rd sub-district corresponding to the region of the 3rd grid line to be formed, the 4th sub-district corresponding to the region of public electrode wire to be formed and fan-out area corresponding to the region of data cable lead wire to be formed is formed photoresist protective layer; and the part that above-mentioned first pattern and above-mentioned second pattern are not photo-etched compound protective layer covering carries out second time patterning processes and processes, formation is positioned at the 3rd pattern of peripheral circuit area, is positioned at the 4th pattern in AA region；Wherein, the region area that the region area that above-mentioned first pattern is etched away and above-mentioned second pattern are etched away has the second preset difference value；Above-mentioned 3rd pattern includes: is positioned at the second gate pattern (i.e. Ngate) in the sub-district of GOA-N and is positioned at the data cable lead wire in fan-out region；Above-mentioned 4th pattern includes: is positioned at the 3rd grid line (i.e. Ngate) in the sub-district of AA-N and is positioned at the public electrode wire in Com district.
The second gate pattern that step S36, utilization are formed in above-mentioned steps S35 is as metal mask, by ion implantation technology by N+Foreign ion is doped to the low-temperature polysilicon silicon active layer being positioned at the sub-district of GOA-N not by the both sides of second gate pattern covers, to form the N being connected with source electrode respectively+Source region, the N being connected with drain electrode+Drain region.Then the N in NMOSTFT region respectively+Source region, N+The LDD region territory (LightlyDopedDrain, low-doped drain region) of higher resistance value is formed in drain region.
Same, utilize the pattern of the 3rd grid line formed in above-mentioned steps S35 as metal mask, by ion implantation technology by N+Foreign ion is doped to the both sides that the low-temperature polysilicon silicon active layer being positioned at the sub-district of AA-N is not covered by the 3rd grid line, to form the N being connected with source electrode respectively+Source region, the N being connected with drain electrode+Drain region.Then the N in NMOSTFT region respectively+Source region, N+The LDD region territory (LightlyDopedDrain, low-doped drain region) of higher resistance value is formed in drain region.
After above-mentioned steps S36, the isostructural step of such as pixel electrode, passivation layer being subsequently formed on source electrode, drain electrode, the data wire being connected with source electrode and array base palte can continue to use the technological process of prior art, does not repeat them here.
Specific embodiment four
In the present embodiment four, first time etching technics forms the gate pattern corresponding to PMOSTFT being positioned at the sub-district of GOA-P in array base palte, is positioned at the part bar paten in AA region and is positioned at the public electrode wire in Com district；Second time etching technics formation is positioned at the grid line corresponding to NMOSTFT in AA region, is positioned at the gate pattern corresponding to NMOSTFT in the sub-district of GOA-P and is positioned at the data cable lead wire in fan-out region.
Specifically comprising the following steps that of above-mentioned technique
Step S41, sequentially form on underlay substrate multiple for stopping light blocking layer that backlight is irradiated on LTPS, cover light blocking layer cushion, be positioned at above cushion and with light blocking layer low-temperature polysilicon silicon active layer one to one and the gate insulation layer covering low-temperature polysilicon silicon active layer.
Step S42, underlay substrate be formed over cover underlay substrate grid metal level.
Step S43, grid metal level is carried out first time patterning processes process, grid metal level corresponding to peripheral circuit area grid metal level Part I etching formed the first pattern, grid metal level corresponding to AA region grid metal layer second portion etching formed the second pattern；Wherein, the region area that the region area that grid metal level Part I etches away and grid metal layer second portion etch away has the first preset difference value；Above-mentioned first pattern includes: the second of the first grid pattern (i.e. Pgate) being positioned at the sub-district of GOA-P, the first reservation pattern covering the sub-district of GOA-N and covering fan-out region retains pattern；Above-mentioned second pattern includes: the pattern of public electrode wire, covers the 3rd of the sub-district of AA-N and retains pattern and be positioned at the bar paten in other regions.
The first grid pattern that step S44, utilization are formed in above-mentioned steps S43 is as metal mask, by ion implantation technology by P+(source ion implantation is such as BF to foreign ion3) it is doped to the low-temperature polysilicon silicon active layer being positioned at the sub-district of GOA-P not by the both sides of first grid pattern covers, to form the P being connected with source electrode respectively+Source region, the P being connected with drain electrode+Drain region.
Now, the grid metal level not etched away due to the low-temperature polysilicon silicon active layer corresponding to NMOSTFT in AA region and the sub-district of GOA-N is completely covered, the therefore P in above-mentioned steps S14+Impure ion injection technology does not interfere with the active layer in NMOSTFT.
Step S45, in the first sub-district, data cable lead wire, the second sub-district corresponding to the region of second gate pattern to be formed, the 3rd sub-district corresponding to the region of the 3rd grid line to be formed and fan-out area corresponding to the region of data cable lead wire to be formed is formed photoresist protective layer; and the part that above-mentioned first pattern and above-mentioned second pattern are not photo-etched compound protective layer covering carries out second time patterning processes and processes, formation is positioned at the 3rd pattern of peripheral circuit area, is positioned at the 4th pattern in the sub-district of AA-N；Wherein, the region area that the region area that above-mentioned first pattern is etched away and above-mentioned second pattern are etched away has the second preset difference value；Above-mentioned 3rd pattern includes: the pattern of the pattern being positioned at the data cable lead wire in fan-out region and the second gate pattern (i.e. Ngate) being positioned at the sub-district of GOA-N；4th pattern is corresponding to the pattern of the 3rd grid line (i.e. Ngate).
The second gate pattern that step S46, utilization are formed in above-mentioned steps S45 is as metal mask, by ion implantation technology by N+Foreign ion is doped to the low-temperature polysilicon silicon active layer being positioned at the sub-district of GOA-N not by the both sides of second gate pattern covers, to form the N being connected with source electrode respectively+Source region, the N being connected with drain electrode+Drain region.Then the N in NMOSTFT region respectively+Source region, N+The LDD region territory (LightlyDopedDrain, low-doped drain region) of higher resistance value is formed in drain region.
Same, utilize the pattern of the 3rd grid line formed in above-mentioned steps S45 as metal mask, by ion implantation technology by N+Foreign ion is doped to the both sides that the low-temperature polysilicon silicon active layer being positioned at the sub-district of AA-N is not covered by the 3rd grid line, to form the N being connected with source electrode respectively+Source region, the N being connected with drain electrode+Drain region.Then the N in NMOSTFT region respectively+Source region, N+The LDD region territory (LightlyDopedDrain, low-doped drain region) of higher resistance value is formed in drain region.
After above-mentioned steps S46, the isostructural step of such as pixel electrode, passivation layer being subsequently formed on source electrode, drain electrode, the data wire being connected with source electrode and array base palte can continue to use the technological process of prior art, does not repeat them here.Further, the embodiment of the present invention additionally provides a kind of display base plate, and this display base plate adopts above-mentioned preparation method to obtain.
Further, the embodiment of the present invention additionally provides a kind of display device, and this display device includes above-mentioned display base plate.
Above-mentioned display device can be specifically that liquid crystal panel, liquid crystal display, LCD TV, ORGANIC ELECTROLUMINESCENCE DISPLAYS (OrganicLight-EmittingDisplay, be called for short OLED) panel, OLED display, OLED TV, DPF, mobile phone, panel computer etc. have product or the parts of any display function.
Above; being only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, any those familiar with the art is in the technical scope that the invention discloses; change can be readily occurred in or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with scope of the claims.
Claims (10)
1. a preparation method for display base plate, described display base plate includes peripheral circuit area and territory, effective display area；It is characterized in that, described preparation method includes:
The metal level covering described underlay substrate it is formed at underlay substrate；Wherein, described metal level includes the metal level Part I corresponding to described peripheral circuit area and the metal layer second portion corresponding to territory, described effective display area；
Described metal level carries out first time patterning processes process, so that described metal level Part I etching forms the first pattern, described metal layer second portion etching forms the second pattern；Wherein, the region area that the region area that described metal level Part I is etched away and described metal layer second portion are etched away has the first preset difference value；
Described first pattern and described second pattern carrying out second time patterning processes process, formation is positioned at the 3rd pattern of described peripheral circuit area, is positioned at the 4th pattern in territory, described effective display area；Wherein, the region area that the region area that described first pattern is etched away and described second pattern are etched away has the second preset difference value.
2. preparation method according to claim 1, it is characterised in that described display base plate is specially array base palte；Described peripheral circuit area includes: GOA gate driving circuit region and fan-out area；Described GOA gate driving circuit region includes: the first sub-district corresponding to P-type TFT and the second sub-district corresponding to N-type TFT；Territory, described effective display area includes: the 3rd sub-district corresponding to N-type TFT, the 4th sub-district corresponding to public electrode wire and other regions.
3. preparation method according to claim 2, it is characterised in that described preparation method includes:
The grid metal level covering described underlay substrate it is formed at underlay substrate；
Described grid metal level carrying out patterning processes for the first time process, the grid metal level Part I etching corresponding to described peripheral circuit area at described grid metal level forms the first pattern, corresponds to grid metal layer second portion etching formation second pattern in territory, described effective display area at described grid metal level；Wherein, the region area that the region area that described grid metal level Part I is etched away and described grid metal layer second portion are etched away has the first preset difference value；Described first pattern includes: the first grid pattern that is positioned at described first sub-district, cover described second sub-district first retain pattern and be positioned at the pattern of data cable lead wire of described fan-out area；Described second pattern includes: cover described 3rd sub-district second retains pattern, is positioned at the pattern of the public electrode wire in described 4th sub-district and is positioned at the bar paten in other regions described；
In described first sub-district, described data cable lead wire, described public electrode wire, described second sub-district corresponding to the region of second gate pattern to be formed and described 3rd sub-district corresponding to the region of the 3rd grid line to be formed is formed photoresist protective layer; and the part that described first pattern and described second pattern do not covered by described photoresist protective layer carries out second time patterning processes and processes, formed and be positioned at the 3rd pattern in described second sub-district, be positioned at the 4th pattern in described 3rd sub-district；Wherein, the region area that the region area that described first pattern is etched away and described second pattern are etched away has the second preset difference value；Described 3rd pattern corresponds to described second gate pattern；Described 4th pattern is corresponding to the pattern of described 3rd grid line.
4. preparation method according to claim 2, it is characterised in that described preparation method includes:
The grid metal level covering described underlay substrate it is formed at underlay substrate；
Described grid metal level carrying out patterning processes for the first time process, the grid metal level Part I etching corresponding to described peripheral circuit area at described grid metal level forms the first pattern, corresponds to grid metal layer second portion etching formation second pattern in territory, described effective display area at described grid metal level；Wherein, the region area that the region area that described grid metal level Part I etches away and described grid metal layer second portion etch away has the first preset difference value；Described first pattern includes: the first grid pattern that is positioned at described first sub-district, cover described second sub-district first retain pattern and be positioned at the pattern of data cable lead wire of described fan-out area；Described second pattern includes: cover described 3rd sub-district second retains pattern, covers the 3rd reservation pattern in described 4th sub-district and be positioned at the bar paten in other regions described；
In described first sub-district, described data cable lead wire, described second sub-district corresponding to the region of second gate pattern to be formed, described 3rd sub-district corresponding to the region of the 3rd grid line to be formed and described 4th sub-district corresponding to the region of public electrode wire to be formed is formed photoresist protective layer; and the part that described first pattern and described second pattern do not covered by described photoresist protective layer carries out second time patterning processes and processes, formed and be positioned at the 3rd pattern in described second sub-district, be positioned at the 4th pattern in territory, described effective display area；Wherein, the region area that the region area that described first pattern is etched away and described second pattern are etched away has the second preset difference value；Described 3rd pattern corresponds to described second gate pattern；Described 4th pattern includes: the pattern of the pattern being positioned at described 3rd grid line in described 3rd sub-district and the described public electrode wire being positioned at described 4th sub-district.
5. preparation method according to claim 2, it is characterised in that described preparation method includes:
The grid metal level covering described underlay substrate it is formed at underlay substrate；
Described grid metal level carrying out patterning processes for the first time process, the grid metal level Part I etching corresponding to described peripheral circuit area at described grid metal level forms the first pattern, corresponds to grid metal layer second portion etching formation second pattern in territory, described effective display area at described grid metal level；Wherein, the region area that the region area that described grid metal level Part I etches away and described grid metal layer second portion etch away has the first preset difference value；Described first pattern includes: the first grid pattern that is positioned at described first sub-district, cover described second sub-district first retain pattern and cover the second of described fan-out area and retain pattern；Described second pattern includes: cover described 3rd sub-district the 3rd retains pattern, covers the 4th reservation pattern in described 4th sub-district and be positioned at the bar paten in other regions described；
In described first sub-district, described second sub-district is corresponding to the region of second gate pattern to be formed, described 3rd sub-district is corresponding to the region of the 3rd grid line to be formed, described 4th sub-district corresponds to form photoresist protective layer on the region of data cable lead wire to be formed corresponding to region and the described fan-out area of public electrode wire to be formed, and the part that described first pattern and described second pattern do not covered by described photoresist protective layer carries out second time patterning processes and processes, form the 3rd pattern being positioned at described peripheral circuit area, it is positioned at the 4th pattern in territory, described effective display area；Wherein, the region area that the region area that described first pattern is etched away and described second pattern are etched away has the second preset difference value；Described 3rd pattern includes: is positioned at the described second gate pattern in described second sub-district and is positioned at the described data cable lead wire of described fan-out area；Described 4th pattern includes: is positioned at described 3rd grid line in described 3rd sub-district and is positioned at the described public electrode wire in described 4th sub-district.
6. preparation method according to claim 2, it is characterised in that described preparation method includes:
The grid metal level covering described underlay substrate it is formed at underlay substrate；
Described grid metal level carrying out patterning processes for the first time process, the grid metal level Part I etching corresponding to described peripheral circuit area at described grid metal level forms the first pattern, corresponds to grid metal layer second portion etching formation second pattern in territory, described effective display area at described grid metal level；Wherein, the region area that the region area that described grid metal level Part I etches away and described grid metal layer second portion etch away has the first preset difference value；Described first pattern includes: the first grid pattern that is positioned at described first sub-district, cover described second sub-district first retain pattern and cover the second of described fan-out area and retain pattern；Described second pattern includes: the pattern of public electrode wire, covers the 3rd of described 3rd sub-district and retains pattern and be positioned at the bar paten in other regions described；
In described first sub-district, described data cable lead wire, described second sub-district corresponding to the region of second gate pattern to be formed, described 3rd sub-district corresponding to the region of the 3rd grid line to be formed and described fan-out area corresponding to the region of data cable lead wire to be formed is formed photoresist protective layer; and the part that described first pattern and described second pattern do not covered by described photoresist protective layer carries out second time patterning processes and processes, formed and be positioned at the 3rd pattern of described peripheral circuit area, be positioned at the 4th pattern in described 3rd sub-district；Wherein, the region area that the region area that described first pattern is etched away and described second pattern are etched away has the second preset difference value；Described 3rd pattern includes: is positioned at the pattern of the described data cable lead wire of described fan-out area and is positioned at the described second gate pattern in described second sub-district；Described 4th pattern is corresponding to the pattern of described 3rd grid line.
7. the preparation method according to any one of claim 1 to 6, it is characterised in that described second pattern is made up of spaced multiple spirtes.
8. the preparation method according to any one of claim 1 to 6, it is characterised in that
Described first preset difference value is the 0～20% of the region area that described metal level Part I is etched away；
And/or,
Described second preset difference value is the 0～20% of the region area that described metal level Part I is etched away.
9. a display base plate, it is characterised in that described display base plate adopts the preparation method described in any one of the claims 1 to 8 to obtain.
10. a display device, it is characterised in that described display device includes display base plate as claimed in claim 9.
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| US6137578A (en) * | 1998-07-28 | 2000-10-24 | International Business Machines Corporation | Segmented bar-in-bar target |
| US6566184B1 (en) * | 2002-02-21 | 2003-05-20 | Taiwan Semiconductor Manufacturing Company | Process to define N/PMOS poly patterns |
| CN1536438A (en) * | 2003-04-08 | 2004-10-13 | 旺宏电子股份有限公司 | Method for eliminating key size deviation of dense pattern and single pattern |
| CN101599430A (en) * | 2008-06-03 | 2009-12-09 | 中芯国际集成电路制造(北京)有限公司 | The formation method of grating of semiconductor element and the control system of grid etch |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108987415A (en) * | 2018-06-26 | 2018-12-11 | 武汉华星光电技术有限公司 | A kind of array substrate and preparation method thereof, touch panel |
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| CN105742298B (en) | 2018-12-11 |
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