CN105741867B - Line decoder and memory - Google Patents

Line decoder and memory Download PDF

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Publication number
CN105741867B
CN105741867B CN201610067359.XA CN201610067359A CN105741867B CN 105741867 B CN105741867 B CN 105741867B CN 201610067359 A CN201610067359 A CN 201610067359A CN 105741867 B CN105741867 B CN 105741867B
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nmos tube
drain electrode
voltage
grid
pmos tube
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CN105741867A (en
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杨光军
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

A kind of line decoder and memory, the line decoder include：First order decoding circuit and second level decoding circuit, wherein：The first order decoding circuit, couples with the second level decoding circuit, suitable for the selection signal of generation and anti-phase selection signal are separately input into the second level decoding circuit；The second level decoding circuit includes the first bias voltage source and the second bias voltage source, and the output voltage values V of the first bias voltage sourcebiasPMeet：0≤|VbiasP|≤1/2×(VCGB‑VNEG)±Vt, the output voltage values V of second bias voltage sourcebiasNMeet：Vt≤|VbiasN|≤1/2×(VCGB‑VNEG)±Vt, and VCGBWith VbiasPDifference and VCGBWith VbiasNDifference be respectively less than preset value.Using the line decoder and memory, it is possible to reduce the circuit area of line decoder, reduces the cost of line decoder.

Description

Line decoder and memory
Technical field
The present invention relates to electronic circuit technology field, more particularly to a kind of line decoder and memory.
Background technology
Decoding is the inverse process of coding, and in coding, each binary code all imparts specific implication, illustrates One definite signal or object.The specific meanings of binary code state are translated the process come and be called decoding, realized The circuit of decoded operation is known as line decoder.That is, line decoder (decoder), which is one kind, will input binary system generation The state transition of code is into output signal, to represent the circuit of its original implication.
In the prior art, the working status of line decoder generally includes programming state, read states and erase status, no With working status, there are different operating voltages.Under different working statuses, the operating voltage of the transistor in line decoder Scope fluctuation is larger, and this requires the transistor in line decoder all allows for tolerating high voltage, it is therefore desirable to selects thick grid Oxygen transistor.However, the cost of thick grid oxygen transistor is higher, area is larger, causes the circuit area of line decoder larger, cost It is higher.
The content of the invention
Present invention solves the technical problem that being the circuit area for reducing line decoder, the cost of line decoder is reduced.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of line decoder, including：First order decoding circuit with And second level decoding circuit, wherein：
The first order decoding circuit, couples with the second level decoding circuit, suitable for by the selection signal of generation and Anti-phase selection signal is separately input into the second level decoding circuit；
The second level decoding circuit, including：First PMOS tube, the second PMOS tube, the 3rd PMOS tube, the 4th PMOS tube, 5th PMOS tube, the 6th PMOS tube, the first NMOS tube, the second NMOS tube, the 3rd NMOS tube and the 4th NMOS tube, wherein：
First PMOS tube, the power supply of source electrode and second level decoding circuit couple, grid and the 2nd PMOS The drain electrode coupling of pipe, drain electrode and the source electrode of the 3rd PMOS tube couple；
Second PMOS tube, the power supply of source electrode and second level decoding circuit couple, grid and the first PMOS The drain electrode coupling of pipe, drain electrode and the source electrode of the 4th PMOS tube couple；
3rd PMOS tube, grid and the first bias voltage source couple, and drain electrode misses coupling with first NMOS tube Connect；
4th PMOS tube, grid are coupled with first bias voltage source, drain electrode and the leakage of second NMOS tube The wordline output signal end of pole and second level decoding circuit couples；
First NMOS tube, grid and the second bias voltage source couple, source electrode and the grid coupling of the 4th NMOS tube Connect；
Second NMOS tube, grid are coupled with second bias voltage source, source electrode and the grid of the 3rd NMOS tube Pole couples, and drain electrode and the wordline output signal end of the second level decoding circuit couple；
3rd NMOS tube, source electrode are coupled with negative voltage source, and drain electrode and the source electrode of first NMOS tube couple；
4th NMOS tube, source electrode are coupled with the negative voltage source, and drain electrode and the source electrode of second NMOS tube couple；
5th PMOS tube, source electrode input address drive signal, grid input the anti-phase selection signal, drain electrode and institute State the drain electrode of the second PMOS tube and the source electrode coupling of the 4th PMOS tube；
6th PMOS tube, source electrode input preset voltage value, grid input the selection signal, drain electrode and the described 5th The drain electrode coupling of PMOS tube；
The output voltage V of first bias voltage sourcebiasPAnd the output voltage V of second bias voltage sourcebiasN Meet the following conditions：0≤|VbiasP|≤1/2×(VCGB-VNEG)±Vt, Vt≤|VbiasN|≤1/2×(VCGB-VNEG)±Vt, and VCGBWith VbiasPDifference be less than preset value, VbiasNWith VNEGDifference be respectively less than preset value, VCGBFor the second level decoding circuit The maximum output voltage value of power supply, VtFor metal-oxide-semiconductor threshold voltage.
Optionally, the first order decoding circuit includes：First NAND gate circuit, the second NAND gate circuit, the 7th PMOS Pipe, the 8th PMOS tube, the 5th NMOS tube, the 6th NMOS tube, the 7th NMOS tube and the 8th NMOS tube, wherein：
7th PMOS tube, the power supply of source electrode and first order decoding circuit couple, grid and the 6th NMOS The grid coupling of pipe, drain electrode and the drain electrode of the 6th NMOS tube couple；
8th PMOS tube, the power supply of source electrode and first order decoding circuit couple, grid and the 7th NMOS The grid coupling of pipe, drain electrode and the drain electrode of the 7th NMOS tube couple；
5th NMOS tube, source electrode and the 3rd bias voltage source couple, and grid is defeated with first NAND gate circuit Outlet couples, and drain electrode exports the anti-phase selection signal；
6th NMOS tube, source electrode are coupled with the 3rd bias voltage source, grid and the leakage of the 8th PMOS tube Pole couples, and drain electrode and the drain electrode of the 5th NMOS tube couple；
7th NMOS tube, source electrode are coupled with the 3rd bias voltage source, grid and the leakage of the 6th NMOS tube Pole couples, and drain electrode and the drain electrode of the 8th NMOS tube couple；
8th NMOS tube, source electrode are coupled with the 3rd bias voltage source, grid and second NAND gate circuit Output terminal coupling, drain electrode exports the selection signal；
First NAND gate circuit, including three signal input parts, a control terminal and an output terminal；
Second NAND gate circuit, including a signal input part and a control terminal, the signal input part with The output terminal coupling of first NAND gate circuit, the control terminal are suitable for input control signal.
Optionally, the output voltage of the power supply of the first order decoding circuit and first NAND gate circuit is defeated The difference for going out the magnitude of voltage of signal is less than 5V.
Optionally, the 6th PMOS tube source electrode input preset voltage value by the first order decoding circuit power supply Power supply provides.
Optionally, when the line decoder switches to read states, the power supply of the second level decoding circuit it is defeated Go out voltage when the first duration arrives from the first voltage value saltus step to second voltage value；
The output voltage of the power supply of the first order decoding circuit is when the first duration arrives from the first voltage It is worth saltus step to the second voltage value；
The output voltage of first bias voltage source is when first duration arrives from 0 saltus step to the first voltage Value；
The corresponding magnitude of voltage of level of described address drive signal is when first duration arrives from the first voltage It is worth saltus step to the second voltage value；
The output voltage of 3rd bias voltage source is when first duration arrives from 0 saltus step to the first voltage Value；
The first voltage value is the output end voltage of first NAND gate, and the first voltage value is less than described the Two magnitudes of voltage.
Optionally, the preset value is 5V.
Optionally, when the line decoder is in programming state and read states, the negative voltage source output voltage is 0；When the line decoder is in erase status, the negative voltage source output voltage is negative value.
The embodiment of the present invention additionally provides a kind of memory, including any of the above-described kind of line decoder.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that：
By increasing the first bias voltage source and the second bias voltage source, the output voltage of the first bias voltage source is controlled VbiasPAnd second bias voltage source output voltage VbiasNValue under different working modes so that in different working condition Under, the V of any metal-oxide-semiconductor in the conduction stateGSAnd VDSNo more than VCGBWith VbiasPDifference or VbiasNWith VNEGDifference, Therefore thin grid oxygen transistor can be used, so as to reduce the circuit area of line decoder, reduces the cost of line decoder.
Brief description of the drawings
Fig. 1 (a) is the circuit structure of the first order level shift circuit of the first order decoding circuit of existing line decoder Figure；
Fig. 1 (b) is the circuit structure of the second level level shift circuit of the first order decoding circuit of existing line decoder Figure；
Fig. 2 is the circuit structure diagram of the second level decoding circuit of existing line decoder；
Fig. 3 is the circuit structure diagram of the second level decoding circuit of the line decoder in the embodiment of the present invention；
Fig. 4 is the circuit structure diagram of the first order decoding circuit of the line decoder in the embodiment of the present invention.
Embodiment
Reference Fig. 1 (a), Fig. 1 (b) and Fig. 2, give a kind of circuit structure diagram of existing line decoder.Row decoding Device includes first order decoding circuit and second level decoding circuit, the circuit structure diagram of first order decoding circuit with reference to Fig. 1 (a), Fig. 1 (b), the structure chart of second level decoding circuit is with reference to Fig. 2.
In Fig. 1 (a), first order decoding circuit includes NAND gate circuit, not circuit, first order level shift circuit. The level of the output signal of NAND gate circuit is Vdd, VddUsually 1.5V.When the output of NAND gate circuit changes, supply Power supply VCGBBy first order level shift circuit, selection signal Sel and corresponding anti-phase selection signal Selb is generated.
First order level shift circuit includes：PMOS tube MP9, PMOS tube MP10, NMOS tube MN9 and NMOS tube MN10, Wherein：
The source electrode of PMOS tube MP9 and the power supply V of first order decoding circuitCGBCoupling, the leakage of grid and PMOS tube MP10 Pole couples, and drain electrode and the drain electrode of NMOS tube MN9 couple；The source electrode and V of PMOS tube MP10CGBCoupling, grid is with PMOS tube MP9's Drain electrode and the drain electrode of NMOS tube MN9 coupling, drain electrode and the drain electrode of NMOS tube MN10 couple；The grid of NMOS tube MN9 with it is non- The output terminal coupling of gate circuit, source electrode are coupled with ground wire；The output terminal coupling of the grid and not circuit of NMOS tube MN10, source electrode Coupled with ground wire.The drain electrode of PMOS tube MP9 exports anti-phase selection signal, the drain electrode output selection signal of PMOS tube MP10.
NAND gate circuit includes three input terminals and a control terminal.Three input terminals are followed successively by X, Y and Z, control Hold as PD.The output terminal of NAND gate circuit is coupled with the first input end of the grid of NMOS tube MN9 and not circuit.NOT gate electricity Second input terminal on road holds PD in order to control, and the grid of output terminal and NMOS tube MN10 couples.
Fig. 1 (b) is the second level level shift circuit of first order decoding circuit.Fig. 1 (a) generation selection signal Sel with And anti-phase selection signal Selb is input in the level shift circuit of the second level.Second level level shift circuit includes：PMOS tube MP11, PMOS tube MP12, PMOS tube MP13, PMOS tube MP14, NMOS tube MN11 and NMOS tube MN12, wherein：
The source electrode and V of PMOS tube MP11CGBCoupling, drain electrode output signal Selh；The source electrode and V of PMOS tube MP12CGBCoupling, The drain electrode of grid and the grid and NMOS tube MN12 of NMOS tube MN11 couples, and drain electrode and the drain electrode of PMOS tube MP11 couple； The source electrode and V of PMOS tube MP13CGBCoupling, the drain electrode of grid and the grid and NMOS tube MN11 of NMOS tube MN12 couple, drain electrode Drain electrode with NMOS tube MN12 couples；The source electrode and V of PMOS tube MP14CGBCoupling, drain electrode output signal Selbh；NMOS tube MN11 Source electrode output be connected with the source electrode of NMOS tube MN12, input negative pressure VNEG, drain electrode and the drain electrode of PMOS tube MP12 couple；NMOS The drain electrode of pipe MN12 is coupled with the drain electrode of PMOS tube MP13.
Reference Fig. 2, gives the structure chart of the second level decoding circuit of existing line decoder.Second level decoding circuit bag NMOS tube MN13, NMOS tube MN14 and PMOS tube MP15 are included, wherein：
The drain electrode input XPCG (m of NMOS tube MN13:0), grid inputs the signal Selh of generation in Fig. 1 (b), source electrode with The drain electrode coupling of PMOS tube MP15；The source electrode input XPCG (m of PMOS tube MP15:0), grid inputs the signal of generation in Fig. 1 (b) Selbh, drain electrode output control gate signal CG (m:0)；The drain electrode of NMOS tube MN14 is coupled with the source electrode of NMOS tube MN13, and grid is defeated Enter the signal Selbh of generation in Fig. 1 (b), source electrode is coupled with ground wire.
When line decoder is in programming state, VCGBMagnitude of voltage be 8V；When line decoder is in read states, VCGB's Magnitude of voltage is 4V；When line decoder is in erase status, VCGBMagnitude of voltage be reduced to 0V from 1.5V.Under three kinds of states, VCGB、VNEG、XPCG(m:And CG (m 0):0) corresponding magnitude of voltage is referred to table 1 below.
Signal end Programming state Read states Erase status
VCGB 8V 4V 1.5V→0
VNEG 0 0 0→-7V
XPCG(m:0) 8V/0 4V/0 -7V/0
CG(m:0) 8V/0 4V/0 -7V/0V
Table 1
When line decoder works, due to VCGBAnd XPCG (m:0) magnitude of voltage is higher, causes first order decoding circuit And the second corresponding V of metal-oxide-semiconductor in the decoding circuit of poleGSAnd VDSIt is larger.For example, when line decoder is in programming shape During state, VCGBFor 8V, when NMOS tube MN9 is turned on, if the grid voltage of NMOS tube is 0, the corresponding V of NMOS tube MN9DSAnd VDS It is 8V.That is, in the course of work of line decoder, the V on each metal-oxide-semiconductorGSAnd VDS5V can be frequently larger than, this is just The metal-oxide-semiconductor in line decoder is needed to bear larger voltage, it is therefore desirable to using thick grid oxygen transistor.
In embodiments of the present invention, when the magnitude of voltage of the power supply of the second level decoding circuit of line decoder is higher, The V of any metal-oxide-semiconductorGSAnd VDSNot over preset voltage value, therefore thin grid oxygen transistor can be used, so as to subtract The circuit area of few line decoder, reduces the cost of line decoder.
It is understandable to enable above-mentioned purpose, feature and the beneficial effect of the present invention to become apparent, below in conjunction with the accompanying drawings to this The specific embodiment of invention is described in detail.
An embodiment of the present invention provides a kind of line decoder, the line decoder includes first order decoding circuit and second Level decoding circuit.First order decoding circuit can produce selection signal Sel and anti-phase selection signal Selb, and be separately input into Corresponding port in the decoding circuit of the second level.
In synchronization, the level of selection signal Sel and the level of anti-phase selection signal Selb are anti-phase, that is, work as selection When the level of signal Sel is high level, the level of anti-phase selection signal Selb is low level；On the contrary, when selection signal Sel's When level is low level, the level of anti-phase selection signal Selb is high level.
With reference to Fig. 3, the circuit structure diagram of the second level decoding circuit of line decoder in the embodiment of the present invention is given.
In embodiments of the present invention, second level decoding circuit includes：First PMOS tube MP1, the second PMOS tube MP2, the 3rd PMOS tube MP3, the 4th PMOS tube MP4, the 5th PMOS tube MP5, the 6th PMOS tube MP6, the first NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3 and the 4th NMOS tube MN4.
First PMOS tube MP1 and the second PMOS tube MP2 composition pull-up latch cicuits, and in the presence of the conducting speed of the two Between it is poor.The source electrode of first PMOS tube MP1 and the power supply V of second level decoding circuitCGBCoupling, grid and the second PMOS tube MP2 Drain electrode coupling, drain electrode couples with the source electrode of the 3rd PMOS tube MP3.The source electrode of second PMOS tube MP2 and power supply VCGBCoupling Connect, the drain electrode coupling of grid and the first PMOS tube MP1, drain electrode and the source electrode of the 4th PMOS tube MP4 couple.
3rd PMOS tube MP3 and the 4th PMOS tube MP4 forms the first bias circuit.The grid of 3rd PMOS tube MP3 and One bias voltage source couples, and drain electrode and the drain electrode of the first NMOS tube MN1 couple, the drain electrode coupling of source electrode and the first PMOS tube MP1, The output voltage values of first bias voltage source are VbiasP.The grid of 4th PMOS tube MP4 and the first bias voltage source couple, drain electrode Drain electrode with the second NMOS tube MN2 couples, the drain electrode coupling of source electrode and the second PMOS tube MP2.
First NMOS tube MN1 and the second NMOS tube MN2 forms the second bias circuit.The grid of first NMOS tube MN1 and Two bias voltage sources couple, and the grid of source electrode and the 4th NMOS tube MN4 couple, and drain electrode and the drain electrode of the 3rd PMOS tube MP3 couple, The output voltage values of second bias voltage source are VbiasN.The grid of second NMOS tube MN2 and the second bias voltage source couple, source electrode Coupled with the grid of the 3rd NMOS tube MN3, drain electrode misses coupling with the 4th PMOS tube MP4's.
In embodiments of the present invention, the output voltage values V of the first bias voltage sourcebiasPMeet the following conditions：0≤|VbiasP |≤1/2×(VCGB-VNEG)±Vt, and VCGBWith VbiasPDifference be less than preset value；The output voltage values of second bias voltage source VbiasNMeet the following conditions：Vt≤|VbiasN|≤1/2×(VCGB-VNEG)±Vt, and VbiasNWith VNEGDifference be less than preset value.
In an embodiment of the present invention, preset value 5V.Due in the on-state, the in the first bias circuit the 3rd The V of PMOS tube MP3 and the 4th PMOS tube MP4GSAnd VDSIt is approximately VCGBWith VbiasPDifference, therefore, the 3rd PMOS tube MP3 with The V of 4th PMOS tube MP4GSAnd VDSIt is not more than 5V.Similarly, the V of the first NMOS tube MN1 and the second NMOS tube MN2GSWith And VDSIt is not more than 5V.
3rd NMOS tube MN3 and the 4th NMOS tube MN4 composition pull-down latch circuits.The source electrode of 3rd NMOS tube MN3 with Negative voltage source VNEGCoupling, drain electrode and the source electrode of the first NMOS tube MN1 couple, and the source electrode of grid and the second NMOS tube MN2 couple. The source electrode of 4th NMOS tube MN4 is coupled with negative voltage source, and drain electrode and the source electrode of the second NMOS tube MN2 couple, grid and first The source electrode coupling of NMOS tube MN1.
In embodiments of the present invention, when line decoder is operated in different working statuses, negative voltage source VNEGOutput electricity Pressure is different.When line decoder is operated in programming state, negative voltage source VNEGOutput voltage be 0；When line decoder is operated in reading During state, negative voltage source VNEGOutput voltage be 0；When line decoder is operated in erase status, negative voltage source VNEGOutput Voltage is negative value.
5th PMOS tube MP5 and the 6th PMOS tube MP6 composition input circuits.The source electrode input ground of 5th PMOS tube MP5 Location drive signal XPCG (m:0), grid input inversion selection signal Selb, drain electrode and the drain electrode of the second PMOS tube MP2 and the The source electrode coupling of four PMOS tube MP4.The source electrode input preset voltage value V of 6th PMOS tube MP6P2, grid input select signal Sel, drain electrode and the drain electrode of the 5th PMOS tube MP5 couple.
With reference to Fig. 4, a kind of circuit structure of the first order decoding circuit of line decoder in the embodiment of the present invention is given Figure.
In embodiments of the present invention, first order decoding circuit includes：First NAND gate circuit, the second NAND gate circuit, Seven PMOS tube MP7, the 8th PMOS tube MP8, the 5th NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7 and the 8th NMOS tube MN8, wherein：
The source electrode of 7th PMOS tube MP7 and power supply VP1The grid of coupling, grid and the 6th NMOS tube MN6, the 7th The drain electrode of NMOS tube MN7 and the drain electrode of the 8th NMOS tube MN8 coupling, drain electrode and the drain electrode of the 6th NMOS tube MN6 couple.8th The source electrode of PMOS tube MP8 and power supply VP1The drain electrode of the grid, the 5th NMOS tube MN5 of coupling, grid and the 7th NMOS tube MN7 And the 6th NMOS tube MN6 drain electrode coupling, drain electrode misses coupling with the 7th NMOS tube MN7.
The grid of 5th NMOS tube MN5 and the output terminal of the first NAND gate circuit couple；Source electrode and the 3rd bias voltage source Coupling, the output voltage values of the 3rd bias voltage source are Xdbias；Drain as the output terminal of anti-phase selection signal Selb.6th The source electrode of NMOS tube MN6 is coupled with Xdbias；The source electrode of 7th NMOS tube MN7 is coupled with Xdbias；The grid of 8th NMOS tube MN8 Pole and the output terminal of the second NAND gate circuit couple, and source electrode is coupled with Xdbias, is drained as the output terminal of selection signal Sel.
First NAND gate circuit includes three input terminals and a control terminal, and three input terminals are followed successively by X, Y and Z, Control terminal is PD.Second NAND gate circuit includes an input terminal and a control terminal, the input terminal of the second NAND gate circuit Coupled with the output terminal of the first NAND gate circuit, control terminal PD.
In practical applications, the working status of line decoder includes programming state, read states and erase status.In difference Working status, corresponding working status parameter can be pre-set.When knowing the working status of line decoder, you can adjust Take corresponding working status parameter.
With reference to table 2, give the line decoder in one embodiment of the invention and be operated in programming state, read states and erasing During state, the corresponding working status parameter of each signal input part voltage.
Table 2
Below under different conditions, the workflow of second level decoding circuit illustrates.
1) line decoder is in programming state.
Under initial state, VCGB=8V.When the level of selection signal Sel is low level, the level of selection signal Sel Corresponding magnitude of voltage is 4V.The source voltage of 6th PMOS tube is 4V, grid voltage 4V, drain voltage 4V+Vt, namely is leaked Pole tension is 4.5V, therefore the 6th PMOS tube MP6 ends.Due to the leakage of the grid and the second PMOS tube MP2 of the first PMOS tube MP1 Pole couples, and the drain electrode of the second PMOS tube MP2 is coupled with the drain electrode of the 6th PMOS tube, therefore when the 6th PMOS tube MP6 is turned on, the The grid voltage of one PMOS tube MP1 is 4.5V, therefore the first PMOS tube MP1 is in the conduction state.The grid electricity of second PMOS tube MP2 Pressure is equal with the drain voltage of the first PMOS tube MP1, when the first PMOS tube MP1 is turned on, the grid voltage of the second PMOS tube MP2 For 8V, therefore the second PMOS tube MP2 is in cut-off state, the grid voltage V of the 3rd PMOS tube M34biasP=4V, therefore the 3rd PMOS tube MP3 is turned on, therefore controls gate signal CG (m:0) magnitude of voltage maintains 0V.
Namely：Under initial state, CG (m:0) magnitude of voltage is 0V.
When the level of anti-phase selection signal is low level, and XPCG (m:0) when being 8V, the 5th PMOS tube MP5 conductings.This When, the source voltage of the 5th PMOS tube MP5 is 8V, and grid voltage is the corresponding magnitude of voltage of level of anti-phase selection signal Selb, Drain voltage is 8V.Correspondingly, the grid voltage of the first PMOS tube MP1 is 8V, and the first PMOS tube MP1 ends.Second PMOS tube MP4 is turned on, its drain voltage is 8V.4th PMOS tube MP4 is turned on, its drain voltage is 8V, namely CG (m:0) magnitude of voltage is 8V。
When the level of anti-phase selection signal is low level, and XPCG (m:0) when being 4V, the 5th PMOS tube MP5 conductings.Second PMOS tube MP2 ends, and the drain voltage of the second PMOS tube is 4V.Namely the 4th the source voltage of PMOS tube be 4V, the 4th PMOS tube is ended, CG (m:0) current potential is pulled down to rapidly 0.Namely：As XPCG (m:0) when being 4V, CG (m:0) magnitude of voltage For 0V.
2) line decoder is in read states.
It is not immediately to adjust the voltage of each input terminal to preset value when line decoder switches to read states, but Preset value is adjusted to through buffering after a while and then by the voltage of each input terminal.
With reference to table 2, when line decoder switches to read states, after the first duration, just by first order decoding circuit The output voltage of power supply, the output voltage of the power supply of second level decoding circuit, address drive signal XPCG (m:0) The corresponding magnitude of voltage of level is from VddSaltus step is to 4V, by the defeated of the output voltage of the first bias voltage source and the 3rd bias voltage source Go out voltage from 0 saltus step to Vdd。
After the completion of the voltage adjustment of each input terminal, the output voltage of the power supply of first order decoding circuit, the second level The output voltage and address drive signal XPCG (m of the power supply of decoding circuit:0) the corresponding magnitude of voltage of level is The output voltage of 4V, the output voltage of the first bias voltage source and the 3rd bias voltage source is Vdd。
In an embodiment of the present invention, Vdd=1.5V, therefore, after the completion of the voltage adjustment of each input terminal, the first biasing The output voltage of the output voltage of voltage source and the 3rd bias voltage source is 1.5V.
After line decoder switches to read states, its workflow is referred to line decoder and switches to the stream after programming state Journey, does not repeat herein.
3) line decoder is in erase status.
It is similar that read states are switched to line decoder, are not by each input when line decoder switches to erase status The voltage at end is adjusted to preset value.But it is adjusted to default through buffering after a while and then by the voltage of each input terminal Value.
With reference to table 2, when line decoder switches to erase status, after the second duration, by the confession of first order decoding circuit The output voltage of power supply is adjusted to 0 from 3V, and the output voltage of the power supply of second level decoding circuit is adjusted to 0 from 3V, The output voltage of first bias voltage source is adjusted to -4V from 0, the output voltage of the second bias voltage source is adjusted to from 3V - 4V, by XPCG (m:0) it is adjusted to 0V.
Under initial state, VCGB=0V.When the level of selection signal Sel is low level, due to the 6th PMOS tube MP6 Source voltage VP2=0, therefore the 6th PMOS tube MP6 ends.Since the grid voltage of the first NMOS tube MN1 is -4V, the The source voltage of one NMOS tube MN1 is -4.5V, namely the grid voltage of the 4th NMOS tube MN4 is -4.5V.4th NMOS tube MN4 Source voltage be -7V, therefore the 4th NMOS tube MN4 is turned on.Correspondingly, the second NMOS tube MN2 is turned on, at this time, CG (m:0) For -7V.
That is, in initial state, the source voltage of the 4th NMOS tube MN4 is -7V, and grid voltage is -4.5V, drain electrode Voltage is -7V.The source voltage of second NMOS tube MN2 is -7V, and grid voltage is -4V, and drain voltage is -7V.4th PMOS tube The drain voltage of MP4 is -7V, and grid voltage is -4V, and source voltage is -3.5V.The grid voltage of first PMOS tube MP1 for- 3.5V, therefore turn on, source voltage 0V, drain voltage 0V.The grid voltage of second PMOS tube MP2 is 0V, source voltage For 0V, drain voltage is -3.5V.The source voltage of 3rd PMOS tube MP3 is 0V, and grid voltage is -4V, drain voltage 0V. The grid voltage of first NMOS tube MN1 is -4V, and drain voltage 0V, source voltage is -4.5V.The drain electrode of 3rd NMOS tube MN3 Voltage is -4.5V, and grid voltage is -7V, and source voltage is -7V.
From the point of view of the source electrode, grid and drain voltage of each metal-oxide-semiconductor, any metal-oxide-semiconductor in the decoding circuit of the second level VGSAnd VDSNot less than 5V.
When the level of anti-phase selection signal Selb is low level, and XPCG (m:0) when being 0V, the state of its each metal-oxide-semiconductor Each metal-oxide-semiconductor state being referred under initial state.
When the level of anti-phase selection signal Selb is low level, and XPCG (m:0) when being 3V, the first PMOS tube MP1 cut-offs, Second PMOS tube MP2 is turned on, and the drain voltage of the second PMOS tube MP2 is 0V.Correspondingly, the 4th PMOS tube turns on, the 4th PMOS The drain voltage of pipe is 0V, namely CG (m:0) it is 0V.
That is, in embodiments of the present invention, increase the first bias voltage source and the second bias voltage source, pass through control Make the output voltage V of the first bias voltage sourcebiasPAnd second bias voltage source output voltage VbiasNIn different working modes Under value so that the V of any metal-oxide-semiconductor in the conduction stateGSAnd VDSFor VCGBWith VbiasPDifference or VNEGWith VbiasNIt Difference.By adjusting VbiasPAnd VbiasNValue, can cause VCGBWith VbiasPDifference be less than 5V, VNEGWith VbiasNDifference be less than 5V, Therefore thin grid oxygen transistor can be used to substitute thick grid oxygen transistor, so as to reduce the area of line decoder, reduces row and translate The cost of code device.
As can be known from Table 2, when line decoder is in programming state, the electricity of the power supply output of first order decoding circuit Pressure value VP1=8V.If the output voltage V of the first NAND gate circuitdd=1.5V, then the 7th PMOS tube in first order decoding circuit MP7, the 8th PMOS tube MP8, the 5th NMOS tube MP5, the 6th NMOS tube MN6, the 7th NMOS tube MN7 and the 8th NMOS tube MN8 In conducting, V thereonGSAnd VDSIn 6.5V or so.
In embodiments of the present invention, when line decoder is in programming state, the can be controlled by external control circuit The output voltage V of one NAND gate circuitdd=4V；5th NMOS tube MN4, the 6th NMOS tube MN6, the 7th NMOS tube MN7 and The voltage Xdbias of the source electrodes of four NMOS tubes such as eight NMOS tube MN8 rises to 4V from 0V.At this time, in first order decoding circuit The V of all metal-oxide-semiconductorsGSAnd VDSNot over 5V, thus all metal-oxide-semiconductors in first order decoding circuit can use it is thin Grid oxygen transistor.When all metal-oxide-semiconductors in first order decoding circuit use thin grid oxygen transistor, first order decoding circuit Area can be reduced, and cost can reduce.
The embodiment of the present invention additionally provides a kind of memory, and the memory can include the row provided in above-described embodiment Decoder, using the line decoder to address signal into row decoding.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, are not departing from this In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute Subject to the scope of restriction.

Claims (8)

  1. A kind of 1. line decoder, it is characterised in that including：First order decoding circuit and second level decoding circuit, wherein：
    The first order decoding circuit, couples with the second level decoding circuit, suitable for by the selection signal of generation and anti-phase Selection signal is separately input into the second level decoding circuit；
    The second level decoding circuit, including：First PMOS tube, the second PMOS tube, the 3rd PMOS tube, the 4th PMOS tube, the 5th PMOS tube, the 6th PMOS tube, the first NMOS tube, the second NMOS tube, the 3rd NMOS tube and the 4th NMOS tube, wherein：
    First PMOS tube, the power supply of source electrode and second level decoding circuit couple, grid and second PMOS tube Drain electrode coupling, drain electrode and the source electrode of the 3rd PMOS tube couple；
    Second PMOS tube, the power supply of source electrode and second level decoding circuit couple, grid and first PMOS tube Drain electrode coupling, drain electrode and the source electrode of the 4th PMOS tube couple；
    3rd PMOS tube, grid and the first bias voltage source couple, and drain electrode misses coupling with first NMOS tube；
    4th PMOS tube, grid and first bias voltage source couple, the drain electrode of drain electrode and second NMOS tube with And the wordline output signal end coupling of second level decoding circuit；
    First NMOS tube, grid and the second bias voltage source couple, and source electrode and the grid of the 4th NMOS tube couple；
    Second NMOS tube, grid are coupled with second bias voltage source, source electrode and the grid coupling of the 3rd NMOS tube Connect, drain electrode and the wordline output signal end of the second level decoding circuit couple；
    3rd NMOS tube, source electrode are coupled with negative voltage source, and drain electrode and the source electrode of first NMOS tube couple；
    4th NMOS tube, source electrode are coupled with the negative voltage source, and drain electrode and the source electrode of second NMOS tube couple；
    5th PMOS tube, source electrode input address drive signal, grid input the anti-phase selection signal, drain electrode and described the The source electrode of the drain electrode of two PMOS tube and the 4th PMOS tube couples；
    6th PMOS tube, source electrode input preset voltage value, grid input the selection signal, drain electrode and the 5th PMOS The drain electrode coupling of pipe；
    The output voltage V of first bias voltage sourcebiasPAnd the output voltage V of second bias voltage sourcebiasNMeet The following conditions：0≤|VbiasP|≤1/2×(VCGB-VNEG)±Vt, Vt≤|VbiasN|≤1/2×(VCGB-VNEG)±Vt, and VCGBWith VbiasPDifference be less than preset value, VbiasNWith VNEGDifference be less than the preset value, VCGBFor the power supply of the second level decoding circuit The maximum output voltage value of power supply, VNEGFor the output voltage values of negative voltage source, VtFor any metal-oxide-semiconductor threshold value electricity in foregoing circuit Pressure.
  2. 2. line decoder as claimed in claim 1, it is characterised in that the first order decoding circuit includes：First NAND gate Circuit, the second NAND gate circuit, the 7th PMOS tube, the 8th PMOS tube, the 5th NMOS tube, the 6th NMOS tube, the 7th NMOS tube with And the 8th NMOS tube, wherein：
    7th PMOS tube, the power supply of source electrode and first order decoding circuit couple, grid and the 6th NMOS tube Grid couples, and drain electrode and the drain electrode of the 6th NMOS tube couple；
    8th PMOS tube, the power supply of source electrode and first order decoding circuit couple, grid and the 7th NMOS tube Grid couples, and drain electrode and the drain electrode of the 7th NMOS tube couple；
    5th NMOS tube, source electrode and the 3rd bias voltage source couple, the output terminal of grid and first NAND gate circuit Coupling, drain electrode export the anti-phase selection signal；
    6th NMOS tube, source electrode are coupled with the 3rd bias voltage source, grid and the drain electrode coupling of the 8th PMOS tube Connect, drain electrode and the drain electrode of the 5th NMOS tube couple；
    7th NMOS tube, source electrode are coupled with the 3rd bias voltage source, grid and the drain electrode coupling of the 6th NMOS tube Connect, drain electrode and the drain electrode of the 8th NMOS tube couple；
    8th NMOS tube, source electrode are coupled with the 3rd bias voltage source, and grid is defeated with second NAND gate circuit Outlet couples, and drain electrode exports the selection signal；
    First NAND gate circuit, including three signal input parts, a control terminal and an output terminal；Described second with Not circuit, including a signal input part and a control terminal, the signal input part and first NAND gate circuit Output terminal coupling, the control terminal is suitable for input control signal.
  3. 3. line decoder as claimed in claim 2, it is characterised in that the output of the power supply of the first order decoding circuit The difference of the magnitude of voltage of the output signal of voltage and first NAND gate circuit is less than 5V.
  4. 4. line decoder as claimed in claim 3, it is characterised in that the predeterminated voltage of the source electrode input of the 6th PMOS tube Value is provided by the power supply of the first order decoding circuit.
  5. 5. line decoder as claimed in claim 4, it is characterised in that described when the line decoder switches to read states The output voltage of the power supply of second level decoding circuit is when the first duration arrives from the first voltage value saltus step to second voltage Value；
    The output voltage of the power supply of the first order decoding circuit is jumped when the first duration arrives from the first voltage value Fade to the second voltage value；
    The output voltage of first bias voltage source is when first duration arrives from 0 saltus step to the first voltage value；
    The corresponding magnitude of voltage of level of described address drive signal is jumped when first duration arrives from the first voltage value Fade to the second voltage value；
    The output voltage of 3rd bias voltage source is when first duration arrives from 0 saltus step to the first voltage value；
    The first voltage value is the output end voltage of first NAND gate, and the first voltage value is less than the described second electricity Pressure value.
  6. 6. line decoder as claimed in claim 1, it is characterised in that the preset value is 5V.
  7. 7. line decoder as claimed in claim 1, it is characterised in that when the line decoder is in programming state and reads shape During state, the output voltage of the negative voltage source is 0；When the line decoder is in erase status, the negative voltage source it is defeated It is negative value to go out voltage.
  8. 8. a kind of memory, it is characterised in that including such as claim 1~7 any one of them line decoder.
CN201610067359.XA 2016-01-29 2016-01-29 Line decoder and memory Active CN105741867B (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101038790A (en) * 2006-03-17 2007-09-19 意法半导体股份有限公司 Level shifter for semiconductor memory device implemented with low-voltage transistors
CN103117085A (en) * 2013-01-25 2013-05-22 上海宏力半导体制造有限公司 Bias voltage generating circuit and memory of line decoder
CN103345934A (en) * 2013-06-03 2013-10-09 上海宏力半导体制造有限公司 Decoding circuit for voltage of control grid

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101635165B (en) * 2008-07-21 2011-12-14 上海华虹Nec电子有限公司 Decoding circuit using low-voltage MOS transistors to realize high-voltage resistance, and realization method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101038790A (en) * 2006-03-17 2007-09-19 意法半导体股份有限公司 Level shifter for semiconductor memory device implemented with low-voltage transistors
CN103117085A (en) * 2013-01-25 2013-05-22 上海宏力半导体制造有限公司 Bias voltage generating circuit and memory of line decoder
CN103345934A (en) * 2013-06-03 2013-10-09 上海宏力半导体制造有限公司 Decoding circuit for voltage of control grid

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