CN105720560B - Current transformer three-level signal protects circuit - Google Patents
Current transformer three-level signal protects circuit Download PDFInfo
- Publication number
- CN105720560B CN105720560B CN201410723107.9A CN201410723107A CN105720560B CN 105720560 B CN105720560 B CN 105720560B CN 201410723107 A CN201410723107 A CN 201410723107A CN 105720560 B CN105720560 B CN 105720560B
- Authority
- CN
- China
- Prior art keywords
- signal
- circuit
- fault
- fpga
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000004224 protection Effects 0.000 claims abstract description 56
- 230000000903 blocking effect Effects 0.000 claims abstract description 34
- 238000006243 chemical reaction Methods 0.000 claims description 37
- 239000000835 fiber Substances 0.000 claims description 25
- 239000013307 optical fiber Substances 0.000 claims description 16
- 238000012545 processing Methods 0.000 claims description 9
- 230000005611 electricity Effects 0.000 claims description 7
- 230000002441 reversible effect Effects 0.000 claims description 3
- 210000001367 artery Anatomy 0.000 claims 2
- 210000003462 vein Anatomy 0.000 claims 2
- 230000004888 barrier function Effects 0.000 claims 1
- 230000005622 photoelectricity Effects 0.000 claims 1
- 230000003534 oscillatory effect Effects 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 4
- 230000010355 oscillation Effects 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 2
- 230000002401 inhibitory effect Effects 0.000 abstract 1
- 230000001681 protective effect Effects 0.000 description 11
- 101100204735 Arabidopsis thaliana OVA3 gene Proteins 0.000 description 8
- 101100045151 Arabidopsis thaliana OVA4 gene Proteins 0.000 description 8
- 230000003287 optical effect Effects 0.000 description 6
- 101100423701 Arabidopsis thaliana OVA1 gene Proteins 0.000 description 4
- 101100479620 Arabidopsis thaliana OVA2 gene Proteins 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Landscapes
- Inverter Devices (AREA)
- Dc-Dc Converters (AREA)
Abstract
The present invention provides a kind of current transformer three-level signal protection circuit, which includes：Excessively protection circuit, FPGA protect circuit, DSP pulse blockings circuit, PWM drive circuit and IPM power modules for sensor, hardware; wherein; FPGA protects circuit; for according to over current fault signal and over-voltage fault signal; and upper bridge arm fault-signal and lower bridge arm fault-signal; down pulse locking signal is generated, the current transformer pulse signal of FPGA, DSP and PWM drive circuit three are blocked；The DSP pulse blockings circuit is set as high-impedance state for the 6 road PWM start pulse signals by output to the FPGA after receiving the down pulse locking signal.The present invention, which solves in converter system in the prior art, easily there is the technical issues of overcurrent oscillation causes IPM to damage, and has reached the technique effect of effective overcurrent oscillatory occurences for inhibiting current transformer internal protection.
Description
Technical field
The present invention relates to electric system power converter technical field, more particularly to a kind of current transformer three-level signal protection electricity
Road.
Background technology
In the applications such as power converter, unsteady flow driving, Switching Power Supply, the application of current transformer is increasingly extensive.In current transformer
In operational process, due to power grid, load-reason or the reason of current transformer itself, cause electric current, voltage considerably beyond volume
Fixed range of operation, in this case, current transformer itself will make a response rapidly, close current transformer, in order to avoid cause current transformer
Power device (such as：IGBT, capacitance etc.) damage.
Current power device mostly uses IPM (intelligent power module), IPM be internally integrated IGBT device, driving circuit,
Circuit etc. is protected, is used more convenient.IPM autoprotection functions include：Control line under-voltage protection, overheating protection, mistake
Flow protection, upper and lower bridge arm error protection etc..
But IPM autoprotections are not consistent sexual acts for all IGTB devices of inside modules, and the report exported
Alert signal does not have retentivity, and the system of being easy to cause overcurrent oscillatory occurences occurs, ultimately causes the damage of IPM.
In view of the above-mentioned problems, currently no effective solution has been proposed.
Invention content
An embodiment of the present invention provides a kind of current transformer three-level signals to protect circuit, to solve current transformer system in the prior art
Easily occur the technical issues of overcurrent oscillation causes IPM to damage in system, which protects circuit, including：
Excessively protection circuit, FPGA protect circuit, DSP pulse blockings circuit, PWM drive circuit and IPM for sensor, hardware
Power module, wherein：
The sensor, for acquiring three-phase current and DC bus-bar voltage；
Excessively protection circuit, input terminal are connected the hardware with the sensor, and output end protects circuit with the FPGA
Input pin be connected, in the case where the three-phase current exceeds preset value output overcurrent fault-signal to the FPGA
Circuit is protected, output overvoltage fault-signal is protected electric to the FPGA in the case where the DC bus-bar voltage exceeds preset value
Road；
The IPM power modules are connected by optical fiber with the PWM drive circuit, for defeated to the PWM drive circuit
Go out upper bridge arm fault-signal and lower bridge arm fault-signal, and receives 6 road PWM trigger pulses letters of the PWM drive circuit output
Number and 1 road down pulse locking signal；
The PWM drive circuit protects circuit and the IPM power modules to be connected with the FPGA, described for receiving
FPGA protects the 1 road down pulse locking signal and 6 road PWM start pulse signals of circuit output, and by 1 road down pulse
Locking signal and 6 road PWM start pulse signals are exported to the IPM power modules, for receiving the IPM power modules output
Upper bridge arm fault-signal and lower bridge arm fault-signal, and by the upper bridge arm fault-signal and lower bridge arm fault-signal export to
The FPGA protects circuit；
The FPGA protects circuit, and excessively protection circuit, DSP pulse blockings circuit, PWM drivings are electric with the hardware respectively
Road is connected, for the over current fault signal and over-voltage fault signal and described according to the excessive protection circuit output of the hardware
The upper bridge arm fault-signal and lower bridge arm fault-signal of IPM power modules output, generate down pulse locking signal, block first
FPGA internal pulses will be set as high-impedance state, then by the down pulse locking signal by the PWM start pulse signals of FPGA
The interrupt pin to the DSP pulse blockings circuit and the PWM drive circuit are exported, the FPGA protections circuit is additionally operable to connect
6 road PWM start pulse signals of the DSP pulse blockings circuit output are received, and 6 road PWM start pulse signals are exported to institute
State PWM drive circuit；
The DSP pulse blockings circuit is connected with FPGA protection circuits, for receiving the down pulse envelope
6 road PWM start pulse signals after lock signal by output to the FPGA are set as high-impedance state.
In one embodiment, excessively protection circuit includes the hardware：
The common cathode full bridge rectifier being made of 6 diode 1N4148, is connected with DC voltage divider circuit, for that will connect
The bipolar signal received is converted to direct current signal, and by the DC signal output to the DC voltage divider circuit；
The DC voltage divider circuit, respectively compared with the common cathode full bridge rectifier, direct current signal input terminal, voltage
Device is connected, and is divided for the direct current signal to input, and the voltage signal after partial pressure is exported to the voltage comparator；
The voltage comparator is connected with the DC voltage divider circuit and reference voltage threshold initialization circuit, is used for respectively
The voltage exported according to the reference voltage threshold initialization circuit compares threshold value, is compared to the voltage signal after partial pressure,
In the case that voltage threshold after partial pressure compares the range of threshold value beyond the voltage, output overcurrent fault-signal or over-voltage fault
Signal.
In one embodiment, the reference voltage threshold initialization circuit includes：Under upper voltage limit initialization circuit and voltage
Limit initialization circuit.
In one embodiment, the zener diode that the reference voltage threshold initialization circuit uses is ZMM10 voltage stabilizing two
Pole pipe, the potentiometer used is 3224W-1-103E potentiometer.
In one embodiment, the PWM drive circuit includes：First photoelectric conversion plate and the second photoelectric conversion plate,
In, it is connected by 8 optical fiber between first photoelectric conversion plate and second photoelectric conversion plate.
In one embodiment, first photoelectric conversion plate includes：Pwm pulse output signal driver circuit and current transformer
Fault signal processing circuit itself, wherein：
The pwm pulse output signal driver circuit includes the first analog line driver and the first fibre optical transmission being sequentially connected in series
Device, first analog line driver are used to receive 6 road PWM start pulse signals and the event of 1 tunnel of the FPGA protections circuit output
Hinder pulse blocking signal, and first fiber optic emitter is driven to export 6 road PWM start pulse signals to the IPM power
Module；
Current transformer fault signal processing circuit itself includes：Locking signal conversion circuit, failure pulse signal receive
Circuit and fault-signal latch and warning circuit, wherein：
The locking signal conversion circuit includes the second analog line driver and the second fiber optic emitter being sequentially connected in series, described
Second analog line driver is used to protect 1 road down pulse locking signal of circuit output to pass through the FPGA received described
Second fiber optic emitter is exported to second photoelectric conversion plate；
The failure pulse signal receiving circuit includes third fiber optic receiver and single order RC filters, and being used for will be described
The upper bridge arm fault-signal and/or lower bridge arm fault-signal of IPM power modules output be converted to electric signal, and will be converted to
Electric signal output is to the protection circuit and the fault-signal latches and warning circuit；
The fault-signal is latched includes with the input signal of warning circuit：Down pulse locking signal, upper bridge arm failure
Signal, lower bridge arm fault-signal, for passing through six reverse phase Schmidt trigger 74LS14 respectively by upper bridge arm fault-signal under
Bridge arm fault-signal negates once, is negated twice to down pulse locking signal, wherein the down pulse block after negating twice
Signal is connected with the cathode of LED alarm lamp, and the upper bridge arm fault-signal and lower bridge arm fault-signal after negating once input respectively
The D-latch constituted to NAND gate chip 74LS00, and reset signal is connected with the D-latch, the signal difference of latch
It is connected with LED alarm lamp, and the upper bridge arm fault-signal, lower bridge arm fault-signal, the down pulse that are latched in the latch seal
Lock signal with door chip 74LS21 phases by with after, being input to buzzer control loop.
In one embodiment, second photoelectric conversion plate includes：Pwm pulse receives signal drive circuit and failure letter
Number radiating circuit, wherein：
The pwm pulse receives signal drive circuit, and the 6 road PWM for receiving the first photoelectric conversion plate output are touched
Pulse signal is sent out, and the 6 road PWM start pulse signals received are exported to the IPM power modules；
The fault-signal radiating circuit, the upper bridge arm failure letter for will be received from the fault-signal radiating circuit
Number and/or lower bridge arm fault-signal, output is to first photoelectric conversion plate.
In one embodiment, the model of the first fiber optic emitter, the second fiber optic emitter and third fiber optic emitter
HFBR1521, the model SN75451 of first analog line driver and the second analog line driver.
In one embodiment, the model PM150CLA120 of the IPM power modules.
In embodiments of the present invention, a kind of current transformer three-level signal protection circuit is provided, by protecting in circuit
FPGA protects circuit and DSP pulse blocking circuits, according to over current fault signal, over-voltage fault signal, upper bridge arm fault-signal and
Lower bridge arm fault-signal generates down pulse locking signal, the three-level pulse blocking to circuit is realized, to solve existing skill
Easily occurs the technical issues of overcurrent oscillation causes IPM to damage in art in converter system, using three-level pulse blocking come maximum journey
The inside and outside failure of degree reply current transformer, the holding by FPGA to fault-signal are effectively inhibited and are protected inside current transformer
The overcurrent oscillatory occurences of shield.
Description of the drawings
Attached drawing described herein is used to provide further understanding of the present invention, and is constituted part of this application, not
Constitute limitation of the invention.In the accompanying drawings：
Fig. 1 is the schematic diagram of the current transformer three-level signal protection circuit of inventive embodiments；
Fig. 2 is that the hardware of the embodiment of the present invention excessively protects circuit diagram；
Fig. 3 is reference voltage threshold initialization circuit Fig. 1 of the embodiment of the present invention；
Fig. 4 is reference voltage threshold initialization circuit Fig. 2 of the embodiment of the present invention；
Fig. 5 is the PWM output pulse signal driving circuit figures of the embodiment of the present invention；
Fig. 6 is the PWM return pulse signal driving circuit figures of the embodiment of the present invention；
Fig. 7 is that the pwm signal of the embodiment of the present invention latches and sound light alarming circuit figure；
Fig. 8 is the FPGA internal logic figures of the embodiment of the present invention；
Fig. 9 is the current transformer software protection flow chart of the embodiment of the present invention.
Specific implementation mode
To make the objectives, technical solutions, and advantages of the present invention clearer, right with reference to embodiment and attached drawing
The present invention is described in further details.Here, the exemplary embodiment and its explanation of the present invention be for explaining the present invention, but simultaneously
It is not as a limitation of the invention.
In embodiments of the present invention, a kind of current transformer three-level signal protection circuit is provided, as shown in Figure 1, including：Sensing
Excessively protection circuit, FPGA protect circuit, DSP pulse blockings circuit, PWM drive circuit and IPM power modules for device, hardware,
In：
Sensor, for acquiring three-phase current and DC bus-bar voltage；
Excessively protection circuit, input terminal are connected hardware with the sensor, and output end protects the defeated of circuit with the FPGA
Enter pin to be connected, in the case where the three-phase current exceeds preset value output overcurrent fault-signal protect to the FPGA
Circuit, the DC bus-bar voltage exceed preset value in the case of output overvoltage fault-signal to the FPGA protect circuit；
IPM power modules are connected by optical fiber with the PWM drive circuit, for being exported to the PWM drive circuit
Bridge arm fault-signal and lower bridge arm fault-signal, and receive the 6 road PWM start pulse signals and 1 of the PWM drive circuit output
Road down pulse locking signal；
PWM drive circuit protects circuit and the IPM power modules to be connected, for receiving the FPGA with the FPGA
The 1 road down pulse locking signal and 6 road PWM start pulse signals of circuit output are protected, and 1 road down pulse is blocked
Signal and 6 road PWM start pulse signals are exported to the IPM power modules, for receiving the IPM power modules output
Bridge arm fault-signal and lower bridge arm fault-signal, and the upper bridge arm fault-signal and lower bridge arm fault-signal are exported to described
FPGA protects circuit；
FPGA protects circuit, excessively protects circuit, DSP pulse blockings circuit, PWM drive circuit phase with the hardware respectively
Even, the over current fault signal for excessively protecting circuit output according to the hardware and over-voltage fault signal and the IPM work(
The upper bridge arm fault-signal and lower bridge arm fault-signal of rate module output, generate down pulse locking signal, and by the failure
Pulse blocking signal is exported to the interrupt pin of the DSP pulse blockings circuit and the PWM drive circuit, the FPGA protections
Circuit is additionally operable to receive 6 road PWM start pulse signals of the DSP pulse blockings circuit output, and by 6 road PWM trigger pulses
Signal is exported to the PWM drive circuit；
DSP pulse blocking circuits are connected with FPGA protection circuits, for receiving the down pulse block letter
6 road PWM start pulse signals after number by output to the FPGA are set as high-impedance state.
Current transformer three-level signal shown in FIG. 1 protection circuit is specifically described with reference to a specific embodiment,
It is important to note, however, that the specific embodiment merely to the present invention is better described, is not constituted to the improper of the present invention
It limits.
Specifically, in this example, provides a kind of software and hardware and be combined, protected with the current transformer that the signal of IPM matches
Circuit, the protection circuit is in addition to that can cope with overcurrent happen suddenly, quick, overvoltage protection, also by the short circuit of IPM itself, mistake
Temperature, under-voltage protection take into account, and transmitted by optical fiber, devise current transformer overvoltage, over current fault alarm and protection circuit with
And three-level pulse lockout circuit.Due to the powerful logical resources of FPGA, fault-signal logic judgment processing electricity is built in FPGA
Road, from DSP, FPGA, PWM driving, locking pulse in terms of IPM tetra-, when there is situations such as overcurrent, overvoltage, IPM failures
When, which can react rapidly, close current transformer and alarm, fully and effectively current transformer itself and outside is protected to set
It is standby.
It is broadly divided into five parts according to the difference of the processing mode of different faults signal：Hardware excessively protects circuit, IPM work(
Rate module, PWM drive circuit, FPGA protections circuit, DSP pulse blockings, below just illustrate this 5 parts：
1) hardware excessively protects circuit
Protected three-phase current and DC bus-bar voltage are after Hall sensor acquires, and into hardware, excessively protection is electric
LV25-P may be used in road, Hall voltage sensor, and LA100-P may be used in current sensor.
As shown in Fig. 2, excessively protection circuit includes the hardware：
Reference voltage threshold initialization circuit, for providing reference voltage for excessive relay protective scheme circuit；
Excessive relay protective scheme circuit, including：Uncontrollable rectifier circuit, DC voltage divider circuit, filter circuit and voltage are more electric
Road, wherein uncontrollable rectifier circuit constitutes common cathode full bridge rectifier by 6 diode 1N4148 (D1 to D6)：
When inputting bipolar signal, it is direct current signal to first pass through uncontrollable rectifier circuit conversion, and the relationship of input and output is：
Ud=2.34*Ui, it is rectified after direct current signal after 2 metalfilmresistors (R7 and R8) partial pressure, then pass through voltage comparator
LM311 is compared with the reference voltage threshold of setting, finally exports fault-signal.
When inputting unipolar signal：Input signal is directly accessed DC voltage divider circuit, passes through voltage comparator and ginseng
It examines voltage to be compared, exports fault-signal.
Reference voltage threshold initialization circuit as shown in Figures 3 and 4 respectively by+15V voltages and -15V power voltage supplies, and uses
Between threshold value setting range is respectively maintained at 0V~+10V and -10V~0V by zener diode ZMM10 respectively, while in order to protect
The correctness judged by protection signal is demonstrate,proved, protection threshold is adjusted using high-precision, high voltage bearing precision potentiator 3224W-1-103E
It is worth the size of datum.
By hardware excessively protection processing of circuit after generation overcurrent OVA1 and over-voltage fault signal OVA2, directly with
The pin that FPGA is distributed is connected.
2) IPM power modules
In this example, the model of IPM power modules is selected as PM150CLA120, inputs as 6 road PWM start pulse signals
With 1 road down pulse locking signal, output is respectively upper bridge arm fault-signal OVA3 and lower bridge arm fault-signal OVA4, pulse letter
Number and fault-signal fault-signal be converted into fiber-optic signal through overdrive circuit and fiber optic emitter be respectively transmitted.
It is important to note, however, that be only in this example PM150CLA120 models IPM power modules for said
It is bright, the IPM power modules of other models, the application can also be used to be not construed as limiting this.
3) PWM drive circuit
As shown in Figure 1, PWM drive circuit is broadly divided into two：One is photoelectric conversion plate A, the other is opto-electronic conversion
Plate B is connected by 8 optical fiber therebetween.
Wherein, photoelectric conversion plate A is made of two parts again：Pwm pulse output signal driver circuit and current transformer are originally die
Hinder signal processing circuit, wherein：
3-1) pwm pulse output signal driver circuit, as shown in Figure 5 by analog line driver SN75451 and fiber optic emitter
HFBR1521 is followed in series to form, from the pin of FPGA export 6 road PWM start pulse signals and 1 tunnel pulse blocking signal/
For XSHUTA together by being input to analog line driver, driving fiber optic emitter sends pwm signal, output signal by optical fiber with
IPM power modules are connected.
3-2) current transformer fault signal processing circuit itself includes three parts：Failure pulse signal receiving circuit, block letter
Number conversion circuit, fault-signal latches and warning circuit, wherein：
3-2-1) locking signal conversion circuit, structure is identical as pwm pulse output signal driver circuit, but analog line driver
Two-way input signal be /XSHUTA, and low level is effective, and passes through optical fiber output to photoelectric conversion plate B.
3-2-2) failure pulse signal receiving circuit, as shown in figure 5, by fiber optic receiver HFBR2521 and single order RC filtering
Device is constituted, and converts optical signals to electric signal, transformed fault-signal, while being input to FPGA and fault latch and alarm electricity
Road.
3-2-3) fault-signal latch and warning circuit, as shown in fig. 7, input signal is locking signal/XSHUTA and change
Device upper and lower bridge arm fault-signal OVA3, OVA4 are flowed, is respectively taken OVA3, OVA4 by six reverse phase Schmidt trigger 74LS14
Anti- primary, right/XSHUTA signals negate twice, and locking signal/XSHUTA is connected with the cathode of LED alarm lamp (D1), failure letter
Number OVA3, OVA4 are separately input to the D-latch that NAND gate chip 74LS00 is constituted, and by reset signal K1 and latch phase
Even, the signal of latch is connected with LED alarm lamp (D2) respectively；The fault-signal and pulse blocking signal of latch pass through and door chip
74LS21 phases are input to buzzer (SP1) control loop, three signals are that low level is effective with after.
Further, photoelectric conversion plate B is corresponding with photoelectric conversion plate A, and is made of two parts：Pwm pulse receives
Signal drive circuit and fault-signal radiating circuit, wherein：
Pwm pulse, which receives signal drive circuit, six tunnels, and the failure pulse signal per Lu Junyu photoelectric conversion plates A receives electricity
Road is identical, inputs the six road PWM start pulse signals for photoelectric conversion plate A outputs, and output is connected with IPM rate modules；Failure is believed
Number radiating circuit, it is identical as the pwm pulse radiating circuit of photoelectric conversion plate A, it exports and light is connected to by optical fiber for fault-signal
Electric change-over panel A.
4) relay protective scheme (i.e. FPGA protects circuit) of FPGA
The relay protective scheme of FPGA with door by constituting, by current transformer itself failure OVA3, OVA4 and AC overcurrent signal OVA1
(i.e. over current fault signal), DC bus-bar voltage overvoltage signal OVA2 (i.e. over-voltage fault signal) mutually with, and generate failure block
Signal/XSHUTA (i.e. down pulse locking signal), the down pulse locking signal block pwm signal inside FPGA, to
Under be transferred to photoelectric conversion plate A by PWM start pulse signals by hardware lockout, be passed up to DSP /PDPINTA pins.
5) pulse blocking (i.e. DSP pulse blockings circuit) of DSP
The pulse blocking of DSP can be power drive protection interruption/PDPINTA by the way that task manager EVA is arranged,
The pulse of PWM1~6 pressure is set to high-impedance state in interrupting, that is, blocks the PWM start pulse signals of DSP.
From the above analysis it can be seen that：Enter what FPGA was handled in current transformer three-level protective circuit as shown in Figure 1
Fault-signal mainly has two parts：Hardware circuit detection DC voltage, alternating current are sent out after exceeding normal operating voltage range
The 2 tunnel alarm signals gone out, 2 roads that IPM power modules generate, lower bridge arm fault-signal, totally 4 road fault-signal.
The ground that the current transformer PWM down pulse locking signals generated by FPGA in the current transformer three-level protective circuit work
There are three parts in side：DSP, FPGA and PWM driving plate, wherein DSP and FPGA constitutes two-stage software protection, and PWM driving plates are constituted
Hardware protection.
The protection met in terms of software and hardware to current transformer is disclosure satisfy that by above-mentioned current transformer three-level protective circuit,
The inside and outside failure of current transformer is utmostly coped with using three-level pulse blocking, by FPGA to the guarantor of fault-signal
It holds, effectively inhibits the overcurrent oscillatory occurences of current transformer internal protection.
In this example from the generation and processing of fault-signal from the aspect of current transformer external fault and failure two itself, outside
By hardware, excessively protection circuit generates portion's fault-signal, and current transformer failure itself directly inputs upper and lower bridge arm event by IPM
Barrier, external fault is transmitted by electric signal, in order to which electromagnetic interference of the primary system to secondary control system, current transformer itself is isolated
Failure FPGA is transferred to by optical fiber, after guiding fault indication signal into FPGA, utilize the logical resource that FPGA is abundant, constitute
Relay protective scheme, and protection signal is generated, the pulse output signals of DSP, FPGA, PWM driving plate are blocked respectively, reach multiple
The purpose of protection.
Above-mentioned current transformer three-level protective circuit is illustrated with reference to a specific embodiment, however is worth noting
, which does not constitute improper limitations of the present invention merely to the present invention is better described.
As shown in Figure 1, three-phase current and DC bus-bar voltage are input to hardware excessively protection circuit by current sensor,
And overcurrent and over-voltage fault signal OVA1, OVA2 are generated, current transformer IPM generates upper and lower bridge arm fault-signal OVA3, OVA4, light
Fault-signal is transmitted by optical fiber between electric change-over panel A and B.Do not having in the event of failure, 6 road PWM start pulse signals are produced by DSP
It is raw, be transmitted to photoelectric conversion plate A and B by medium of FPGA, be finally output to six bridge arms of IPM, generation current transformer overcurrent,
When overvoltage and internal bridge arm failure, it is blocked by the PWM of DSP, FPGA, photoelectric conversion plate A.In Fig. 1, Iabc tables
Show that three-phase alternating current, Udc indicate that DC bus-bar voltage, OVA1 indicate that overvoltage fault-signal, OVA2 indicate overcurrent fault
Bridge arm fault-signal on signal, OVA3 expressions, OVA4 indicate lower bridge arm fault-signal ,/XSHUTA indicate pulse blocking signal ,/
PDPINTA indicates power drive interrupt signal.
Hardware excessively protection circuit as shown in Fig. 2, constitute uncontrollable rectifier circuit using diode 1N4148, and with voltage ratio
Compared with the method that circuit is combined, the function of compatible with alternating and direct current signal excess detector is realized by the switching of input channel.I.e.
AC signal can enter from 3,4,5 pins of J1, and first pass through three-phase uncontrollable rectifier becomes direct current by AC signal, using electricity
Resistance partial pressure, is compared through voltage comparator LM311 with the reference voltage level of setting, finally exports overvoltage signal to J2's
Pin 5 inputs if input is direct current signal from 1,7 pins of J1, crosses rectification circuit and is directly entered voltage and compares ring
Section, export excessive signal, specifically may be used zener diode ZMM10 by threshold value setting range maintain 0V~+10V and-
Between 10V~0V, while in order to ensure the correctness judged by protection signal, as shown in Figures 3 and 4 using high-precision, it is high pressure resistant
Precision potentiator 3224W-1-103E adjust the size of rotection thresholds level, when the threshold value for by protection signal level being more than setting
When level, comparator exports low level, after dropping below threshold level by protection signal level, cancels excessive signal.
In Fig. 2 to 4, R1~R14 indicates that conventional, electric-resistance, R15, R16 indicate that adjustable resistance, D1~D6 indicate that diode, D7, D8 indicate steady
Diode, C1~C4 is pressed to indicate that ceramic condenser, U1, U2 indicate that excessive protection module, J1~J3 indicate seven foot insert rows, TP1~TP4
Indicate that test point ,+REF indicate that positive datum ,-REF indicate to bear datum.
Pwm pulse driving circuit as it can be seen in figures 5 and 6, be respectively transmitting and receiving circuit, when PWM be high level when, optical fiber
Transmitter is bright, sends optical signal, and when/XSHUTA is low level, no matter PWM is high level or low level, and optical fiber head is not
Bright, i.e., pulse signal is blocked.Optical signal receiving circuit is similar to radiating circuit, is converted electrical signals to by fiber optic receiver
Optical signal, and the 15V level that the level that pwm pulse signal is transported to six bridge arms of IPM is mutually compatible with.In figs. 5 and 6, U1
Indicate that fiber optic receiver, R1 indicate that conventional, electric-resistance, U1A indicate that analog line driver, XPWM1~6 indicate pulse signal, C1~C21
Indicate ceramic condenser.
When current transformer internal fault, IPM will send out upper and lower bridge arm fault-signal OVA3, OVA4, which is input to light
Electric signal change-over panel B, and photosignal pinboard A is sent to by fiber optic emitter, transmission and reception circuit is such as the hair of PWM
It send and receiving circuit, details are not described herein.When fractureing in order to avoid optical fiber, fault-signal is not received, is needed to IPM
The fault-signal of output negates, you can six anti-Schmidt triggers of access so that when IPM fault-signals are low level, emits light
It is to be always on when fine hair light, i.e. normal operation；And optical signal is converted electrical signals to by fiber optic emitter.It is transmitted by optical fiber
To after photoelectric conversion plate A, as shown in fig. 7, being converted to electric signal by fiber optic receiver, and latches and alarm by fault-signal
Fault-signal is latched and is alarmed by circuit, and U1 indicates that hex inverter, U2. indicate that 42 input nand gates, U3 indicate double in the figure 7
Four inputs and door, R1~7 indicate that conventional, electric-resistance, D1, D2. indicate that red LED lamp, C1 indicate that ceramic condenser, Q1.PNP indicate three
Pole pipe, SP1 indicate buzzer.
Specifically, fault latch state equation is：
Fault-alarming state equation is：
Wherein, K1 indicates push button signalling, is normally high level, by being low level, as reset signal when key pressing.
After above-mentioned four road fault-signal enters FPGA, relay protective scheme is built in FPGA, and generates pwm pulse locking signal
Power drive interrupt signal/PDPINTA of SHUTA and DSP, as shown in figure 8, the relay protective scheme state equation of FPGA is：
Wherein, the whole Software for Design flow inside FPGA is produced at once as shown in figure 9, after judging to generate fault-signal
Raw pulse blocking signal blocks the pwm pulse output inside FPGA, then generates fault interrupting to DSP respectively and driven to PWM first
Dynamic circuit sends locking signal and blocks its PWM.
It can be seen from the above description that the embodiment of the present invention realizes following technique effect：Provide a kind of unsteady flow
Device three-level signal protects circuit, by protecting the FPGA in circuit to protect circuit and DSP pulse blocking circuits, according to over current fault
Signal, over-voltage fault signal, upper bridge arm fault-signal and lower bridge arm fault-signal generate down pulse locking signal, realize to electricity
The three-level pulse blocking on road, to solve easily occur in converter system in the prior art overcurrent oscillation cause IPM damage
Technical problem utmostly copes with the inside and outside failure of current transformer, by FPGA to failure using three-level pulse blocking
The holding of signal effectively inhibits the overcurrent oscillatory occurences of current transformer internal protection.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the embodiment of the present invention can have various modifications and variations.All within the spirits and principles of the present invention, made by
Any modification, equivalent substitution, improvement and etc. should all be included in the protection scope of the present invention.
Claims (7)
1. a kind of current transformer three-level signal protects circuit, which is characterized in that including：Sensor, hardware excessively protect circuit, FPGA
Circuit, DSP pulse blockings circuit, PWM drive circuit and IPM power modules are protected, wherein：
The sensor, for acquiring three-phase current and DC bus-bar voltage；
Excessively protection circuit, input terminal are connected the hardware with the sensor, and output end protects the defeated of circuit with the FPGA
Enter pin to be connected, in the case where the three-phase current exceeds preset value output overcurrent fault-signal protect to the FPGA
Circuit, the DC bus-bar voltage exceed preset value in the case of output overvoltage fault-signal to the FPGA protect circuit；
The IPM power modules are connected by optical fiber with the PWM drive circuit, for being exported to the PWM drive circuit
Bridge arm fault-signal and lower bridge arm fault-signal, and receive the 6 road PWM start pulse signals and 1 of the PWM drive circuit output
Road down pulse locking signal；
The PWM drive circuit protects circuit and the IPM power modules to be connected, for receiving the FPGA with the FPGA
The 1 road down pulse locking signal and 6 road PWM start pulse signals of circuit output are protected, and 1 road down pulse is blocked
Signal and 6 road PWM start pulse signals are exported to the IPM power modules, for receiving the IPM power modules output
Bridge arm fault-signal and lower bridge arm fault-signal, and the upper bridge arm fault-signal and lower bridge arm fault-signal are exported to described
FPGA protects circuit；
The FPGA protects circuit, excessively protects circuit, DSP pulse blockings circuit, PWM drive circuit phase with the hardware respectively
Even, the over current fault signal for excessively protecting circuit output according to the hardware and over-voltage fault signal and the IPM work(
The upper bridge arm fault-signal and lower bridge arm fault-signal of rate module output, generate down pulse locking signal, block FPGA first
Internal pulses will be set as high-impedance state by the PWM start pulse signals of FPGA, then export the down pulse locking signal
Interrupt pin to the DSP pulse blockings circuit and the PWM drive circuit, the FPGA protections circuit are additionally operable to receive institute
6 road PWM start pulse signals of DSP pulse blocking circuit outputs are stated, and 6 road PWM start pulse signals are exported to the PWM
Driving circuit；
The DSP pulse blockings circuit is connected with FPGA protection circuits, for receiving the down pulse block letter
6 road PWM start pulse signals after number by output to the FPGA are set as high-impedance state；
Wherein, the PWM drive circuit includes：First photoelectric conversion plate and the second photoelectric conversion plate, wherein first photoelectricity
It is connected by 8 optical fiber between change-over panel and second photoelectric conversion plate；
Wherein, first photoelectric conversion plate includes：At pwm pulse output signal driver circuit and current transformer fault-signal itself
Circuit is managed, wherein：
The pwm pulse output signal driver circuit includes the first analog line driver and the first fiber optic emitter being sequentially connected in series,
First analog line driver is used to receive the 6 road PWM start pulse signals and 1 tunnel failure arteries and veins of the FPGA protections circuit output
Locking signal is rushed, and first fiber optic emitter is driven to export 6 road PWM start pulse signals to the IPM power modules；
Current transformer fault signal processing circuit itself includes：Locking signal conversion circuit, failure pulse signal receiving circuit,
With fault-signal latch and warning circuit, wherein：
The locking signal conversion circuit includes the second analog line driver and the second fiber optic emitter being sequentially connected in series, and described second
Analog line driver is used to protect 1 road down pulse locking signal of circuit output by described second the FPGA received
Fiber optic emitter is exported to second photoelectric conversion plate；
The failure pulse signal receiving circuit includes third fiber optic receiver and single order RC filters, is used for the IPM work(
The upper bridge arm fault-signal and/or lower bridge arm fault-signal of rate module output are converted to electric signal, and the telecommunications that will be converted to
Number output protects circuit and the fault-signal to latch and warning circuit to the FPGA；
The fault-signal is latched includes with the input signal of warning circuit：Down pulse locking signal, upper bridge arm fault-signal,
Lower bridge arm fault-signal, for passing through six reverse phase Schmidt trigger 74LS14 respectively by upper bridge arm fault-signal and lower bridge arm event
Barrier signal negates once, is negated twice to down pulse locking signal, wherein down pulse locking signal after negating twice and
The cathode of LED alarm lamp is connected, negate it is primary after upper bridge arm fault-signal and lower bridge arm fault-signal be separately input to it is non-
The D-latch that door chip 74LS00 is constituted, and reset signal is connected with the D-latch, the signal of latch is reported with LED respectively
Warning lamp is connected, and upper bridge arm fault-signal, lower bridge arm fault-signal, the down pulse locking signal warp latched in the latch
It crosses with door chip 74LS21 phases with after, is input to buzzer control loop；
Wherein, the hardware, which is excessively protected in circuit, includes：The common cathode full-bridge rectification electricity being made of 6 diode 1N4148
Road is connected with DC voltage divider circuit, for the bipolar signal received to be converted to direct current signal, and by the direct current signal
It exports to the DC voltage divider circuit.
2. current transformer three-level signal as described in claim 1 protects circuit, which is characterized in that the hardware excessively protects circuit
Further include：
The DC voltage divider circuit, respectively with the common cathode full bridge rectifier, direct current signal input terminal, voltage comparator phase
Even, it is divided for the direct current signal to input, and the voltage signal after partial pressure is exported to the voltage comparator；
The voltage comparator is connected with the DC voltage divider circuit and reference voltage threshold initialization circuit respectively, is used for basis
The voltage of the reference voltage threshold initialization circuit output compares threshold value, is compared, is dividing to the voltage signal after partial pressure
In the case that voltage threshold afterwards compares the range of threshold value beyond the voltage, output overcurrent fault-signal or over-voltage fault letter
Number.
3. current transformer three-level signal as claimed in claim 2 protects circuit, which is characterized in that the reference voltage threshold setting
Circuit includes：Upper voltage limit initialization circuit and lower voltage limit initialization circuit.
4. current transformer three-level signal as claimed in claim 2 protects circuit, which is characterized in that the reference voltage threshold setting
The zener diode that circuit uses is ZMM10 zener diode, and the potentiometer used is 3224W-1-103E potentiometer.
5. current transformer three-level signal as described in claim 1 protects circuit, which is characterized in that the second photoelectric conversion plate packet
It includes：Pwm pulse receives signal drive circuit and fault-signal radiating circuit, wherein：
The pwm pulse receives signal drive circuit, and the 6 road PWM for receiving the first photoelectric conversion plate output trigger arteries and veins
Signal is rushed, and the 6 road PWM start pulse signals received are exported to the IPM power modules；
The fault-signal radiating circuit, the upper bridge arm fault-signal for will be received from the fault-signal radiating circuit
And/or lower bridge arm fault-signal, output to first photoelectric conversion plate.
6. current transformer three-level signal as claimed in claim 5 protects circuit, which is characterized in that the first fiber optic emitter, second
The model HFBR1521 of fiber optic emitter and third fiber optic emitter, first analog line driver and the second analog line driver
Model SN75451.
7. as current transformer three-level signal according to any one of claims 1 to 6 protects circuit, which is characterized in that the IPM work(
The model PM150CLA120 of rate module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410723107.9A CN105720560B (en) | 2014-12-03 | 2014-12-03 | Current transformer three-level signal protects circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410723107.9A CN105720560B (en) | 2014-12-03 | 2014-12-03 | Current transformer three-level signal protects circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105720560A CN105720560A (en) | 2016-06-29 |
| CN105720560B true CN105720560B (en) | 2018-09-18 |
Family
ID=56146654
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410723107.9A Active CN105720560B (en) | 2014-12-03 | 2014-12-03 | Current transformer three-level signal protects circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105720560B (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106329506B (en) * | 2016-11-07 | 2017-08-04 | 西安科技大学 | The adjustable servo controller overvoltage of rotection thresholds is released protection device and method |
| CN107482582A (en) * | 2017-10-09 | 2017-12-15 | 赵东顺 | A kind of guard method of motor circuit |
| CN107908129B (en) * | 2017-10-27 | 2019-08-23 | 上海交通大学 | The control method of DSP and the interconnection of FPGA/CPLD multidimensional |
| CN108256277A (en) * | 2018-03-13 | 2018-07-06 | 南京双启新能源科技有限公司 | A kind of Digital Simulation switch power amplifier |
| CN110350486B (en) * | 2019-07-19 | 2022-02-11 | 广东美的暖通设备有限公司 | Fault protection device, frequency converter and motor driving system |
| CN112230118A (en) * | 2020-10-20 | 2021-01-15 | 珠海格力电器股份有限公司 | Fault location device, method, apparatus, electronic device, and computer readable medium |
| CN112255524B (en) * | 2020-12-06 | 2024-02-06 | 中车永济电机有限公司 | Protection method and detection device for electric transmission traction system |
| CN112600171A (en) * | 2020-12-24 | 2021-04-02 | 中冶南方（武汉）自动化有限公司 | Fault locking circuit of frequency converter |
| US11513880B1 (en) * | 2021-08-26 | 2022-11-29 | Powerchip Semiconductor Manufacturing Corporation | Failure bit count circuit for memory and method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201061130Y (en) * | 2007-06-19 | 2008-05-14 | 中国兵器工业第二0六研究所 | Protective circuit of intelligent power module IPM |
| CN101895097A (en) * | 2009-05-20 | 2010-11-24 | 北京四方继保自动化股份有限公司 | Realization method of protecting circuit with converter |
| CN203537247U (en) * | 2013-11-13 | 2014-04-09 | 湖南大学 | Universal control circuit board of multi-level converter |
| CN204205569U (en) * | 2014-12-03 | 2015-03-11 | 国家电网公司 | Current transformer three grades of signal protection circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013190752A1 (en) * | 2012-06-22 | 2013-12-27 | 富士電機株式会社 | Overcurrent detecting apparatus, and intelligent power module using same |
-
2014
- 2014-12-03 CN CN201410723107.9A patent/CN105720560B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201061130Y (en) * | 2007-06-19 | 2008-05-14 | 中国兵器工业第二0六研究所 | Protective circuit of intelligent power module IPM |
| CN101895097A (en) * | 2009-05-20 | 2010-11-24 | 北京四方继保自动化股份有限公司 | Realization method of protecting circuit with converter |
| CN203537247U (en) * | 2013-11-13 | 2014-04-09 | 湖南大学 | Universal control circuit board of multi-level converter |
| CN204205569U (en) * | 2014-12-03 | 2015-03-11 | 国家电网公司 | Current transformer three grades of signal protection circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105720560A (en) | 2016-06-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105720560B (en) | Current transformer three-level signal protects circuit | |
| CN202550515U (en) | High-power IGBT (insulated gate bipolar transistor) comprehensive overcurrent protection circuit | |
| US20140002933A1 (en) | Modular multilevel converter valve protection method | |
| CN102931684A (en) | Photovoltaic alternate current and direct current intelligent distribution box | |
| CN105762767B (en) | Hardware protection circuit based on APFC | |
| CN105576952B (en) | STO control circuits and system | |
| CN105490511A (en) | T-type three-level IGBT drive circuit | |
| CN101895097A (en) | Realization method of protecting circuit with converter | |
| CN103208784A (en) | Battery protection circuit and method thereof | |
| CN109672149A (en) | A kind of hybrid detection protection circuit and method for NPC three-level current transformer over current fault | |
| CN204205569U (en) | Current transformer three grades of signal protection circuit | |
| CN107069668A (en) | A kind of frequency converter failure protection device and frequency converter | |
| CN208143129U (en) | Ac-dc-ac frequency control circuit based on tri- level vector controlled of IGCT | |
| CN107492871B (en) | A kind of flexible direct current line direction longitudinal protection method based on total current amount | |
| CN105929220A (en) | Over-current detection circuit | |
| CN100353639C (en) | Photoelectricity triggering and detecting system for static reactive-load compensation equipment based on multi-mode optical fibre | |
| CN107390006B (en) | A kind of light-operated converter valve thyristor voltage monitoring unit | |
| CN204243725U (en) | A kind of phase shortage monitoring and protecting circuit | |
| CN111030493A (en) | Submodule of modular multilevel converter and protection circuit thereof | |
| CN204046134U (en) | A kind of phase failure protector circuit | |
| CN108845178A (en) | A kind of over-current detection circuit and real-time detection and control method of three phase alternating current motor | |
| CN203071901U (en) | Three-phase solid-state relay | |
| CN207039214U (en) | Cell equalizing protecting circuit and battery equalization system | |
| CN202586293U (en) | A leakage protection circuit of vehicle-mounted inverter and a corresponding vehicle-mounted inverter | |
| CN204089173U (en) | A kind of frequency changer direct current bus voltage protection circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |