CN105720560A - Converter three-grade signal protection circuit - Google Patents

Abstract

The invention provides a converter three-grade signal protection circuit. The protection circuit comprises a sensor, a hardware excess protection circuit, an FPGA protection circuit, a DSP pulse blocking circuit, a PWM driving circuit and an IPM power module. The FPGA protection circuit is used for generating a fault pulse blocking signal according to an over-current fault signal, an overvoltage fault signal, an upper bridge arm fault signal and a lower bridge arm fault signal and blocking converter pulse signals of an FPGA, a DSP and the PWM driving circuit. The DSP pulse blocking circuit is used for setting six paths of PWM trigger pulse signals output to the FPGA to a high-resistance state after receiving the fault pulse blocking signal. The technical problem in the prior art that over-current oscillation may easily occur to a converter system to cause damage to an IPM is solved, and the over-current oscillation phenomenon of internal protection of the converter is restrained effectively.

Description

Three-level signal protection circuit of converter

technical field

The invention relates to the technical field of power system power conversion, in particular to a three-stage signal protection circuit for a converter.

Background technique

In applications such as power conversion, variable current drives, and switching power supplies, converters are increasingly used. During the operation of the converter, the current and voltage far exceed the rated operating range due to grid reasons, load reasons or the converter itself. In this case, the converter itself must respond quickly , turn off the converter, so as not to cause damage to the power components of the converter (such as: IGBT, capacitor, etc.).

The current power devices mostly use IPM (Intelligent Power Module), which integrates IGBT devices, drive circuits, protection circuits, etc., which is more convenient to use. IPM's own protection functions include: control power supply undervoltage protection, overheat protection, overcurrent protection, upper and lower bridge arm fault protection, etc.

However, the IPM self-protection does not act consistently for all IGTB devices inside the module, and the output alarm signal is not retentive, which may easily lead to overcurrent oscillation in the system and eventually cause damage to the IPM.

For the above problems, no effective solution has been proposed yet.

Contents of the invention

An embodiment of the present invention provides a three-level signal protection circuit for a converter to solve the technical problem that overcurrent oscillations in the current converter system easily cause IPM damage in the prior art. The three-level signal protection circuit for the converter, include:

Sensors, hardware overload protection circuit, FPGA protection circuit, DSP pulse blocking circuit, PWM drive circuit and IPM power module, of which:

The sensor is used to collect three-phase current and DC bus voltage;

The hardware excessive protection circuit, the input end is connected to the sensor, and the output end is connected to the input pin of the FPGA protection circuit, and is used to output an overcurrent fault signal to the The FPGA protection circuit outputs an overvoltage fault signal to the FPGA protection circuit when the DC bus voltage exceeds a preset value;

The IPM power module is connected to the PWM driving circuit through an optical fiber, and is used to output the upper bridge arm fault signal and the lower bridge arm fault signal to the PWM driving circuit, and receive the 6-way PWM trigger output from the PWM driving circuit Pulse signal and 1 fault pulse blocking signal;

The PWM driving circuit is connected with the FPGA protection circuit and the IPM power module, and is used to receive the 1-way fault pulse blocking signal and the 6-way PWM trigger pulse signal output by the FPGA protection circuit, and send the 1-way The fault pulse blocking signal and 6 PWM trigger pulse signals are output to the IPM power module for receiving the upper bridge arm fault signal and the lower bridge arm fault signal output by the IPM power module, and transmitting the upper bridge arm fault signal and the lower bridge arm fault signal are output to the FPGA protection circuit;

Described FPGA protection circuit is connected with described hardware excessive protection circuit, DSP pulse blockade circuit, PWM drive circuit respectively, for the overcurrent fault signal and overvoltage fault signal output according to described hardware excessive protection circuit, and described IPM The upper bridge arm fault signal and the lower bridge arm fault signal output by the power module generate a fault pulse blocking signal, first block the internal pulse of the FPGA, set the PWM trigger pulse signal through the FPGA to a high-impedance state, and then block the fault pulse signal Output to the interrupt pin of the DSP pulse blockade circuit and the PWM drive circuit, the FPGA protection circuit is also used to receive the 6-way PWM trigger pulse signal output by the DSP pulse blocker circuit, and send the 6-way PWM trigger pulse The signal is output to the PWM driving circuit;

The DSP pulse blocking circuit is connected with the FPGA protection circuit, and is used to set the 6 PWM trigger pulse signals output to the FPGA to a high-impedance state after receiving the fault pulse blocking signal.

In one embodiment, the hardware overload protection circuit includes:

A common-cathode full-bridge rectifier circuit composed of 6 diodes 1N4148, connected to a DC voltage divider circuit, used to convert the received bipolar signal into a DC signal, and output the DC signal to the DC voltage divider circuit ;

The DC voltage divider circuit is respectively connected to the common cathode full bridge rectifier circuit, the DC signal input terminal, and the voltage comparator, and is used to divide the input DC signal and output the divided voltage signal to the the voltage comparator;

The voltage comparator is connected to the DC voltage dividing circuit and the reference voltage threshold setting circuit respectively, and is used to compare the divided voltage signal according to the voltage comparison threshold output by the reference voltage threshold setting circuit, When the divided voltage threshold exceeds the range of the voltage comparison threshold, an overcurrent fault signal or an overvoltage fault signal is output.

In one embodiment, the reference voltage threshold setting circuit includes: a voltage upper limit setting circuit and a voltage lower limit setting circuit.

In one embodiment, the Zener diode used in the reference voltage threshold setting circuit is a ZMM10 Zener diode, and the potentiometer used is a 3224W-1-103E potentiometer.

In one embodiment, the PWM drive circuit includes: a first photoelectric conversion board and a second photoelectric conversion board, wherein the first photoelectric conversion board and the second photoelectric conversion board are connected by 8 optical fibers.

In one embodiment, the first photoelectric conversion board includes: a PWM pulse output signal driving circuit and a fault signal processing circuit of the converter itself, wherein:

The PWM pulse output signal drive circuit includes a first power driver and a first optical fiber transmitter connected in series in sequence, and the first power driver is used to receive 6 PWM trigger pulse signals and 1 fault pulse output by the FPGA protection circuit Blocking the signal, and driving the first optical fiber transmitter to output 6 PWM trigger pulse signals to the IPM power module;

The fault signal processing circuit of the converter itself includes: a blocking signal conversion circuit, a fault pulse signal receiving circuit, and a fault signal latch and alarm circuit, wherein:

The blocking signal conversion circuit includes a second power driver and a second optical fiber transmitter connected in series in sequence, and the second power driver is used to pass the received 1-way fault pulse blocking signal output by the FPGA protection circuit through the first Two optical fiber transmitters are output to the second photoelectric conversion board;

The fault pulse signal receiving circuit includes a third optical fiber receiver and a first-order RC filter for converting the upper bridge arm fault signal and/or the lower bridge arm fault signal output by the IPM power module into an electrical signal, and The converted electrical signal is output to the protection circuit and the fault signal latch and alarm circuit;

The input signals of the fault signal latch and alarm circuit include: fault pulse blockade signal, upper bridge arm fault signal, and lower bridge arm fault signal, which are used to respectively convert the upper bridge arm fault signal Reverse the fault signal of the lower bridge arm once, and reverse the fault pulse blocking signal twice. Among them, the fault pulse blocking signal after the two inversions is connected to the cathode of the LED warning light, and the fault signal of the upper bridge arm is reversed once. and the fault signal of the lower bridge arm are respectively input to the D latch composed of the NAND gate chip 74LS00, and the reset signal is connected to the D latch, and the latched signals are respectively connected to the LED warning light, and the latch The upper bridge arm fault signal, the lower bridge arm fault signal, and the fault pulse blocking signal latched in the device are input to the buzzer control circuit after being phase-ANDed by the AND gate chip 74LS21.

In one embodiment, the second photoelectric conversion board includes: a PWM pulse receiving signal driving circuit and a fault signal transmitting circuit, wherein:

The PWM pulse receiving signal drive circuit is configured to receive the 6-way PWM trigger pulse signals output by the first photoelectric conversion board, and output the received 6-way PWM trigger pulse signals to the IPM power module;

The fault signal transmitting circuit is configured to output the fault signal of the upper bridge arm and/or the fault signal of the lower bridge arm received from the fault signal transmitting circuit to the first photoelectric conversion board.

In one embodiment, the model of the first fiber transmitter, the second fiber transmitter and the third fiber transmitter is HFBR1521, and the model of the first power driver and the second power driver is SN75451.

In one embodiment, the model of the IPM power module is PM150CLA120.

In the embodiment of the present invention, a three-level signal protection circuit for a converter is provided. Through the FPGA protection circuit and the DSP pulse blocking circuit in the protection circuit, the overcurrent fault signal, the overvoltage fault signal, and the upper bridge arm fault signal Generate a fault pulse blockade signal with the fault signal of the lower bridge arm to realize a three-stage pulse blockade of the circuit, thereby solving the technical problem of IPM damage caused by overcurrent oscillation in the converter system in the prior art, and using a three-stage pulse blockade To deal with the internal and external faults of the converter to the greatest extent, the fault signal is maintained by the FPGA, which effectively suppresses the overcurrent oscillation phenomenon of the internal protection of the converter.

Description of drawings

The drawings described here are used to provide further understanding of the present invention, constitute a part of the application, and do not limit the present invention. In the attached picture:

FIG. 1 is a schematic diagram of a three-stage signal protection circuit of a converter according to an embodiment of the invention;

Fig. 2 is the circuit diagram of the hardware overload protection of the embodiment of the present invention;

3 is a reference voltage threshold setting circuit diagram 1 of an embodiment of the present invention;

Fig. 4 is the reference voltage threshold setting circuit Fig. 2 of the embodiment of the present invention;

Fig. 5 is the PWM output pulse signal driving circuit diagram of the embodiment of the present invention;

Fig. 6 is the PWM receiving pulse signal driving circuit diagram of the embodiment of the present invention;

Fig. 7 is the circuit diagram of PWM signal latch and sound and light alarm of the embodiment of the present invention;

Fig. 8 is the FPGA internal logic diagram of the embodiment of the present invention;

Fig. 9 is a flow chart of converter software protection according to the embodiment of the present invention.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with the embodiments and accompanying drawings. Here, the exemplary embodiments and descriptions of the present invention are used to explain the present invention, but not to limit the present invention.

In the embodiment of the present invention, a converter three-level signal protection circuit is provided, as shown in Figure 1, including: sensors, hardware overload protection circuit, FPGA protection circuit, DSP pulse blockade circuit, PWM drive circuit and IPM power module, where:

Sensors for collecting three-phase current and DC bus voltage;

A hardware overload protection circuit, the input terminal is connected to the sensor, the output terminal is connected to the input pin of the FPGA protection circuit, and is used to output an overcurrent fault signal to the The FPGA protection circuit outputs an overvoltage fault signal to the FPGA protection circuit when the DC bus voltage exceeds a preset value;

The IPM power module is connected to the PWM driving circuit through an optical fiber, and is used to output the upper bridge arm fault signal and the lower bridge arm fault signal to the PWM driving circuit, and receive the 6-way PWM trigger pulse signal output by the PWM driving circuit And 1 channel fault pulse blocking signal;

The PWM driving circuit is connected with the FPGA protection circuit and the IPM power module, and is used to receive the 1-way fault pulse blocking signal and the 6-way PWM trigger pulse signal output by the FPGA protection circuit, and send the 1-way fault pulse The blocking signal and 6 PWM trigger pulse signals are output to the IPM power module for receiving the upper bridge arm fault signal and the lower bridge arm fault signal output by the IPM power module, and the upper bridge arm fault signal and the lower bridge arm fault signal The bridge arm fault signal is output to the FPGA protection circuit;

The FPGA protection circuit is connected with the hardware excessive protection circuit, the DSP pulse blocking circuit, and the PWM driving circuit respectively, and is used for outputting an overcurrent fault signal and an overvoltage fault signal according to the hardware excessive protection circuit, and the IPM power module The output upper bridge arm fault signal and the lower bridge arm fault signal generate a fault pulse blocking signal, and output the fault pulse blocking signal to the interrupt pin of the DSP pulse blocking circuit and the PWM drive circuit, the FPGA The protection circuit is also used to receive the 6-way PWM trigger pulse signal output by the DSP pulse blocking circuit, and output the 6-way PWM trigger pulse signal to the PWM drive circuit;

The DSP pulse blocking circuit is connected with the FPGA protection circuit, and is used to set the 6 PWM trigger pulse signals output to the FPGA to a high-impedance state after receiving the fault pulse blocking signal.

The three-level signal protection circuit of the converter shown in Fig. 1 will be described in detail below in conjunction with a specific embodiment. Improperly qualified.

Specifically, in this example, a converter protection circuit that combines software and hardware and matches the IPM signal is provided. This protection circuit can not only deal with sudden and rapid overcurrent and overvoltage protection, but also Considering the short-circuit, over-temperature and under-voltage protection of the IPM itself, and through optical fiber transmission, the over-voltage and over-current fault alarm protection circuit of the converter and the three-level pulse blockade circuit are designed. Due to the powerful logic resources of FPGA, a fault signal logic judgment processing circuit is built in FPGA to block pulses from four aspects: DSP, FPGA, PWM drive, and IPM. When over-current, over-voltage, IPM faults, etc. It can respond quickly, shut down the converter and give an alarm, comprehensively and effectively protecting the converter itself and external equipment.

According to the different processing methods of different fault signals, it is mainly divided into five parts: hardware overload protection circuit, IPM power module, PWM drive circuit, FPGA protection circuit, and DSP pulse blockade. The following five parts will be explained in detail:

1) Hardware overload protection circuit

The protected three-phase current and DC bus voltage are collected by the Hall sensor and then enter the hardware overload protection circuit. The Hall voltage sensor can be LV25-P, and the current sensor can be LA100-P.

As shown in Figure 2, the hardware overload protection circuit includes:

The reference voltage threshold setting circuit is used to provide a reference voltage for the over-protection logic circuit;

Over-protection logic circuit, including: uncontrolled rectification circuit, DC voltage divider circuit, filter circuit and voltage comparison circuit, wherein, the uncontrolled rectification circuit is composed of 6 diodes 1N4148 (D1 to D6) to form a common cathode full bridge rectification circuit:

When a bipolar signal is input, it is first converted to a DC signal through an uncontrolled rectification circuit. The relationship between input and output is: U _d = 2.34*U _i , and the rectified DC signal passes through two metal film resistors (R7 and R8) After the voltage is divided, the voltage comparator LM311 is used to compare with the set reference voltage threshold, and finally output the fault signal.

When a unipolar signal is input: connect the input signal directly to the DC voltage divider circuit, compare it with the reference voltage through a voltage comparator, and output a fault signal.

The reference voltage threshold setting circuit, as shown in Figure 3 and 4, is powered by +15V voltage and -15V voltage respectively, and uses Zener diode ZMM10 to maintain the threshold setting range between 0V ~ +10V and -10V ~ 0V respectively , At the same time, in order to ensure the correctness of the judgment of the protected signal, the precision potentiometer 3224W-1-103E with high precision and high voltage resistance is used to adjust the size of the protection threshold reference level.

The over-current OVA1 and over-voltage fault signal OVA2 generated after being processed by the hardware over-load protection circuit are directly connected to the allocated pins of the FPGA.

2) IPM power module

In this example, the model of the IPM power module is selected as PM150CLA120, the input is 6 channels of PWM trigger pulse signal and 1 channel of fault pulse blocking signal, and the output is respectively the fault signal of the upper bridge arm OVA3 and the fault signal of the lower bridge arm OVA4, the pulse signal and The fault signal is converted into an optical fiber signal through the drive circuit and the fiber optic transmitter for transmission.

However, it should be noted that in this example, the PM150CLA120 type IPM power module is used as an example for illustration, and other types of IPM power modules can also be used, which is not limited in this application.

3) PWM drive circuit

As shown in Figure 1, the PWM drive circuit is mainly divided into two parts: one is the photoelectric conversion board A, and the other is the photoelectric conversion board B, and the two are connected by 8 optical fibers.

Among them, the photoelectric conversion board A is composed of two parts: the PWM pulse output signal drive circuit and the fault signal processing circuit of the converter itself, in which:

3-1) The PWM pulse output signal drive circuit, as shown in Figure 5, is composed of a power driver SN75451 and a fiber optic transmitter HFBR1521 in series, and 6 channels of PWM trigger pulse signals and 1 channel of pulse blocking signals/XSHUTA are output from FPGA pins Together, they are input to the power driver to drive the optical fiber transmitter to send PWM signals, and the output signals are connected to the IPM power module through optical fibers.

3-2) The fault signal processing circuit of the converter itself includes three parts: the fault pulse signal receiving circuit, the blocking signal conversion circuit, the fault signal latch and alarm circuit, of which:

3-2-1) The blockade signal conversion circuit has the same structure as the PWM pulse output signal drive circuit, but the two input signals of the power driver are /XSHUTA, and the low level is active, and output to the photoelectric conversion board B through the optical fiber.

3-2-2) The fault pulse signal receiving circuit, as shown in Figure 5, is composed of a fiber optic receiver HFBR2521 and a first-order RC filter, which converts optical signals into electrical signals, and the converted fault signals are simultaneously input to FPGA and Fault latch and alarm circuit.

3-2-3) The fault signal latch and alarm circuit, as shown in Figure 7, the input signal is the blocking signal/XSHUTA and the fault signals OVA3 and OVA4 of the upper and lower bridge arms of the converter, which are triggered by six inverting Schmitt The device 74LS14 respectively inverts OVA3 and OVA4 once, and inverts the /XSHUTA signal twice, the blocking signal /XSHUTA is connected to the cathode of the LED warning light (D1), and the fault signals OVA3 and OVA4 are respectively input to the NAND gate chip 74LS00. D latch, and connect the reset signal K1 to the latch, and the latched signals are respectively connected to the LED warning lights (D2); the latched fault signal and pulse blocking signal are input to the Buzzer (SP1) control loop, three signals are active low.

Further, the photoelectric conversion board B corresponds to the photoelectric conversion board A, and is also composed of two parts: a PWM pulse receiving signal driving circuit and a fault signal transmitting circuit, wherein:

There are six PWM pulse receiving signal driving circuits, each of which is the same as the fault pulse signal receiving circuit of photoelectric conversion board A, the input is six PWM trigger pulse signals output by photoelectric conversion board A, and the output is connected to the IPM rate module; the fault signal transmitting circuit , which is the same as the PWM pulse transmitting circuit of the photoelectric conversion board A, and the output is a fault signal connected to the photoelectric conversion board A through an optical fiber.

4) FPGA protection logic (i.e. FPGA protection circuit)

The protection logic of the FPGA is composed of AND gates, which AND the faults OVA3 and OVA4 of the converter itself, the AC overcurrent signal OVA1 (that is, the overcurrent fault signal), the DC bus voltage overvoltage signal OVA2 (that is, the overvoltage fault signal), and Generate a fault blocking signal /XSHUTA (that is, a fault pulse blocking signal), which blocks the PWM signal inside the FPGA and transmits it down to the photoelectric conversion board A. Blocks the PWM trigger pulse signal through hardware and transmits it up to the DSP's / PDPINTA pin.

5) DSP pulse blockade (that is, DSP pulse blockade circuit)

The pulse blockade of DSP can be by setting the power drive protection interrupt/PDPINTA of the event manager EVA, and the pulses of PWM1-6 are forced to be in a high-impedance state within the interrupt, that is, the PWM trigger pulse signal of the DSP is blocked.

From the above analysis, it can be seen that the fault signal entering the FPGA for processing in the three-level protection circuit of the converter shown in Figure 1 mainly has two parts: the hardware circuit detects the DC voltage and the AC current exceeds the normal operating voltage range and sends it out 2-way alarm signal, 2-way and lower bridge arm fault signals generated by IPM power module, 4-way fault signal in total.

In the three-level protection circuit of the converter, the converter PWM fault pulse blocking signal generated by FPGA has three parts: DSP, FPGA, and PWM driver board, among which, DSP and FPGA constitute two-level software protection, and PWM drive board constitutes hardware protection.

Through the above-mentioned three-level protection circuit of the converter, the protection of the converter can be satisfied from the aspects of software and hardware, and the three-level pulse blockade is used to deal with the internal and external faults of the converter to the greatest extent. The fault signal is maintained by FPGA, Effectively suppress the overcurrent oscillation phenomenon of the internal protection of the converter.

In this example, the generation and processing of the fault signal is considered from the two aspects of the external fault of the converter and its own fault. The external fault signal is generated through the hardware excessive protection circuit, and the fault of the converter itself is directly input to the fault of the upper and lower bridge arms through the IPM. External faults are transmitted through electrical signals. In order to isolate the electromagnetic interference of the primary system to the secondary control system, the faults of the converter itself are transmitted to the FPGA through optical fibers. After the fault indication signal is led to the FPGA, the rich logic resources of the FPGA are used to form a protection Logic, and generate protection action signals, respectively block the pulse output signals of DSP, FPGA, and PWM driver boards, to achieve the purpose of multiple protections.

The above-mentioned three-stage protection circuit of the converter will be described below in combination with a specific embodiment. However, it should be noted that the specific embodiment is only for better illustration of the present invention, and does not constitute an improper limitation of the present invention.

As shown in Figure 1, the three-phase current and DC bus voltage are input to the hardware over-voltage protection circuit through the current sensor, and generate over-current and over-voltage fault signals OVA1, OVA2, and the converter IPM generates upper and lower bridge arm fault signals OVA3, OVA4, the fault signal is transmitted between the photoelectric conversion boards A and B through the optical fiber. When there is no fault, the 6 PWM trigger pulse signals are generated by the DSP, transmitted to the photoelectric conversion boards A and B through the FPGA, and finally output to the six bridge arms of the IPM. When the bridge arm of the bridge fails, the PWM through DSP, FPGA, and photoelectric conversion board A are all blocked. In Figure 1, Iabc represents the three-phase AC current, Udc represents the DC bus voltage, OVA1 represents the overvoltage fault signal, OVA2 represents the overcurrent fault signal, OVA3 represents the upper bridge arm fault signal, OVA4 represents the lower bridge arm fault signal, /XSHUTA Indicates pulse blocking signal, /PDPINTA indicates power drive interruption signal.

The hardware overload protection circuit is shown in Figure 2. The diode 1N4148 is used to form an uncontrolled rectification circuit, combined with a voltage comparison circuit, and the function of compatible AC and DC signal excessive detection is realized by switching the input channel. That is, the AC signal can enter from pins 3, 4, and 5 of J1. First, the AC signal is converted into DC through three-phase uncontrolled rectification, and then divided by resistors, and compared with the set reference voltage value by the voltage comparator LM311 , and finally output the excess voltage signal to pin 5 of J2. If the input is a DC signal, input it from pins 1 and 7 of J1, bypass the rectifier circuit and directly enter the voltage comparison link, and output the excess signal. Specifically, a Zener diode can be used ZMM10 maintains the threshold setting range between 0V～+10V and -10V～0V. At the same time, in order to ensure the correctness of the protected signal judgment, a high-precision, high-voltage-resistant precision potentiometer 3224W-1 is used as shown in Figures 3 and 4. -103E adjusts the size of the protection threshold level. When the protected signal level exceeds the set threshold level, the comparator outputs a low level. When the protected signal level drops below the threshold level, the excessive signal is canceled. In Figures 2 to 4, R1~R14 represent ordinary resistors, R15 and R16 represent adjustable resistors, D1~D6 represent diodes, D7 and D8 represent voltage regulator diodes, C1~C4 represent ceramic capacitors, and U1 and U2 represent excessive protection modules , J1~J3 represent seven-pin sockets, TP1~TP4 represent test points, +REF represents positive reference level, -REF represents negative reference level.

The PWM pulse driving circuit is shown in Figures 5 and 6, which are the transmitting and receiving circuits respectively. When the PWM is at a high level, the fiber optic transmitter lights up and sends optical signals. When /XSHUTA is at a low level, no matter whether the PWM is at a high level or When the level is low, the fiber optic heads are not lit, that is, the pulse signal is blocked. The optical signal receiving circuit is similar to the transmitting circuit. The electrical signal is converted into an optical signal through the optical fiber receiver, and the PWM pulse signal is sent to the 15V level compatible with the six bridge arms of the IPM. In Figures 5 and 6, U1 represents a fiber optic receiver, R1 represents an ordinary resistor, U1A represents a power driver, XPWM1~6 represent pulse signals, and C1~C21 represent ceramic capacitors.

When the converter fails internally, the IPM will send the fault signals OVA3 and OVA4 of the upper and lower bridge arms, input the signal to the photoelectric signal conversion board B, and send it to the photoelectric signal conversion board A through the optical fiber transmitter, and the sending and receiving circuits Both are like the sending and receiving circuits of PWM, and will not be repeated here. In order to prevent failure signals from being received when the optical fiber is broken, it is necessary to invert the fault signal output by the IPM to connect a six-reverse Schmitt trigger, so that when the IPM fault signal is at a low level, the fiber head emits light. That is, it is always on during normal operation; and the electrical signal is converted into an optical signal through a fiber optic transmitter. After the optical fiber is transmitted to the photoelectric conversion board A, as shown in Figure 7, it is converted into an electrical signal through the optical fiber receiver, and the fault signal is latched and alarmed by the fault signal latch and alarm circuit. In Figure 7, U1 represents six Inverter, U2. Indicates four 2-input NAND gates, U3 indicates dual four-input AND gates, R1~7 indicates ordinary resistors, D1, D2. Indicates red LED lights, C1 indicates ceramic capacitors, Q1.PNP indicates triodes, SP1 Indicates the buzzer.

Specifically, the fault latch state equation is:

$\left\{\begin{array}{c}{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; OVA</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}^{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; XOVA</span>}\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; OVA</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}^{\mathrm{<span\; class="notranslate">\; no</span>}}}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; XOVA</span>}\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; OVA</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}^{\mathrm{<span\; class="notranslate">\; no</span>}}<span\; class="notranslate">\; +</span>\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}\\ {\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; OCA</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}^{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; XOVA</span>}\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; OVA</span>}}^{\mathrm{<span\; class="notranslate">\; no</span>}}}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; XOVA</span>}\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; OVA</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}^{\mathrm{<span\; class="notranslate">\; no</span>}}<span\; class="notranslate">\; +</span>\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}\end{array}\right.$

The fault alarm state equation is:

$\mathrm{<span\; class="notranslate">\; SP</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; XSHUTA</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; OVA</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}^{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; OVA</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}^{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}}$

Among them, K1 represents the key signal, which is normally high level, and is low level when the key is pressed, which is the reset signal.

After the above four-way fault signals enter the FPGA, the protection logic is built in the FPGA, and the PWM pulse blockade signal SHUTA and the DSP power drive interrupt signal /PDPINTA are generated, as shown in Figure 8, the FPGA protection logic state equation is:

$\left\{\begin{array}{c}{\mathrm{<span\; class="notranslate">\; Q</span>}}^{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span><span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; OVA</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; OVA</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; \&Center\; Dot;</span><span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; OVA</span>}\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; \&Center\; Dot;</span><span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; OVA</span>}\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}^{\mathrm{<span\; class="notranslate">\; no</span>}}<span\; class="notranslate">\; +</span>\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; RST</span>}}\\ <span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; PDPINTA</span>}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}^{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}}\\ \mathrm{<span\; class="notranslate">\; SHUTA</span>}<span\; class="notranslate">\; =</span>\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{{\mathrm{<span\; class="notranslate">\; Q</span>}}^{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}}}\end{array}\right.$

Among them, the overall software design process inside the FPGA is shown in Figure 9. After the fault signal is judged, a pulse blockade signal is generated immediately. First, the PWM pulse output inside the FPGA is blocked, and then the fault interrupt is generated to the DSP and sent to the PWM drive circuit. Block signal blocks its PWM.

From the above description, it can be seen that the embodiment of the present invention achieves the following technical effects: a three-stage signal protection circuit for a converter is provided, through the FPGA protection circuit and the DSP pulse blocking circuit in the protection circuit, according to the overcurrent The fault signal, overvoltage fault signal, upper bridge arm fault signal and lower bridge arm fault signal generate a fault pulse blocking signal to realize three-level pulse blocking of the circuit, thereby solving the problem of overcurrent in the converter system in the prior art For the technical problem of IPM damage caused by oscillation, the three-level pulse blockade is used to deal with the internal and external faults of the converter to the greatest extent, and the maintenance of the fault signal by FPGA effectively suppresses the overcurrent oscillation phenomenon of the internal protection of the converter.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, various modifications and changes may be made to the embodiments of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (9)

1. three grades of signal protection circuit of a current transformer, it is characterised in that including: the excessive protection circuit of sensor, hardware, FPGA protect circuit, DSP pulse blocking circuit, PWM drive circuit and IPM power model, wherein:

Described sensor, is used for gathering three-phase current and DC bus-bar voltage；

The excessive protection circuit of described hardware; input is connected with described sensor; outfan protects the input pin of circuit to be connected with described FPGA; protecting circuit for the output overcurrent fault-signal when described three-phase current is beyond preset value to described FPGA, when described DC bus-bar voltage is beyond preset value, output overvoltage fault-signal protects circuit to described FPGA；

Described IPM power model, it is connected with described PWM drive circuit by optical fiber, for exporting upper brachium pontis fault-signal and lower brachium pontis fault-signal to described PWM drive circuit, and receive 6 road PWM start pulse signals and the 1 road down pulse locking signal of the output of described PWM drive circuit；

Described PWM drive circuit; circuit and described IPM power model is protected to be connected with described FPGA; 1 road down pulse locking signal and the 6 road PWM start pulse signals of circuit output are protected for receiving described FPGA; and by described 1 road down pulse locking signal and 6 road PWM start pulse signal output extremely described IPM power models; for receiving the upper brachium pontis fault-signal of described IPM power model output and lower brachium pontis fault-signal, and described upper brachium pontis fault-signal and lower brachium pontis fault-signal are exported to described FPGA protection circuit；

Described FPGA protects circuit, protection circuit excessive in described hardware respectively, DSP pulse blocking circuit, PWM drive circuit is connected, for the over current fault signal according to the excessive protection circuit output of described hardware and overvoltage fault-signal, and the upper brachium pontis fault-signal of described IPM power model output and lower brachium pontis fault-signal, generate down pulse locking signal, first block FPGA internal pulses, high-impedance state will be set to by the PWM start pulse signal of FPGA, then by the interrupt pin of described down pulse locking signal output to described DSP pulse blocking circuit and described PWM drive circuit, described FPGA protects circuit to be additionally operable to receive 6 road PWM start pulse signals of described DSP pulse blocking circuit output, and by 6 road PWM start pulse signal outputs to described PWM drive circuit；

Described DSP pulse blocking circuit, protects circuit to be connected with described FPGA, for 6 road PWM start pulse signals of output to described FPGA being set to high-impedance state after receiving described down pulse locking signal.

2. three grades of signal protection circuit of current transformer as claimed in claim 1, it is characterised in that the excessive protection circuit of described hardware includes:

The common cathode full bridge rectifier being made up of 6 diode 1N4148, is connected with DC voltage divider circuit, for the bipolar signal received is converted to direct current signal, and by described DC signal output to described DC voltage divider circuit；

Described DC voltage divider circuit, is connected with described common cathode full bridge rectifier, direct current signal input, voltage comparator respectively, for the direct current signal of input carries out dividing potential drop, and exports the voltage signal after dividing potential drop to described voltage comparator；

Described voltage comparator, it is connected with described DC voltage divider circuit and reference voltage threshold initialization circuit respectively, for the voltage ratio relatively threshold value exported according to described reference voltage threshold initialization circuit, voltage signal after dividing potential drop is compared, voltage threshold after dividing potential drop beyond described voltage ratio compared with the scope of threshold value, output overcurrent fault-signal or overvoltage fault-signal.

3. three grades of signal protection circuit of current transformer as claimed in claim 2, it is characterised in that described reference voltage threshold initialization circuit includes: upper voltage limit initialization circuit and lower voltage limit initialization circuit.

4. three grades of signal protection circuit of current transformer as claimed in claim 2, it is characterised in that the Zener diode that described reference voltage threshold initialization circuit adopts is ZMM10 Zener diode, and the potentiometer of employing is 3224W-1-103E potentiometer.

5. three grades of signal protection circuit of current transformer as claimed in claim 1; it is characterized in that; described PWM drive circuit includes: the first photoelectric conversion plate and the second photoelectric conversion plate, wherein, is connected by 8 optical fiber between described first photoelectric conversion plate with described second photoelectric conversion plate.

6. three grades of signal protection circuit of current transformer as claimed in claim 5, it is characterised in that described first photoelectric conversion plate includes: pwm pulse output signal driver circuit and the fault-signal of current transformer own process circuit, wherein:

Described pwm pulse output signal driver circuit includes the first analog line driver and the first fiber optic emitter that are sequentially connected in series; 6 road PWM start pulse signals and the 1 road down pulse locking signal of circuit output protected by described first analog line driver for receiving described FPGA, and drives described first fiber optic emitter by 6 road PWM start pulse signal outputs to described IPM power model；

The fault-signal of described current transformer own processes circuit and includes: locking signal change-over circuit, failure pulse signal receive circuit and fault-signal latches and warning circuit, wherein:

Described locking signal change-over circuit includes the second analog line driver and the second fiber optic emitter that are sequentially connected in series, and described second analog line driver protects 1 road down pulse locking signal of circuit output by described second fiber optic emitter output to described second photoelectric conversion plate for the described FPGA that will receive；

Described failure pulse signal receives circuit and includes the 3rd fiber optic receiver and single order RC wave filter; be converted to the signal of telecommunication for the upper brachium pontis fault-signal exported by described IPM power model and/or lower brachium pontis fault-signal, and the signal of telecommunication output being converted to is latched and warning circuit to described protection circuit and described fault-signal；

The input signal that described fault-signal latches with warning circuit includes: down pulse locking signal, upper brachium pontis fault-signal, lower brachium pontis fault-signal, for respectively upper brachium pontis fault-signal and lower brachium pontis fault-signal being negated once by six anti-phase Schmidt trigger 74LS14, down pulse locking signal is negated twice, wherein, negate the down pulse locking signal after twice to be connected with the negative electrode of LED alarm lamp, negate the upper brachium pontis fault-signal after once and lower brachium pontis fault-signal is separately input to the NAND gate chip 74LS00 D-latch constituted, and reset signal is connected with described D-latch, the signal latched is connected with LED alarm lamp respectively, and the upper brachium pontis fault-signal latched in described latch, lower brachium pontis fault-signal, down pulse locking signal through with door chip 74LS21 phase with after, input to buzzer control loop.

7. three grades of signal protection circuit of current transformer as claimed in claim 6, it is characterised in that described second photoelectric conversion plate includes: pwm pulse receives signal drive circuit and fault-signal radiating circuit, wherein:

Described pwm pulse receives signal drive circuit, for receiving 6 road PWM start pulse signals of described first photoelectric conversion plate output, and the 6 road PWM start pulse signal output extremely described IPM power models that will receive；

Described fault-signal radiating circuit, for by the upper brachium pontis fault-signal received from described fault-signal radiating circuit and/or lower brachium pontis fault-signal, output is described first photoelectric conversion plate extremely.

8. three grades of signal protection circuit of current transformer as claimed in claim 7; it is characterized in that; the model of the first fiber optic emitter, the second fiber optic emitter and the 3rd fiber optic emitter is HFBR1521, and the model of described first analog line driver and the second analog line driver is SN75451.

9. three grades of signal protection circuit of the current transformer as according to any one of claim 1 to 8, it is characterised in that the model of described IPM power model is PM150CLA120.