CN105720560A - Converter three-grade signal protection circuit - Google Patents
Converter three-grade signal protection circuit Download PDFInfo
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- CN105720560A CN105720560A CN201410723107.9A CN201410723107A CN105720560A CN 105720560 A CN105720560 A CN 105720560A CN 201410723107 A CN201410723107 A CN 201410723107A CN 105720560 A CN105720560 A CN 105720560A
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Abstract
The invention provides a converter three-grade signal protection circuit. The protection circuit comprises a sensor, a hardware excess protection circuit, an FPGA protection circuit, a DSP pulse blocking circuit, a PWM driving circuit and an IPM power module. The FPGA protection circuit is used for generating a fault pulse blocking signal according to an over-current fault signal, an overvoltage fault signal, an upper bridge arm fault signal and a lower bridge arm fault signal and blocking converter pulse signals of an FPGA, a DSP and the PWM driving circuit. The DSP pulse blocking circuit is used for setting six paths of PWM trigger pulse signals output to the FPGA to a high-resistance state after receiving the fault pulse blocking signal. The technical problem in the prior art that over-current oscillation may easily occur to a converter system to cause damage to an IPM is solved, and the over-current oscillation phenomenon of internal protection of the converter is restrained effectively.
Description
Technical field
The present invention relates to power system power converter technical field, particularly to a kind of three grades of signal protection circuit of current transformer.
Background technology
In the application such as power converter, unsteady flow driving, Switching Power Supply, the application of current transformer is increasingly extensive.In the running of current transformer, reason due to electrical network reason, load-reason or current transformer self, cause that electric current, voltage are considerably beyond specified range of operation, in this case, current transformer self to be made a response rapidly, close current transformer, in order to avoid causing the damage of current transformer power device (such as: IGBT, electric capacity etc.).
Current power device many employings IPM (SPM), IPM has been internally integrated IGBT device, drive circuit, protection circuit etc., uses more convenient.IPM autoprotection function includes: control line under-voltage protection, overtemperature protection, overcurrent protection, upper and lower bridge arm error protection etc..
But, IPM autoprotection is not concordance action for all IGTB devices of inside modules, and the alarm signal exported does not have retentivity, it is easy to causes that stream oscillatory occurences occurred in system, ultimately causes the damage of IPM.
For the problems referred to above, effective solution is not yet proposed at present.
Summary of the invention
Embodiments provide a kind of three grades of signal protection circuit of current transformer, to solve prior art easily occurred in converter system the technical problem that stream vibration causes IPM to damage, three grades of signal protection circuit of this current transformer, including:
The excessive protection circuit of sensor, hardware, FPGA protect circuit, DSP pulse blocking circuit, PWM drive circuit and IPM power model, wherein:
Described sensor, is used for gathering three-phase current and DC bus-bar voltage；
The excessive protection circuit of described hardware; input is connected with described sensor; outfan protects the input pin of circuit to be connected with described FPGA; protecting circuit for the output overcurrent fault-signal when described three-phase current is beyond preset value to described FPGA, when described DC bus-bar voltage is beyond preset value, output overvoltage fault-signal protects circuit to described FPGA；
Described IPM power model, it is connected with described PWM drive circuit by optical fiber, for exporting upper brachium pontis fault-signal and lower brachium pontis fault-signal to described PWM drive circuit, and receive 6 road PWM start pulse signals and the 1 road down pulse locking signal of the output of described PWM drive circuit；
Described PWM drive circuit; circuit and described IPM power model is protected to be connected with described FPGA; 1 road down pulse locking signal and the 6 road PWM start pulse signals of circuit output are protected for receiving described FPGA; and by described 1 road down pulse locking signal and 6 road PWM start pulse signal output extremely described IPM power models; for receiving the upper brachium pontis fault-signal of described IPM power model output and lower brachium pontis fault-signal, and described upper brachium pontis fault-signal and lower brachium pontis fault-signal are exported to described FPGA protection circuit；
Described FPGA protects circuit, protection circuit excessive in described hardware respectively, DSP pulse blocking circuit, PWM drive circuit is connected, for the over current fault signal according to the excessive protection circuit output of described hardware and overvoltage fault-signal, and the upper brachium pontis fault-signal of described IPM power model output and lower brachium pontis fault-signal, generate down pulse locking signal, first block FPGA internal pulses, high-impedance state will be set to by the PWM start pulse signal of FPGA, then by the interrupt pin of described down pulse locking signal output to described DSP pulse blocking circuit and described PWM drive circuit, described FPGA protects circuit to be additionally operable to receive 6 road PWM start pulse signals of described DSP pulse blocking circuit output, and by 6 road PWM start pulse signal outputs to described PWM drive circuit；
Described DSP pulse blocking circuit, protects circuit to be connected with described FPGA, for 6 road PWM start pulse signals of output to described FPGA being set to high-impedance state after receiving described down pulse locking signal.
In one embodiment, the excessive protection circuit of described hardware includes:
The common cathode full bridge rectifier being made up of 6 diode 1N4148, is connected with DC voltage divider circuit, for the bipolar signal received is converted to direct current signal, and by described DC signal output to described DC voltage divider circuit；
Described DC voltage divider circuit, is connected with described common cathode full bridge rectifier, direct current signal input, voltage comparator respectively, for the direct current signal of input carries out dividing potential drop, and exports the voltage signal after dividing potential drop to described voltage comparator；
Described voltage comparator, it is connected with described DC voltage divider circuit and reference voltage threshold initialization circuit respectively, for the voltage ratio relatively threshold value exported according to described reference voltage threshold initialization circuit, voltage signal after dividing potential drop is compared, voltage threshold after dividing potential drop beyond described voltage ratio compared with the scope of threshold value, output overcurrent fault-signal or overvoltage fault-signal.
In one embodiment, described reference voltage threshold initialization circuit includes: upper voltage limit initialization circuit and lower voltage limit initialization circuit.
In one embodiment, the Zener diode that described reference voltage threshold initialization circuit adopts is ZMM10 Zener diode, and the potentiometer of employing is 3224W-1-103E potentiometer.
In one embodiment, described PWM drive circuit includes: the first photoelectric conversion plate and the second photoelectric conversion plate, wherein, is connected by 8 optical fiber between described first photoelectric conversion plate with described second photoelectric conversion plate.
In one embodiment, described first photoelectric conversion plate includes: pwm pulse output signal driver circuit and the fault-signal of current transformer own process circuit, wherein:
Described pwm pulse output signal driver circuit includes the first analog line driver and the first fiber optic emitter that are sequentially connected in series; 6 road PWM start pulse signals and the 1 road down pulse locking signal of circuit output protected by described first analog line driver for receiving described FPGA, and drives described first fiber optic emitter by 6 road PWM start pulse signal outputs to described IPM power model；
The fault-signal of described current transformer own processes circuit and includes: locking signal change-over circuit, failure pulse signal receive circuit and fault-signal latches and warning circuit, wherein:
Described locking signal change-over circuit includes the second analog line driver and the second fiber optic emitter that are sequentially connected in series, and described second analog line driver protects 1 road down pulse locking signal of circuit output by described second fiber optic emitter output to described second photoelectric conversion plate for the described FPGA that will receive；
Described failure pulse signal receives circuit and includes the 3rd fiber optic receiver and single order RC wave filter; be converted to the signal of telecommunication for the upper brachium pontis fault-signal exported by described IPM power model and/or lower brachium pontis fault-signal, and the signal of telecommunication output being converted to is latched and warning circuit to described protection circuit and described fault-signal；
The input signal that described fault-signal latches with warning circuit includes: down pulse locking signal, upper brachium pontis fault-signal, lower brachium pontis fault-signal, for respectively upper brachium pontis fault-signal and lower brachium pontis fault-signal being negated once by six anti-phase Schmidt trigger 74LS14, down pulse locking signal is negated twice, wherein, negate the down pulse locking signal after twice to be connected with the negative electrode of LED alarm lamp, negate the upper brachium pontis fault-signal after once and lower brachium pontis fault-signal is separately input to the NAND gate chip 74LS00 D-latch constituted, and reset signal is connected with described D-latch, the signal latched is connected with LED alarm lamp respectively, and the upper brachium pontis fault-signal latched in described latch, lower brachium pontis fault-signal, down pulse locking signal through with door chip 74LS21 phase with after, input to buzzer control loop.
In one embodiment, described second photoelectric conversion plate includes: pwm pulse receives signal drive circuit and fault-signal radiating circuit, wherein:
Described pwm pulse receives signal drive circuit, for receiving 6 road PWM start pulse signals of described first photoelectric conversion plate output, and the 6 road PWM start pulse signal output extremely described IPM power models that will receive；
Described fault-signal radiating circuit, for by the upper brachium pontis fault-signal received from described fault-signal radiating circuit and/or lower brachium pontis fault-signal, output is described first photoelectric conversion plate extremely.
In one embodiment, the model of the first fiber optic emitter, the second fiber optic emitter and the 3rd fiber optic emitter is HFBR1521, and the model of described first analog line driver and the second analog line driver is SN75451.
In one embodiment, the model of described IPM power model is PM150CLA120.
In embodiments of the present invention, provide a kind of three grades of signal protection circuit of current transformer, by protecting the FPGA in circuit to protect circuit and DSP pulse blocking circuit, according to over current fault signal, overvoltage fault-signal, upper brachium pontis fault-signal and lower brachium pontis fault-signal generate down pulse locking signal, realize the tertiary vein to circuit and rush block, thus solving, prior art easily occurred in converter system the technical problem that stream vibration causes IPM to damage, tertiary vein punching block is utilized at utmost to tackle the fault that current transformer is inside and outside, by the FPGA maintenance to fault-signal, what effectively inhibit current transformer internal protection crosses stream oscillatory occurences.
Accompanying drawing explanation
Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes the part of the application, is not intended that limitation of the invention.In the accompanying drawings:
Fig. 1 is the schematic diagram of three grades of signal protection circuit of current transformer of inventive embodiments；
Fig. 2 is the excessive protection circuit diagram of hardware of the embodiment of the present invention；
Fig. 3 is reference voltage threshold initialization circuit Fig. 1 of the embodiment of the present invention；
Fig. 4 is reference voltage threshold initialization circuit Fig. 2 of the embodiment of the present invention；
Fig. 5 is the PWM output pulse signal drive circuit figure of the embodiment of the present invention；
Fig. 6 is the PWM return pulse signal drive circuit figure of the embodiment of the present invention；
The pwm signal that Fig. 7 is the embodiment of the present invention latches and sound light alarming circuit figure；
Fig. 8 is the FPGA internal logic figure of the embodiment of the present invention；
Fig. 9 is the current transformer software protection flow chart of the embodiment of the present invention.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearly understand, below in conjunction with embodiment and accompanying drawing, the present invention is described in further details.At this, the exemplary embodiment of the present invention and explanation thereof are used for explaining the present invention, but not as a limitation of the invention.
In embodiments of the present invention, it is provided that a kind of three grades of signal protection circuit of current transformer, as it is shown in figure 1, include: the excessive protection circuit of sensor, hardware, FPGA protect circuit, DSP pulse blocking circuit, PWM drive circuit and IPM power model, wherein:
Sensor, is used for gathering three-phase current and DC bus-bar voltage；
The excessive protection circuit of hardware; input is connected with described sensor; outfan protects the input pin of circuit to be connected with described FPGA; protecting circuit for the output overcurrent fault-signal when described three-phase current is beyond preset value to described FPGA, when described DC bus-bar voltage is beyond preset value, output overvoltage fault-signal protects circuit to described FPGA；
IPM power model, it is connected with described PWM drive circuit by optical fiber, for exporting upper brachium pontis fault-signal and lower brachium pontis fault-signal to described PWM drive circuit, and receive 6 road PWM start pulse signals and the 1 road down pulse locking signal of the output of described PWM drive circuit；
PWM drive circuit; circuit and described IPM power model is protected to be connected with described FPGA; 1 road down pulse locking signal and the 6 road PWM start pulse signals of circuit output are protected for receiving described FPGA; and by described 1 road down pulse locking signal and 6 road PWM start pulse signal output extremely described IPM power models; for receiving the upper brachium pontis fault-signal of described IPM power model output and lower brachium pontis fault-signal, and described upper brachium pontis fault-signal and lower brachium pontis fault-signal are exported to described FPGA protection circuit；
FPGA protects circuit, protection circuit excessive in described hardware respectively, DSP pulse blocking circuit, PWM drive circuit is connected, for the over current fault signal according to the excessive protection circuit output of described hardware and overvoltage fault-signal, and the upper brachium pontis fault-signal of described IPM power model output and lower brachium pontis fault-signal, generate down pulse locking signal, and described down pulse locking signal is exported the interrupt pin to described DSP pulse blocking circuit and described PWM drive circuit, described FPGA protects circuit to be additionally operable to receive 6 road PWM start pulse signals of described DSP pulse blocking circuit output, and by 6 road PWM start pulse signal outputs to described PWM drive circuit；
DSP pulse blocking circuit, protects circuit to be connected with described FPGA, for 6 road PWM start pulse signals of output to described FPGA being set to high-impedance state after receiving described down pulse locking signal.
Below in conjunction with a specific embodiment, three grades of signal protection circuit of the current transformer shown in Fig. 1 are specifically described, it is important to note, however, that this specific embodiment is merely to be better described the present invention, are not intended that inappropriate limitation of the present invention.
Concrete; in this example; provide the protecting circuit with converter that a kind of software and hardware combines and the signal of IPM matches; this protection circuit is except tackling burst, quick overcurrent, overvoltage protection; also the short circuit of IPM itself, excess temperature, under-voltage protection are taken into account; and by fiber-optic transfer, devise current transformer overvoltage, over current fault alarm and protection circuit and tertiary vein and rush lockout circuit.Due to the logical resource that FPGA is powerful; in FPGA, build fault-signal logical judgment process circuit; from DSP, FPGA, PWM driving, tetra-aspect locking pulses of IPM; when the situations such as overcurrent, overvoltage, IPM fault occur; this protection circuit can react rapidly; close current transformer and report to the police, fully and effectively protection current transformer self and external equipment.
The difference of the processing mode according to different faults signal is broadly divided into five parts: the excessive protection circuit of hardware, IPM power model, PWM drive circuit, FPGA protect circuit, DSP pulse blocking, below these 5 parts are just illustrated:
1) the excessive protection circuit of hardware
Protected three-phase current and DC bus-bar voltage, after Hall element gathers, enter the excessive protection circuit of hardware, and Hall voltage sensor can adopt LV25-P, and current sensor can adopt LA100-P.
As in figure 2 it is shown, the excessive protection circuit of this hardware includes:
Reference voltage threshold initialization circuit, for providing reference voltage for excessive relay protective scheme circuit；
Excessive relay protective scheme circuit, including: uncontrollable rectifier circuit, DC voltage divider circuit, filter circuit and voltage comparator circuit, wherein, uncontrollable rectifier circuit is constituted common cathode full bridge rectifier by 6 diodes 1N4148 (D1 to D6):
When inputting bipolar signal, first passing through uncontrollable rectifier circuit conversion is direct current signal, and the relation of input and output is: Ud=2.34*Ui, the direct current signal after rectified is after 2 metalfilmresistor (R7 and R8) dividing potential drops, and the reference voltage threshold again through voltage comparator LM311 Yu setting compares, and finally exports fault-signal.
When inputting unipolar signal: input signal is directly accessed DC voltage divider circuit, compared by voltage comparator and reference voltage, export fault-signal.
Reference voltage threshold initialization circuit; as shown in Figures 3 and 4 respectively by+15V voltage and-15V power voltage supply; and adopt Zener diode ZMM10 that threshold value arranges scope respectively to be respectively maintained between 0V～+10V and-10V～0V; simultaneously in order to ensure the correctness that protected signal judges, high accuracy, high voltage bearing precision potentiator 3224W-1-103E is adopted to regulate the size of protection threshold reference potential.
The stream OVA1 and overvoltage fault-signal OVA2 excessively of the generation after the excessive protection processing of circuit of hardware, the pin directly distributed with FPGA is connected.
2) IPM power model
In this example, the model of IPM power model is chosen as PM150CLA120, input is 6 road PWM start pulse signals and 1 road down pulse locking signal, brachium pontis fault-signal OVA3 is respectively gone up in output and fault-signal is converted to fiber-optic signal respectively through drive circuit and fiber optic emitter and is transmitted by lower brachium pontis fault-signal OVA4, pulse signal and fault-signal.
It is important to note, however, that be only the IPM power model of PM150CLA120 model be in this example that example illustrates, it is also possible to adopting the IPM power model of other model, this is not construed as limiting by the application.
3) PWM drive circuit
As it is shown in figure 1, it is photoelectric conversion plate A that PWM drive circuit is broadly divided into two: one, another is photoelectric conversion plate B, is connected by 8 optical fiber therebetween.
Wherein, photoelectric conversion plate A is made up of two parts again: pwm pulse output signal driver circuit and the fault-signal of current transformer own process circuit, wherein:
3-1) pwm pulse output signal driver circuit, it is followed in series to form by analog line driver SN75451 and fiber optic emitter HFBR1521 as shown in Figure 5, the 6 road PWM start pulse signals exported from the pin of FPGA and 1 tunnel pulse blocking signal/XSHUTA are together through being input to analog line driver, driving fiber optic emitter to send pwm signal, output signal is connected with IPM power model by optical fiber.
3-2) the fault-signal process circuit of current transformer own includes three parts: failure pulse signal receives circuit, locking signal change-over circuit, fault-signal latch and warning circuit, wherein:
3-2-1) locking signal change-over circuit, structure is identical with pwm pulse output signal driver circuit, but the two-way of analog line driver input signal is /XSHUTA and Low level effective, and exports photoelectric conversion plate B by optical fiber.
3-2-2) failure pulse signal receives circuit, as it is shown in figure 5, be made up of fiber optic receiver HFBR2521 and single order RC wave filter, converts optical signals to the signal of telecommunication, and the fault-signal after conversion is input simultaneously to FPGA and fault latch and warning circuit.
3-2-3) fault-signal latches and warning circuit, as shown in Figure 7, input signal is on locking signal/XSHUTA and current transformer, lower brachium pontis fault-signal OVA3, OVA4, by six anti-phase Schmidt trigger 74LS14 respectively by OVA3, OVA4 negates once, right/XSHUTA signal negates twice, locking signal/XSHUTA is connected with the negative electrode of LED alarm lamp (D1), fault-signal OVA3, OVA4 is separately input to the NAND gate chip 74LS00 D-latch constituted, and reset signal K1 is connected with latch, the signal latched is connected with LED alarm lamp (D2) respectively；Latch fault-signal and pulse blocking signal through with door chip 74LS21 phase with after, be input to buzzer (SP1) and control loop, three signals are Low level effective.
Further, photoelectric conversion plate B is corresponding with photoelectric conversion plate A, is also be made up of two parts: pwm pulse receives signal drive circuit and fault-signal radiating circuit, wherein:
Pwm pulse receives signal drive circuit six tunnels, and it is identical that the failure pulse signal of every Lu Junyu photoelectric conversion plate A receives circuit, inputs the six road PWM start pulse signals into photoelectric conversion plate A output, and output leads module with IPM and is connected；Fault-signal radiating circuit, identical with the pwm pulse radiating circuit of photoelectric conversion plate A, it is output as fault-signal and is connected to photoelectric conversion plate A by optical fiber.
4) relay protective scheme (namely FPGA protects circuit) of FPGA
The relay protective scheme of FPGA is constituted by with door; by for current transformer fault OVA3 own, OVA4 and AC overcurrent signal OVA1 (i.e. over current fault signal), DC bus-bar voltage overvoltage signal OVA2 (i.e. overvoltage fault-signal) with; and produce fault locking signal/XSHUTA (i.e. down pulse locking signal); pwm signal is blocked by this down pulse locking signal inside FPGA; be transported down to photoelectric conversion plate A by PWM start pulse signal by hardware lockout, be passed up to DSP /PDPINTA pin.
5) pulse blocking (i.e. DSP pulse blocking circuit) of DSP
The pulse blocking of DSP can be through arranging the power drive protection interruption/PDPINTA of task manager EVA, forces to be set to high-impedance state by the pulse of PWM1～6, namely block the PWM start pulse signal of DSP in interrupting.
By above-mentioned analysis it can be seen that current transformer three-level protective circuit as shown in Figure 1 enters the FPGA fault-signal carrying out processing mainly have two parts: hardware circuit detection DC voltage, alternating current are beyond the 2 tunnel alarm signals sent after normal operating voltage range; the 2 upper and lower brachium pontis fault-signals in tunnel that IPM power model produces, totally 4 road fault-signal.
There are three parts in the place that the current transformer PWM down pulse locking signal produced by FPGA in this current transformer three-level protective circuit works: DSP, FPGA and PWM drive plate, and wherein, DSP and FPGA constitutes two-stage software protection, and PWM drives plate to constitute hardware protection.
Be disclosure satisfy that by above-mentioned current transformer three-level protective circuit and meet the protection to current transformer from software and hardware aspect; tertiary vein punching block is utilized at utmost to tackle the fault that current transformer is inside and outside; by the FPGA maintenance to fault-signal, what effectively inhibit current transformer internal protection crosses stream oscillatory occurences.
In this example from the viewpoint of the generation of current transformer external fault and two fault-signals of fault own and process, external fault signal is produced by the excessive protection circuit of hardware, the fault of current transformer own is directly inputted by IPM, lower brachium pontis fault, external fault passes through signal of telecommunication transmission, in order to isolate the primary system electromagnetic interference to secondary control system, the fault of current transformer itself is by fiber-optic transfer to FPGA, after guiding fault indication signal into FPGA, utilize logical resource abundant for FPGA, constitute relay protective scheme, and generate protection act signal, block DSP respectively, FPGA, PWM drives the pulse output signals of plate, reach the purpose of multiple protective.
Below in conjunction with a specific embodiment, above-mentioned current transformer three-level protective circuit is illustrated, it is important to note, however, that this specific embodiment is merely to be better described the present invention, be not intended that inappropriate limitation of the present invention.
As shown in Figure 1; three-phase current and DC bus-bar voltage are input to the excessive protection circuit of hardware by current sensor; and produced stream and overvoltage fault-signal OVA1, OVA2; current transformer IPM produces upper and lower brachium pontis fault-signal OVA3, OVA4, transmits fault-signal by optical fiber between photoelectric conversion plate A and B.When there is no fault, 6 road PWM start pulse signals are produced by DSP, it is delivered to photoelectric conversion plate A and B for medium with FPGA, it is finally output to six brachium pontis of IPM, when producing current transformer and crossing the brachium pontis fault of stream, overvoltage and inside, by DSP, FPGA, photoelectric conversion plate A PWM be all blocked.In FIG, Iabc represents that three-phase alternating current, Udc represent that DC bus-bar voltage, OVA1 represent that overvoltage fault-signal, OVA2 represent that overcurrent fault signal, OVA3 represent that brachium pontis fault-signal, OVA4 represent that lower brachium pontis fault-signal ,/XSHUTA represent that pulse blocking signal ,/PDPINTA represent power drive interrupt signal.
The excessive protection circuit of hardware, as in figure 2 it is shown, adopt diode 1N4148 to constitute uncontrollable rectifier circuit the method combined with voltage comparator circuit, realizes compatible with alternating and the function of direct current signal excess detector by the switching of input channel.Namely AC signal can from the 3 of J1, 4, 5 pins enter, first pass through three-phase uncontrollable rectifier and AC signal is become direct current, then through electric resistance partial pressure, compare through the reference voltage level of voltage comparator LM311 Yu setting, finally export the overvoltage signal pin 5 to J2, if input is direct current signal, then from the 1 of J1, 7 pin inputs, cross rectification circuit and be directly entered voltage comparing element, output excessive signal, concrete can adopt Zener diode ZMM10 that threshold value arranges scope to maintain between 0V～+10V and-10V～0V, simultaneously in order to ensure the correctness that protected signal judges, adopt high accuracy as shown in Figures 3 and 4, high voltage bearing precision potentiator 3224W-1-103E regulates the size of protection threshold level, when protected signal level exceedes the threshold level of setting, comparator output low level, after protected signal level drops below threshold level, cancel excessive signal.In Fig. 2 is to 4; R1～R14 represents conventional, electric-resistance; R15, R16 represent that adjustable resistance, D1～D6 represent diode, and D7, D8 represent Zener diode; C1～C4 represents ceramic condenser; U1, U2 represent excessive protection module, and J1～J3 represents seven foot insert rows, and TP1～TP4 represents test point; + REF represents positive datum, and-REF represents negative datum.
Pwm pulse drive circuit is as it can be seen in figures 5 and 6, respectively launch and receive circuit, when PWM is high level, fiber optic emitter is bright, sends optical signal, when/XSHUTA is low level, no matter PWM is high level or low level, and optical fiber head does not all work, and namely pulse signal is blocked.Optical signal receiving circuit is similar to radiating circuit, converts electrical signals to optical signal the compatible 15V level of level that pwm pulse signal is transported to six brachium pontis of IPM by fiber optic receiver.In figs. 5 and 6, U1 represents that fiber optic receiver, R1 represent that conventional, electric-resistance, U1A represent analog line driver, and XPWM1～6 represent pulse signal, and C1～C21 represents ceramic condenser.
During current transformer internal fault, IPM will send upper and lower brachium pontis fault-signal OVA3, OVA4, this signal be input to photoelectric signal transformation plate B, and be sent to photosignal keyset A by fiber optic emitter, transmission and reception circuit, all such as the transmission and reception circuit of PWM, does not repeat them here.When optical fiber fractures, not receiving fault-signal, it is necessary to the fault-signal of IPM output is negated, i.e. accessible six anti-Schmidt triggers so that when IPM fault-signal is low level, launching fiber hair light, is Chang Liang time namely properly functioning；And convert electrical signals to optical signal by fiber optic emitter.After fiber-optic transfer to photoelectric conversion plate A, as it is shown in fig. 7, be converted to the signal of telecommunication by fiber optic receiver, and latched and warning circuit by fault-signal, being latched by fault-signal and report to the police, U1 represents that hex inverter, U2. represent 42 input nand gates in the figure 7, U3 represents double; two four input and doors, R1～7 represent conventional, electric-resistance, and D1, D2. represent red LED lamp, and C1 represents ceramic condenser, Q1.PNP represents audion, and SP1 represents buzzer.
Concrete, fault latch state equation is:
Fault-alarming state equation is:
Wherein, K1 represents push button signalling, is normally high level, is low level, is reset signal when button is pressed.
After above-mentioned four road fault-signals enter FPGA, structure relay protective scheme in FPGA, and produce the power drive interrupt signal/PDPINTA of pwm pulse locking signal SHUTA and DSP, as shown in Figure 8, the relay protective scheme state equation of FPGA is:
Wherein, overall software design flow process within FPGA is as it is shown in figure 9, after judging generation fault-signal, produce pulse blocking signal at once, first block pwm pulse output within FPGA, then produce fault interrupting to DSP respectively and block its PWM to PWM drive circuit transmission locking signal.
In from the description above, can be seen that, the embodiment of the present invention achieves following technique effect: provide a kind of three grades of signal protection circuit of current transformer, by protecting the FPGA in circuit to protect circuit and DSP pulse blocking circuit, according to over current fault signal, overvoltage fault-signal, upper brachium pontis fault-signal and lower brachium pontis fault-signal generate down pulse locking signal, realize the tertiary vein to circuit and rush block, thus solving, prior art easily occurred in converter system the technical problem that stream vibration causes IPM to damage, tertiary vein punching block is utilized at utmost to tackle the fault that current transformer is inside and outside, by the FPGA maintenance to fault-signal, what effectively inhibit current transformer internal protection crosses stream oscillatory occurences.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the embodiment of the present invention can have various modifications and variations.All within the spirit and principles in the present invention, any amendment of making, equivalent replacement, improvement etc., should be included within protection scope of the present invention.
Claims (9)
1. three grades of signal protection circuit of a current transformer, it is characterised in that including: the excessive protection circuit of sensor, hardware, FPGA protect circuit, DSP pulse blocking circuit, PWM drive circuit and IPM power model, wherein:
Described sensor, is used for gathering three-phase current and DC bus-bar voltage；
The excessive protection circuit of described hardware; input is connected with described sensor; outfan protects the input pin of circuit to be connected with described FPGA; protecting circuit for the output overcurrent fault-signal when described three-phase current is beyond preset value to described FPGA, when described DC bus-bar voltage is beyond preset value, output overvoltage fault-signal protects circuit to described FPGA；
Described IPM power model, it is connected with described PWM drive circuit by optical fiber, for exporting upper brachium pontis fault-signal and lower brachium pontis fault-signal to described PWM drive circuit, and receive 6 road PWM start pulse signals and the 1 road down pulse locking signal of the output of described PWM drive circuit；
Described PWM drive circuit; circuit and described IPM power model is protected to be connected with described FPGA; 1 road down pulse locking signal and the 6 road PWM start pulse signals of circuit output are protected for receiving described FPGA; and by described 1 road down pulse locking signal and 6 road PWM start pulse signal output extremely described IPM power models; for receiving the upper brachium pontis fault-signal of described IPM power model output and lower brachium pontis fault-signal, and described upper brachium pontis fault-signal and lower brachium pontis fault-signal are exported to described FPGA protection circuit；
Described FPGA protects circuit, protection circuit excessive in described hardware respectively, DSP pulse blocking circuit, PWM drive circuit is connected, for the over current fault signal according to the excessive protection circuit output of described hardware and overvoltage fault-signal, and the upper brachium pontis fault-signal of described IPM power model output and lower brachium pontis fault-signal, generate down pulse locking signal, first block FPGA internal pulses, high-impedance state will be set to by the PWM start pulse signal of FPGA, then by the interrupt pin of described down pulse locking signal output to described DSP pulse blocking circuit and described PWM drive circuit, described FPGA protects circuit to be additionally operable to receive 6 road PWM start pulse signals of described DSP pulse blocking circuit output, and by 6 road PWM start pulse signal outputs to described PWM drive circuit；
Described DSP pulse blocking circuit, protects circuit to be connected with described FPGA, for 6 road PWM start pulse signals of output to described FPGA being set to high-impedance state after receiving described down pulse locking signal.
2. three grades of signal protection circuit of current transformer as claimed in claim 1, it is characterised in that the excessive protection circuit of described hardware includes:
The common cathode full bridge rectifier being made up of 6 diode 1N4148, is connected with DC voltage divider circuit, for the bipolar signal received is converted to direct current signal, and by described DC signal output to described DC voltage divider circuit；
Described DC voltage divider circuit, is connected with described common cathode full bridge rectifier, direct current signal input, voltage comparator respectively, for the direct current signal of input carries out dividing potential drop, and exports the voltage signal after dividing potential drop to described voltage comparator；
Described voltage comparator, it is connected with described DC voltage divider circuit and reference voltage threshold initialization circuit respectively, for the voltage ratio relatively threshold value exported according to described reference voltage threshold initialization circuit, voltage signal after dividing potential drop is compared, voltage threshold after dividing potential drop beyond described voltage ratio compared with the scope of threshold value, output overcurrent fault-signal or overvoltage fault-signal.
3. three grades of signal protection circuit of current transformer as claimed in claim 2, it is characterised in that described reference voltage threshold initialization circuit includes: upper voltage limit initialization circuit and lower voltage limit initialization circuit.
4. three grades of signal protection circuit of current transformer as claimed in claim 2, it is characterised in that the Zener diode that described reference voltage threshold initialization circuit adopts is ZMM10 Zener diode, and the potentiometer of employing is 3224W-1-103E potentiometer.
5. three grades of signal protection circuit of current transformer as claimed in claim 1; it is characterized in that; described PWM drive circuit includes: the first photoelectric conversion plate and the second photoelectric conversion plate, wherein, is connected by 8 optical fiber between described first photoelectric conversion plate with described second photoelectric conversion plate.
6. three grades of signal protection circuit of current transformer as claimed in claim 5, it is characterised in that described first photoelectric conversion plate includes: pwm pulse output signal driver circuit and the fault-signal of current transformer own process circuit, wherein:
Described pwm pulse output signal driver circuit includes the first analog line driver and the first fiber optic emitter that are sequentially connected in series; 6 road PWM start pulse signals and the 1 road down pulse locking signal of circuit output protected by described first analog line driver for receiving described FPGA, and drives described first fiber optic emitter by 6 road PWM start pulse signal outputs to described IPM power model；
The fault-signal of described current transformer own processes circuit and includes: locking signal change-over circuit, failure pulse signal receive circuit and fault-signal latches and warning circuit, wherein:
Described locking signal change-over circuit includes the second analog line driver and the second fiber optic emitter that are sequentially connected in series, and described second analog line driver protects 1 road down pulse locking signal of circuit output by described second fiber optic emitter output to described second photoelectric conversion plate for the described FPGA that will receive；
Described failure pulse signal receives circuit and includes the 3rd fiber optic receiver and single order RC wave filter; be converted to the signal of telecommunication for the upper brachium pontis fault-signal exported by described IPM power model and/or lower brachium pontis fault-signal, and the signal of telecommunication output being converted to is latched and warning circuit to described protection circuit and described fault-signal；
The input signal that described fault-signal latches with warning circuit includes: down pulse locking signal, upper brachium pontis fault-signal, lower brachium pontis fault-signal, for respectively upper brachium pontis fault-signal and lower brachium pontis fault-signal being negated once by six anti-phase Schmidt trigger 74LS14, down pulse locking signal is negated twice, wherein, negate the down pulse locking signal after twice to be connected with the negative electrode of LED alarm lamp, negate the upper brachium pontis fault-signal after once and lower brachium pontis fault-signal is separately input to the NAND gate chip 74LS00 D-latch constituted, and reset signal is connected with described D-latch, the signal latched is connected with LED alarm lamp respectively, and the upper brachium pontis fault-signal latched in described latch, lower brachium pontis fault-signal, down pulse locking signal through with door chip 74LS21 phase with after, input to buzzer control loop.
7. three grades of signal protection circuit of current transformer as claimed in claim 6, it is characterised in that described second photoelectric conversion plate includes: pwm pulse receives signal drive circuit and fault-signal radiating circuit, wherein:
Described pwm pulse receives signal drive circuit, for receiving 6 road PWM start pulse signals of described first photoelectric conversion plate output, and the 6 road PWM start pulse signal output extremely described IPM power models that will receive；
Described fault-signal radiating circuit, for by the upper brachium pontis fault-signal received from described fault-signal radiating circuit and/or lower brachium pontis fault-signal, output is described first photoelectric conversion plate extremely.
8. three grades of signal protection circuit of current transformer as claimed in claim 7; it is characterized in that; the model of the first fiber optic emitter, the second fiber optic emitter and the 3rd fiber optic emitter is HFBR1521, and the model of described first analog line driver and the second analog line driver is SN75451.
9. three grades of signal protection circuit of the current transformer as according to any one of claim 1 to 8, it is characterised in that the model of described IPM power model is PM150CLA120.
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| CN201410723107.9A CN105720560B (en) | 2014-12-03 | 2014-12-03 | Current transformer three-level signal protects circuit |
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| CN107482582A (en) * | 2017-10-09 | 2017-12-15 | 赵东顺 | A kind of guard method of motor circuit |
| CN107908129A (en) * | 2017-10-27 | 2018-04-13 | 上海交通大学 | DSP and the control method of FPGA/CPLD multidimensional interconnection |
| CN108256277A (en) * | 2018-03-13 | 2018-07-06 | 南京双启新能源科技有限公司 | A kind of Digital Simulation switch power amplifier |
| CN110350486A (en) * | 2019-07-19 | 2019-10-18 | 广东美的暖通设备有限公司 | Failure protecting device, frequency converter and motor driven systems |
| CN112230118A (en) * | 2020-10-20 | 2021-01-15 | 珠海格力电器股份有限公司 | Fault location device, method, apparatus, electronic device, and computer readable medium |
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| CN106329506A (en) * | 2016-11-07 | 2017-01-11 | 西安科技大学 | Over-voltage discharge protection device and method for server controller with adjustable protection threshold |
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| CN107908129B (en) * | 2017-10-27 | 2019-08-23 | 上海交通大学 | The control method of DSP and the interconnection of FPGA/CPLD multidimensional |
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| CN112230118A (en) * | 2020-10-20 | 2021-01-15 | 珠海格力电器股份有限公司 | Fault location device, method, apparatus, electronic device, and computer readable medium |
| CN112255524A (en) * | 2020-12-06 | 2021-01-22 | 中车永济电机有限公司 | Protection method and detection device for electric transmission traction system |
| CN112255524B (en) * | 2020-12-06 | 2024-02-06 | 中车永济电机有限公司 | Protection method and detection device for electric transmission traction system |
| CN112600171A (en) * | 2020-12-24 | 2021-04-02 | 中冶南方（武汉）自动化有限公司 | Fault locking circuit of frequency converter |
| US11513880B1 (en) * | 2021-08-26 | 2022-11-29 | Powerchip Semiconductor Manufacturing Corporation | Failure bit count circuit for memory and method thereof |
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