CN105719694B

CN105719694B - More program bits method and devices of nand memory

Info

Publication number: CN105719694B
Application number: CN201610046803.XA
Authority: CN
Inventors: 靳旭; 伍冬; 吴华强; 钱鹤; 曹堪宇; 朱一明
Original assignee: Tsinghua University; GigaDevice Semiconductor Beijing Inc
Current assignee: Zhaoyi Innovation Technology Group Co ltd; Tsinghua University
Priority date: 2016-01-22
Filing date: 2016-01-22
Publication date: 2019-12-03
Anticipated expiration: 2036-01-22
Also published as: CN105719694A

Abstract

Provide a kind of more program bits method and devices of nand memory.The described method includes: data latches group is written in programmed multi-bit data；The multi-bit data is converted into acceleration coding codeword from Gray code codeword；Determine that the storage unit for needing programmed target threshold voltage to be greater than predetermined voltage in storage array and target threshold voltage are not more than the storage unit of the predetermined voltage；Each storage unit that target threshold voltage is greater than the predetermined voltage is pre-programmed into intermediate state voltage；Programming verification operation is programmed and executed no more than each storage unit of the predetermined voltage to target threshold voltage, latch scan operation and confirmation scan operation；Programming verification operation is programmed and executed to each storage unit that target threshold voltage is greater than the predetermined voltage, latch scan operation and confirmation scan operation.The method is redesigned according to the structure of latch and is encoded, and reduces the quantity of redundant operation complicated in programming process, thus can accelerate the speed of programming, reduces power consumption.

Description

More program bits method and devices of nand memory

Technical field

The disclosure generally relates to a kind of more program bits method and device thereof of NAND (NAND gate) memory.

Background technique

Each storage unit of nand flash memory can store multi-bit data, i.e., each storage unit can store with accordingly The corresponding voltage class of more bits (bit) data.For example, each storage unit of nand flash memory can store the number of 4 bits According to that is, each storage unit storage 2⁴A voltage class in=16 voltage class.It is carried out in nand flash memory storage unit It when storage, needs to encode stored multi-bit data, and Gray code usually can be used in order to reduce error rate.In In Gray code, it is different that the adjacent code of any two only has a bit, and also only has between maximum number and minimum number One bit is different.However, in the programming process of NAND-flash memory, Gray code not adaptive circuit structure, because And the operation in cataloged procedure is made to become complicated cumbersome.For example, in realizing cataloged procedure, since there is no bases for Gray code The circuit structure of coding optimizes, so being directly programmed the operation that will lead to bulk redundancy using Gray's code table, increases Power consumption and programming time.Moreover, the increase of the bit number with the storage of each storage unit, is directly programmed using Gray code The operation in cataloged procedure will be made to become more complicated the cumbersome and more power consumptions of increase and programming time.

Summary of the invention

Embodiment of the disclosure provides a kind of more program bits method and devices of nand memory, can be in programming It is preceding that coding remaps, to optimize programming process.

At least one embodiment of the disclosure provides a kind of more program bits methods of nand memory, comprising: will be by Data latches group is written in the multi-bit data of programming, and the multi-bit data is Gray code codeword；By the multi-bit data Acceleration coding codeword is converted to from the Gray code codeword；Determine and need programmed storage unit in storage array, need by The storage unit of programming includes that target threshold voltage is not more than greater than the storage unit and target threshold voltage of predetermined voltage The storage unit of the predetermined voltage；Each storage unit that target threshold voltage is greater than the predetermined voltage is pre-programmed into Intermediate state voltage；Each storage unit to target threshold voltage no more than the predetermined voltage is programmed；To target threshold Threshold voltage be not more than the predetermined voltage each storage unit: execute programming verification operation, execute latch scan operation with And execute confirmation scan operation；Each storage unit for being greater than the predetermined voltage to target threshold voltage is programmed；With And it is greater than each storage unit of the predetermined voltage to target threshold voltage: executes programming verification operation, executes to latch and sweep It retouches operation and executes confirmation scan operation.

At least one embodiment of the disclosure additionally provides a kind of more program bits devices of nand memory, comprising: writes Enter module, for programmed multi-bit data to be written in data latches group, the multi-bit data is Gray code code Word；Transcoding module, for the multi-bit data to be converted to acceleration coding codeword from the Gray code codeword；Data are swept Module is retouched, needs programmed storage unit in storage array for determining, needing the programmed storage unit includes mesh Mark the storage unit that threshold voltage is not more than the predetermined voltage greater than the storage unit and target threshold voltage of predetermined voltage；In advance Programming and authentication module, the storage unit for target threshold voltage to be greater than the predetermined voltage are pre-programmed into intermediate state Voltage；Programming module, for being not more than the storage unit and target threshold of the predetermined voltage to target threshold voltage respectively Threshold voltage is greater than the storage unit of the predetermined voltage to be programmed；Authentication module is programmed, for respectively to target threshold Threshold voltage is greater than the described of the predetermined voltage no more than the storage unit and target threshold voltage of the predetermined voltage and deposits Storage unit executes programming verification operation；Scan module is latched, for being not more than the predetermined electricity to target threshold voltage respectively The storage unit and target threshold voltage of pressure are greater than the storage unit of the predetermined voltage to execute and latch scanning behaviour Make；And confirmation scan module, for respectively to target threshold voltage no more than the predetermined voltage the storage unit and Target threshold voltage is greater than the storage unit of the predetermined voltage to execute confirmation scan operation.

For example, the storage unit that target threshold voltage is greater than the predetermined voltage is to accelerate the highest order of coding codeword For 0 storage unit, target threshold voltage is to accelerate coding codeword most no more than the storage unit of the predetermined voltage The storage unit that a high position is 1.

For example, being not more than each storage unit of the predetermined voltage to target threshold voltage, programming authentication module is held Whether row programming verification operation includes: the first verifying voltage of selection, and verify and be incorporated into the voltage of each storage unit and reach To first verifying voltage.It is not more than each storage unit of the predetermined voltage to target threshold voltage, latches scanning Module, which executes and latches scan operation to include:, to be institute by the programming verifying and target threshold voltage of first verifying voltage The data latches group for stating the storage unit of the first verifying voltage is set as latch mode, and will not verify by described first The programming verifying of voltage and/or target threshold voltage are not the data latches groups of the storage unit of first verifying voltage State remains unchanged.It is not more than each storage unit of the predetermined voltage to target threshold voltage, confirmation scan module is held Row confirmation scan operation includes: the storage unit for data latches group for latch mode, is judged that latch is set as Success latch mode, and be not the storage unit of latch mode for data latches group, judged that latch is set as Latch unsuccessful state.

For example, latching scan module will be institute by the programming verifying and target threshold voltage of first verifying voltage The data latches group for stating the storage unit of the first verifying voltage is set as latch mode, and will not verify by described first The programming verifying of voltage and/or target threshold voltage are not the data latches groups of the storage unit of first verifying voltage State remains unchanged, comprising: detects the highest of the acceleration coding codeword of the corresponding data latches group storage of the storage unit Whether position is " 1 ", detect in the acceleration coding codeword of the storage unit corresponding data latches group storage the quantity of " 0 " and Whether position is corresponding with first verifying voltage to accelerate the quantity of " 0 " and position in coding codeword consistent, and detects Whether the corresponding voltage verification latch of the storage unit is to pass through state；If the corresponding data of the storage unit latch The highest order of the acceleration coding codeword of device group storage is " 1 ", the acceleration of the corresponding data latches group storage of the storage unit In coding codeword the quantity of " 0 " and position it is corresponding with first verifying voltage accelerate coding codeword in " 0 " quantity and position Set consistent, and the corresponding voltage verification latch of the storage unit is to be arranged corresponding with the storage unit by state Data latches group be latch mode；And if the acceleration of the corresponding data latches group storage of the storage unit encodes The highest order of code word is not in the acceleration coding codeword of " 1 " and/or the corresponding data latches group storage of the storage unit The quantity of " 0 " and position are inconsistent in the quantity of " 0 " and position acceleration coding codeword corresponding with first verifying voltage, And/or the corresponding voltage verification latch of the storage unit is to keep number corresponding with the storage unit not by state State according to latch group is constant.

For example, being greater than each storage unit of the predetermined voltage to target threshold voltage, programming authentication module is executed Whether programming verification operation includes: the second verifying voltage of selection, and verify and be incorporated into the voltage of each storage unit and reach Second verifying voltage, second verifying voltage are greater than the intermediate state voltage.Target threshold voltage is greater than described pre- Each storage unit of constant voltage, latching scan module and executing latch scan operation includes: that will verify electricity by described second The programming of pressure is verified and target threshold voltage is set as the data latches group of the storage unit of second verifying voltage Latch mode, and by the programming verifying and/or target threshold voltage not by second verifying voltage be not described second The state of the data latches group of the storage unit of verifying voltage remains unchanged.The predetermined voltage is greater than to target threshold voltage Each storage unit, confirmation scan module execute confirmation scan operation include: for data latches group be latch mode Storage unit, judged that latch is set as successfully latch mode, and be not latch mode for data latches group Storage unit, judged that latch is set as latching unsuccessful state.

For example, latching scan module will be institute by the programming verifying and target threshold voltage of second verifying voltage The data latches group for stating the storage unit of the second verifying voltage is set as latch mode, and will not verify by described second The programming verifying of voltage and/or target threshold voltage are not the data latches groups of the storage unit of second verifying voltage State remains unchanged, comprising: detects " 0 " in the acceleration coding codeword of the corresponding data latches group storage of the storage unit The quantity of " 0 " and position are consistent in quantity and position acceleration coding codeword whether corresponding with second verifying voltage, and And whether the corresponding voltage verification latch of the detection storage unit is to pass through state；If the corresponding number of the storage unit The quantity of " 0 " and position acceleration coding corresponding with second verifying voltage in the acceleration coding codeword of latch group storage The quantity of " 0 " and position are consistent in code word, and the corresponding voltage verification latch of the storage unit is by state, setting Data latches group corresponding with the storage unit is latch mode；And if the corresponding data of the storage unit latch In the acceleration coding codeword of device group storage in quantity and position the acceleration coding codeword corresponding with second verifying voltage of " 0 " The quantity of " 0 " and position is inconsistent and/or the corresponding voltage verification latch of the storage unit is to keep not by state The state of data latches group corresponding with the storage unit is constant.

For example, data scanning module, which determines, needs programmed storage unit in storage array, comprising: scan the data Latch group stores the data latches group that information is erase status and the data lock that storage information is not erase status to determine Storage group；It will be that the corresponding storage unit of the data latches group of erase status is set as not programming state with storage information； And will not be that the corresponding storage unit of the data latches group of erase status is set as programming state with storage information, In, needing the programmed storage unit is to be arranged to the storage unit of programming state.

At least one embodiment of the disclosure additionally provides a kind of storage medium, stores program on said storage Instruction, when described program instruction is run by computer or processor for executing the nand memory of embodiment of the disclosure More program bits methods, and for realizing more program bits devices of nand memory according to an embodiment of the present disclosure.

The more program bits method and devices for the nand memory that the embodiment of the present disclosure provides, according to the structure weight of latch New design coding, reduces the quantity of redundant operation complicated in programming process, thus can accelerate the speed of programming, reduces function Consumption.

Detailed description of the invention

Embodiment of the disclosure is described in more detail in conjunction with the accompanying drawings, the above-mentioned and other mesh of the disclosure , feature and advantage will be apparent.Attached drawing is used to provide to further understand the embodiment of the present disclosure, and constitutes A part of bright book is used to explain the disclosure together with embodiment of the disclosure, does not constitute the limitation to the disclosure.In attached drawing In, identical reference label typically represents same parts or step.

Fig. 1 is the schematic block diagram for the multiple bit unit storage array that the embodiment of the present disclosure provides；

Fig. 2 is the schematic block diagram for the sense amplifier that the embodiment of the present disclosure provides；

Fig. 3 is the exemplary structure for the latch that the embodiment of the present disclosure provides；

Fig. 4 is the schematic block diagram for the control circuit that the embodiment of the present disclosure provides；

Fig. 5 A is a kind of schematic flow chart of the more program bits methods for nand memory that the embodiment of the present disclosure provides One of；

Fig. 5 B and 5C are a kind of schematic stream of the more program bits methods for nand memory that the embodiment of the present disclosure provides The two of journey figure；

Fig. 6 A is one of a kind of programming verifying that the embodiment of the present disclosure provides and the schematic flow chart of method latched；

Fig. 6 B is the two of the schematic flow chart of a kind of programming verifying that the embodiment of the present disclosure provides and the method latched；

Fig. 6 C is the illustrative profiles for four bit unit threshold voltages that the embodiment of the present disclosure provides；

Fig. 6 D is the programming pulse for four bit datas that the embodiment of the present disclosure provides and the illustrative profiles of verifying voltage；

Fig. 7 A-7P is the illustrative programming process for four bit datas that the embodiment of the present disclosure provides；

Fig. 8 A-8H is the programming verifying of the acceleration coding for four bit data of one kind that the embodiment of the present disclosure provides and latches Method schematic flow chart；

Fig. 9 is that illustrative four bit that the embodiment of the present disclosure provides accelerates coding code table；And

Figure 10 is a kind of schematic block diagram of the more program bits devices for nand memory that the embodiment of the present disclosure provides.

Specific embodiment

In order to enable the purposes, technical schemes and advantages of the disclosure become apparent, root is described in detail below with reference to accompanying drawings According to the example embodiment of the disclosure.Obviously, described embodiment is only a part of this disclosure embodiment, rather than this public affairs The whole embodiments opened, it should be appreciated that the disclosure is not limited by example embodiment described herein.Based on described in the disclosure The embodiment of the present disclosure, those skilled in the art's obtained all other embodiment in the case where not making the creative labor It should all fall within the protection scope of the disclosure.

Embodiment of the disclosure provides a kind of more program bits method and devices of nand memory, can be in programming It is preceding that coding remaps, to optimize programming process.The more program bits for the nand memory that the embodiment of the present disclosure provides Method and device is redesigned according to the structure of latch and is encoded, multi-bit data is converted to accordingly from Gray code codeword Accelerate coding codeword, reduce the quantity of redundant operation complicated in programming process, thus the speed of programming can be accelerated, reduces Power consumption.The more program bits method and devices for the nand memory that the embodiment of the present disclosure provides, can be applied to be greater than or equal to The programming of two bits of data, for example, the programming of the multi-bit datas such as four bit datas, five bit datas and/or six bit datas.

In the embodiments of the present disclosure, nand memory can be two-dimentional nand memory, be also possible to three dimensional NAND storage Device, the disclosure do not limit this.Three dimensional NAND memory improves mistake of the plane nand memory in terms of more bit storages The problems such as narrow threshold value is distributed, serious floating gate couples, so that three dimensional NAND memory increases depositing for each storage unit Energy storage power is possibly realized.

Fig. 1 is a kind of schematic frame for system 100 including multiple bit unit storage array that the embodiment of the present disclosure provides Figure.As shown in Figure 1, system 100 may include peripheral circuit 101, line decoder 104, column decoder 106, storage array 108, Sense amplifier 110 and input/output interface 112.In some embodiments, system 100 also may include that other are not shown Component, for example, voltage-stablizer (voltage regulator), logic circuit (logic circuits) etc..

Peripheral circuit 101 is the circuit structure outside storage array 108.Peripheral circuit 101 may include control electricity Road 102.Control circuit 102 can control the address choice of storage array 108.For example, control circuit 102 can control capable decoding Device 104, so that line decoder 104 selects the row address of storage array 108 by wordline 114；Control circuit 102 can also be controlled Column decoder 106 processed, so that column decoder 106 selects the column address of storage array by bit line 116.Control circuit 102 is also It can control the programming process of storage array 108.For example, as described below, control circuit 102 can control Fig. 5 A method 500, The method 550 of Fig. 5 B and 5C, the method 600 of Fig. 6 A, the method 800 and 8000 of the method 630 of Fig. 6 B and Fig. 8 A-8H are held Row.

Referring to fig. 4, control circuit 102 may include processor 402, memory 404 and other unshowned components.Control It can directly or indirectly be communicated with each other between each component of circuit 102 processed, for example, each component of control circuit 102 can be mutual Mutually send and receive data and/or signal.In another example can be connected by bus between each component of control circuit 102.One In a little embodiments, control circuit 102 may include one or more processors 402 and one or more memories 404.

Processor 402 can handle data-signal, may include various calculating structures, such as Complex Instruction Set Computer (CISC) structure, structure Reduced Instruction Set Computer (RISC) structure or a kind of structure for carrying out a variety of instruction set combinations.In In some embodiments, processor 402 is also possible to microprocessor, such as X 86 processor or arm processor, or can be number Word processing device (DSP) etc..Processor 402 can control other components in control circuit 102 to execute desired function.

Memory 404 can save the instruction and/or data of the execution of processor 402.For example, memory 404 may include One or more computer program products, the computer program product may include various forms of computer-readable storage mediums Matter, such as volatile memory and/or nonvolatile memory.The volatile memory for example may include that arbitrary access is deposited Reservoir (RAM) and/or cache memory (cache) etc..The nonvolatile memory for example may include read-only storage Device (ROM), hard disk, flash memory etc..It can store one or more computer programs on the computer readable storage medium to refer to It enables, processor 402 can run described program instruction, to realize in the embodiment of the present disclosure described below and (be realized by processor) More program bits functions and/or other desired functions.It can also be stored in the computer readable storage medium Various application programs and various data, such as application program use and/or the various data generated etc..

Referring to Fig. 1, storage array 108 voltage status can be used determine storage multi-bit data size.For example, Each storage unit of storage array 108 can store a multi-bit data, i.e., each storage unit can store more with this The corresponding voltage class of bit data.In another example Fig. 6 C shows the threshold voltage V of four bit memory cells_thDistribution map 655 comprising erase status (erase, ER) and L1-L15 totally 2⁴=16 voltage class.According to stored multi-bit According to numerical values recited, each storage unit can store one in voltage class.

Input/output interface 112 can provide input data to sense amplifier 110 and (need to be programmed into for example, providing The multi-bit data of storage array 108), and the output data of sense amplifier 110 is received (for example, receiving from storage array The data read in 108).Input/output interface 112 can be universal serial bus (universal serial bus, USB) Interface, thunder and lightning (thunderbolt) interface or other feasible interface types, the disclosure are not construed as limiting this.In some implementations In example, input/output interface 112 can also be used as a component of peripheral circuit 101.

In some embodiments, the threshold of the current value and the storage unit that are stored in the storage unit of storage array 108 Threshold voltage grade is corresponding, the current value that sense amplifier 110 can store the storage unit be converted to digital numerical value (for example, Multi-bit value).Sense amplifier 110 can be connected with one or more bit lines 116.

Fig. 2 shows the exemplary block diagrams 200 of sense amplifier 110.Sense amplifier 110 may include buffer lock Storage 202, data latches group 203, sensor circuit 214 and induction latch 216.Each component of sense amplifier 110 can To be connected with each other by bus 218.In some embodiments, the data of each data latches group 203 in sense amplifier 110 The number of latch is identical as the bit number for the numerical value that each storage unit stores；Alternatively, each data in sense amplifier 110 The number of data latches in latch group 203 is greater than the bit number of the numerical value of each storage unit storage.For example, storage battle array Each storage unit of column 108 can store the numerical value of four bits, and each data latches group 203 of sense amplifier 110 at least may be used To include four data latches, i.e., the first data latches 204 as shown in Figure 2, the second data latches 206, third number According to latch 208 and the 4th latch 210.Alternatively, each data latches group 203 of sense amplifier 110 can also include Other data latches, for example, ephemeral data latch 212 as shown in phantom in Figure 2.As shown in Fig. 2, sense amplifier The bus of 110 each latch links together.

In some embodiments, it is that unit is programmed that storage array 108, which is with " row ",；That is, by row to storage array 108 storage unit is programmed, and in the programming of every row, with a line the storage unit of programming in need will simultaneously It is programmed.Therefore, number including the induction latch 216 in sense amplifier 110 with include the one of storage array 108 The number of storage unit in row is identical；That is, respectively each storage unit in induction latch 216 and a line is one-to-one closes System.In addition, include the data latches group 203 in sense amplifier 110 number also with include in storage array 108 one The number of storage unit in row is identical；That is, each data latches group 203 and each storage unit in a line are one-to-one Relationship.

Fig. 3 shows the exemplary circuit diagram of latch 300.In the latch 300 of Fig. 3, " X " represents latch 300 The data of storage, " INVX " represent the anti-of the data of storage, and " SETX " represents storing data set signal, and " RETX " representative is deposited Data reset signal is stored up, VDD represents supply voltage, and READ represents read signal and " BUS " represents bus.Buffer lock in Fig. 2 Storage 202, sensitive latch 216, the first data latches 204, the second data latches 206, third data latches 208, The structure of 4th latch 210 and interim latch 212 can be same or similar with the structure of latch 300, herein not It repeats again.

Fig. 5 A is a kind of schematic flow of the more program bits methods 500 for nand memory that the embodiment of the present disclosure provides One of figure.In some embodiments, method 500 may include shown in Fig. 5 A some or all the step of.Certainly, method 500 It also may include the step of other do not show in fig. 5.In the following description, the sense amplifier 110 of Fig. 2 will be combined Method 500 is described in detail in structure.

Firstly, programmed multi-bit data is written in data latches group in step S502, wherein described more Bit data is Gray code codeword.In some embodiments, when the line storage unit to storage array 108 is programmed, By programmed each multi-bit data be respectively written into in the one-to-one data latches group 203 of the storage unit of the row. For example, then caching latches by input/output interface 112 by programmed each multi-bit data write-in caching latch 202 Programmed each multi-bit data is respectively written into corresponding each data latches group 203 by device 202.

In step S504, the multi-bit data is converted into acceleration coding codeword from Gray code codeword.In some implementations In example, before executing step S504, it can establish the Gray code code table of multi-bit data, accelerate coding code table and the lattice Thunder code code table and the transformational relation for accelerating coding code table.For example, Gray code conversion is that the process of coding is accelerated to can satisfy Three condition (1)-(3) below:

(1) keep the highest invariant position of each Gray code codeword (for example, being the Gray code codeword of " 1 ", phase for highest order The highest order for the acceleration coding codeword answered still is " 1 "；It is the Gray code codeword of " 0 " for highest order, it is corresponding to accelerate coding The highest order of code word is still " 0 ")；

(2) it is the code word of " 1 " for highest order: code word is re-started into arrangement according to the quantity of " 0 ", with comprising more The code word of " 0 " indicates the lower voltage class (that is, being the code word of " 1 ", low-voltage-grade corresponding accelerations volume for highest order The number of " 0 " that includes in code code word is no less than the number of corresponding " 0 " for accelerating to include in coding codeword of voltage levels)； And for the voltage class including equal " 0 " number, by converting Gray code codeword corresponding with the voltage class most A small number of purpose data latches come obtain the voltage class acceleration coding codeword (that is, highest order be " 1 " code word in, For containing " 0 " voltage class equal in number, during being to accelerate coding from Gray code conversion, make to need to become as far as possible The number of the data latches of change is minimum)；And

(3) similarly, it is the code word of " 0 " for highest order: code word is re-started into arrangement according to the quantity of " 0 ", with packet (that is, being the code word of " 0 " for highest order, low-voltage-grade is corresponding to indicate lower voltage class for code word containing more " 0 " The number of " 0 " that includes in coding codeword is accelerated to be no less than corresponding " 0 " for accelerating to include in coding codeword of voltage levels Number)；And for the voltage class including equal " 0 " number, by converting Gray code code corresponding with the voltage class The data latches of the minimal number of word come obtain the voltage class acceleration coding codeword (that is, highest order be " 0 " code In word, for containing " 0 " voltage class equal in number, during being to accelerate coding from Gray code conversion, make as far as possible The number for the data latches for needing to change is minimum).

According to Gray code code table and the transformational relation of coding code table is accelerated described can mostly to compare each in step S504 Special data are converted to corresponding acceleration coding codeword from Gray code codeword.

For example, Fig. 9 shows the Gray code code table 900 of four bit datas, accelerates coding code table 950 and the Gray code Code table 900 and the transformational relation for accelerating coding code table 950.Filling shade partially illustrates when Gray code code table in Fig. 9 900 be converted to acceleration coding code table 950 when, the numerical value for the data latches for needing to change.For example, the Gray code of voltage class L1 Code word " 1110 ", which corresponds to, accelerates coding codeword " 1000 "；When corresponding four bit data of voltage class L1 from Gray code codeword When " 1110 " are converted to acceleration coding codeword " 1000 ", " 1 " of the first data latches 204 storage is remained unchanged, the 4th data " 0 " that latch 210 stores remains unchanged, and " 1 " that stores the second data latches 206 is needed to become " 0 ", and by third " 1 " that data latches 208 store becomes " 0 ".It should be noted that coding code table 950 is accelerated only to meet above-mentioned condition (1) the exemplary acceleration in-(3) encodes code table, and other similar acceleration coding code table also can satisfy condition (1)-(3), this public affairs It opens and this is not construed as limiting.

In some embodiments, the acceleration coding encodes multiple voltage class, wherein first part's voltage etc. The highest order of the acceleration coding codeword of grade is that the highest order of the acceleration coding codeword of " 0 " and second part voltage class is " 1 ", first part's voltage class are all larger than the second part voltage class.For first part's voltage class: (1) the corresponding number for accelerating " 0 " that includes in coding codeword of low-voltage-grade is no less than the corresponding acceleration of voltage levels and compiles The number of " 0 " that includes in code code word；And (2) pass through conversion and the electricity for the voltage class including equal " 0 " number The data latches of the minimal number of the corresponding Gray code codeword of grade are pressed to obtain the acceleration coding codeword of the voltage class. Similarly, for the second part voltage class: (1) corresponding " 0 " for accelerating to include in coding codeword of low-voltage-grade Number is no less than the number of corresponding " 0 " for accelerating to include in coding codeword of voltage levels；And (2) for include it is equal The voltage class of " 0 " number is latched by converting the data of minimal number of Gray code codeword corresponding with the voltage class Device obtains the acceleration coding codeword of the voltage class.

It in step S506, determines and needs programmed storage unit in storage array, wherein deposited described in needs are programmed Storage unit includes: the storage unit that target threshold voltage is greater than predetermined voltage；And target threshold voltage is predetermined no more than described The storage unit of voltage.The predetermined voltage can be preset voltage.For example, the predetermined voltage can be single by storage Member is divided into high voltage memory cell group and low-voltage memory cell group.When the target threshold voltage of storage unit is greater than described make a reservation for When voltage, the storage unit is by cut-in high voltage memory cell group；When the target threshold voltage of storage unit is no more than described When predetermined voltage, the storage unit is by cut-in low-voltage memory cell group.Acceleration corresponding to low-voltage memory cell group is compiled The code word of code is the code word that highest order is " 1 "；The code word of acceleration coding is that highest order is corresponding to high voltage memory cell group The code word of " 0 ".For example, with reference to Fig. 9, the storage unit that target threshold voltage is greater than predetermined voltage includes that target threshold voltage is Each storage unit of L8-L15, the corresponding highest order for accelerating coding codeword is " 0 "；Target threshold voltage is no more than predetermined The storage unit of voltage includes each storage unit that target threshold voltage is L1-L7, the corresponding highest for accelerating coding codeword Position is " 1 ".

In some embodiments, when executing step S506, the data latches group is scanned first to determine storage letter It ceases the data latches group for erasing (erase) state and stores the data latches group that information is not erase status.For example, working as When the information of data latches group storage is " 1111 ", the information of data latches group storage is the information of erase status；When When the information of data latches group storage is not " 1111 ", the information of data latches group storage is not the letter of erase status Breath.

It then, is the data latches group of erase status for storage information, it will be corresponding with the data latches group Storage unit is set as not programming state；It is not the data latches group of erase status for storage information, it will be with the data The corresponding storage unit of latch group is set as programming state.That is, when the information of data latches group storage is " 1111 ", no The corresponding storage unit of data latches group is programmed；When the information of data latches group storage is not " 1111 ", The corresponding storage unit of data latches group can be programmed.For example, it is desired to which programmed storage unit can be quilt It is set as the storage unit of programming state, not needing programmed storage unit can be to be arranged to the storage of not programming state Unit.

Then, according to the respective target threshold voltage of the storage unit in programming state, programming state will be in Storage unit is divided into the storage unit (that is, high voltage memory cell group) and targets threshold that target threshold voltage is greater than predetermined voltage Voltage is not more than the storage unit (that is, low-voltage memory cell group) of predetermined voltage.

In step S508, to needing programmed target threshold voltage to be greater than the predetermined voltage in storage array 108 Each storage unit is pre-programmed into intermediate state voltage.For example, when the line storage unit to storage array 108 is programmed, it can It is grounded with the channel drain terminal for each storage unit that programmed and target threshold voltage will be needed to be greater than the predetermined voltage, and The storage unit for not needing programming and target threshold voltage are connect no more than the channel drain terminal of the storage unit of the predetermined voltage Supply voltage.In some embodiments, the intermediate state voltage (L_temp) it is not more than the minimum target of high voltage memory cell group Threshold voltage.For example, with reference to Fig. 9, high voltage memory cell group includes each storage unit that target threshold voltage is L8-L15, institute The minimum target threshold voltage for stating high voltage memory cell group is L8, so intermediate state voltage L_temp≤L8。

In some embodiments, can be used standard or off-gauge incremental steps pulse program (ISPP) sequence or its He is programmed the storage unit of storage array 108 programmed sequence.In order to enable target threshold voltage is greater than the predetermined electricity The voltage of each storage unit of pressure is programmed into intermediate state voltage, and multiple programming pulses can be used and be greater than to target threshold voltage Each storage unit of the predetermined voltage is repeatedly programmed, and is verified after each programming.For example, step S508 can be with Include:

(1) pre-programmed is carried out using each storage unit that programming pulse is greater than the predetermined voltage to target threshold voltage (for example, to accelerating the storage unit that coding codeword highest order is " 0 " to carry out pre-programmed)；

(2) verify programmed and target threshold voltage be greater than the predetermined voltage each storage unit voltage whether Intermediate state voltage is had reached (for example, verifying is programmed and accelerates coding codeword highest order for the voltage of the storage unit of " 0 " Whether intermediate state voltage is had reached)；

(3) for having reached the acceleration coding codeword highest order of intermediate state voltage as the storage unit of " 0 ", stop to it Carry out pre-programmed；And the acceleration coding codeword highest order for intermediate state voltage has not yet been reached is the storage unit of " 0 ", returns to behaviour Make (1) to continue to carry out pre-programmed to it and operate (2) to continue to verify, until each storage unit reaches intermediate state electricity Pressure.

For example, with reference to 680 parts of Fig. 6 D, programming pulse PGM is being used_1,nTarget threshold voltage is greater than described predetermined After each storage unit of voltage is programmed, verifying voltage VFY can be used_TempIt is verified (for example, verifying voltage VFY_Temp Equal to intermediate state voltage).Target threshold voltage for having reached intermediate state voltage is greater than the storage list of the predetermined voltage Member, stopping carry out pre-programmed to it；And the target threshold voltage for intermediate state voltage has not yet been reached is greater than the predetermined voltage Storage unit, use next programming pulse PGM_1,n+1Each storage unit is programmed, verifying voltage is then used VFY_TempVerified, and so on repetitive operation, until target threshold voltage be greater than the predetermined voltage each storage unit Reach intermediate state voltage.

It is predetermined no more than described to programmed and target threshold voltage is needed in storage array 108 in step S509 Each storage unit of voltage is programmed.For example, can be incited somebody to action when the line storage unit to storage array 108 is programmed Programmed and target threshold voltage is needed to be grounded no more than the channel drain terminal of each storage unit of the predetermined voltage, and incite somebody to action The channel drain terminal for each storage unit that the storage unit and target threshold voltage for not needing programming are greater than the predetermined voltage connects Supply voltage.In some embodiments, it is desirable to which programmed and target threshold voltage is not more than the storage of the predetermined voltage Unit is to need highest order that is programmed and accelerating coding codeword for the storage unit of " 1 ".

In some embodiments, can be used standard or off-gauge incremental steps pulse program (ISPP) sequence or its His programmed sequence is to needing programmed and target threshold voltage respectively depositing no more than the predetermined voltage in storage array 108 Storage unit is programmed.After the programming of each step, as shown in following step S510 and S512, one or more can be used Scan operation is verified and latched to a verifying voltage to execute programming.It will need to program by the programming pulse voltage of stairstepping The voltage of storage unit be moved to target threshold voltage from erase status, the number of the programming pulse needed and the programming of every step Depending on the specific programming situation of the foundation of verifying voltage number later.After each programming pulse applies, require using testing Card voltage currently programs the target whether voltage of storage unit has successfully been successfully moved to the storage unit to verify Threshold voltage.If the voltage of the storage unit has successfully been moved to target threshold voltage (the i.e. programming of the storage unit Success), then it needs data latches group corresponding with the storage unit latching (as shown in following step S512), and carry out Corresponding label (as shown in following step S514), to prevent the storage unit to be programmed again.

For example, with reference to 682 parts of Fig. 6 D, to needing programmed and target threshold voltage not in storage array 108 It is programmed greater than each storage unit of the predetermined voltage (that is, being " 1 " to programmed acceleration coding codeword highest order is needed Each storage unit be programmed).After each programming pulse of four bit datas, multiple verifying voltages can be used and carry out Verifying, and have corresponding latch operation after using the verifying of each verifying voltage.For example, using programming pulse PGM_2,n After being programmed, it can be verified first using verifying voltage VFY1 and carry out latch operation 671, then use verifying voltage VFY2 is verified and is carried out latch operation 672, then respectively using verifying voltage VFY2, VFY3, VFY4, VFY5, VFY6 with And VFY7 is verified and is carried out corresponding latch operation.If there is storage unit not yet reaches target threshold voltage, can make With next programming pulse PGM_2,n+1It is programmed next time and carries out corresponding verification operation and latch operation.

In step S510, each storage unit of the predetermined voltage is not more than to target threshold voltage, executes programming Verification operation.For example, can choose verifying voltage in step S510, and verifies and be incorporated into target threshold voltage no more than institute Whether the voltage for stating each storage unit of predetermined voltage reaches the verifying voltage.The verifying electricity is had reached for voltage Corresponding voltage verification latch can be labeled as passing through state by the storage unit of pressure；Institute is had not yet been reached for voltage The storage unit of verifying voltage is stated, corresponding voltage verification latch can be labeled as not passing through state.The storage list First corresponding induction latch 216 or ephemeral data latch 212 corresponding with the storage unit can be used as the storage The voltage verification latch of unit come using.

In step 512, each storage unit of the predetermined voltage is not more than to target threshold voltage, executes to latch and sweep Retouch operation.For example, by the storage by the programming verifying and target threshold voltage of the verifying voltage for the verifying voltage The data latches group of unit is set as latch mode；And the storage unit and/or targets threshold of programming verifying will not passed through Voltage is not that the state of the data latches group of the storage unit of the verifying voltage remains unchanged.

In some embodiments, in step S512, it can detecte the corresponding data latches group storage of the storage unit The highest order of acceleration coding codeword whether be " 1 ", detect the acceleration of the corresponding data latches group storage of the storage unit In coding codeword the quantity of " 0 " and position it is whether corresponding with the verifying voltage accelerate coding codeword in " 0 " quantity and position It sets consistent, and detects whether corresponding with storage unit voltage verification latch is to pass through state.If described deposit The highest order of the acceleration coding codeword of storage unit corresponding data latches group storage is " 1 ", the corresponding number of the storage unit Quantity and position the acceleration coding codeword corresponding with the verifying voltage of " 0 " in the acceleration coding codeword of latch group storage In " 0 " quantity and position it is consistent, and the corresponding voltage verification latch of the storage unit be pass through state, setting and institute Stating the corresponding data latches group of storage unit is latch mode.However, if the corresponding data latches of the storage unit The highest order of the acceleration coding codeword of group storage is not that " 1 " and/or the corresponding data latches group of the storage unit store Accelerate coding codeword in " 0 " quantity and position it is corresponding with the verifying voltage acceleration coding codeword in " 0 " quantity and position Setting the corresponding voltage verification latch of the inconsistent and/or described storage unit is to keep the storage unit pair not by state The state for the data latches group answered is constant.

For example, when the corresponding voltage verification latch of the storage unit is not pass through state, the voltage verification lock The value of storage is " 1 "；When the voltage verification latch is to pass through state, the value of the voltage verification latch is " 0 ".On State operation " whether the highest order for detecting the acceleration coding codeword of the storage unit corresponding data latches group storage is ' 1 ', Detect in the acceleration coding codeword of the storage unit corresponding data latches group storage ' 0 ' quantity and position whether with institute It is consistent to state ' 0 ' quantity and position in the corresponding acceleration coding codeword of the first verifying voltage, and detects the storage unit Whether corresponding voltage verification latch is to pass through state " it may include: to charge to bus, draw high label latch；It is right Bus charges, read the storage unit and the acceleration highest order of coding codeword with the verifying voltage it is opposite The value for the data latches answered, and draw high the label latch；Read the storage unit and with the verifying electricity The value of the corresponding data latches in position of " 0 " in the acceleration coding codeword of pressure reads the label latch, and reads The value of voltage verification latch corresponding with the storage unit；It draws high in the acceleration coding codeword with the verifying voltage " 0 " The corresponding data latches in position.If data corresponding with the acceleration highest order of coding codeword of the verifying voltage The value of latch is " 1 ", and data latches corresponding with the position of " 0 " in the acceleration coding codeword of the verifying voltage Value and the value of the voltage verification latch be " 0 ", data latches group corresponding with the storage unit is set For latch mode；If the value of data latches corresponding with the acceleration highest order of coding codeword of the verifying voltage is not " 1 ", and/or value and/or the institute of data latches corresponding with the position of " 0 " in the acceleration coding codeword of the verifying voltage Stating at least one in the value of voltage verification latch is not " 0 ", the state of data latches group corresponding with the storage unit It remains unchanged.Ephemeral data latch 212 corresponding with the storage unit can be used as the label latch come using.

In step S514, each storage unit of the predetermined voltage is not more than to target threshold voltage, executes confirmation Scan operation.For example, being latched as the storage unit of latch mode for data latches group, sentencing for the storage unit is set Disconnected latch is to latch success status, to prevent the storage unit from continuing to program；Data latches group is not locked The storage unit for saving as latch mode, the storage unit is arranged judges latch to latch unsuccessful state.It is deposited with described The corresponding induction latch 216 of storage unit or ephemeral data latch 212 corresponding with the storage unit can be used as institute State judge latch come using.

In step S515, to needing programmed and target threshold voltage to be greater than the predetermined electricity in storage array 108 Each storage unit of pressure is programmed.It, can need to for example, when the line storage unit to storage array 108 is programmed Channel drain terminal ground connection of the programmed and target threshold voltage greater than each storage unit of the predetermined voltage is wanted, and will be not required to The storage unit and target threshold voltage to be programmed connect electricity no more than the channel drain terminal of each storage unit of the predetermined voltage Source voltage.In some embodiments, it is desirable to which programmed and target threshold voltage is greater than the storage unit of the predetermined voltage It is the storage unit of " 0 " to need highest order that is programmed and accelerating coding codeword.

In some embodiments, can be used standard or off-gauge incremental steps pulse program (ISPP) sequence or its Each storage of his programmed sequence to needing programmed and target threshold voltage to be greater than the predetermined voltage in storage array 108 Unit is programmed.After the programming of each step, as shown in following step S516 and S518, one or more can be used Scan operation is verified and latched to verifying voltage to execute programming.Needs are programmed by the programming pulse voltage of stairstepping The voltage of storage unit is moved to target threshold voltage from erase status, and the number of the programming pulse needed and every step program it Depending on the specific programming situation of the foundation of verifying voltage number afterwards.After each programming pulse applies, require using verifying Voltage currently programs the target the threshold whether voltage of storage unit has successfully been successfully moved to the storage unit to verify Threshold voltage.If the voltage of the storage unit has successfully been moved to target threshold voltage, (i.e. the storage unit is programmed to Function), then it needs data latches group corresponding with the storage unit latching (as shown in following step S518), and carry out phase The label (as shown in following step S520) answered, to prevent the storage unit to be programmed again.

For example, with reference to 684 parts of Fig. 6 D, to needing programmed and target threshold voltage big in storage array 108 It is programmed in each storage unit of the predetermined voltage (that is, being " 0 " to programmed acceleration coding codeword highest order is needed Each storage unit is programmed).After each programming pulse of four bit datas, multiple verifying voltages can be used and tested Card, and have corresponding latch operation after using the verifying of each verifying voltage.For example, using programming pulse PGM_3,nInto After row programming, it can be verified first using verifying voltage VFY8 and carry out latch operation, then use verifying voltage VFY9 Verified and carry out latch operation, then respectively using verifying voltage VFY10, VFY11, VFY12, VFY13, VFY14 and VFY15 is verified and is carried out corresponding latch operation.If there is storage unit not yet reaches target threshold voltage, can be used Next programming pulse PGM_3,n+1It is programmed next time and carries out corresponding verification operation and latch operation.

In step S516, each storage unit of the predetermined voltage is greater than to target threshold voltage, programming is executed and tests Card operation.For example, can choose verifying voltage in step S516, and verifies and be incorporated into target threshold voltage greater than described pre- Whether the voltage of each storage unit of constant voltage reaches the verifying voltage.The verifying voltage is had reached for voltage Corresponding voltage verification latch can be labeled as passing through state by storage unit；Described test is had not yet been reached for voltage The storage unit of voltage is demonstrate,proved, corresponding voltage verification latch can be labeled as not passing through state.With the storage unit Corresponding induction latch 216 or ephemeral data latch 212 corresponding with the storage unit can be used as the storage list Member voltage verification latch come using.

It will be the verifying voltage by the programming verifying of the verifying voltage and target threshold voltage in step 518 The data latches group of storage unit be set as latch mode；And the storage unit and/or mesh of programming verifying will not passed through Mark threshold voltage is not that the state of the data latches group of the storage unit of the verifying voltage remains unchanged.

In some embodiments, in step S518, it can detecte the corresponding data latches group storage of the storage unit Acceleration coding codeword in " 0 " quantity and position it is whether corresponding with the verifying voltage accelerate coding codeword in " 0 " number Amount is consistent with position, and detects whether voltage verification latch corresponding with the storage unit is to pass through state.If The quantity of " 0 " and position and the verifying are electric in the acceleration coding codeword of the corresponding data latches group storage of the storage unit Press the quantity of " 0 " and position in corresponding acceleration coding codeword consistent, and the corresponding voltage verification of the storage unit latches Device is by state, and it is latch mode that data latches group corresponding with the storage unit, which is arranged,.However, if the storage The quantity of " 0 " and position are corresponding with the verifying voltage in the acceleration coding codeword of the corresponding data latches group storage of unit Accelerate the quantity of " 0 " in coding codeword and position is inconsistent and/or the corresponding voltage verification latch of the storage unit is not By state, keep the state of the corresponding data latches group of the storage unit constant.

For example, when the corresponding voltage verification latch of the storage unit is not pass through state, the voltage verification lock The value of storage is " 1 "；When the voltage verification latch is to pass through state, the value of the voltage verification latch is " 0 ".Example Such as, aforesaid operations " detect in the acceleration coding codeword of the storage unit corresponding data latches group storage ' 0 ' quantity and Whether position is corresponding with first verifying voltage to accelerate ' 0 ' quantity and position in coding codeword consistent, and detects Whether the corresponding voltage verification latch of the storage unit is to pass through state " it may include: to charge to bus；Read institute State storage unit and the acceleration coding codeword with the verifying voltage in the position of " 0 " corresponding data latches Value, and read the value of voltage verification latch corresponding with the storage unit；It draws high and is compiled with the acceleration of the verifying voltage The corresponding data latches in position of " 0 " in code code word.If the position of " 0 " in the acceleration coding codeword of the verifying voltage The value of the value and the voltage verification latch of setting corresponding data latches is " 0 ", corresponding with the storage unit Data latches group be arranged to latch mode；If the position phase of " 0 " in the acceleration coding codeword of the verifying voltage At least one in the value of corresponding data latches and/or the value of the voltage verification latch is not " 0 ", single with the storage The state of the corresponding data latches group of member remains unchanged.

In another example aforesaid operations " detect the acceleration coding codeword of the corresponding data latches group storage of the storage unit In ' 0 ' quantity and position it is whether corresponding with first verifying voltage accelerate coding codeword in ' 0 ' quantity and position phase Unanimously, and detect whether the corresponding voltage verification latch of the storage unit is to pass through state " may include: to bus into Row charging, draws high label latch；Read the storage unit and the acceleration coding codeword with the verifying voltage in The value of the corresponding data latches in the position of " 0 " reads the label latch, and reads corresponding with the storage unit Voltage verification latch value；Draw high the corresponding data in the position of " 0 " in the acceleration coding codeword with the verifying voltage Latch.If the value of data latches corresponding with the position of " 0 " in the acceleration coding codeword of the verifying voltage, described The value of the value and the voltage verification latch that mark latch is " 0 ", and data corresponding with the storage unit latch Device group is arranged to latch mode；If data corresponding with the position of " 0 " in the acceleration coding codeword of the verifying voltage The value of latch, and/or it is described label latch value, and/or the voltage verification latch value at least one be not The state of " 0 ", data latches group corresponding with the storage unit remains unchanged.Nonce corresponding with the storage unit It can be used as the label latch according to latch 212 to come using induction latch 216 corresponding with the storage unit can be used as The voltage verification latch come using.

In step S520, each storage unit of the predetermined voltage is greater than to target threshold voltage, confirmation is executed and sweeps Retouch operation.For example, being latched as the storage unit of latch mode for data latches group, the judgement of the storage unit is set Latch is to latch success status, to prevent the storage unit from continuing to program；Data latches group is not latched For the storage unit of latch mode, the storage unit is arranged judges latch to latch unsuccessful state.With the storage The corresponding induction latch 216 of unit or ephemeral data latch 212 corresponding with the storage unit can be used as described Judge latch come using.

Fig. 5 B-5C is a kind of the schematic of the more program bits methods 550 for nand memory that the embodiment of the present disclosure provides The two of flow chart.In some embodiments, method 550 may include shown in Fig. 5 B and 5C some or all the step of.Certainly, Method 550 also may include other not steps shown in Fig. 5 B and 5C.It in the following description, will be in conjunction with the sensitive of Fig. 2 Method 550 is described in detail in the structure of amplifier 110.

Firstly, programmed multi-bit data is written in data latches group in step S552, wherein described more Bit data is Gray code codeword.In some embodiments, operation similar with the step S502 of Fig. 5 A can be executed to realize Step S552.

In step 554, pre-processes the multi-bit and be accordingly converted to each multi-bit data from Gray code codeword Accelerate coding codeword.In some embodiments, operation similar with the step S504 of Fig. 5 A can be executed to realize step S554.

In step S556, the data latches group is scanned to determine that storage information is to wipe the data of (erase) state Latch group and storage information are not the data latches groups of erase status.For example, when the information of data latches group storage is When " 1111 ", the information of data latches group storage is the information of erase status；When data latches group storage information not When being " 1111 ", the information of data latches group storage is not the information of erase status.

It is the data latches group of erase status for storage information in step S558, it will be with the data latches group Corresponding storage unit is set as not programming state；It is not the data latches group of erase status for storage information, it will be with institute It states the corresponding storage unit of data latches group and is set as programming state.That is, when the information of data latches group storage is When " 1111 ", which is not programmed；When data latches group storage information not When being " 1111 ", which can be programmed.

In step S559, to needing programmed and target threshold voltage to be greater than predetermined voltage in storage array 108 Each storage unit is pre-programmed into intermediate state voltage.In some embodiments, behaviour similar with the step S508 of Fig. 5 A can be executed Make to realize step S559.

It is predetermined no more than described to programmed and target threshold voltage is needed in storage array 108 in step S560 Each storage unit of voltage is programmed.In some embodiments, operation similar with the step S509 of Fig. 5 A can be executed to come Realize step S560.

In step 562, each storage unit of the predetermined voltage is not more than to target threshold voltage, programming is executed and tests Card operation.For example, selection verifying voltage, and verifies and be incorporated into the voltage of each storage unit whether to reach the verifying electric Pressure.In some embodiments, operation similar with the step S510 of Fig. 5 A can be executed to realize step S562.

In step 564, each storage unit of the predetermined voltage is not more than to target threshold voltage, executes to latch and sweep Retouch operation.For example, by the storage by the programming verifying and target threshold voltage of the verifying voltage for the verifying voltage The data latches group of unit is set as latch mode.In some embodiments, it can execute similar to the step S512 of Fig. 5 A Operation realize step S564.

In step S566, each storage unit of the predetermined voltage is not more than to target threshold voltage, executes confirmation Scan operation.For example, being latched as the storage unit of latch mode for data latches group, sentencing for the storage unit is set Disconnected latch is to latch success status；It is not latched as the storage unit of latch mode for data latches group, institute is set That states storage unit judges latch to latch unsuccessful state.In some embodiments, the step of can executing with Fig. 5 A The similar operation of S514 is to realize step S566.

In step S568, it is determined whether choose next verifying voltage to be programmed verifying.For example, if all tests It is equal no more than the voltage of the storage unit of predetermined voltage that card voltage has been used to verify this programming or target threshold voltage Verifying voltage in not up to step S562, method 550 will no longer choose next verifying voltage be programmed verifying but Then next step S570 is executed；Otherwise, method 550 can choose next verifying voltage to be programmed verifying, and return Return step S562.

In step S570, it is determined whether programming of the target threshold voltage no more than the storage unit of predetermined voltage is completed. For example, in step S570, determine target threshold voltage no more than in the storage unit of predetermined voltage whether there are one or it is multiple Respective target threshold voltage has not yet been reached in storage unit in this programming.If there are one or multiple storage units are at this Respective target threshold voltage has not yet been reached in secondary programming, method 550 can be programmed next time with return step S560.If All storage units are reached respective target threshold voltage in this programming, and method 550 can move to the step of Fig. 5 C Rapid S572.

In step S572, to needing programmed and target threshold voltage to be greater than the predetermined electricity in storage array 108 Each storage unit of pressure is programmed.In some embodiments, operation similar with the step S515 of Fig. 5 A can be executed to come in fact Existing step S572.

In step 574, each storage unit of the predetermined voltage is greater than to target threshold voltage, executes programming verifying Operation.For example, selection verifying voltage, and verifies and be incorporated into the voltage of each storage unit whether to reach the verifying electric Pressure.In some embodiments, operation similar with the step S516 of Fig. 5 A can be executed to realize step S574.

In step 576, each storage unit of the predetermined voltage is greater than to target threshold voltage, executes and latches scanning Operation.For example, by the storage list by the programming verifying and target threshold voltage of the verifying voltage for the verifying voltage The data latches group of member is set as latch mode.In some embodiments, it can execute similar with the step S518 of Fig. 5 A Operation is to realize step S576.

In step S578, each storage unit of the predetermined voltage is greater than to target threshold voltage, confirmation is executed and sweeps Retouch operation.For example, being latched as the storage unit of latch mode for data latches group, the judgement of the storage unit is set Latch is to latch success status；The storage unit of latch mode is not latched as data latches group, described in setting Storage unit judges latch to latch unsuccessful state.In some embodiments, the step S520 with Fig. 5 A can be executed Similar operation is to realize step S578.

In step S580, it is determined whether choose next verifying voltage to be programmed verifying.For example, if all tests Card voltage has been used to verify this programming or target threshold voltage be greater than predetermined voltage storage unit voltage not Reach the verifying voltage in step S574, method 550 will no longer choose next verifying voltage and connect to be programmed verifying Execution next step S582；Otherwise, method 550 can choose next verifying voltage to be programmed verifying, and return Step S574.

In step S582, it is determined whether programming of the target threshold voltage greater than the storage unit of predetermined voltage is completed.Example Such as, in step S582, determine target threshold voltage be greater than in the storage unit of predetermined voltage whether there are one or multiple storages Respective target threshold voltage has not yet been reached in unit in this programming.If there are one or multiple storage units are in this volume Respective target threshold voltage has not yet been reached in journey, method 550 can be programmed next time with return step S572.If all Storage unit respective target threshold voltage is reached in this programming, method 550 can move to step S584.

In step S584, since all storage units have reached respective target threshold voltage, method by programming 550 complete the programming to the multi-bit data.

What Fig. 6 A was that the embodiment of the present disclosure provides a kind of is programmed verifying and latch operation after one-time programming The schematic flow chart of method 600.Method 600 is in step S510, S512 and S514 and Fig. 5 B of the method 500 in Fig. 5 A Step S562, S564, S566 and S568 of method 550 illustratively illustrated.It needs to be compiled in storage array After the target threshold voltage of journey is programmed no more than each storage unit of predetermined voltage, the following of method 600 can be executed Step is programmed verifying and latch operation.

Firstly, in step S602, select verifying voltage L1, and verify be incorporated into each storage unit voltage whether Reach the verifying voltage L1.

In step S604, the programming by verifying voltage L1 is verified and target threshold voltage is verifying voltage L1's Storage unit, it is latch mode (for example, the number can be set that data latches group corresponding with the storage unit, which is arranged, Information according to the storage of latch group is " 1111 ")；And in step S606, the storage unit is arranged judges latch for lock Success status is deposited, to prevent the storage unit from continuing to program.

In step S608, for the storage unit and/or target threshold voltage of the programming verifying of unverified voltage L1 It is not the storage unit of verifying voltage L1, keeps the state of data latches group corresponding with the storage unit constant；And And in step S610, the storage unit is arranged judges latch to latch unsuccessful state.

In step S612, verifying voltage L2 is selected, and is verified and has been incorporated into the voltage of each storage unit and whether reaches Verifying voltage L2.

In step S614, the programming by verifying voltage L2 is verified and target threshold voltage is verifying voltage L2's Storage unit, it is latch mode (for example, the data can be set that data latches corresponding with the storage unit, which are arranged, The information of latch group storage is " 1111 ")；And in step S616, the storage unit is arranged judges latch to latch Success status.

In step S618, for the storage unit and/or target threshold voltage of the programming verifying of unverified voltage L2 It is not the storage unit of verifying voltage L2, keeps the state of data latches corresponding with the storage unit constant；And In step S620, the storage unit is arranged judges latch to latch unsuccessful state.

In step S622, verifying voltage L3 is selected, and is verified and has been incorporated into the voltage of each storage unit and whether reaches Verifying voltage L3.Similarly, method 600 can also include the latch scan operation and confirmation scan operation to verifying voltage L3, And be programmed verifying using other verifying voltages, latch the operation for scanning and confirming scanning, the disclosure is no longer superfluous herein It states.

What Fig. 6 B was that the embodiment of the present disclosure provides a kind of is programmed verifying and latch operation after one-time programming The schematic flow chart of method 630.Method 630 is in step S516, S518 and S520 and Fig. 5 C of the method 500 in Fig. 5 A Step S574, S576, S578 and S580 of method 550 illustratively illustrated.It needs to be compiled in storage array After each storage unit that the target threshold voltage of journey is greater than predetermined voltage is programmed, the following step of method 630 can be executed It is rapid to be programmed verifying and latch operation.

Firstly, in step S631, select verifying voltage L8, and verify be incorporated into each storage unit voltage whether Reach the verifying voltage L8.

In step S632, the programming by verifying voltage L8 is verified and target threshold voltage is verifying voltage L8's Storage unit, it is latch mode (for example, the number can be set that data latches group corresponding with the storage unit, which is arranged, Information according to the storage of latch group is " 1111 ")；And in step S633, the storage unit is arranged judges latch for lock Success status is deposited, to prevent the storage unit from continuing to program.

In step S634, for the storage unit and/or target threshold voltage of the programming verifying of unverified voltage L8 It is not the storage unit of verifying voltage L8, keeps the state of data latches group corresponding with the storage unit constant；And And in step S635, the storage unit is arranged judges latch to latch unsuccessful state.

In step S636, verifying voltage L9 is selected, and is verified and has been incorporated into the voltage of each storage unit and whether reaches Verifying voltage L9.

In step S637, the programming by verifying voltage L9 is verified and target threshold voltage is verifying voltage L9's Storage unit, it is latch mode (for example, the data can be set that data latches corresponding with the storage unit, which are arranged, The information of latch group storage is " 1111 ")；And in step S638, the storage unit is arranged judges latch to latch Success status.

In step S639, for the storage unit and/or target threshold voltage of the programming verifying of unverified voltage L9 It is not the storage unit of verifying voltage L9, keeps the state of data latches corresponding with the storage unit constant；And In step S640, the storage unit is arranged judges latch to latch unsuccessful state.

In step S641, verifying voltage L10 is selected, and is verified and has been incorporated into the voltage of each storage unit and whether reaches Verifying voltage L10.Similarly, method 630 can also include the latch scan operation to verifying voltage L10 and confirmation scanning behaviour Make, and be programmed verifying using other verifying voltages, latch and scan and the operation of confirmation scanning, the disclosure is herein no longer It repeats.

Fig. 7 A-7P is the illustrative programming process for four bit datas that the embodiment of the present disclosure provides.As shown in Figure 7 A, table Lattice 700 are shown: needing programmed storage unit 1, storage unit 2, storage unit 3, storage unit 4 and storage unit 5 Target threshold voltage be respectively L1, L2, L3, L3 and L8；And storage unit 1, storage unit 2, storage unit 3, storage list Member 4 and the code word of the corresponding data latches group of storage unit 5 storage are respectively acceleration coding codeword corresponding with L1 The corresponding acceleration coding codeword " 1100 " of " 1000 " and L2 and the corresponding acceleration coding codeword " 1001 " of L3, it is corresponding with L3 plus Fast coding codeword " 1001 " and acceleration coding codeword " 0000 " corresponding with L8.

Fig. 7 B shows voltage of each storage unit after pre-programmed.Storage unit 1, storage unit 2, storage unit 3 with And the highest order of the acceleration coding codeword of storage unit 4 is " 1 ", is low-voltage memory cell group；It is not right in preprogramming process Each storage unit of low-voltage memory cell group carries out pre-programmed.The highest order of the acceleration coding codeword of storage unit 5 is " 0 ", For high voltage memory cell group；In preprogramming process, pre-programmed is carried out to the storage unit 5 of high voltage memory cell group.

Fig. 7 C is shown using verifying voltage L_tempVerifying is programmed to storage unit 5, verification result is shown in table In lattice 716.Verifying voltage L_tempEqual to intermediate state voltage.In conjunction with chart 715 and table 716 it is found that the voltage of storage unit 5 Verifying voltage L is passed through_tempVerifying, so storage unit 5 is programmed to have arrived intermediate state voltage L_temp。

Fig. 7 D shows voltage of each storage unit of low-voltage memory cell group after first time programs.For example, storage Unit 1 is programmed into voltage L1, and storage unit 2 is programmed into voltage L2, and storage unit 3 is programmed into voltage L3 and storage is single Member 4 is programmed into voltage L2.The storage unit 5 for belonging to high voltage memory cell group does not have when low-voltage memory cell group is programmed It is programmed, keeps original voltage level.

Fig. 7 E, which is shown, is programmed verifying using each storage unit of the verifying voltage L1 to low-voltage memory cell group, Verification result is shown in table 730.In conjunction with chart 725 and table 730 it is found that each storage of low-voltage memory cell group is single The voltage of member has reached verifying voltage L1, so verifying voltage latch corresponding with each storage unit is all set to pass through State.

Fig. 7 F shows the storage unit for latching that target threshold voltage is verifying voltage L1 (accelerating coding codeword " 1000 ") Process.Table 735 shows the voltage verification result and corresponding data of each storage unit of low-voltage memory cell group The code word of latch group storage.Since the voltage that storage unit 1 is programmed into has passed through the verifying of voltage L1, and storage unit 1 target threshold voltage is equal to verifying voltage L1 (for example, the acceleration coding codeword that the data latches group of storage unit 1 stores Identical as the acceleration coding codeword of verifying voltage L1, be " 1000 "), thus the data latches group of storage unit 1 from " 1000 " are latched as latch mode " 1111 " (as shown in arrow 736), and the state quilt for judging latch of storage unit 1 It is set as latching successfully.However, even if the voltage that storage unit 2, storage unit 3 and storage unit 4 are programmed into passes through The verifying of voltage L1, but since the target threshold voltage of storage unit 2, storage unit 3 and storage unit 4 is not equal to Verifying voltage L1 is (for example, the acceleration coding that the data latches group of storage unit 2, storage unit 3 and storage unit 4 stores Code word is not all identical as the acceleration coding codeword of verifying voltage L1), so storage unit 2, storage unit 3 and storage unit 4 The state of data latches group remain unchanged, and the judgement of storage unit 2, storage unit 3 and storage unit 4 is latched The state of device is arranged to latch unsuccessful.It is verifying voltage L1's that table 737, which shows above-mentioned latch target threshold voltage, As a result.

Since storage unit 2, storage unit 3 and storage unit 4 are not latched as respective target threshold voltage, And the voltage of storage unit 2, storage unit 3 and storage unit 4 is verified by the programming of last voltage L1, so also It needs to choose next verifying voltage L2 and carries out encoding verification.Fig. 7 G is shown using verifying voltage L2 to low-voltage storage unit Each storage unit of group is programmed verifying, and verification result is shown in table 742.It can in conjunction with chart 740 and table 742 Know, the voltage of storage unit 2, storage unit 3 and storage unit 4 has reached verifying voltage L2, so with storage unit 2, Storage unit 3 and the corresponding verifying voltage latch of storage unit 4 are all set to pass through state；The voltage of storage unit 1 Not up to verifying voltage L2, so verifying voltage latch corresponding with storage unit 1 is arranged to not pass through state.

Fig. 7 H shows the storage unit for latching that target threshold voltage is verifying voltage L2 (accelerating coding codeword " 1100 ") Process.Table 745 shows the voltage verification result and corresponding data of each storage unit of low-voltage memory cell group The code word of latch group storage.Since storage unit 1 has successfully reached its target threshold voltage L1 and its data latches group It is successfully latched, so storage unit 1 can't impact storage unit 1 not over the verifying of verifying voltage L2. Since the program voltage of storage unit 2 has passed through the verifying of voltage L2, and the target threshold voltage of storage unit 2 is equal to verifying Voltage L2 is (for example, the acceleration coding code for accelerating coding codeword with verifying voltage L2 that the data latches group of storage unit 2 stores Word is identical, is " 1100 "), so the data latches group of storage unit 2 is latched as latch mode " 1111 " from " 1100 " (as shown in arrow 746), and storage unit 2 judges that the state of latch is arranged to latch successfully.Due to storage unit 3 And the target threshold voltage of storage unit 4 is not equal to verifying voltage L2 (for example, the number of storage unit 3 and storage unit 4 It is all different according to the acceleration coding codeword of latch group storage and the acceleration coding codeword of verifying voltage L2), so storage unit 3 And the state of the data latches group of storage unit 4 remains unchanged, and the judgement of storage unit 3 and storage unit 4 The state of latch is arranged to latch unsuccessful.It is verifying voltage that table 747, which shows above-mentioned latch target threshold voltage, The result of L2.

Since storage unit 3 and storage unit 4 are not latched as respective target threshold voltage, and store list The voltage of member 3 and storage unit 4 passes through the programming verifying of last voltage L2, so also needing to choose next verifying voltage L3 carries out encoding verification.Fig. 7 I, which is shown, is programmed verifying to each storage unit using verifying voltage L3, and verification result shows Out in table 755.In conjunction with chart 750 and table 755 it is found that the voltage of storage unit 3 has reached verifying voltage L3, so Verifying voltage latch corresponding with storage unit 3 is arranged to pass through state；Storage unit 1, storage unit 2 and storage are single The voltage of member 4 is not up to verifying voltage L3, so verifying corresponding with storage unit 1, storage unit 2 and storage unit 4 is electric Pressure latch is all set to not pass through state.

Fig. 7 J shows the storage unit for latching that target threshold voltage is verifying voltage L3 (accelerating coding codeword " 1001 ") Process.Table 760 shows the voltage verification result and corresponding data of each storage unit of low-voltage memory cell group The code word of latch group storage.Since storage unit 1 and storage unit 2 have successfully reached its respective target threshold voltage simultaneously And its respective data latches group is also successfully latched, so storage unit 1 and storage unit 2 are not over verifying voltage The verifying of L3 can't impact storage unit 1 and storage unit 2.Since the program voltage of storage unit 3 has passed through electricity The verifying of L3 is pressed, and the target threshold voltage of storage unit 3 is equal to verifying voltage L3 (for example, the data of storage unit 3 latch The acceleration coding codeword of device group storage is identical as the acceleration coding codeword of verifying voltage L3, is " 1001 "), so storage unit 3 data latches group is latched as latch mode " 1111 " (as shown in arrow 762) from " 1001 ", and storage unit 3 Judge that the state of latch is arranged to latch successfully.Although the target threshold voltage of storage unit 4 is equal to verifying voltage L3 (example Such as, the acceleration coding codeword of the data latches group storage of storage unit 4 is identical as the acceleration coding codeword of verifying voltage L3), But the program voltage of storage unit 4 does not pass through the programming verifying of verifying voltage L3, so the data of storage unit 4 latch The state of device group remains unchanged, and storage unit 4 to judge that the state of latch is arranged to latch unsuccessful.Table 765 Show the result that above-mentioned latch target threshold voltage is verifying voltage L3.

Since storage unit 4 is not latched as its target threshold voltage, and the voltage of storage unit 4 is not over upper The programming of primary voltage L3 is verified, and is verified so no longer choosing next verifying voltage L4 to the programming of storage unit 4, and It is to carry out second to storage unit 4 to program.Fig. 7 K shows the voltage L3 after storage unit 4 is programmed at second.Due to Storage unit 4 is verified by the programming of verifying voltage L2 without being tested by the programming of verifying voltage L3 when programming for the first time Card, so can directly be verified using verifying voltage L3 to storage unit 4 when second programs rather than from verifying electricity Pressure L1 starts.

Fig. 7 L, which is shown, is programmed verifying to storage unit 4 using verifying voltage L3, and verification result is shown in table In 772.In conjunction with chart 770 and table 772 it is found that the voltage of storage unit 4 has reached verifying voltage L3, so single with storage First 4 corresponding verifying voltage latch are arranged to pass through state.

Fig. 7 M shows the storage unit for latching that target threshold voltage is verifying voltage L3 (accelerating coding codeword " 1001 ") Process.Table 775 shows the voltage verification result of storage unit 4 and the code word of corresponding data latches group storage. Since the voltage of storage unit 4 has passed through the verifying of verifying voltage L3, and the target threshold voltage of storage unit 4 is equal to verifying Voltage L3 is (for example, the acceleration coding code for accelerating coding codeword with verifying voltage L4 that the data latches group of storage unit 4 stores Word is identical, is

" 1001 "), so the data latches group of storage unit 4 is latched as latch mode " 1111 " (such as from " 1001 " Shown in arrow 776), and storage unit 4 judges that the state of latch is arranged to latch successfully.Table 778 is shown The latch target threshold voltage stated is the latch result of verifying voltage L3.So far, storage unit 1, storage unit 2, storage unit 3 And the corresponding each data latches group of storage unit 4 is successfully latched, to the storage unit 1 of low-voltage memory cell group, The programming of storage unit 2, storage unit 3 and storage unit 4 all terminates.

Fig. 7 N shows the voltage of each storage unit of high voltage memory cell group after programming.For example, 5 quilt of storage unit It is programmed into voltage L8.Storage unit 1, storage unit 2, storage unit 3 and the storage unit 4 of low-voltage memory cell group do not have It is programmed, keeps latch mode.

Fig. 7 O, which is shown, is programmed verifying using storage unit 5 of the verifying voltage L8 to high voltage memory cell group, Verification result is shown in table 786.In conjunction with chart 785 and table 786 it is found that the voltage of storage unit 5 has reached verifying Voltage L8, so verifying voltage latch corresponding with storage unit 5 is arranged to pass through state.

Fig. 7 P shows the storage unit for latching that target threshold voltage is verifying voltage L8 (accelerating coding codeword " 0000 ") Process.Table 790 shows the voltage verification result of storage unit 5 and the code word of corresponding data latches group storage. Since the voltage that storage unit 5 is programmed into has passed through the verifying of voltage L8, and the target threshold voltage of storage unit 5 is equal to Verifying voltage L8 is (for example, the acceleration volume for accelerating coding codeword with verifying voltage L8 that the data latches group of storage unit 5 stores Code code word is identical, is " 0000 "), so the data latches group of storage unit 5 is latched as latch mode from " 0000 " " 1111 " (as shown in arrow 791), and storage unit 5 judges that the state of latch is arranged to latch successfully.Table 792 Show the result that above-mentioned latch target threshold voltage is verifying voltage L8.

So far, all storage unit 1-5 are successfully latched, and are all terminated to the programming of all storage unit 1-5.

Fig. 8 A-8H is a kind of programming verifying for acceleration coding 950 based on Fig. 9 that the embodiment of the present disclosure provides and latches Method 8000 exemplary process diagram.As the programming verifying and the comparison of the method 8000 latched for accelerating coding, Fig. 8 A- The exemplary process diagram for the method 800 that the programming that 8H further comprises a kind of Gray code 900 based on Fig. 9 is verified and latched. For example, the programming verifying of Gray code 900 and the method 800 latched are shown on the left side of dotted line in Fig. 8 A-8H, accelerate The programming verifying of coding 950 and the method 8000 latched are shown on the right of dotted line.The verifying electricity of method 800 and method 8000 Pressure is to be followed successively by L1-L7 and L8-L15 according to the sequence from low-voltage to high voltage.

For convenience described below, data latches group corresponding with programmed storage unit may include four Data latches ADL (Data Latch A), BDL (Data Latch B), CDL (Data Latch C) and DDL (Data Latch D), the code word of Gray code or accelerate each bit of the code word of coding be sequentially stored in data latches ADL, BDL, In CDL and DDL.For example, data latches ADL, BDL, CDL and DDL store " 1 " respectively, " 0 ", " 1 " for code word " 1010 ", " 0 " (that is, ADL=1, BDL=0, CDL=1, DDL=0).Induction latch can be expressed as SDL (Sensing Data Latch), ephemeral data latch can be expressed as TDL (Temporary Data Latch), and bus can be expressed as BUS.

In some embodiments, programming verifying and latch scan operation may include: (1) detection voltage verification the result is that It is no to pass through；(2) data latches group is compared by turn, judges the code word of the target threshold voltage of data latches group storage Whether be verifying voltage code word；(3) if having passed through the target threshold of the verifying of verifying voltage and the storage of data latches group The code word of threshold voltage is the code word of verifying voltage, i.e. the voltage of storage unit has reached target threshold voltage, then latches data Device group is set as latch mode " 1111 ".

In some embodiments, following step (1)-(3) detection data latch (for example, ADL) storage can be passed through " 0 " and " 1 ":

(1) it charges to bus B US, to label latch set, (TDL or SDL or other data latches be can be used as Mark latch use).

(2) read data latch ADL.If ADL=0, bus B US does not discharge, and label latch is still " 1 "；If ADL=1, then bus B US discharges, and marks latch by reset.

(3) label latch is drawn high again.If bus B US does not discharge in (2), label latch is still " 1 ", then exists The label latch success set being raised in step (3), to judge ADL=0；If bus B US is put in (2) Electricity marks latch by reset, then the label latch being raised in step (3) cannot succeed set, to judge ADL=1.

By above-mentioned steps (1)-(3) it is found that because bus B US discharges, needing one when detection data latch is " 1 " A " 1 " connects one " 1 " and is detected, and cannot detect more than two " 1 " simultaneously (that is, two data locks cannot be detected simultaneously Whether storage is " 1 ")；And detection data latch be " 0 " when, can directly detect detection in need " 0 " (that is, Can detect whether more than two data latches are " 0 " simultaneously).Therefore, accelerate coding can be by changing cataloged procedure In each code word each sequence, allow to faster be detected containing " 0 " a fairly large number of code word it is preceding (that is, with contain " 0 " A fairly large number of code word represents lower verifying voltage), and contain the code word of " 0 " negligible amounts it is rear (that is, with containing " 0 " quantity compared with Few code word represents higher verifying voltage), so as to save the redundant operation of detection " 1 ".Therefore, accelerate the programming of coding Speed can be accelerated, and power consumption can also reduce.

For example, with reference to the coding in Fig. 9, for encoding L1, L2, when detection, in order to current list Primitive encoding is distinguished with all units on the right side of it.Because " 0 " and " 1 " relationship of Gray code is indefinite, using When Gray code, if L1 (" 1110 ") distinguished with L2-L15, needs to detect ADL=1, then detect BDL=1, so After detect CDL=1, finally detect DDL=0.And after being recompiled using acceleration coding, code word corresponding for L1 " 1000 " can detecte ADL=1, detect three " 0 " (that is, BDL=CDL=DDL=0).Similarly, for voltage L2, make When with Gray code, if L2 (" 1100 ") distinguished with L3-L15, needs to detect ADL=1, then detects BDL=1, Then CDL=DDL=0 is detected.And after using acceleration coding to recode, code word " 1100 " corresponding for L2 can detecte ADL=1, detecting two " 0 " (that is, CDL=DDL=0) can just be such that L2 distinguishes with L3-L15, because not having in L3-L15 ADL is " 1 " and CDL and DDL are the code word of " 0 ".Therefore, compared with Gray code, accelerate coding that can save at least one Sorting surveys the redundant operation of " 1 ", and program speed can be accelerated, and power consumption can also reduce.

Referring to Fig. 8 A, in method 800, the Gray code code word of verifying voltage L1 is " 1110 ", and method 800 includes: step Rapid S801 verifies pulse L1 (that is, verifying voltage L1) to programmed storage unit；Step S802, it is single to programmed storage Member executes the latch of pulse L1；Step S803, first " 1 " of detection (that is, detection ADL=1)；Step S804 detects second " 1 " (that is, detection BDL=1)；Step S805, detection third " 1 " (that is, detection CDL=1)；Step S806 detects one " 0 " (that is, detection DDL=0)；And step S807, above-mentioned steps S803-S806 will be met and by the verifying of verifying voltage L1 The data latches group of storage unit is latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL= 1, DDL=1)；Also, it will not meet above-mentioned steps S803-S806 or not by the storage unit of the verifying of verifying voltage L1 The state of data latches group remain unchanged.

For example, the verifying and latch of L1 (Gray code " 1110 ") may include following operation A)-E):

A) to BUS charging (that is, setting BUS=1), label latch (for example, setting flag latch TDL=1) is drawn high.

B) BUS charges (BUS=1), reads ADL, then draw high TDL=1.If ADL=1, then TDL=0；Otherwise TDL=1.

C) BUS charges (BUS=1), reads BDL, then draw high TDL=1.If BDL=1, TDL=0；Otherwise TDL=1.

D) BUS charging BUS=1, reads CDL, then draw high TDL=1.If CDL=1, then TDL=0；Otherwise TDL=1.

E) BUS charging BUS=1, reads DDL, SDL, TDL, draws high DDL=1.If DDL=0, SDL=0, TDL=0, then DDL =1；Otherwise DDL=0.

In method 8000, the acceleration coding codeword of verifying voltage L1 is " 1000 ", and method 8000 includes: step S8001, Pulse L1 (that is, verifying voltage L1) is verified to programmed storage unit；Step S8002 executes programmed storage unit The latch of pulse L1；Step S8003, first " 1 " of detection (that is, detection ADL=1)；Step S8006, three " 0 " of detection (that is, Detect BDL=CDL=DDL=0)；And step S8007, above-mentioned steps S8003 and S8006 will be met and pass through verifying voltage The data latches group of the storage unit of the verifying of L1 be latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, it will not meet above-mentioned steps S8003, S8006 and/or not by verifying voltage L1 The state of data latches group of storage unit of verifying remain unchanged.

For example, the verifying and latch of L1 (accelerating coding " 1000 ") may include following operation:

BUS charging BUS=1, draws high TDL=1.BUS charging BUS=1, reads ADL, then draw high TDL=1；If ADL=1, then TDL=0；Otherwise TDL=1.BDL, CDL, DDL, TDL, SDL are read, then draws high BDL=1, CDL=1, DDL=1；If BDL=0, CDL=0, DDL=0, TDL=0, SDL=0 (wherein, SDL=0 indicates that the voltage of storage unit has reached verifying voltage L1), then BDL=1, CDL=1, DDL=1；Otherwise BDL=0, CDL=0, DDL=0.

Therefore, compared to Gray code, accelerate coding that can save step S804 and S805, so that operation number subtracts It is few, accelerate program speed, while reducing power consumption.

In method 800, the Gray code code word of verifying voltage L2 is " 1100 ", method 800 further include: step S808, Pulse L2 (that is, verifying voltage L2) is verified to programmed storage unit；Step S809 executes arteries and veins to programmed storage unit Rush the latch of L2；Step S810, first " 1 " of detection (that is, detection ADL=1)；Step S811, second " 1 " of detection is (that is, inspection Survey BDL=1)；Step S812, two " 0 " of detection (that is, detection CDL=DDL=0)；And step S813, above-mentioned step will be met Rapid S810-S812 and " 1111 " are latched as (that is, several by the data latches group of the storage unit of the verifying of verifying voltage L2 ADL=1, BDL=1, CDL=1, DDL=1 are latched as according to latch group)；Also, it will not meet above-mentioned steps S810- It S812 and/or is remained unchanged not over the state of data latches group of the storage unit of the verifying of verifying voltage L2.

For example, the verifying and latch of L2 (Gray code " 1100 ") may include following operation:

A) BUS charging BUS=1, draws high TDL=1.

B) BUS charging BUS=1, reads ADL, then draw high TDL=1.If ADL=1, then TDL=0；Otherwise TDL=1.

C) BUS charging BUS=1, reads BDL, then draw high TDL=1.If BDL=1, then TDL=0；Otherwise TDL=1.

D) BUS charging BUS=1, reads CDL, DDL, SDL, TDL, draws high CDL, DDL=1.If CDL=0, DDL=0, SDL =0, TDL=0, then CDL=1, DDL=1；Otherwise CDL=0, DDL=0.

In method 8000, the acceleration coding codeword of verifying voltage L2 is " 1100 ", method 8000 further include: step S8008 verifies pulse L2 (that is, verifying voltage L2) to programmed storage unit；Step S8009, it is single to programmed storage Member executes the latch of pulse L2；Step S8010, first " 1 " of detection (that is, detection ADL=1)；Step S8012 detects two " 0 " (that is, detection CDL=DDL=0)；And step S8013, above-mentioned steps S8010 and S8012 will be met and pass through verifying The data latches group of the storage unit of the verifying of voltage L2 is latched as " 1111 " (that is, data latches group is latched as ADL= 1, BDL=1, CDL=1, DDL=1)；Also, it will not meet above-mentioned steps S8010, S8012 and/or not over verifying electricity The state of the data latches group of the storage unit of the verifying of L2 is pressed to remain unchanged.

For example, the verifying and latch of L2 (accelerating coding " 1100 ") may include following operation:

BUS charging BUS=1, draws high TDL=1.BUS charging BUS=1, reads ADL, then draw high TDL=1, if ADL=1, TDL=0, otherwise TDL=1.CDL, DDL, TDL, SDL are read, then draws high CDL=1, DDL=1；If CDL=0, DDL=0, TDL= 0, SDL=0, then CDL=1, DDL=1, otherwise CDL=0, DDL=0.

Therefore, compared to Gray code, accelerate coding that can save step S811, so that operation number is reduced, accelerate Program speed, while reducing power consumption.

Referring to Fig. 8 B, in method 800, the Gray code code word of verifying voltage L3 is " 1000 ", and method 800 includes: step Rapid S814 verifies pulse L3 (that is, verifying voltage L3) to programmed storage unit；Step S815, it is single to programmed storage Member executes the latch of pulse L3；Step S816, first " 1 " of detection (that is, detection ADL=1)；Step S817 detects three " 0 " (that is, detection BDL=CDL=DDL=0)；And step S818, above-mentioned steps S816-S817 will be met and by verifying electricity Press the data latches group of the storage unit of the verifying of L3 be latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, it will not meet above-mentioned steps S816-S817 and/or not over verifying voltage L3 The state of data latches group of storage unit of verifying remain unchanged.

For example, the verifying and latch of L3 (Gray code " 1000 ") may include following operation:

A) to BUS charging (that is, setting BUS=1), label latch (for example, setting TDL=1) is drawn high.

C) BUS charging BUS=1, reads BDL, CDL, DDL, SDL, TDL, draws high BDL, CDL, DDL.If BDL=0, CDL= 0, DDL=0, SDL=0, TDL=0, then BDL=1, CDL=1, DDL=1；Otherwise BDL=0, CDL=0, DDL=0.

In method 8000, the acceleration coding codeword of verifying voltage L3 is " 1001 ", method 8000 further include: step S8014 verifies pulse L3 (that is, verifying voltage L3) to programmed storage unit；Step S8015, it is single to programmed storage Member executes the latch of pulse L3；Step S8016, first " 1 " of detection (that is, detection ADL=1)；Step S8017 detects two " 0 " (that is, detection BDL=CDL=0)；And step S8018, above-mentioned steps S8016 and S8017 will be met and pass through verifying The data latches group of the storage unit of the verifying of voltage L3 is latched as " 1111 " (that is, data latches group is latched as ADL= 1, BDL=1, CDL=1, DDL=1)；Also, it will not meet above-mentioned steps S8016, S8017 and/or not over verifying electricity The state of the data latches group of the storage unit of the verifying of L3 is pressed to remain unchanged.

For example, the verifying and latch of L3 (accelerating coding " 1001 ") may include following operation:

BUS charging BUS=1, draws high TDL=1.BUS charging BUS=1, reads ADL, then draw high TDL=1, if ADL=1, TDL=0, otherwise TDL=1.BDL, CDL, TDL, SDL are read, then draws high BDL=1, CDL=1；If BDL=0, CDL=0, TDL= 0, SDL=0, then BDL=1, CDL=1, otherwise BDL=0, CDL=0.

In method 800, the Gray code code word of verifying voltage L4 is " 1010 ", method 800 further include: step S819, Pulse L4 (that is, verifying voltage L4) is verified to programmed storage unit；Step S820 executes arteries and veins to programmed storage unit Rush the latch of L4；Step S821, first " 1 " of detection (that is, detection ADL=1)；Step S822, second " 1 " of detection is (that is, inspection Survey CDL=1)；Step S823, two " 0 " of detection (that is, detection BDL=DDL=0)；And step S824, above-mentioned step will be met Rapid S821-S823 and " 1111 " are latched as (that is, several by the data latches group of the storage unit of the verifying of verifying voltage L4 ADL=1, BDL=1, CDL=1, DDL=1 are latched as according to latch group)；Also, it will not meet above-mentioned steps S821- It S823 and/or is remained unchanged not over the state of data latches group of the storage unit of the verifying of verifying voltage L4.

For example, the verifying and latch of L4 (Gray code " 1010 ") may include following operation:

A) BUS charging BUS=1, draws high TDL=1.

C) BUS charging BUS=1, reads CDL, then draw high TDL=1.If CDL=1, then TDL=0；Otherwise TDL=1.

D) BUS charging BUS=1, reads BDL, DDL, SDL, TDL, draws high BDL=1, DDL=1.If BDL=0, DDL=0, SDL=0, TDL=0, then BDL=1, DDL=1；Otherwise BDL=0, DDL=0.

In method 8000, the acceleration coding codeword of verifying voltage L4 is " 1010 ", method 8000 further include: step S8019 verifies pulse L4 (that is, verifying voltage L4) to programmed storage unit；Step S8020, it is single to programmed storage Member executes the latch of pulse L4；Step S8021, first " 1 " of detection (that is, detection ADL=1)；Step S8023 detects two " 0 " (that is, detection BDL=DDL=0)；And step S8024, above-mentioned steps S8021 and S8023 will be met and pass through verifying The data latches group of the storage unit of the verifying of voltage L4 is latched as " 1111 " (that is, data latches group is latched as ADL= 1, BDL=1, CDL=1, DDL=1)；Also, it will not meet above-mentioned steps S8021, S8023 and/or not over verifying electricity The state of the data latches group of the storage unit of the verifying of L4 is pressed to remain unchanged.

For example, the verifying and latch of L4 (accelerating coding " 1010 ") may include following operation:

BUS charging BUS=1, draws high TDL=1.BUS charging BUS=1, reads ADL, then draw high TDL=1, if ADL=1, TDL=0；Otherwise TDL=1.BDL, DDL, TDL, SDL are read, then draws high BDL=1, DDL=1；If BDL=0, DDL=0, TDL= 0, SDL=0, then BDL=1, DDL=1, otherwise BDL=0, DDL=0.

Therefore, compared to Gray code, accelerate coding that can save step S822, so that operation number is reduced, accelerate Program speed, while reducing power consumption.

Referring to Fig. 8 C, in method 800, the Gray code code word of verifying voltage L5 is " 1011 ", method 800 further include: Step S825 verifies pulse L5 (that is, verifying voltage L5) to programmed storage unit；Step S826, to programmed storage The latch of unit execution pulse L5；Step S827, first " 1 " of detection (that is, detection ADL=1)；Step S828, detection second A " 1 " (that is, detection CDL=1)；Step S829, detection third " 1 " (that is, detection DDL=1)；Step S830 detects one " 0 " (that is, detection BDL=0)；And step S831, above-mentioned steps S827-S830 and testing by verifying voltage L5 will be met The data latches group of the storage unit of card be latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, it will not meet above-mentioned steps S827-S830 and/or not over the verifying of verifying voltage L5 The state of data latches group of storage unit remain unchanged.

For example, the verifying and latch of L5 (Gray code " 1011 ") may include following operation:

A) BUS charging BUS=1, draws high TDL=1.

C) BUS charging BUS=1, reads CDL, then draw high TDL=1.If CDL=1, then TDL=0；Otherwise TDL=1

D) BUS charging BUS=1, reads DDL, then draw high TDL=1.If DDL=1, then TDL=0；Otherwise TDL=1.

E) BUS charging BUS=1, reads BDL, SDL, TDL, draws high BDL=1.If BDL=0, SDL=0, TDL=0, then BDL =1；Otherwise BDL=0.

In method 8000, the acceleration coding codeword of verifying voltage L5 is " 1011 ", method 8000 further include: step S8025 verifies pulse L5 (that is, verifying voltage L5) to programmed storage unit；Step S8026, it is single to programmed storage Member executes the latch of pulse L5；Step S8027, first " 1 " of detection (that is, detection ADL=1)；Step S8030 detects one " 0 " (that is, detection BDL=0)；And step S8031, above-mentioned steps S8027 and S8030 will be met and by verifying voltage L5 The data latches group of storage unit of verifying be latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL =1, CDL=1, DDL=1)；Also, it will not meet above-mentioned steps S8027, S8030 and/or not over verifying voltage L5 The state of data latches group of storage unit of verifying remain unchanged.

For example, the verifying and latch of L5 (accelerating coding " 1011 ") may include following operation:

BUS charging BUS=1, draws high TDL=1.BUS charging BUS=1, reads ADL, then draw high TDL=1, if ADL=1, TDL=0；Otherwise TDL=1.BDL, TDL, SDL are read, then draws high BDL=1；If BDL=0, TDL=0, SDL=0, then BDL=1, Otherwise BDL=0.

Therefore, compared to Gray code, accelerate coding that can save step S828-S829, so that operation number is reduced, Accelerate program speed, while reducing power consumption

In method 800, the Gray code code word of verifying voltage L6 is " 1001 ", method 800 further include: step S832, Pulse L6 (that is, verifying voltage L6) is verified to programmed storage unit；Step S833 executes arteries and veins to programmed storage unit Rush the latch of L6；Step S834, first " 1 " of detection (that is, detection ADL=1)；Step S835, second " 1 " of detection is (that is, inspection Survey DDL=1)；Step S836, two " 0 " of detection (that is, detection BDL=CDL=0)；And step S837, above-mentioned step will be met Rapid S834-S836 and " 1111 " are latched as (that is, several by the data latches group of the storage unit of the verifying of verifying voltage L6 ADL=1, BDL=1, CDL=1, DDL=1 are latched as according to latch group)；Also, it will not meet above-mentioned steps S834- It S836 and/or is remained unchanged not over the state of data latches group of the storage unit of the verifying of verifying voltage L5.

For example, the verifying and latch of L6 (Gray code " 1001 ") may include following operation:

A) BUS charging BUS=1, draws high TDL=1.

C) BUS charging BUS=1, reads DDL, then draw high TDL=1.If DDL=1, then TDL=0；Otherwise TDL=1.

D) BUS charging BUS=1, reads BDL, CDL, SDL, TDL, draws high BDL=1, CDL=1.If BDL=0, CDL=0, SDL=0, TDL=0, then BDL=1, CDL=1；Otherwise BDL=0, CDL=0.

In method 8000, the acceleration coding codeword of verifying voltage L6 is " 1110 ", method 8000 further include: step S8032 verifies pulse L6 (that is, verifying voltage L6) to programmed storage unit；Step S8033, it is single to programmed storage Member executes the latch of pulse L6；Step S8034, first " 1 " of detection (that is, detection ADL=1)；Step S8036 detects one " 0 " (that is, detection DDL=0)；And step S8037, above-mentioned steps S8034, S8036 will be met and by verifying voltage L6 The data latches group of storage unit of verifying be latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL =1, CDL=1, DDL=1)；Also, it will not meet above-mentioned steps S8034, S8036 and/or not over verifying voltage L6 The state of data latches group of storage unit remain unchanged.

For example, the verifying and latch of L6 (accelerating coding " 1110 ") may include following operation:

BUS charging BUS=1, draws high TDL=1.BUS charging BUS=1, reads ADL, then draw high TDL=1, if ADL=1, TDL=0；Otherwise TDL=1.DDL, TDL, SDL are read, then draws high DDL=1；If DDL=0, TDL=0, SDL=0, then DDL=1, Otherwise DDL=0.

Therefore, compared to Gray code, accelerate coding that can save step S835, so that operation number is reduced, accelerate Program speed, while reducing power consumption.

Referring to Fig. 8 D, in method 800, the Gray code code word of verifying voltage L7 is " 1101 ", and method 800 includes: step Rapid S838 verifies pulse L7 (that is, verifying voltage L7) to programmed storage unit；Step S839, it is single to programmed storage Member executes the latch of pulse L7；Step S840, first " 1 " of detection (that is, detection ADL=1)；Step S841 detects second " 1 " (that is, detection BDL=1)；Step S842, detection third " 1 " (that is, detection DDL=1)；Step S843 detects one " 0 " (that is, detection CDL=0)；And step S844, above-mentioned steps S840-S843 will be met and by the verifying of verifying voltage L7 The data latches group of storage unit be latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL =1, DDL=1)；Also, it will not meet above-mentioned steps S840-S843 and/or deposited not over the verifying of verifying voltage L7 The state of the data latches group of storage unit remains unchanged.

For example, the verifying and latch of L7 (Gray code " 1101 ") may include following operation:

A) BUS charging BUS=1, draws high TDL=1.

E) BUS charging BUS=1, reads CDL, SDL, TDL, draws high CDL=1.If CDL=0, SDL=0, TDL=0, then CDL =1；Otherwise CDL=0.

In method 8000, the acceleration coding codeword of verifying voltage L7 is " 1101 ", and method 8000 includes: step S8038, Pulse L7 (that is, verifying voltage L7) is verified to programmed storage unit；Step S8039 executes programmed storage unit The latch of pulse L7；Step S8040, first " 1 " of detection (that is, detection ADL=1)；Step S8043, one " 0 " of detection (that is, Detect CDL=0)；And step S8044, above-mentioned steps S8040, S8043 will be met and by the verifying of verifying voltage L7 The data latches group of storage unit is latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL= 1, DDL=1)；Also, it will not meet above-mentioned steps S8040, S8043 and/or deposited not over the verifying of verifying voltage L7 The state of the data latches group of storage unit remains unchanged.

For example, the verifying and latch of L7 (accelerating coding " 1101 ") may include following operation:

BUS charging BUS=1, draws high TDL=1.BUS charging BUS=1, reads ADL, then draw high TDL=1, if ADL=1, TDL=0；Otherwise TDL=1.CDL, TDL, SDL are read, then draws high CDL=1；If CDL=0, TDL=0, SDL=0, then CDL=1, Otherwise CDL=0.

Therefore, compared to Gray code, accelerate coding that can save step S841-S842, so that operation number is reduced, Accelerate program speed, while reducing power consumption.

In method 800, the Gray code code word of verifying voltage L8 is " 0101 ", method 800 further include: step S845, Pulse L8 (that is, verifying voltage L8) is verified to programmed storage unit；Step S846 executes arteries and veins to programmed storage unit Rush the latch of L8；Step S847, first " 1 " of detection (that is, detection BDL=1)；Step S848, second " 1 " of detection is (that is, inspection Survey DDL=1)；Step S849, two " 0 " of detection (that is, detection ADL=CDL=0)；And step S850, above-mentioned step will be met Rapid S847-S849 and " 1111 " are latched as (that is, several by the data latches group of the storage unit of the verifying of verifying voltage L8 ADL=1, BDL=1, CDL=1, DDL=1 are latched as according to latch group)；Also, it will not meet above-mentioned steps S847- It S849 and/or is remained unchanged not over the state of data latches group of the storage unit of the verifying of verifying voltage L8.

For example, the verifying and latch of L8 (Gray code " 0101 ") may include following operation:

A) BUS charging BUS=1, draws high TDL=1.

B) BUS charging BUS=1, reads BDL, then draw high TDL=1.If BDL=1, then TDL=0；Otherwise TDL=1.

D) BUS charging BUS=1, reads ADL, CDL, SDL, TDL, draws high ADL=1, CDL=1.If ADL=0, CDL=0, SDL=0, TDL=0, then ADL=1, CDL=1；Otherwise ADL=0, CDL=0.

In method 8000, the acceleration coding codeword of verifying voltage L8 is " 0000 ", method 8000 further include: step S8045 verifies pulse L8 (that is, verifying voltage L8) to programmed storage unit；Step S8046, it is single to programmed storage Member executes the latch of pulse L8；Step S8049, four " 0 " of detection (that is, detection ADL=BDL=CDL=DDL=0)；And step Rapid S8050 will meet above-mentioned steps S8049 and be locked by the data latches group of the storage unit of the verifying of verifying voltage L8 Save as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, it will be without full Sufficient above-mentioned steps S8049 and/or not over verifying voltage L8 verifying storage unit data latches group state protect It holds constant.

For example, the verifying and latch of L8 (accelerating coding " 0000 ") may include following operation:

BUS charging BUS=1, draws high TDL=1, reads ADL, BDL, CDL, DDL, TDL, SDL, then draw high ADL=1, BDL= 1, CDL=1, DDL=1.If ADL=0, BDL=0, CDL=0, DDL=0, TDL=0, SDL=0, then ADL=1, BDL=1, CDL=1, DDL=1；Otherwise ADL=0, BDL=0, CDL=0, DDL=0.

Therefore, compared to Gray code, accelerate coding that can save step S847-S848, so that operation number is reduced, Accelerate program speed, while reducing power consumption.

Referring to Fig. 8 E, in method 800, the Gray code code word of verifying voltage L9 is " 0001 ", method 800 further include: Step S851 verifies pulse L9 (that is, verifying voltage L9) to programmed storage unit；Step S852, to programmed storage The latch of unit execution pulse L9；Step S853, first " 1 " of detection (that is, detection DDL=1)；Step S854 detects three " 0 " (that is, detection ADL=BDL=CDL=0)；And step S855, above-mentioned steps S853-S854 will be met and pass through verifying The data latches group of the storage unit of the verifying of voltage L9 is latched as " 1111 " (that is, data latches group is latched as ADL= 1, BDL=1, CDL=1, DDL=1)；Also, it will not meet above-mentioned steps S853-S854 and/or not over verifying voltage The state of the data latches group of the storage unit of the verifying of L9 remains unchanged.

For example, the verifying and latch of L9 (Gray code " 0001 ") may include following operation:

A) BUS charging BUS=1, draws high TDL=1.

B) BUS charging BUS=1, reads DDL, then draw high TDL=1.If DDL=1, then TDL=0；Otherwise TDL=1.

C) BUS charging BUS=1, reads ADL, BDL, CDL, SDL, TDL, draws high ADL=1, BDL=1, CDL=1.If ADL =0, BDL=0, CDL=0, SDL=0, TDL=0, then ADL=1, BDL=1, CDL=1；Otherwise ADL=0, BDL=0, CDL =0.

In method 8000, the acceleration coding codeword of verifying voltage L9 is " 0001 ", method 8000 further include: step S8051 verifies pulse L9 (that is, verifying voltage L9) to programmed storage unit；Step S8052, it is single to programmed storage Member executes the latch of pulse L9；Step S8054, three " 0 " of detection (that is, detection ADL=BDL=CDL=0)；And step S8055 will meet above-mentioned steps S8054 and is latched as by the data latches group of the storage unit of the verifying of verifying voltage L9 " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, on will be without meeting State step S8054 and/or not over verifying voltage L9 verifying storage unit data latches group state keep not Become.

For example, the verifying and latch of L9 (accelerating coding " 0001 ") may include following operation:

BUS charging BUS=1, draws high TDL=1, reads ADL, BDL, CDL, TDL, SDL, then draw high ADL=1, BDL=1, CDL=1.If ADL=0, BDL=0, CDL=0, TDL=0, SDL=0, then ADL=1, BDL=1, CDL=1, otherwise ADL= 0, BDL=0, CDL=0.

Therefore, compared to Gray code, accelerate coding that can save step S853, so that operation number is reduced, accelerate Program speed, while reducing power consumption.

In method 800, the Gray code code word of verifying voltage L10 is " 0011 ", method 800 further include: step S856, Pulse L10 (that is, verifying voltage L10) is verified to programmed storage unit；Step S857 executes programmed storage unit The latch of pulse L10；Step S858, first " 1 " of detection (that is, detection CDL=1)；Step S859 detects second " 1 " (that is, detection DDL=1)；Step S860, two " 0 " of detection (that is, detection ADL=BDL=0)；And step S861, it will meet It above-mentioned steps S858-S860 and is latched as by the data latches group of the storage unit of the verifying of verifying voltage L10 " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, on will be without meeting State step S858-S860 and/or not over verifying voltage L10 verifying storage unit data latches group state protect It holds constant.

For example, the verifying and latch of L10 (Gray code " 0011 ") may include following operation:

A) BUS charging BUS=1, draws high TDL=1.

B) BUS charging BUS=1, reads CDL, then draw high TDL=1.If CDL=1, then TDL=0；Otherwise TDL=1.

D) BUS charging BUS=1, reads ADL, BDL, SDL, TDL, draws high ADL=1, BDL=1.If ADL=0, BDL=0, SDL=0, TDL=0, then ADL=1, BDL=1；Otherwise ADL=0, BDL=0.

In method 8000, the acceleration coding codeword of verifying voltage L10 is " 0100 ", method 8000 further include: step S8056 verifies pulse L10 (that is, verifying voltage L10) to programmed storage unit；Step S8057, to programmed storage The latch of unit execution pulse L10；Step S8060, three " 0 " of detection (that is, detection ADL=CDL=DDl=0)；And step S8061 will meet above-mentioned steps S8060 and be locked by the data latches group of the storage unit of the verifying of verifying voltage L10 Save as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, it will be without full Sufficient above-mentioned steps S8060 and/or not over verifying voltage L10 verifying storage unit data latches group state protect It holds constant.

For example, the verifying and latch of L10 (accelerating coding " 0100 ") may include following operation:

BUS charging BUS=1, draws high TDL=1, reads ADL, CDL, DDL, TDL, SDL, then draw high ADL=1, CDL=1, DDL=1.If ADL=0, CDL=0, DDL=0, TDL=0, SDL=0, then ADL=1, CDL=1, DDL=1, otherwise ADL= 0, CDL=0, DDL=0.

Therefore, compared to Gray code, accelerate coding that can save step S858-S859, so that operation number is reduced, Accelerate program speed, while reducing power consumption.

Referring to Fig. 8 F, in method 800, the Gray code code word of verifying voltage L11 is " 0010 ", and method 800 includes: step Rapid S862 verifies pulse L11 (that is, verifying voltage L11) to programmed storage unit；Step S863, to programmed storage The latch of unit execution pulse L11；Step S864, first " 1 " of detection (that is, detection CDL=1)；Step S865 detects three " 0 " (that is, detection ADL=BDL=DDL=0)；And step S866, above-mentioned steps S864-S865 will be met and pass through verifying The data latches group of the storage unit of the verifying of voltage L11 is latched as " 1111 " (that is, data latches group is latched as ADL =1, BDL=1, CDL=1, DDL=1)；Also, it will not meet above-mentioned steps S864-S865 and/or not over verifying electricity The state of the data latches group of the storage unit of the verifying of L11 is pressed to remain unchanged.

For example, the verifying and latch of L11 (Gray code " 0010 ") may include following operation:

A) BUS charging BUS=1, draws high TDL=1.

C) BUS charging BUS=1, reads ADL, BDL, DDL, SDL, TDL, draws high ADL=1, BDL=1, DDL=1.If ADL =0, BDL=0, DDL=0, SDL=0, TDL=0, then ADL=1, BDL=1, DDL=1；Otherwise ADL=0, BDL=0, DDL =0.

In method 8000, the acceleration coding codeword of verifying voltage L11 is " 0010 ", and method 8000 includes: step S8062 verifies pulse L11 (that is, verifying voltage L11) to programmed storage unit；Step S8063, to programmed storage The latch of unit execution pulse L11；Step S8065, three " 0 " of detection (that is, detection ADL=BDL=DDL=0)；And step S8066 will meet above-mentioned steps S8066 and be locked by the data latches group of the storage unit of the verifying of verifying voltage L11 Save as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, it will be without full Sufficient above-mentioned steps S8066 and/or not over verifying voltage L11 verifying storage unit data latches group state protect It holds constant.

For example, the verifying and latch of L11 (accelerating coding " 0010 ") may include following operation:

BUS charging BUS=1, draws high TDL=1, reads ADL, BDL, DDL, TDL, SDL, then draw high ADL=1, BDL=1, DDL=1.If ADL=0, BDL=0, DDL=0, TDL=0, SDL=0, then ADL=1, BDL=1, DDL=1, otherwise ADL= 0, BDL=0, DDL=0.

Therefore, compared to Gray code, accelerate coding that can save step S864, so that operation number is reduced, accelerate Program speed, while reducing power consumption.

In method 800, the Gray code code word of verifying voltage L12 is " 0000 ", method 800 further include: step S867, Pulse L12 (that is, verifying voltage L12) is verified to programmed storage unit；Step S868 executes programmed storage unit The latch of pulse L12；Step S869, four " 0 " of detection (that is, detection ADL=BDL=CDL=DDL=0)；And step S870 will meet above-mentioned steps S869 and be latched by the data latches group of the storage unit of the verifying of verifying voltage L12 For " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, will it not meet Above-mentioned steps S869 and/or not over verifying voltage L12 verifying storage unit data latches group state keep It is constant.

For example, the verifying and latch of L12 (Gray code " 0000 ") may include following operation:

A) BUS charging BUS=1, draws high TDL=1.

B) BUS charging BUS=1, reads ADL, BDL, CDL, DDL, SDL, TDL, draws high ADL=1, BDL=1, CDL=1, DDL=1,.If ADL=0, BDL=0, CDL=0, DDL=0, SDL=0, TDL=0, then ADL=1, BDL=1, CDL=1, DDL=1；Otherwise ADL=0, BDL=0, CDL=0, DDL=0.

In method 8000, the acceleration coding codeword of verifying voltage L12 is " 0011 ", method 8000 further include: step S8067 verifies pulse L12 (that is, verifying voltage L12) to programmed storage unit；Step S8068, to programmed storage The latch of unit execution pulse L12；Step S8069, two " 0 " of detection (that is, detection ADL=BDL=0)；And step S8070 will meet above-mentioned steps S8069 and be locked by the data latches group of the storage unit of the verifying of verifying voltage L12 Save as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, it will be without full Sufficient above-mentioned steps S8069 and/or not over verifying voltage L12 verifying storage unit data latches group state protect It holds constant.

For example, the verifying and latch of L12 (accelerating coding " 0011 ") may include following operation:

BUS charging BUS=1, draws high TDL=1, reads ADL, BDL, TDL, SDL, then draw high ADL=1, BDL=1.If ADL =0, BDL=0, TDL=0, SDL=0, then ADL=1, BDL=1, otherwise ADL=0, BDL=0.

Referring to Fig. 8 G, in method 800, the Gray code code word of verifying voltage L13 is " 0100 ", and method 800 includes: step Rapid S871 verifies pulse L13 (that is, verifying voltage L13) to programmed storage unit；Step S872, to programmed storage The latch of unit execution pulse L13；Step S873, three " 0 " of detection (that is, detection ADL=CDL=DDL=0)；And step S874 will meet above-mentioned steps S873 and be latched by the data latches group of the storage unit of the verifying of verifying voltage L13 For " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, will it not meet Above-mentioned steps S873 and/or not over verifying voltage L13 verifying storage unit data latches group state keep It is constant.

For example, the verifying and latch of L13 (Gray code " 0100 ") may include following operation:

A) BUS charging BUS=1, draws high TDL=1.

C) BUS charging BUS=1, reads ADL, CDL, DDL, SDL, TDL, draws high ADL=1, CDL=1, DDL=1.If ADL =0, CDL=0, DDL=0, SDL=0, TDL=0, then ADL=1, CDL=1, DDL=1；Otherwise ADL=0, CDL=0, DDL =0.

In method 8000, the acceleration coding codeword of verifying voltage L13 is " 0101 ", and method 8000 includes: step S8071 verifies pulse L13 (that is, verifying voltage L13) to programmed storage unit；Step S8072, to programmed storage The latch of unit execution pulse L13；Step S8073, two " 0 " of detection (that is, detection ADL=CDL=0)；And step S8074 will meet above-mentioned steps S8073 and be locked by the data latches group of the storage unit of the verifying of verifying voltage L13 Save as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, it will be without full Sufficient above-mentioned steps S8073 and/or not over verifying voltage L13 verifying storage unit data latches group state protect It holds constant.

For example, the verifying and latch of L13 (accelerating coding " 0101 ") may include following operation:

BUS charging BUS=1, draws high TDL=1, reads ADL, CDL, TDL, SDL, then draw high ADL=1, CDL=1.If ADL =0, CDL=0, TDL=0, SDL=0, then ADL=1, CDL=1, otherwise ADL=0, CDL=0.

In method 800, the Gray code code word of verifying voltage L14 is " 0110 ", method 800 further include: step S875, Pulse L14 (that is, verifying voltage L14) is verified to programmed storage unit；Step S876 executes programmed storage unit The latch of pulse L14；Step S877, two " 0 " of detection (that is, detection ADL=DDL=0)；And step S878, it will be in satisfaction It states step S877 and " 1111 " is latched as (that is, number by the data latches group of the storage unit of the verifying of verifying voltage L14 ADL=1, BDL=1, CDL=1, DDL=1 are latched as according to latch group)；Also, will not meet above-mentioned steps S877 and/ Or it is remained unchanged not over the state of data latches group of the storage unit of the verifying of verifying voltage L14.

For example, the verifying and latch of L14 (Gray code " 0110 ") may include following operation:

A) BUS charging BUS=1, draws high TDL=1.

D) BUS charging BUS=1, reads ADL, DDL, SDL, TDL, draws high ADL=1, DDL=1.If ADL=0, DDL=0, SDL=0, TDL=0, then ADL=1, DDL=1；Otherwise ADL=0, DDL=0.

In method 8000, the acceleration coding codeword of verifying voltage L14 is " 0110 ", method 8000 further include: step S8075 verifies pulse L14 (that is, verifying voltage L14) to programmed storage unit；Step S8076, to programmed storage The latch of unit execution pulse L14；Step S8077, two " 0 " of detection (that is, detection ADL=DDL=0)；And step S8078 will meet above-mentioned steps S8077 and be locked by the data latches group of the storage unit of the verifying of verifying voltage L14 Save as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, it will be without full Sufficient above-mentioned steps S8077 and/or not over verifying voltage L14 verifying storage unit data latches group state protect It holds constant.

For example, the verifying and latch of L14 (accelerating coding " 0110 ") may include following operation:

BUS charging BUS=1, draws high TDL=1, reads ADL, DDL, TDL, SDL, then draw high ADL=1, DDL=1.If ADL =0, DDL=0, TDL=0, SDL=0, then ADL=1, DDL=1, otherwise ADL=0, DDL=0.

Referring to Fig. 8 H, in method 800, the Gray code code word of verifying voltage L15 is " 0111 ", and method 800 includes: step Rapid S879 verifies pulse L15 (that is, verifying voltage L15) to programmed storage unit；Step S880, to programmed storage The latch of unit execution pulse L15；Step S881, one " 0 " of detection (that is, detection ADL=0)；And step S882, it will meet Above-mentioned steps S881 and " 1111 " are latched as by the data latches group of the storage unit of the verifying of verifying voltage L15

(that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, will it not meet Above-mentioned steps S881 and/or not over verifying voltage L15 verifying storage unit data latches group state keep It is constant.

For example, the verifying and latch of L15 (Gray code " 0111 ") may include following operation:

A) BUS charging BUS=1, draws high TDL=1.

E) BUS charging BUS=1, reads ADL, SDL, TDL, draws high ADL=1.If ADL=0, SDL=0, TDL=0, then ADL =1；Otherwise ADL=0.

In method 8000, the acceleration coding codeword of verifying voltage L15 is " 0111 ", and method 8000 includes: step S8079 verifies pulse L15 (that is, verifying voltage L15) to programmed storage unit；Step S8080, to programmed storage The latch of unit execution pulse L15；Step S8081, one " 0 " of detection (that is, detection ADL=0)；And step S8082, it will expire Sufficient above-mentioned steps S8081 and " 1111 " are latched as by the data latches group of the storage unit of the verifying of verifying voltage L15 (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, it will not meet above-mentioned steps It S8081 and/or is remained unchanged not over the state of data latches group of the storage unit of the verifying of verifying voltage L15.

For example, the verifying and latch of L15 (accelerating coding " 0111 ") may include following operation:

BUS charging BUS=1, draws high TDL=1, reads ADL, TDL, SDL, then draw high ADL=1.If ADL=0, TDL=0, SDL=0, then ADL=1, otherwise ADL=0.

Figure 10 is a kind of schematic frame of the more program bits devices 1000 for nand memory that the embodiment of the present disclosure provides Figure.As shown in Figure 10, device 1000 may include writing module 1002, transcoding module 1004, data scanning module 1006, Pre-programmed and authentication module 1007, programming authentication module 1010, latch scan module 1012, confirmation scanning at programming module 1008 Module 1014 and judgment module 1016.

Writing module 1002 is for programmed multi-bit data to be written in data latches group, the multi-bit According to for Gray code codeword.Writing module 1002 can 402 run memory 404 of processor in controller 102 as shown in Figure 4 The program instruction of middle storage is realized, and can execute more program bits sides of the nand memory according to the embodiment of the present disclosure The step S552 in step S502 and/or method 550 in method 500.

Transcoding module 1004 is used to the multi-bit data being converted to acceleration coding codeword from Gray code codeword.It compiles The program that code conversion module 1004 can store in 402 run memory 404 of processor in controller 102 as shown in Figure 4 Instruction can execute the step in more program bits methods 500 according to the nand memory of the embodiment of the present disclosure to realize Step S554 in rapid S504 and/or method 550.

Data scanning module 1006 needs programmed storage unit for determining in storage array, wherein needing to be programmed The storage unit include storage unit and target threshold voltage that target threshold voltage is greater than predetermined voltage no more than described The storage unit of predetermined voltage.For example, data scanning module 1006 determines storage letter for scanning the data latches group Breath is the data latches group of erase status and stores the data latches group that information is not erase status, will be with storage information The corresponding storage unit of data latches group of erase status is set as not programming state, and will not be to wipe with storage information Except the corresponding storage unit of data latches group of state is set as programming state, wherein need the programmed storage Unit is the storage unit for being arranged to programming state.Data scanning module 1006 can be in controller 102 as shown in Figure 4 The program instruction that stores in 402 run memory 404 of processor is realized, and can be executed according to the embodiment of the present disclosure Step S506 in more program bits methods 500 of nand memory and/or step S556 and S558 in method 550.

Each storage that pre-programmed and authentication module 1007 are used to for target threshold voltage being greater than the predetermined voltage is single Member is pre-programmed into intermediate state voltage.Programming module 1007 can the operation of processor 402 in controller 102 as shown in Figure 4 deposit The program instruction stored in reservoir 404 realizes, and can execute more comparing according to the nand memory of the embodiment of the present disclosure The step S559 in step S508 and/or method 550 in special programmed method 500.

Programming module 1008 is used for needing programmed storage unit to be programmed in storage array.For example, programming mould Block 1008 is used for: each storage unit to target threshold voltage no more than the predetermined voltage is programmed；And to mesh Each storage unit that mark threshold voltage is greater than the predetermined voltage is programmed.Programming module 1008 can be as shown in Figure 4 Controller 102 in 402 run memory 404 of processor in the program instruction that stores realize, and basis can be executed In step S510 and S515 and/or method 550 in more program bits methods 500 of the nand memory of the embodiment of the present disclosure S560 and S572.

Authentication module 1010 is programmed to be used to execute programming verification operation to programmed each storage unit.For example, compiling Journey authentication module 1010 is used for: being not more than each storage unit of the predetermined voltage to target threshold voltage, is executed programming Verification operation；And it is greater than each storage unit of the predetermined voltage to target threshold voltage, execute programming verification operation. The journey that programming authentication module 1010 can store in 402 run memory 404 of processor in controller 102 as shown in Figure 4 Sequence instructs to realize, and can execute in more program bits methods 500 according to the nand memory of the embodiment of the present disclosure Programming verification operation, Fig. 6 B of method 600 in step S562 and S574, Fig. 6 A in step S510 and step S516, method 550 Programming verification operation in the programming verification operation of middle method 630, the programming verification operation and Fig. 8 A-8H in Fig. 7 A-7P.

Scan module 1012 is latched to be used to execute latch scan operation to programmed each storage unit.For example, lock It deposits scan module 1012 to be used for: being not more than each storage unit of the predetermined voltage to target threshold voltage, execute latch Scan operation；And it is greater than each storage unit of the predetermined voltage to target threshold voltage, it executes and latches scan operation. Latch the journey that scan module 1012 can store in 402 run memory 404 of processor in controller 102 as shown in Figure 4 Sequence instructs to realize, and can execute in more program bits methods 500 according to the nand memory of the embodiment of the present disclosure The volume of method 600 latches scan operation, in Fig. 6 B in step S564 and S576, Fig. 6 A in step S512 and S518, method 550 Method 630 latches scan operation, the latch scan operation in Fig. 7 A-7P and the latch scan operation in Fig. 8 A-8H.

Confirm that scan module 1014 is used to execute confirmation scan operation to programmed each storage unit.For example, really Recognize scan module 1014 to be used for: being not more than each storage unit of the predetermined voltage to target threshold voltage, execute confirmation Scan operation；And it is greater than each storage unit of the predetermined voltage to target threshold voltage, execute confirmation scan operation. The journey that confirmation scan module 1014 can store in 402 run memory 404 of processor in controller 102 as shown in Figure 4 Sequence instructs to realize, and can execute in more program bits methods 500 according to the nand memory of the embodiment of the present disclosure Step S514 and S520, the confirmation scan operation of method 600 in step S566 and S578, Fig. 6 A in method 550, in Fig. 6 B The confirmation scan operation of method 630 confirmed in scan operation and Fig. 7 A-7P.

Judgment module 1016 is used for, and is tested executing programming to programmed storage unit using one or more verifying voltages Card operation after latching scan operation and confirmation scan operation, determines whether also to need in the programmed storage unit There are one or more storage units that respective target threshold voltage has not yet been reached in this programming.It is there are one if or multiple Respective target threshold voltage has not yet been reached in storage unit in this programming, and the programming module 1008 is to one or more A storage unit is programmed again；The programming authentication module 1010 executes programming to one or more of storage units and tests Card operation；The latch scan module 1012 executes one or more of storage units and latches scan operation；And it is described Confirm that scan module 1014 executes confirmation scan operation to one or more of storage units.The judgment module 1016 can be with The program instruction that stores in 402 run memory 404 of processor in controller 102 as shown in Figure 4 realizes, and can be with Execute according in more program bits methods 550 of the nand memory of the embodiment of the present disclosure step S568, S570, S580 and S582。

In addition, additionally providing a kind of storage medium according to the embodiment of the present disclosure, storing program on said storage Instruction, when described program instruction is run by computer or processor for execute the embodiment of the present disclosure nand memory it is more The corresponding steps of program bits method and/or other methods, and for realizing according to the nand memory of the embodiment of the present disclosure More program bits devices in corresponding module.The storage medium for example may include the storage card of smart phone, plate electricity The storage unit of brain, the hard disk of personal computer, read-only memory (ROM), Erasable Programmable Read Only Memory EPROM (EPROM), Portable compact disc read-only memory (CD-ROM), any combination of USB storage or above-mentioned storage medium.

Although describing example embodiment by reference to attached drawing here, it should be understood that above example embodiment are only exemplary , and be not intended to the scope of the present disclosure limited to this.Those of ordinary skill in the art can carry out various changes wherein And modification, without departing from the scope of the present disclosure and spirit.All such changes and modifications are intended to be included in appended claims Within required the scope of the present disclosure.

Claims

1. a kind of more program bits methods of nand memory, comprising:

Data latches group is written into programmed multi-bit data, the multi-bit data is Gray code codeword；

By accelerating coding that the multi-bit data is converted to acceleration coding codeword from the Gray code codeword；

It determines and needs programmed storage unit in storage array, needing the programmed storage unit includes targets threshold electricity Pressure is not more than the storage unit of the predetermined voltage greater than the storage unit and target threshold voltage of predetermined voltage；

Each storage unit that target threshold voltage is greater than the predetermined voltage is pre-programmed into intermediate state voltage；

Each storage unit to target threshold voltage no more than the predetermined voltage is programmed；

It is not more than each storage unit of the predetermined voltage to target threshold voltage:

Execute programming verification operation；

It executes and latches scan operation；And

Execute confirmation scan operation；

Each storage unit for being greater than the predetermined voltage to target threshold voltage is programmed；And

It is greater than each storage unit of the predetermined voltage to target threshold voltage:

Execute programming verification operation；

It executes and latches scan operation；And

Confirmation scan operation is executed,

Wherein, the acceleration coding includes encoding to multiple voltage class, wherein the corresponding acceleration coding of low-voltage-grade The number of " 0 " that includes in code word is no less than the number of corresponding " 0 " for accelerating to include in coding codeword of voltage levels, and

For the voltage class including equal " 0 " number, by converting Gray code codeword corresponding with the voltage class most A small number of purpose data latches obtain the acceleration coding codeword of the voltage class.

2. the method for claim 1, wherein target threshold voltage is greater than the storage unit of the predetermined voltage Accelerate the storage unit that the highest order of coding codeword is 0, target threshold voltage is not more than the storage list of the predetermined voltage Member is to accelerate the storage unit that the highest order of coding codeword is 1.

3. the method for claim 1, wherein

It is not more than each storage unit of the predetermined voltage to target threshold voltage, executing programming verification operation includes:

It selects the first verifying voltage, and verifies and be incorporated into the voltage of each storage unit and whether reach the first verifying electricity Pressure；

It is not more than each storage unit of the predetermined voltage to target threshold voltage, executing latch scan operation includes:

By the storage by the programming verifying and target threshold voltage of first verifying voltage for first verifying voltage The data latches group of unit is set as latch mode, and will not by the programming verifying of first verifying voltage and/or Target threshold voltage is not that the state of the data latches group of the storage unit of first verifying voltage remains unchanged；

It is not more than each storage unit of the predetermined voltage to target threshold voltage, executing confirmation scan operation includes:

It is the storage unit of latch mode for data latches group, is judged that latch is set as successfully latch mode, with And be not the storage unit of latch mode for data latches group, judged that latch is set as latching unsuccessful state.

4. method as claimed in claim 3, wherein the programming verifying of first verifying voltage and targets threshold will be passed through Voltage is that the data latches group of the storage unit of first verifying voltage is set as latch mode, and will not pass through described The programming verifying of first verifying voltage and/or target threshold voltage are not the data locks of the storage unit of first verifying voltage The state of storage group remains unchanged, comprising:

Whether the highest order for detecting the acceleration coding codeword of the corresponding data latches group storage of the storage unit is " 1 ", inspection Survey in the acceleration coding codeword of the storage unit corresponding data latches group storage the quantity of " 0 " and position whether with it is described First verifying voltage is corresponding to accelerate the quantity of " 0 " and position in coding codeword consistent, and detects the storage unit pair Whether the voltage verification latch answered is to pass through state；

If the highest order of the acceleration coding codeword of the corresponding data latches group storage of the storage unit is " 1 ", described to deposit The quantity of " 0 " and position and first verifying voltage in the acceleration coding codeword of the corresponding data latches group storage of storage unit The quantity of " 0 " and position are consistent in corresponding acceleration coding codeword, and the corresponding voltage verification latch of the storage unit For by state, it is latch mode that data latches group corresponding with the storage unit, which is arranged,；And

If the highest order of the acceleration coding codeword of the corresponding data latches group storage of the storage unit is not " 1 ", and/or The quantity of " 0 " and position are tested with described first in the acceleration coding codeword of the corresponding data latches group storage of the storage unit Card voltage is corresponding to accelerate the quantity of " 0 " in coding codeword and position is inconsistent and/or the corresponding voltage of the storage unit is tested Demonstrate,proving latch is to keep the state of data latches group corresponding with the storage unit constant not by state.

5. the method for claim 1, wherein

It is greater than each storage unit of the predetermined voltage to target threshold voltage, executing programming verification operation includes:

It selects the second verifying voltage, and verifies and be incorporated into the voltage of each storage unit and whether reach the second verifying electricity Pressure, second verifying voltage are greater than the intermediate state voltage；

It is greater than each storage unit of the predetermined voltage to target threshold voltage, executing latch scan operation includes:

By the storage by the programming verifying and target threshold voltage of second verifying voltage for second verifying voltage The data latches group of unit is set as latch mode, and will not by the programming verifying of second verifying voltage and/or Target threshold voltage is not that the state of the data latches group of the storage unit of second verifying voltage remains unchanged；

It is greater than each storage unit of the predetermined voltage to target threshold voltage, executing confirmation scan operation includes:

6. method as claimed in claim 5, wherein the programming verifying of second verifying voltage and targets threshold will be passed through Voltage is that the data latches group of the storage unit of second verifying voltage is set as latch mode, and will not pass through described The programming verifying of second verifying voltage and/or target threshold voltage are not the data locks of the storage unit of second verifying voltage The state of storage group remains unchanged, comprising:

Whether detect in the acceleration coding codeword of the storage unit corresponding data latches group storage the quantity of " 0 " and position It is corresponding with second verifying voltage to accelerate the quantity of " 0 " and position in coding codeword consistent, and detect the storage Whether the corresponding voltage verification latch of unit is to pass through state；

If the quantity of " 0 " and position and institute in the acceleration coding codeword of the corresponding data latches group storage of the storage unit It is consistent to state the quantity of " 0 " and position in the corresponding acceleration coding codeword of the second verifying voltage, and the storage unit is corresponding Voltage verification latch is by state, and it is latch mode that data latches group corresponding with the storage unit, which is arranged,；And

If the quantity of " 0 " and position and institute in the acceleration coding codeword of the corresponding data latches group storage of the storage unit State that the second verifying voltage is corresponding to accelerate the quantity of " 0 " in coding codeword and position is inconsistent and/or the storage unit is corresponding Voltage verification latch be to keep the state of data latches group corresponding with the storage unit constant not by state.

7. the method for claim 1, wherein determining in storage array needs the programmed storage unit to include:

The data latches group is scanned to determine that store the data latches group that information is erase status is not with storage information The data latches group of erase status；

It will be that the corresponding storage unit of the data latches group of erase status is set as not programming state with storage information；And

It will not be that the corresponding storage unit of the data latches group of erase status is set as programming state with storage information, In, needing the programmed storage unit is to be arranged to the storage unit of programming state.

8. the method for claim 1, wherein acceleration coding codeword of first part's voltage class of the voltage class Highest order be the highest order of acceleration coding codeword of second part voltage class of " 0 " and the voltage class be " 1 ", First part's voltage class is all larger than the second part voltage class.

9. a kind of more program bits devices of nand memory, comprising:

Writing module, for programmed multi-bit data to be written in data latches group, the multi-bit data is lattice Thunder code code word；

Transcoding module, for being compiled by accelerating coding that the multi-bit data is converted to acceleration from the Gray code codeword Code code word；

Data scanning module needs programmed storage unit for determining in storage array, need the programmed storage Unit includes the storage unit that target threshold voltage is greater than predetermined voltage and target threshold voltage no more than the predetermined voltage Storage unit；

Pre-programmed and authentication module, the storage unit for target threshold voltage to be greater than the predetermined voltage are pre-programmed into Intermediate state voltage；

Programming module, for being not more than the storage unit and targets threshold of the predetermined voltage to target threshold voltage respectively The storage unit that voltage is greater than the predetermined voltage is programmed；

Authentication module is programmed, for being not more than the storage unit and target of the predetermined voltage to target threshold voltage respectively The storage unit that threshold voltage is greater than the predetermined voltage executes programming verification operation；

Scan module is latched, for being not more than the storage unit and target of the predetermined voltage to target threshold voltage respectively The storage unit that threshold voltage is greater than the predetermined voltage, which executes, latches scan operation；And

Scan module is confirmed, for being not more than the storage unit and target of the predetermined voltage to target threshold voltage respectively The storage unit that threshold voltage is greater than the predetermined voltage executes confirmation scan operation,

10. device as claimed in claim 9, wherein target threshold voltage is greater than the storage unit of the predetermined voltage To accelerate the storage unit that the highest order of coding codeword is 0, target threshold voltage is not more than the storage of the predetermined voltage Unit is to accelerate the storage unit that the highest order of coding codeword is 1.

11. device as claimed in claim 9, wherein

It is not more than each storage unit of the predetermined voltage to target threshold voltage, programming authentication module executes programming verifying Operation includes:

It is not more than each storage unit of the predetermined voltage to target threshold voltage, latches scan module and execute latch scanning Operation includes:

It is not more than each storage unit of the predetermined voltage to target threshold voltage, confirmation scan module executes confirmation scanning Operation includes:

12. device as claimed in claim 11, wherein latching scan module will be tested by the programming of first verifying voltage Card and target threshold voltage are that the data latches group of the storage unit of first verifying voltage is set as latch mode, with It and will not be depositing for first verifying voltage not by the programming verifying of first verifying voltage and/or target threshold voltage The state of the data latches group of storage unit remains unchanged, comprising:

13. device as claimed in claim 9, wherein

It is greater than each storage unit of the predetermined voltage to target threshold voltage, programming authentication module executes programming verifying behaviour Work includes:

It is greater than each storage unit of the predetermined voltage to target threshold voltage, latches scan module and execute latch scanning behaviour Work includes:

It is greater than each storage unit of the predetermined voltage to target threshold voltage, confirmation scan module executes confirmation scanning behaviour Work includes:

14. device as claimed in claim 13, wherein latching scan module will be tested by the programming of second verifying voltage Card and target threshold voltage are that the data latches group of the storage unit of second verifying voltage is set as latch mode, with It and will not be depositing for second verifying voltage not by the programming verifying of second verifying voltage and/or target threshold voltage The state of the data latches group of storage unit remains unchanged, comprising:

15. device as claimed in claim 9, wherein data scanning module, which determines, needs programmed storage in storage array Unit, comprising: