CN105719694A

CN105719694A - Multi-bit programming method and device of NAND memory

Info

Publication number: CN105719694A
Application number: CN201610046803.XA
Authority: CN
Inventors: 靳旭; 伍冬; 吴华强; 钱鹤; 曹堪宇; 朱一明
Original assignee: Tsinghua University; GigaDevice Semiconductor Beijing Inc
Current assignee: Zhaoyi Innovation Technology Group Co ltd; Tsinghua University
Priority date: 2016-01-22
Filing date: 2016-01-22
Publication date: 2016-06-29
Anticipated expiration: 2036-01-22
Also published as: CN105719694B

Abstract

Provided are a multi-bit programming method and device of an NAND memory. The method comprises: writing multi-bit data to be programmed into a data latch set; converting the multi-bit data from Gray code codon into accelerating encoding codon; determining, in a storage array, storage units to be programmed with a target threshold voltage greater than a preset voltage and storage units with a target threshold voltage not greater than the preset voltage; programming the storage units with the target threshold voltage greater than the preset voltage to an intermediate stage voltage; subjecting the storage units with the target threshold voltage not greater than the preset voltage to programming, programming verification, latching scanning and confirm scanning; subjecting the storage units with the target threshold voltage greater than the preset voltage to programming, programming verification, latching scanning and confirm scanning. The code herein is redesigned according to the structure of a latch, complex redundant operations in the programming process are reduced, and thereby programming speed can be increased and power consumption can be reduced.

Description

Many program bits method of nand memory and device

Technical field

The disclosure generally relates to many program bits method and the device thereof of a kind of NAND (NAND gate) memorizer.

Background technology

Each memory element of nand flash memory can storing multi-bit data, namely each memory element can store the electric pressure corresponding with corresponding many bits (bit) data.Such as, each memory element of nand flash memory can store the data of 4 bits, i.e. each memory element storage 2⁴An electric pressure in=16 electric pressures.When nand flash memory memory element stores, it is necessary to stored multi-bit data is encoded, and generally can use Gray code to reduce error rate.In Gray code, the code that any two is adjacent only has a bit different, and it is different also to only have a bit between maximum number from minimum number.But, in the programming process of NAND-flash memory, Gray code is adaptive circuit structure not, so that the operation in cataloged procedure becomes complicated loaded down with trivial details.Such as, in realizing cataloged procedure, owing to Gray code is not optimized according to the circuit structure encoded, so using Gray's code table to be made directly programming will cause the operation of bulk redundancy, increase power consumption and programming time.And, along with the increase of the bit number that each memory element stores, directly use Gray code to be programmed making the operation in cataloged procedure become more complicated loaded down with trivial details and increase more power consumption and programming time.

Summary of the invention

Embodiment of the disclosure the many program bits method and device that provide a kind of nand memory, it is possible to remapped by coding before programming, thus optimizing programming process.

At least one embodiment of the disclosure provides a kind of many program bits method of nand memory, including: being programmed that multi-bit data write data bank of latches, described multi-bit data is Gray code codeword；Described multi-bit data is converted to speech coding code word from described Gray code codeword；Determine and storage array needs be programmed that memory element, it is necessary to be programmed that described memory element includes target threshold voltage and is not more than the memory element of described predetermined voltage more than the memory element of predetermined voltage and target threshold voltage；Target threshold voltage is pre-programmed into intermediate state voltage more than each described memory element of described predetermined voltage；The each described memory element that target threshold voltage is not more than described predetermined voltage is programmed；Target threshold voltage is not more than each described memory element of described predetermined voltage: perform programming verification operation, performs latch scan operation and perform to confirm scan operation；Target threshold voltage is programmed more than each described memory element of described predetermined voltage；And to the target threshold voltage each described memory element more than described predetermined voltage: perform programming verification operation, perform latch scan operation and perform to confirm scan operation.

At least one embodiment of the disclosure additionally provides many program bits device of a kind of nand memory, including: writing module, for being programmed that multi-bit data is written in data latches group, described multi-bit data is Gray code codeword；Transcoding module, for being converted to speech coding code word by described multi-bit data from described Gray code codeword；Data scanning module, being used for determining in storage array needs to be programmed that memory element, it is necessary to be programmed that described memory element includes target threshold voltage and is not more than the memory element of described predetermined voltage more than the memory element of predetermined voltage and target threshold voltage；Pre-programmed and authentication module, for being pre-programmed into intermediate state voltage by target threshold voltage more than the described memory element of described predetermined voltage；Programming module, is programmed more than the described memory element of described predetermined voltage for the described memory element and target threshold voltage that target threshold voltage is not more than described predetermined voltage respectively；Programming authentication module, performs programming verification operation for the described memory element and target threshold voltage that target threshold voltage is not more than described predetermined voltage respectively more than the described memory element of described predetermined voltage；Latch scan module, perform to latch scan operation more than the described memory element of described predetermined voltage for the described memory element and target threshold voltage that target threshold voltage is not more than described predetermined voltage respectively；And confirmation scan module, perform to confirm scan operation more than the described memory element of described predetermined voltage for the described memory element and target threshold voltage that target threshold voltage is not more than described predetermined voltage respectively.

Such as, target threshold voltage is more than the memory element that the highest order that described memory element is speech coding code word is 0 of described predetermined voltage, and target threshold voltage is not more than the memory element that the highest order that described memory element is speech coding code word is 1 of described predetermined voltage.

Such as, target threshold voltage is not more than each described memory element of described predetermined voltage, programming authentication module performs programming verification operation and includes: selects the first verifying voltage, and verifies whether the voltage having enrolled each described memory element reaches described first verifying voltage.Target threshold voltage is not more than each described memory element of described predetermined voltage, latch scan module to perform to latch scan operation and include: latch mode will be set to by the programming checking of described first verifying voltage and the data latches group of memory element that target threshold voltage is described first verifying voltage, and the programming checking of described first verifying voltage will do not passed through and/or target threshold voltage is not that the state of data latches group of memory element of described first verifying voltage remains unchanged.Target threshold voltage is not more than each described memory element of described predetermined voltage, confirm that scan module performs to confirm that scan operation includes: be the memory element of latch mode for data latches group, judged that latch is set to successfully latch mode, and be not the memory element of latch mode for data latches group, judged that latch is set to latch unsuccessful state.

Such as, latch scan module and will be set to latch mode by the data latches group of the memory element that programming is verified and target threshold voltage is described first verifying voltage of described first verifying voltage, and the programming checking of described first verifying voltage will do not passed through and/or target threshold voltage is not that the state of data latches group of memory element of described first verifying voltage remains unchanged, including: whether the highest order of the speech coding code word detecting data latches group storage corresponding to described memory element is " 1 ", quantity and the position of detecting " 0 " in the speech coding code word that in the speech coding code word of data latches group storage corresponding to described memory element, whether the quantity of " 0 " is corresponding with described first verifying voltage with position are consistent, and whether detect voltage verification latch corresponding to described memory element for passing through state；If the highest order of the speech coding code word of the data latches group storage that described memory element is corresponding is " 1 ", in the speech coding code word that in the speech coding code word of the data latches group storage that described memory element is corresponding, the quantity of " 0 " is corresponding with described first verifying voltage with position, the quantity of " 0 " and position are consistent, and voltage verification latch corresponding to described memory element is by state, arranging the data latches group corresponding with described memory element is latch mode；And if the highest order of speech coding code word of data latches group storage corresponding to described memory element is not " 1 ", and/or the quantity of " 0 " and position are inconsistent in the speech coding code word that in the speech coding code word of data latches group storage corresponding to described memory element, the quantity of " 0 " is corresponding with described first verifying voltage with position, and/or voltage verification latch corresponding to described memory element is that the state keeping the data latches group corresponding with described memory element is constant not by state.

Such as, to the target threshold voltage each described memory element more than described predetermined voltage, programming authentication module performs programming verification operation and includes: select the second verifying voltage, and verifying whether the voltage having enrolled each described memory element reaches described second verifying voltage, described second verifying voltage is more than described intermediate state voltage.To the target threshold voltage each described memory element more than described predetermined voltage, latch scan module to perform to latch scan operation and include: latch mode will be set to by the programming checking of described second verifying voltage and the data latches group of memory element that target threshold voltage is described second verifying voltage, and the programming checking of described second verifying voltage will do not passed through and/or target threshold voltage is not that the state of data latches group of memory element of described second verifying voltage remains unchanged.To the target threshold voltage each described memory element more than described predetermined voltage, confirm that scan module performs to confirm that scan operation includes: be the memory element of latch mode for data latches group, judged that latch is set to successfully latch mode, and be not the memory element of latch mode for data latches group, judged that latch is set to latch unsuccessful state.

Such as, latch scan module and will be set to latch mode by the data latches group of the memory element that programming is verified and target threshold voltage is described second verifying voltage of described second verifying voltage, and the programming checking of described second verifying voltage will do not passed through and/or target threshold voltage is not that the state of data latches group of memory element of described second verifying voltage remains unchanged, including: quantity and the position of detecting " 0 " in the speech coding code word that in the speech coding code word of data latches group storage corresponding to described memory element, whether the quantity of " 0 " is corresponding with described second verifying voltage with position are consistent, and whether detect voltage verification latch corresponding to described memory element for passing through state；If the quantity of " 0 " and position are consistent in the speech coding code word that in the speech coding code word of the data latches group storage that described memory element is corresponding, the quantity of " 0 " is corresponding with described second verifying voltage with position, and voltage verification latch corresponding to described memory element is by state, arranging the data latches group corresponding with described memory element is latch mode；And if the quantity of " 0 " and position are inconsistent in the speech coding code word that in the speech coding code word of data latches group storage corresponding to described memory element, the quantity of " 0 " is corresponding with described second verifying voltage with position, and/or voltage verification latch corresponding to described memory element is that the state keeping the data latches group corresponding with described memory element is constant not by state.

Such as, data scanning module is determined to be needed in storage array to be programmed that memory element, including: scan described data latches group to determine that data latches group that storage information is erasing state and storage information are not the data latches groups of erasing state；The memory element corresponding with the data latches group that storage information is erasing state is set to not programming state；And memory element corresponding for the data latches group with storage information not being erasing state is set to programming state, wherein it is desired to it is programmed that described memory element is the memory element being set to programming state.

At least one embodiment of the disclosure additionally provides a kind of storage medium, store programmed instruction on said storage, when described programmed instruction is run by computer or processor for performing the many program bits method of nand memory that embodiment of the disclosure, and for realizing the many program bits device according to the nand memory that embodiment of the disclosure.

Many program bits method of the nand memory that disclosure embodiment provides and device, redesign coding according to the structure of latch, decreases the quantity of redundant operation complicated in programming process, thus can accelerate the speed programmed, reduces power consumption.

Accompanying drawing explanation

Embodiment of this disclosure in conjunction with the drawings is described in more detail, and above-mentioned and other purpose, feature and the advantage of the disclosure will be apparent from.Accompanying drawing is for providing being further appreciated by disclosure embodiment, and constitutes a part for description, for explaining the disclosure together with embodiment of the disclosure, is not intended that restriction of this disclosure.In the accompanying drawings, identical reference number typically represents same parts or step.

The schematic block diagram of the multiple bit unit storage array that Fig. 1 provides for disclosure embodiment；

The schematic block diagram of the sense amplifier that Fig. 2 provides for disclosure embodiment；

The example arrangement of the latch that Fig. 3 provides for disclosure embodiment；

The schematic block diagram of the control circuit that Fig. 4 provides for disclosure embodiment；

One of indicative flowchart of many program bits method of a kind of nand memory that Fig. 5 A provides for disclosure embodiment；

The two of the indicative flowchart of many program bits method of a kind of nand memory that Fig. 5 B and 5C provides for disclosure embodiment；

One of a kind of indicative flowchart of method programming checking and latch that Fig. 6 A provides for disclosure embodiment；

The two of the indicative flowchart of a kind of method programming checking and latch that Fig. 6 B provides for disclosure embodiment；

The illustrative profiles of four bit unit threshold voltages that Fig. 6 C provides for disclosure embodiment；

The programming pulse of four Bit datas that Fig. 6 D provides for disclosure embodiment and the illustrative profiles of verifying voltage；

The exemplary programming process of four Bit datas that Fig. 7 A-7P provides for disclosure embodiment；

The indicative flowchart of the programming checking of the speech coding of a kind of four Bit datas that Fig. 8 A-8H provides for disclosure embodiment and the method for latch；

The four exemplary bit speech coding code tables that Fig. 9 provides for disclosure embodiment；And

The schematic block diagram of many program bits device of a kind of nand memory that Figure 10 provides for disclosure embodiment.

Detailed description of the invention

So that the purpose of the disclosure, technical scheme and advantage become apparent from, example embodiment according to the disclosure is described in detail below with reference to accompanying drawings.Obviously, described embodiment is only a part of this disclosure embodiment, rather than whole embodiments of the disclosure, it should be appreciated that the disclosure is not by the restriction of example embodiment described herein.Based on the disclosure embodiment described in the disclosure, those skilled in the art's all other embodiments obtained when not paying creative work all should fall within the protection domain of the disclosure.

Embodiment of the disclosure the many program bits method and device that provide a kind of nand memory, it is possible to remapped by coding before programming, thus optimizing programming process.Many program bits method of the nand memory that disclosure embodiment provides and device, structure according to latch redesigns coding, multi-bit data is converted to corresponding speech coding code word from Gray code codeword, decrease the quantity of redundant operation complicated in programming process, thus the speed programmed can be accelerated, reduce power consumption.Many program bits method of the nand memory that disclosure embodiment provides and device, it is possible to be applied to the programming more than or equal to two bits of data, for instance, the programming of the multi-bit datas such as four Bit datas, five Bit datas and/or six Bit datas.

In the disclosed embodiments, nand memory can be two dimension nand memory, it is also possible to being three dimensional NAND memory, this is not limited by the disclosure.Three dimensional NAND memory improves the problems such as the narrow threshold value distribution in many bit storage of the plane nand memory, serious floating boom coupling so that three dimensional NAND memory increases the storage capacity of each memory element and is possibly realized.

The schematic block diagram of a kind of system 100 including multiple bit unit storage array that Fig. 1 provides for disclosure embodiment.As it is shown in figure 1, system 100 can include peripheral circuit 101, line decoder 104, column decoder 106, storage array 108, sense amplifier 110 and input/output interface 112.In certain embodiments, system 100 can also include other unshowned parts, for instance, manostat (voltageregulator), logic circuit (logiccircuits) etc..

Peripheral circuit 101 is be in the circuit structure outside storage array 108.Peripheral circuit 101 can include control circuit 102.Control circuit 102 can control the address choice of storage array 108.Such as, control circuit 102 can control line decoder 104 so that line decoder 104 selects the row address of storage array 108 by wordline 114；Control circuit 102 can also control column decoder 106 so that column decoder 106 selects the column address of storage array by bit line 116.Control circuit 102 can also control the programming process of storage array 108.Such as, as described below, control circuit 102 can control the execution of the method 800 and 8000 of the method 500 of Fig. 5 A, the method 550 of Fig. 5 B and 5C, the method 600 of Fig. 6 A, the method 630 of Fig. 6 B and Fig. 8 A-8H.

Referring to Fig. 4, control circuit 102 can include processor 402, memorizer 404 and other unshowned parts.Can intercommunication directly or indirectly between each parts of control circuit 102, for instance, each parts of control circuit 102 can send mutually and receive data and/or signal.Again such as, can be connected by bus between each parts of control circuit 102.In certain embodiments, control circuit 102 can include one or more processor 402 and one or more memorizer 404.

Processor 402 can process data signal, it is possible to includes various computation structure, for instance complex instruction set computer (CISC) (CISC) structure, structure Reduced Instruction Set Computer (RISC) structure or a kind of structure carrying out the combination of multiple instruction set.In certain embodiments, processor 402 can also be microprocessor, for instance X 86 processor or arm processor, or can be digital processing unit (DSP) etc..Processor 402 can control other assembly in control circuit 102 to perform desired function.

Memorizer 404 can preserve instruction and/or the data that processor 402 performs.Such as, memorizer 404 can include one or more computer program, and described computer program can include various forms of computer-readable recording medium, for instance volatile memory and/or nonvolatile memory.Described volatile memory such as can include random access memory (RAM) and/or cache memory (cache) etc..Described nonvolatile memory such as can include read only memory (ROM), hard disk, flash memory etc..Described computer-readable recording medium can store one or more computer program instructions, processor 402 can run described programmed instruction, to realize many program bits function and/or other desired function of (being realized by processor) in disclosure embodiment hereinafter described.Described computer-readable recording medium can also store various application program and various data, for instance the various data etc. that described application program uses and/or produces.

Referring to Fig. 1, storage array 108 can use voltage status to determine the size of the multi-bit data of storage.Such as, each memory element of storage array 108 can store a multi-bit data, and namely each memory element can store the electric pressure corresponding with this multi-bit data.Again such as, Fig. 6 C illustrates the threshold voltage V of four bit memory cell_thScattergram 655, it includes erasing state (erase, ER) and L1-L15 totally 2⁴=16 electric pressures.Numerical values recited according to stored multi-bit data, each memory element can store one in electric pressure.

Input/output interface 112 can provide input data (such as to sense amplifier 110, there is provided and need to be programmed into the multi-bit data of storage array 108), and receive the output data (such as, receiving the data read from storage array 108) of sense amplifier 110.Input/output interface 112 can be USB (universal serial bus) (universalserialbus, USB) interface, thunder and lightning (thunderbolt) interface or other feasible interface types, and this is not construed as limiting by the disclosure.In certain embodiments, input/output interface 112 can also as peripheral circuit 101 parts.

In certain embodiments, in the memory element of storage array 108, the current value of storage is corresponding with the threshold voltage level of this memory element, the current value that this memory element stores can be converted to digital numerical value (such as, multi-bit value) by sense amplifier 110.Sense amplifier 110 can be connected with one or more bit lines 116.

Fig. 2 illustrates the exemplary block diagram 200 of sense amplifier 110.Sense amplifier 110 can include buffer lock storage 202, data latches group 203, sensor circuit 214 and induction lock storage 216.Each parts of sense amplifier 110 can pass through bus 218 and be connected with each other.In certain embodiments, the number of the data latches of each data latches group 203 in sense amplifier 110 is identical with the bit number of the numerical value that each memory element stores；Or, the bit number of the numerical value that the number of the data latches in each data latches group 203 in sense amplifier 110 stores more than each memory element.Such as, each memory element of storage array 108 can store the numerical value of four bits, each data latches group 203 of sense amplifier 110 at least can include four data latches, i.e. the first data latches the 204, second data latches the 206, the 3rd data latches 208 and the 4th latch 210 as shown in Figure 2.Or, each data latches group 203 of sense amplifier 110 can also include other data latches, for instance, ephemeral data latch 212 as shown in phantom in Figure 2.As in figure 2 it is shown, the bus of each latch of sense amplifier 110 links together.

In certain embodiments, storage array 108 is programmed with " OK " for unit；That is, by row, the memory element of storage array 108 is programmed, and in the programming of each row, will be simultaneously programmed with the memory element that be there is a need to programming of a line.Therefore, identical with the number of the memory element included in a line of storage array 108 including the number of the induction lock storage 216 in sense amplifier 110；That is, each induction lock storage 216 and each memory element in a line are relation one to one.It addition, the number of the data latches group 203 included in sense amplifier 110 is also identical with the number of the memory element included in a line of storage array 108；That is, each data latches group 203 and each memory element in a line are relation one to one.

Fig. 3 illustrates the exemplary circuit diagram of latch 300.In the latch 300 of Fig. 3, " X " represents the data of latch 300 storage, " INVX " represents the anti-of the data of storage, " SETX " represents storage data set signal, " RETX " represents storage data reset signal, VDD represents supply voltage, and READ represents read signal and " BUS " represents bus.The structure of the buffer lock storage 202 in Fig. 2, sensitive latch the 216, first data latches the 204, second data latches the 206, the 3rd data latches the 208, the 4th latch 210 and interim latch 212 all can be same or similar with the structure of latch 300, does not repeat them here.

One of indicative flowchart of many program bits method 500 of a kind of nand memory that Fig. 5 A provides for disclosure embodiment.In certain embodiments, method 500 can include the some or all of step shown in Fig. 5 A.Certainly, method 500 can also include other steps not illustrated in fig. 5.In the following description, method 500 is described in detail by the structure of the sense amplifier 110 in conjunction with Fig. 2.

First, in step S502, being programmed that multi-bit data is written in data latches group, wherein, described multi-bit data is Gray code codeword.In certain embodiments, when a line storage unit of storage array 108 is programmed, will be programmed that each multi-bit data is respectively written in the data latches group 203 one to one of the memory element with this row.Such as, being programmed that each multi-bit data write buffer lock storage 202 by input/output interface 112, then buffer lock storage 202 will be programmed that in each data latches group 203 that each multi-bit data is respectively written into correspondence.

In step S504, described multi-bit data is converted to speech coding code word from Gray code codeword.In certain embodiments, before performing step S504, it is possible to set up the transformational relation of the Gray code code table of multi-bit data, speech coding code table and described Gray code code table and described speech coding code table.Such as, Gray code conversion is that the process of speech coding can meet three below condition (1)-(3):

(1) keeping the highest order of each Gray code codeword, constant (such as, for the Gray code codeword that highest order is " 1 ", the highest order of its corresponding speech coding code word is still " 1 "；For the Gray code codeword that highest order is " 0 ", the highest order of its corresponding speech coding code word is still " 0 ")；

(2) for code word that highest order is " 1 ": code word is re-started arrangement according to the quantity of " 0 ", represent that relatively low electric pressure is (namely by the code word comprising more " 0 ", for the code word that highest order is " 1 ", the number of " 0 " that the speech coding code word that the number of " 0 " that the speech coding code word that low-voltage-grade is corresponding includes is corresponding no less than voltage levels includes)；And for including the electric pressure of equal " 0 " number, the speech coding code word of described electric pressure is obtained (namely by changing the data latches of the minimal number of the Gray code codeword corresponding with described electric pressure, in the code word that highest order is " 1 ", for containing " 0 " equal numbers of electric pressure, from the process that Gray code conversion is speech coding, making to need the minimum number of the data latches of change as far as possible)；And

(3) similarly, code word for highest order is " 0 ": code word is re-started arrangement according to the quantity of " 0 ", represent that relatively low electric pressure is (namely by the code word comprising more " 0 ", for the code word that highest order is " 0 ", the number of " 0 " that the speech coding code word that the number of " 0 " that the speech coding code word that low-voltage-grade is corresponding includes is corresponding no less than voltage levels includes)；And for including the electric pressure of equal " 0 " number, the speech coding code word of described electric pressure is obtained (namely by changing the data latches of the minimal number of the Gray code codeword corresponding with described electric pressure, in the code word that highest order is " 0 ", for containing " 0 " equal numbers of electric pressure, from the process that Gray code conversion is speech coding, making to need the minimum number of the data latches of change as far as possible).

Transformational relation according to Gray code code table Yu speech coding code table, in step S504, it is possible to from Gray code codeword, each described multi-bit data is converted to corresponding speech coding code word.

Such as, Fig. 9 illustrates the transformational relation of the Gray code code table 900 of four Bit datas, speech coding code table 950 and described Gray code code table 900 and described speech coding code table 950.In Fig. 9, filling shade partially illustrates when Gray code code table 900 is converted to speech coding code table 950, it is necessary to the numerical value of the data latches of change.Such as, the Gray code codeword " 1110 " of electric pressure L1 is corresponding to speech coding code word " 1000 "；When four corresponding for electric pressure L1 Bit datas are converted to speech coding code word " 1000 " from Gray code codeword " 1110 ", " 1 " of the first data latches 204 storage remains unchanged, " 0 " of the 4th data latches 210 storage remains unchanged, need " 1 " by the second data latches 206 stores to become " 0 ", and " 1 " that the 3rd data latches 208 stores is become " 0 ".It should be noted that, speech coding code table 950 simply meets the exemplary speech coding code table of above-mentioned condition (1)-(3), other similar speech coding code tables can also satisfy condition (1)-(3), and this is not construed as limiting by the disclosure.

In certain embodiments, multiple electric pressures are encoded by described speech coding, wherein, the highest order of the speech coding code word that the highest order of the speech coding code word of Part I electric pressure is " 0 " and Part II electric pressure is " 1 ", and described Part I electric pressure is all higher than described Part II electric pressure.For described Part I electric pressure: the number of " 0 " that the speech coding code word that the number of " 0 " that the speech coding code word that (1) low-voltage-grade is corresponding includes is corresponding no less than voltage levels includes；And (2) are for including the electric pressure of equal " 0 " number, obtain the speech coding code word of described electric pressure by changing the data latches of the minimal number of the Gray code codeword corresponding with described electric pressure.Similarly, for described Part II electric pressure: the number of " 0 " that the speech coding code word that the number of " 0 " that the speech coding code word that (1) low-voltage-grade is corresponding includes is corresponding no less than voltage levels includes；And (2) are for including the electric pressure of equal " 0 " number, obtain the speech coding code word of described electric pressure by changing the data latches of the minimal number of the Gray code codeword corresponding with described electric pressure.

In step S506, it is determined that storage array needs be programmed that memory element, wherein it is desired to be programmed that described memory element includes: target threshold voltage is more than the memory element of predetermined voltage；And target threshold voltage is not more than the memory element of described predetermined voltage.Described predetermined voltage can be voltage set in advance.Such as, memory element can be divided into high voltage memory element group and low-voltage memory element group by described predetermined voltage.When the target threshold voltage of memory element is more than described predetermined voltage, described memory element is put under high voltage memory element group；When the target threshold voltage of memory element is not more than described predetermined voltage, described memory element is put under low-voltage memory element group.The code word of the speech coding corresponding to low-voltage memory element group is highest order is the code word of " 1 "；The code word of the speech coding corresponding to high voltage memory element group is highest order is the code word of " 0 ".For example, with reference to Fig. 9, target threshold voltage includes, more than the memory element of predetermined voltage, each memory element that target threshold voltage is L8-L15, and the highest order of the speech coding code word of its correspondence is " 0 "；Target threshold voltage is not more than the memory element of predetermined voltage and includes each memory element that target threshold voltage is L1-L7, and the highest order of the speech coding code word of its correspondence is " 1 ".

In certain embodiments, when performing step S506, first scan described data latches group to determine that storage information be wipe the data latches group of (erase) state and storage information is not the data latches group of erasing state.Such as, when the information of data latches group storage is " 1111 ", the information that information is erasing state of this data latches group storage；When the information of data latches group storage is not " 1111 ", the information of this data latches group storage is not the information of erasing state.

Then, for the data latches group that storage information is erasing state, the memory element corresponding with described data latches group is set to not programming state；For the data latches group that storage information is not erasing state, the memory element corresponding with described data latches group is set to programming state.That is, when the information of data latches group storage is " 1111 ", the memory element that this data latches group is corresponding is not programmed；When the information of data latches group storage is not " 1111 ", it is possible to the memory element that this data latches group is corresponding is programmed.For example, it is desired to be programmed that memory element can be the memory element being set to programming state, it is not necessary to be programmed that memory element can be the memory element being set to not programming state.

Then, respective target threshold voltage according to the memory element being in programming state, the memory element being in programming state is divided into target threshold voltage more than predetermined voltage memory element (namely, high voltage memory element group) and target threshold voltage be not more than the memory element (that is, low-voltage memory element group) of predetermined voltage.

In step S508, to storage array 108 needing be programmed that target threshold voltage is pre-programmed into intermediate state voltage more than each memory element of described predetermined voltage.Such as, when a line storage unit of storage array 108 is programmed, can be programmed that needing and target threshold voltage is more than the raceway groove drain terminal ground connection of each memory element of described predetermined voltage, and the raceway groove drain terminal that the memory element that need not program and target threshold voltage are not more than the memory element of described predetermined voltage connects supply voltage.In certain embodiments, described intermediate state voltage (L_temp) it is not more than the minimum target threshold voltage of high voltage memory element group.For example, with reference to Fig. 9, high voltage memory element group includes each memory element that target threshold voltage is L8-L15, and the minimum target threshold voltage of described high voltage memory element group is L8, so intermediate state voltage L_temp≤L8。

In certain embodiments, it is possible to use the memory element of storage array 108 is programmed by standard or off-gauge incremental steps pulse program (ISPP) sequence or other programmed sequences.So that target threshold voltage is programmed into intermediate state voltage more than the voltage of each memory element of described predetermined voltage, can use multiple programming pulse that target threshold voltage is repeatedly programmed more than each memory element of described predetermined voltage, and be verified after programming every time.Such as, step S508 may include that

(1) use programming pulse that more than each memory element of described predetermined voltage, target threshold voltage is carried out pre-programmed (such as, the memory element that speech coding code word highest order is " 0 " being carried out pre-programmed)；

(2) checking is programmed that and target threshold voltage is more than whether the voltage of each memory element of described predetermined voltage has reached intermediate state voltage (such as, checking be programmed that and whether the voltage of memory element that speech coding code word highest order is " 0 " has reached intermediate state voltage)；

(3) for reaching the memory element that speech coding code word highest order is " 0 " of intermediate state voltage, stop it being carried out pre-programmed；And for not yet reaching the memory element that speech coding code word highest order is " 0 " of intermediate state voltage, it is carried out pre-programmed in return operation (1) continuation and operation (2) proceeds checking, all reaches intermediate state voltage until each memory element.

For example, with reference to 680 parts of Fig. 6 D, using programming pulse PGM_1,nAfter target threshold voltage is programmed more than each memory element of described predetermined voltage, it is possible to use verifying voltage VFY_TempIt is verified (such as, verifying voltage VFY_TempEqual to intermediate state voltage).For reaching the target threshold voltage memory element more than described predetermined voltage of intermediate state voltage, stop it being carried out pre-programmed；And for not yet reaching the target threshold voltage memory element more than described predetermined voltage of intermediate state voltage, use next programming pulse PGM_1,n+1Each memory element is programmed, then uses verifying voltage VFY_TempBe verified, the like repetitive operation, until target threshold voltage all reaches intermediate state voltage more than each memory element of described predetermined voltage.

In step S509, to storage array 108 needing be programmed that and target threshold voltage is not more than each memory element of described predetermined voltage and is programmed.Such as, when a line storage unit of storage array 108 is programmed, can be programmed that needing and target threshold voltage is not more than the raceway groove drain terminal ground connection of each memory element of described predetermined voltage, and the memory element that need not program and target threshold voltage are connect supply voltage more than the raceway groove drain terminal of each memory element of described predetermined voltage.In some embodiments, it is desirable to be programmed that and target threshold voltage to be not more than the memory element of described predetermined voltage be that needs are programmed that and the memory element that highest order is " 1 " of speech coding code word.

In certain embodiments, it is possible to use standard or off-gauge incremental steps pulse program (ISPP) sequence or other programmed sequences are to needing in storage array 108 to be programmed that and target threshold voltage is not more than each memory element of described predetermined voltage and is programmed.After the programming of each step, as shown in below step S510 and S512, it is possible to use one or more verifying voltages perform programming checking and latch scan operation.By the programming pulse voltage of stairstepping, the voltage of memory element needing programming is moved to target threshold voltage from erasing state, it is necessary to programming pulse number and often verifying voltage number after step programming all determine according to concrete programming situation.After each programming pulse applies, it is required for using verifying voltage to verify whether current programming has successfully been successfully moved to the target threshold voltage of this memory element by the voltage of memory element.If the voltage of this memory element is successfully moved to target threshold voltage (i.e. the programming success of this memory element), then need the data latches group corresponding with this memory element is latched (as shown in below step S512), and carry out corresponding labelling (as shown in below step S514), to prevent this memory element to be programmed again.

Such as, 682 parts referring to Fig. 6 D, to storage array 108 needing be programmed that and target threshold voltage is not more than each memory element of described predetermined voltage and is programmed (that is, to needing to be programmed that each memory element that speech coding code word highest order is " 1 " is programmed).After each programming pulse of four Bit datas, it is possible to use multiple verifying voltages are verified, and all there is corresponding latch operation after using the checking of each verifying voltage.Such as, programming pulse PGM is being used_2,nAfter being programmed, can be verified first by verifying voltage VFY1 and carry out latch operation 671, then use verifying voltage VFY2 be verified and carry out latch operation 672, then use verifying voltage VFY2, VFY3, VFY4, VFY5, VFY6 and VFY7 are verified and carry out corresponding latch operation respectively.If there being memory element not yet to arrive target threshold voltage, it is possible to use next programming pulse PGM_2,n+1Program next time and carry out corresponding verification operation and latch operation.

In step S510, target threshold voltage is not more than each described memory element of described predetermined voltage, performs programming verification operation.Such as, in step S510, it is possible to select verifying voltage, and verify whether the voltage having enrolled each described memory element that target threshold voltage is not more than described predetermined voltage reaches described verifying voltage.Voltage is reached to the memory element of described verifying voltage, it is possible to be labeled as by corresponding voltage verification latch and pass through state；Voltage is not yet reached to the memory element of described verifying voltage, it is possible to corresponding voltage verification latch is labeled as the state of not passing through.Induction lock storage 216 or the ephemeral data latch 212 corresponding with this memory element that this memory element is corresponding all can use as the voltage verification latch of this memory element.

In step 512, target threshold voltage is not more than each described memory element of described predetermined voltage, performs to latch scan operation.Such as, latch mode will be set to by the data latches group of the memory element that programming is verified and target threshold voltage is described verifying voltage of described verifying voltage；And the memory element of programming checking will do not passed through and/or target threshold voltage is not that the state of data latches group of memory element of described verifying voltage remains unchanged.

In certain embodiments, in step S512, whether the highest order of the speech coding code word that can detect data latches group storage corresponding to described memory element is " 1 ", quantity and the position of detecting " 0 " in the speech coding code word that in the speech coding code word of data latches group storage corresponding to described memory element, whether the quantity of " 0 " is corresponding with described verifying voltage with position are consistent, and whether detect the voltage verification latch corresponding with described memory element for passing through state.If the highest order of the speech coding code word of the data latches group storage that described memory element is corresponding is " 1 ", in the speech coding code word that in the speech coding code word of the data latches group storage that described memory element is corresponding, the quantity of " 0 " is corresponding with described verifying voltage with position, the quantity of " 0 " and position are consistent, and voltage verification latch corresponding to described memory element is by state, arranging the data latches group corresponding with described memory element is latch mode.But, if the highest order of the speech coding code word of the data latches group storage that described memory element is corresponding is not " 1 ", and/or the quantity of " 0 " and position are inconsistent in the speech coding code word that in the speech coding code word of data latches group storage corresponding to described memory element, the quantity of " 0 " is corresponding with described verifying voltage with position, and/or voltage verification latch corresponding to described memory element is not by state, the state keeping data latches group corresponding to described memory element is constant.

Such as, when the voltage verification latch that described memory element is corresponding is not by state, the value of described voltage verification latch is " 1 "；When described voltage verification latch is by state, the value of described voltage verification latch is " 0 ".Aforesaid operations " whether the highest order of speech coding code word detecting data latches group storage corresponding to described memory element is ' 1 '; detect in the speech coding code word that in the speech coding code word of data latches group storage corresponding to described memory element, whether the quantity of ' 0 ' corresponding with described first verifying voltage with position ' 0 ' quantity and position consistent; and whether detect voltage verification latch corresponding to described memory element for passing through state " may include that bus is charged, draw high labelling latch；Bus is charged, the value of the data latches that read described memory element and speech coding code word with described verifying voltage highest order is corresponding, and draws high described labelling latch；The value of that read described memory element and corresponding with the position of " 0 " in the speech coding code word of described verifying voltage data latches, reads described labelling latch, and reads the value of the voltage verification latch corresponding with described memory element；Draw high the data latches corresponding with the position of " 0 " in the speech coding code word of described verifying voltage.If the value of the data latches corresponding with the highest order of the speech coding code word of described verifying voltage is " 1 ", and the value of the value of the data latches corresponding with the position of " 0 " in the speech coding code word of described verifying voltage and described voltage verification latch is " 0 ", the data latches group corresponding with described memory element is set to latch mode；If the value of the data latches corresponding with the highest order of the speech coding code word of described verifying voltage is not " 1 ", and/or at least one is not " 0 " in the value of the value of the data latches corresponding with the position of " 0 " in the speech coding code word of described verifying voltage and/or described voltage verification latch, the state of the data latches group corresponding with described memory element remains unchanged.The ephemeral data latch 212 corresponding with described memory element can use as described labelling latch.

In step S514, target threshold voltage is not more than each described memory element of described predetermined voltage, performs to confirm scan operation.Such as, data latches group being latched as to the memory element of latch mode, what arrange described memory element judges that latch is as latching success status, to prevent described memory element from continuing programming；Data latches group not being latched as to the memory element of latch mode, what arrange described memory element judges that latch is as latching unsuccessful state.The induction lock storage 216 corresponding with described memory element or the ephemeral data latch 212 corresponding with described memory element all can use as described judgement latch.

In step S515, to storage array 108 needing be programmed that and target threshold voltage is programmed more than each memory element of described predetermined voltage.Such as, when a line storage unit of storage array 108 is programmed, can be programmed that needing and target threshold voltage is more than the raceway groove drain terminal ground connection of each memory element of described predetermined voltage, and the raceway groove drain terminal that the memory element that need not program and target threshold voltage are not more than each memory element of described predetermined voltage connects supply voltage.In some embodiments, it is desirable to be programmed that and target threshold voltage is need to be programmed that and the memory element that highest order is " 0 " of speech coding code word more than the memory element of described predetermined voltage.

In certain embodiments, it is possible to use standard or off-gauge incremental steps pulse program (ISPP) sequence or other programmed sequences are to needing in storage array 108 to be programmed that and target threshold voltage is programmed more than each memory element of described predetermined voltage.After the programming of each step, as shown in below step S516 and S518, it is possible to use one or more verifying voltages perform programming checking and latch scan operation.By the programming pulse voltage of stairstepping, the voltage of memory element needing programming is moved to target threshold voltage from erasing state, it is necessary to programming pulse number and often verifying voltage number after step programming all determine according to concrete programming situation.After each programming pulse applies, it is required for using verifying voltage to verify whether current programming has successfully been successfully moved to the target threshold voltage of this memory element by the voltage of memory element.If the voltage of this memory element is successfully moved to target threshold voltage (i.e. the programming success of this memory element), then need the data latches group corresponding with this memory element is latched (as shown in below step S518), and carry out corresponding labelling (as shown in below step S520), to prevent this memory element to be programmed again.

Such as, 684 parts referring to Fig. 6 D, to storage array 108 needing be programmed that and target threshold voltage is programmed (that is, to needing to be programmed that each memory element that speech coding code word highest order is " 0 " is programmed) more than each memory element of described predetermined voltage.After each programming pulse of four Bit datas, it is possible to use multiple verifying voltages are verified, and all there is corresponding latch operation after using the checking of each verifying voltage.Such as, programming pulse PGM is being used_3,nAfter being programmed, can be verified first by verifying voltage VFY8 and carry out latch operation, then use verifying voltage VFY9 be verified and carry out latch operation, then use verifying voltage VFY10, VFY11, VFY12, VFY13, VFY14 and VFY15 are verified and carry out corresponding latch operation respectively.If there being memory element not yet to arrive target threshold voltage, it is possible to use next programming pulse PGM_3,n+1Program next time and carry out corresponding verification operation and latch operation.

In step S516, to the target threshold voltage each described memory element more than described predetermined voltage, perform programming verification operation.Such as, in step S516, it is possible to select verifying voltage, and checking has enrolled target threshold voltage more than whether the voltage of each described memory element of described predetermined voltage reaches described verifying voltage.Voltage is reached to the memory element of described verifying voltage, it is possible to be labeled as by corresponding voltage verification latch and pass through state；Voltage is not yet reached to the memory element of described verifying voltage, it is possible to corresponding voltage verification latch is labeled as the state of not passing through.The induction lock storage 216 corresponding with this memory element or the ephemeral data latch 212 corresponding with this memory element all can use as the voltage verification latch of this memory element.

In step 518, latch mode will be set to by the data latches group of the memory element that programming is verified and target threshold voltage is described verifying voltage of described verifying voltage；And the memory element of programming checking will do not passed through and/or target threshold voltage is not that the state of data latches group of memory element of described verifying voltage remains unchanged.

In certain embodiments, in step S518, quantity and the position that can detect " 0 " in the speech coding code word that in the speech coding code word of data latches group storage corresponding to described memory element, whether the quantity of " 0 " is corresponding with described verifying voltage with position are consistent, and whether detect the voltage verification latch corresponding with described memory element for passing through state.If the quantity of " 0 " and position are consistent in the speech coding code word that in the speech coding code word of the data latches group storage that described memory element is corresponding, the quantity of " 0 " is corresponding with described verifying voltage with position, and voltage verification latch corresponding to described memory element is by state, arranging the data latches group corresponding with described memory element is latch mode.But, if the quantity of " 0 " and position are inconsistent in the speech coding code word that in the speech coding code word of the data latches group storage that described memory element is corresponding, the quantity of " 0 " is corresponding with described verifying voltage with position, and/or voltage verification latch corresponding to described memory element is not by state, the state keeping data latches group corresponding to described memory element is constant.

Such as, when the voltage verification latch that described memory element is corresponding is not by state, the value of described voltage verification latch is " 1 "；When described voltage verification latch is by state, the value of described voltage verification latch is " 0 ".Such as, aforesaid operations " detect in the speech coding code word of data latches group storage corresponding to described memory element in the quantity speech coding code word whether corresponding with described first verifying voltage with position of ' 0 ' ' 0 ' quantity and position consistent, and whether detect voltage verification latch corresponding to described memory element for passing through state " may include that bus is charged；The value of that read described memory element and corresponding with the position of " 0 " in the speech coding code word of described verifying voltage data latches, and read the value of the voltage verification latch corresponding with described memory element；Draw high the data latches corresponding with the position of " 0 " in the speech coding code word of described verifying voltage.If the value of the value of the data latches corresponding with the position of " 0 " in the speech coding code word of described verifying voltage and described voltage verification latch is " 0 ", the data latches group corresponding with described memory element is set to latch mode；If at least one is not " 0 " in the value of the value of the data latches corresponding with the position of " 0 " in the speech coding code word of described verifying voltage and/or described voltage verification latch, the state of the data latches group corresponding with described memory element remains unchanged.

Again such as, aforesaid operations " detect in the speech coding code word of data latches group storage corresponding to described memory element in the quantity speech coding code word whether corresponding with described first verifying voltage with position of ' 0 ' ' 0 ' quantity and position consistent; and whether detect voltage verification latch corresponding to described memory element for passing through state " may include that bus is charged, draw high labelling latch；The value of that read described memory element and corresponding with the position of " 0 " in the speech coding code word of described verifying voltage data latches, reads described labelling latch, and reads the value of the voltage verification latch corresponding with described memory element；Draw high the data latches corresponding with the position of " 0 " in the speech coding code word of described verifying voltage.If the value of the value of the value of the data latches corresponding with the position of " 0 " in the speech coding code word of described verifying voltage, described labelling latch and described voltage verification latch is " 0 ", the data latches group corresponding with described memory element is set to latch mode；If at least one is not " 0 " in the value of the value of the value of the data latches corresponding with the position of " 0 " in the speech coding code word of described verifying voltage and/or described labelling latch and/or described voltage verification latch, the state of the data latches group corresponding with described memory element remains unchanged.The ephemeral data latch 212 corresponding with described memory element can use as described labelling latch, and the induction lock storage 216 corresponding with described memory element can use as described voltage verification latch.

In step S520, to the target threshold voltage each described memory element more than described predetermined voltage, perform to confirm scan operation.Such as, data latches group being latched as to the memory element of latch mode, what arrange described memory element judges that latch is as latching success status, to prevent described memory element from continuing programming；Data latches group not being latched as to the memory element of latch mode, what arrange described memory element judges that latch is as latching unsuccessful state.The induction lock storage 216 corresponding with described memory element or the ephemeral data latch 212 corresponding with described memory element all can use as described judgement latch.

The two of the indicative flowchart of many program bits method 550 of a kind of nand memory that Fig. 5 B-5C provides for disclosure embodiment.In certain embodiments, method 550 can include the some or all of step shown in Fig. 5 B and 5C.Certainly, method 550 can also include other not steps shown in Fig. 5 B and 5C.In the following description, method 550 is described in detail by the structure of the sense amplifier 110 in conjunction with Fig. 2.

First, in step S552, being programmed that multi-bit data is written in data latches group, wherein, described multi-bit data is Gray code codeword.In certain embodiments, it is possible to perform the operation similar to the step S502 of Fig. 5 A and realize step S552.

In step 554, each described multi-bit data is converted to speech coding code word from Gray code codeword by multi-bit according to this described in pretreatment.In certain embodiments, it is possible to perform the operation similar to the step S504 of Fig. 5 A and realize step S554.

In step S556, scan described data latches group to determine that data latches group that storage information is erasing (erase) state and storage information are not the data latches groups of erasing state.Such as, when the information of data latches group storage is " 1111 ", the information that information is erasing state of this data latches group storage；When the information of data latches group storage is not " 1111 ", the information of this data latches group storage is not the information of erasing state.

In step S558, for the data latches group that storage information is erasing state, the memory element corresponding with described data latches group is set to not programming state；For the data latches group that storage information is not erasing state, the memory element corresponding with described data latches group is set to programming state.That is, when the information of data latches group storage is " 1111 ", the memory element that this data latches group is corresponding is not programmed；When the information of data latches group storage is not " 1111 ", it is possible to the memory element that this data latches group is corresponding is programmed.

In step S559, to storage array 108 needing be programmed that and target threshold voltage is pre-programmed into intermediate state voltage more than each memory element of predetermined voltage.In certain embodiments, it is possible to perform the operation similar to the step S508 of Fig. 5 A and realize step S559.

In step S560, to storage array 108 needing be programmed that and target threshold voltage is not more than each memory element of described predetermined voltage and is programmed.In certain embodiments, it is possible to perform the operation similar to the step S509 of Fig. 5 A and realize step S560.

In step 562, target threshold voltage is not more than each described memory element of described predetermined voltage, performs programming verification operation.Such as, select verifying voltage, and verify whether the voltage having enrolled each described memory element reaches described verifying voltage.In certain embodiments, it is possible to perform the operation similar to the step S510 of Fig. 5 A and realize step S562.

In step 564, target threshold voltage is not more than each described memory element of described predetermined voltage, performs to latch scan operation.Such as, latch mode will be set to by the data latches group of the memory element that programming is verified and target threshold voltage is described verifying voltage of described verifying voltage.In certain embodiments, it is possible to perform the operation similar to the step S512 of Fig. 5 A and realize step S564.

In step S566, target threshold voltage is not more than each described memory element of described predetermined voltage, performs to confirm scan operation.Such as, data latches group being latched as to the memory element of latch mode, what arrange described memory element judges that latch is as latching success status；Data latches group not being latched as to the memory element of latch mode, what arrange described memory element judges that latch is as latching unsuccessful state.In certain embodiments, it is possible to perform the operation similar to the step S514 of Fig. 5 A and realize step S566.

In step S568, it is determined whether choose next verifying voltage and be programmed checking.Such as, all it is used to if all of verifying voltage verify that this programs, or target threshold voltage is not more than the voltage of the memory element of predetermined voltage all not up to the verifying voltage in step S562, method 550 will no longer be chosen next verifying voltage and be programmed checking but then perform next step S570；Otherwise, method 550 can be chosen next verifying voltage and be programmed checking, and returns step S562.

In step S570, it is determined whether completed the programming that target threshold voltage is not more than the memory element of predetermined voltage.Such as, in step S570, it is determined that whether target threshold voltage is not more than in the memory element of predetermined voltage and also has one or more memory element not yet to reach respective target threshold voltage in this programming.If also having one or more memory element not yet to reach respective target threshold voltage in this programming, method 550 can return step S560 and program next time.Being reached respective target threshold voltage if all of memory element in this programming, method 550 can move to the step S572 of Fig. 5 C.

In step S572, to storage array 108 needing be programmed that and target threshold voltage is programmed more than each memory element of described predetermined voltage.In certain embodiments, it is possible to perform the operation similar to the step S515 of Fig. 5 A and realize step S572.

In step 574, to the target threshold voltage each described memory element more than described predetermined voltage, perform programming verification operation.Such as, select verifying voltage, and verify whether the voltage having enrolled each described memory element reaches described verifying voltage.In certain embodiments, it is possible to perform the operation similar to the step S516 of Fig. 5 A and realize step S574.

In step 576, to the target threshold voltage each described memory element more than described predetermined voltage, perform to latch scan operation.Such as, latch mode will be set to by the data latches group of the memory element that programming is verified and target threshold voltage is described verifying voltage of described verifying voltage.In certain embodiments, it is possible to perform the operation similar to the step S518 of Fig. 5 A and realize step S576.

In step S578, to the target threshold voltage each described memory element more than described predetermined voltage, perform to confirm scan operation.Such as, data latches group being latched as to the memory element of latch mode, what arrange described memory element judges that latch is as latching success status；Data latches group not being latched as to the memory element of latch mode, what arrange described memory element judges that latch is as latching unsuccessful state.In certain embodiments, it is possible to perform the operation similar to the step S520 of Fig. 5 A and realize step S578.

In step S580, it is determined whether choose next verifying voltage and be programmed checking.Such as, all it is used to if all of verifying voltage verify that this programs, or target threshold voltage is more than the voltage of the memory element of predetermined voltage all not up to the verifying voltage in step S574, and method 550 will no longer be chosen next verifying voltage and be programmed checking but then perform next step S582；Otherwise, method 550 can be chosen next verifying voltage and be programmed checking, and returns step S574.

In step S582, it is determined whether completed the target threshold voltage programming more than the memory element of predetermined voltage.Such as, in step S582, it is determined that target threshold voltage not yet reaches respective target threshold voltage more than whether also having one or more memory element in the memory element of predetermined voltage in this programming.If also having one or more memory element not yet to reach respective target threshold voltage in this programming, method 550 can return step S572 and program next time.Being reached respective target threshold voltage if all of memory element in this programming, method 550 can move to step S584.

In step S584, owing to all of memory element has reached respective target threshold voltage all through programming, method 550 completes the programming to described multi-bit data.

The indicative flowchart of a kind of method 600 being programmed checking and latch operation after one-time programming that Fig. 6 A provides for disclosure embodiment.The step S510 of method 500 in Fig. 5 A, the step S562 of method 550 in S512 and S514 and Fig. 5 B, S564, S566 and S568 are carried out exemplary explanation by method 600.Need to be programmed that target threshold voltage is not more than after each memory element of predetermined voltage is programmed in storage array, it is possible to the following steps of execution method 600 are programmed checking and latch operation.

First, in step S602, select verifying voltage L1, and verify whether the voltage having enrolled each described memory element reaches described verifying voltage L1.

In step S604, for by the memory element that programming is verified and target threshold voltage is verifying voltage L1 of verifying voltage L1, arranging the data latches group corresponding with described memory element is latch mode (for example, it is possible to the information arranging the storage of described data latches group is " 1111 ")；And in step S606, what arrange described memory element judges that latch is as latching success status, to prevent described memory element from continuing programming.

In step S608, not being the memory element of verifying voltage L1 for the memory element of programming checking of not verified voltage L1 and/or target threshold voltage, the state keeping the data latches group corresponding with described memory element is constant；And in step S610, what arrange described memory element judges that latch is as latching unsuccessful state.

In step S612, select verifying voltage L2, and verify whether the voltage having enrolled each described memory element reaches verifying voltage L2.

In step S614, for by the memory element that programming is verified and target threshold voltage is verifying voltage L2 of verifying voltage L2, arranging the data latches corresponding with described memory element is latch mode (for example, it is possible to the information arranging the storage of described data latches group is " 1111 ")；And in step S616, what arrange described memory element judges that latch is as latching success status.

In step S618, not being the memory element of verifying voltage L2 for the memory element of programming checking of not verified voltage L2 and/or target threshold voltage, the state keeping the data latches corresponding with described memory element is constant；And in step S620, what arrange described memory element judges that latch is as latching unsuccessful state.

In step S622, select verifying voltage L3, and verify whether the voltage having enrolled each described memory element reaches verifying voltage L3.Similarly, method 600 can also include the latch scan operation to verifying voltage L3 and confirm scan operation, and uses other verifying voltages to be programmed checking, latches scanning and confirm the operation of scanning, and the disclosure does not repeat them here.

The indicative flowchart of a kind of method 630 being programmed checking and latch operation after one-time programming that Fig. 6 B provides for disclosure embodiment.The step S516 of method 500 in Fig. 5 A, the step S574 of method 550 in S518 and S520 and Fig. 5 C, S576, S578 and S580 are carried out exemplary explanation by method 630.After needing to be programmed that target threshold voltage is programmed more than each memory element of predetermined voltage in storage array, it is possible to the following steps of execution method 630 are programmed checking and latch operation.

First, in step S631, select verifying voltage L8, and verify whether the voltage having enrolled each described memory element reaches described verifying voltage L8.

In step S632, for by the memory element that programming is verified and target threshold voltage is verifying voltage L8 of verifying voltage L8, arranging the data latches group corresponding with described memory element is latch mode (for example, it is possible to the information arranging the storage of described data latches group is " 1111 ")；And in step S633, what arrange described memory element judges that latch is as latching success status, to prevent described memory element from continuing programming.

In step S634, not being the memory element of verifying voltage L8 for the memory element of programming checking of not verified voltage L8 and/or target threshold voltage, the state keeping the data latches group corresponding with described memory element is constant；And in step S635, what arrange described memory element judges that latch is as latching unsuccessful state.

In step S636, select verifying voltage L9, and verify whether the voltage having enrolled each described memory element reaches verifying voltage L9.

In step S637, for by the memory element that programming is verified and target threshold voltage is verifying voltage L9 of verifying voltage L9, arranging the data latches corresponding with described memory element is latch mode (for example, it is possible to the information arranging the storage of described data latches group is " 1111 ")；And in step S638, what arrange described memory element judges that latch is as latching success status.

In step S639, not being the memory element of verifying voltage L9 for the memory element of programming checking of not verified voltage L9 and/or target threshold voltage, the state keeping the data latches corresponding with described memory element is constant；And in step S640, what arrange described memory element judges that latch is as latching unsuccessful state.

In step S641, select verifying voltage L10, and verify whether the voltage having enrolled each described memory element reaches verifying voltage L10.Similarly, method 630 can also include the latch scan operation to verifying voltage L10 and confirm scan operation, and uses other verifying voltages to be programmed checking, latches scanning and confirm the operation of scanning, and the disclosure does not repeat them here.

The exemplary programming process of four Bit datas that Fig. 7 A-7P provides for disclosure embodiment.As shown in Figure 7 A, form 700 illustrates: need to be programmed that the target threshold voltage respectively L1 of memory element 1, memory element 2, memory element 3, memory element 4 and memory element 5, L2, L3, L3 and L8；And respectively corresponding with the L1 speech coding code word " 1000 " of code word of the data latches group storage of memory element 1, memory element 2, memory element 3, memory element 4 and memory element 5 correspondence speech coding code word " 1100 " corresponding with L2 speech coding code word " 1001 " corresponding with L3 speech coding code word " 1001 " corresponding with L3 and speech coding code word " 0000 " corresponding with L8.

Fig. 7 B illustrates each memory element voltage after pre-programmed.The highest order of the speech coding code word of memory element 1, memory element 2, memory element 3 and memory element 4 is " 1 ", for low-voltage memory element group；In preprogramming process, each memory element of low-voltage memory element group is not carried out pre-programmed.The highest order of the speech coding code word of memory element 5 is " 0 ", for high voltage memory element group；In preprogramming process, the memory element 5 of high voltage memory element group is carried out pre-programmed.

Fig. 7 C illustrates use verifying voltage L_tempMemory element 5 is programmed checking, and its result is shown in form 716.Verifying voltage L_tempEqual to intermediate state voltage.In conjunction with chart 715 and form 716 it can be seen that the voltage of memory element 5 has passed through verifying voltage L_tempChecking, so memory element 5 is programmed has arrived intermediate state voltage L_temp。

Fig. 7 D illustrates each memory element of low-voltage memory element group voltage after first time programming.Such as, memory element 1 is programmed into voltage L1, and memory element 2 is programmed into voltage L2, and memory element 3 is programmed into voltage L3 and memory element 4 is programmed into voltage L2.The memory element 5 belonging to high voltage memory element group is not programmed when low-voltage memory element group is programmed, and keeps original voltage levvl.

Fig. 7 E illustrates that each memory element of low-voltage memory element group is programmed checking by use verifying voltage L1, and its result is shown in form 730.In conjunction with chart 725 and form 730 it can be seen that the voltage of each memory element of low-voltage memory element group has reached verifying voltage L1 all, so the verifying voltage latch corresponding with each memory element is all set to pass through state.

Fig. 7 F illustrates the process latching the memory element that target threshold voltage is verifying voltage L1 (speech coding code word " 1000 ").Form 735 illustrates the voltage verification result of each memory element of low-voltage memory element group and the code word of the data latches group storage of correspondence.The voltage being programmed into due to memory element 1 has passed through the checking of voltage L1, and the target threshold voltage of memory element 1 is equal to verifying voltage L1 (such as, the speech coding code word of the data latches group storage of memory element 1 is identical with the speech coding code word of verifying voltage L1, it is " 1000 "), so the data latches group of memory element 1 is latched as latch mode " 1111 " (as shown in arrow 736) from " 1000 ", and the state judging latch of memory element 1 is set to latch successfully.But, even if memory element 2, the voltage that memory element 3 and memory element 4 are programmed into is each through the checking of voltage L1, but due to memory element 2, the target threshold voltage of memory element 3 and memory element 4 is all not equal to verifying voltage L1 (such as, memory element 2, the speech coding code word of the data latches group storage of memory element 3 and memory element 4 all differs with the speech coding code word of verifying voltage L1), so memory element 2, the state of the data latches group of memory element 3 and memory element 4 all remains unchanged, and memory element 2, it is unsuccessful that the state judging latch of memory element 3 and memory element 4 is set to latch.Form 737 illustrates the above-mentioned result that latch target threshold voltage is verifying voltage L1.

Owing to memory element 2, memory element 3 and memory element 4 are not all latched as respective target threshold voltage, and the voltage of memory element 2, memory element 3 and memory element 4 is each through the programming checking of last voltage L1, so also needing to choose next verifying voltage L2 to be encoded checking.Fig. 7 G illustrates that each memory element of low-voltage memory element group is programmed checking by use verifying voltage L2, and its result is shown in form 742.Known in conjunction with chart 740 and form 742, the voltage of memory element 2, memory element 3 and memory element 4 has reached verifying voltage L2 all, so the verifying voltage latch corresponding with memory element 2, memory element 3 and memory element 4 is all set to pass through state；The voltage of memory element 1 is not up to verifying voltage L2, so the verifying voltage latch corresponding with memory element 1 is set to not pass through state.

Fig. 7 H illustrates the process latching the memory element that target threshold voltage is verifying voltage L2 (speech coding code word " 1100 ").Form 745 illustrates the voltage verification result of each memory element of low-voltage memory element group and the code word of the data latches group storage of correspondence.Memory element 1 successfully reaches its target threshold voltage L1 due to memory element 1 and its data latches group also successfully latched, so can't be impacted not over the checking of verifying voltage L2 by memory element 1.Owing to the program voltage of memory element 2 has passed through the checking of voltage L2, and the target threshold voltage of memory element 2 is equal to verifying voltage L2 (such as, the speech coding code word of the data latches group storage of memory element 2 is identical with the speech coding code word of verifying voltage L2, it is " 1100 "), so the data latches group of memory element 2 is latched as latch mode " 1111 " (as shown in arrow 746) from " 1100 ", and the state judging latch of memory element 2 is set to latch successfully.Owing to the target threshold voltage of memory element 3 and memory element 4 is all not equal to verifying voltage L2 (such as, the speech coding code word of data latches group storage of memory element 3 and memory element 4 all differs with the speech coding code word of verifying voltage L2), so the state of the data latches group of memory element 3 and memory element 4 all remains unchanged, and the state judging latch of memory element 3 and memory element 4 be set to latch unsuccessful.Form 747 illustrates the above-mentioned result that latch target threshold voltage is verifying voltage L2.

Owing to memory element 3 and memory element 4 are not all latched as respective target threshold voltage, and the programming checking that the voltage of memory element 3 and memory element 4 is by last voltage L2, so also need to choose next verifying voltage L3 to be encoded checking.Fig. 7 I illustrates that each memory element is programmed checking by use verifying voltage L3, and its result is shown in form 755.In conjunction with chart 750 and form 755 it can be seen that the voltage of memory element 3 has reached verifying voltage L3, so the verifying voltage latch corresponding with memory element 3 is arranged by state；The voltage of memory element 1, memory element 2 and memory element 4 is not up to verifying voltage L3, so the verifying voltage latch corresponding with memory element 1, memory element 2 and memory element 4 is all set to not pass through state.

Fig. 7 J illustrates the process latching the memory element that target threshold voltage is verifying voltage L3 (speech coding code word " 1001 ").Form 760 illustrates the voltage verification result of each memory element of low-voltage memory element group and the code word of the data latches group storage of correspondence.Memory element 1 and memory element 2 successfully reach its respective target threshold voltage due to memory element 1 and memory element 2 and its respective data latches group also successfully latched, so can't be impacted not over the checking of verifying voltage L3 by memory element 1 and memory element 2.Owing to the program voltage of memory element 3 has passed through the checking of voltage L3, and the target threshold voltage of memory element 3 is equal to verifying voltage L3 (such as, the speech coding code word of the data latches group storage of memory element 3 is identical with the speech coding code word of verifying voltage L3, it is " 1001 "), so the data latches group of memory element 3 is latched as latch mode " 1111 " (as shown in arrow 762) from " 1001 ", and the state judging latch of memory element 3 is set to latch successfully.Although the target threshold voltage of memory element 4 is equal to verifying voltage L3 (such as, the speech coding code word of the data latches group storage of memory element 4 is identical with the speech coding code word of verifying voltage L3), but the program voltage of memory element 4 is not verified by the programming of verifying voltage L3, so the state of the data latches group of memory element 4 remains unchanged, and the state judging latch of memory element 4 be set to latch unsuccessful.Form 765 illustrates the above-mentioned result that latch target threshold voltage is verifying voltage L3.

Owing to memory element 4 is not latched as its target threshold voltage, and the voltage of memory element 4 is not over the programming checking of last voltage L3, so no longer choosing next verifying voltage L4, the programming of memory element 4 is verified, but memory element 4 is carried out second time programming.Fig. 7 K illustrates the memory element 4 voltage L3 after second time programming.Due to first time programming time memory element 4 have passed through verifying voltage L2 programming checking verify without by the programming of verifying voltage L3, so second time program time can directly use verifying voltage L3 that memory element 4 is verified rather than from verifying voltage L1.

Fig. 7 L illustrates that memory element 4 is programmed checking by use verifying voltage L3, and its result is shown in form 772.In conjunction with chart 770 and form 772 it can be seen that the voltage of memory element 4 has reached verifying voltage L3, so the verifying voltage latch corresponding with memory element 4 is arranged by state.

Fig. 7 M illustrates the process latching the memory element that target threshold voltage is verifying voltage L3 (speech coding code word " 1001 ").Form 775 illustrates the voltage verification result of memory element 4 and the code word of the data latches group storage of correspondence.Owing to the voltage of memory element 4 has passed through the checking of verifying voltage L3, and the target threshold voltage of memory element 4 is equal to verifying voltage L3 (such as, the speech coding code word of the data latches group storage of memory element 4 is identical with the speech coding code word of verifying voltage L4, is

" 1001 "), so the data latches group of memory element 4 is latched as latch mode " 1111 " (as shown in arrow 776) from " 1001 ", and the state judging latch of memory element 4 is set to latch successfully.Form 778 illustrates the above-mentioned latch result that latch target threshold voltage is verifying voltage L3.So far, each data latches group of memory element 1, memory element 2, memory element 3 and memory element 4 correspondence is all successfully latched, and the programming of the memory element 1 of low-voltage memory element group, memory element 2, memory element 3 and memory element 4 is all terminated.

Fig. 7 N illustrates each memory element of high voltage memory element group voltage after programming.Such as, memory element 5 is programmed into voltage L8.The memory element 1 of low-voltage memory element group, memory element 2, memory element 3 and memory element 4 are not programmed, keep latch mode.

Fig. 7 O illustrates that the memory element 5 of high voltage memory element group is programmed checking by use verifying voltage L8, and its result is shown in form 786.In conjunction with chart 785 and form 786 it can be seen that the voltage of memory element 5 has reached verifying voltage L8, so the verifying voltage latch corresponding with memory element 5 is arranged by state.

Fig. 7 P illustrates the process latching the memory element that target threshold voltage is verifying voltage L8 (speech coding code word " 0000 ").Form 790 illustrates the voltage verification result of memory element 5 and the code word of the data latches group storage of correspondence.The voltage being programmed into due to memory element 5 has passed through the checking of voltage L8, and the target threshold voltage of memory element 5 is equal to verifying voltage L8 (such as, the speech coding code word of the data latches group storage of memory element 5 is identical with the speech coding code word of verifying voltage L8, it is " 0000 "), so the data latches group of memory element 5 is latched as latch mode " 1111 " (as shown in arrow 791) from " 0000 ", and the state judging latch of memory element 5 is set to latch successfully.Form 792 illustrates the above-mentioned result that latch target threshold voltage is verifying voltage L8.

So far, all memory element 1-5 are all successfully latched, and the programming of all memory element 1-5 is all terminated.

The exemplary process diagram of the programming checking of a kind of speech coding 950 based on Fig. 9 that Fig. 8 A-8H provides for disclosure embodiment and the method 8000 of latch.The comparison of the method 8000 that the programming as speech coding is verified and latched, Fig. 8 A-8H further comprises the exemplary process diagram programming the method 800 verified and latch of a kind of Gray code 900 based on Fig. 9.Such as, in Fig. 8 A-8H, the programming checking of Gray code 900 and the method 800 of latch are shown in the left side of dotted line, and the method 8000 that the programming of speech coding 950 is verified and latched is shown in the right of dotted line.The verifying voltage of method 800 and method 8000 is all be followed successively by L1-L7 and L8-L15 according to from low-voltage to high-tension order.

For convenience described below, the data latches group corresponding with being programmed that memory element can include four data latches ADL (DataLatchA), BDL (DataLatchB), CDL (DataLatchC) and DDL (DataLatchD), and each bit of the code word of Gray code or the code word of speech coding is sequentially stored in data latches ADL, BDL, CDL and DDL.Such as, for code word " 1010 ", data latches ADL, BDL, CDL and DDL store " 1 " respectively, " 0 ", " 1 ", " 0 " (that is, ADL=1, BDL=0, CDL=1, DDL=0).Induction lock storage can be expressed as SDL (SensingDataLatch), and ephemeral data latch can be expressed as TDL (TemporaryDataLatch), and bus can be expressed as BUS.

In certain embodiments, programming checking and latch scan operation may include that whether (1) detection voltage verification result is passed through；(2) data bank of latches is compared by turn, it is judged that whether the code word of the target threshold voltage of data latches group storage is the code word of verifying voltage；(3) if having passed through the checking of verifying voltage and the code word that code word is verifying voltage of the target threshold voltage of data latches group storage, namely the voltage of memory element has reached target threshold voltage, then data latches group is set to latch mode " 1111 ".

In certain embodiments, it is possible to detect, by following step (1)-(3), " 0 " and " 1 " that data latches (such as, ADL) stores:

(1) bus B US is charged, to labelling latch set (TDL or SDL or other data latches all can use as labelling latch).

(2) read data latch ADL.If ADL=0, then bus B US does not discharge, and labelling latch is still " 1 "；If ADL=1, then bus B US electric discharge, labelling latch is by reset.

(3) labelling latch is drawn high again.If in (2), bus B US does not discharge, and labelling latch is still " 1 ", then the labelling latch success set being driven high in step (3), thus judging ADL=0；If in (2), bus B US discharges, labelling latch by reset, then the labelling latch being driven high in step (3) can not success set, thus judging ADL=1.

From above-mentioned steps (1)-(3), when detecting data latches and being " 1 ", because bus B US discharges, need one " 1 " to connect one " 1 " to detect, and plural " 1 " (namely, it is impossible to whether two data latches of detection are " 1 " simultaneously) can not be detected simultaneously；And when detecting data latches and being " 0 ", it is possible to directly detection be there is a need to " 0 " (i.e., it is possible to whether detection two or more data latches is " 0 " simultaneously) of detection.Therefore, speech coding can be passed through to change each order of each code word in cataloged procedure, allow to faster to be detected containing " 0 " a fairly large number of code word front (namely, relatively low verifying voltage is represented) with containing " 0 " a fairly large number of code word, and the code word containing " 0 " negligible amounts rear (namely, higher verifying voltage is represented by the code word containing " 0 " negligible amounts), such that it is able to save the redundant operation of detection " 1 ".Therefore, the program speed of speech coding can be accelerated, and power consumption can also reduce.

For example, with reference to the coding in Fig. 9, to encode L1, L2, when detection, it is therefore an objective in order to current cell encoding is separated with all cellular zones on the right side of it.Because " 0 " of Gray code and " 1 " relation is indefinite, so when using Gray code, if L1 (" 1110 ") and L2-L15 is distinguished, it is necessary to detection ADL=1, then detecting BDL=1, then detecting CDL=1, finally detect DDL=0.And after using speech coding to recompile, for code word " 1000 " corresponding for L1, it is possible to detection ADL=1, detect three " 0 " (that is, BDL=CDL=DDL=0).Similarly, for voltage L2, when using Gray code, if L2 (" 1100 ") and L3-L15 is distinguished, it is necessary to detection ADL=1, then detect BDL=1, then detect CDL=DDL=0.And after using speech coding to recode, for code word " 1100 " corresponding for L2, ADL=1 can be detected, detect two " 0 " (namely, CDL=DDL=0) L2 and L3-L15 just can be made to distinguish, because not having ADL in L3-L15 is the code word that " 1 " and CDL and DDL are " 0 ".Therefore, with Gray's code-phase ratio, speech coding can save at least some of redundant operation detecting " 1 ", and program speed can be accelerated, and power consumption can also reduce.

Referring to Fig. 8 A, in method 800, the Gray code code word of verifying voltage L1 is " 1110 ", and method 800 includes: step S801, to being programmed that memory element checking pulse L1 (that is, verifying voltage L1)；Step S802, to being programmed that memory element performs the latch of pulse L1；Step S803, detects first " 1 " (that is, detection ADL=1)；Step S804, detects second " 1 " (that is, detection BDL=1)；Step S805, the 3rd " 1 " of detection (that is, detection CDL=1)；Step S806, detects one " 0 " (that is, detection DDL=0)；And step S807, above-mentioned steps S803-S806 will be met and the data latches group by the memory element of the checking of verifying voltage L1 is latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Further, will not meet above-mentioned steps S803-S806 or do not remained unchanged by the state of the data latches group of the memory element of the checking of verifying voltage L1.

Such as, L1 (Gray code " 1110 ") checking and latch can include following operation A)-E):

A) BUS is charged (that is, arranging BUS=1), draw high labelling latch (such as, labelling latch TDL=1 is set).

B) BUS charging (BUS=1), reads ADL, then draws high TDL=1.If ADL=1, then TDL=0；Otherwise TDL=1.

C) BUS charging (BUS=1), reads BDL, then draws high TDL=1.If BDL=1, then TDL=0；Otherwise TDL=1.

D) BUS charging BUS=1, reads CDL, then draws high TDL=1.If CDL=1, then TDL=0；Otherwise TDL=1.

E) BUS charging BUS=1, reads DDL, SDL, TDL, draws high DDL=1.If DDL=0, SDL=0, TDL=0, then DDL=1；Otherwise DDL=0.

In method 8000, the speech coding code word of verifying voltage L1 is " 1000 ", and method 8000 includes: step S8001, to being programmed that memory element checking pulse L1 (that is, verifying voltage L1)；Step S8002, to being programmed that memory element performs the latch of pulse L1；Step S8003, detects first " 1 " (that is, detection ADL=1)；Step S8006, detects three " 0 " (that is, detection BDL=CDL=DDL=0)；And step S8007, above-mentioned steps S8003 and S8006 will be met and the data latches group by the memory element of the checking of verifying voltage L1 is latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Further, will not meet above-mentioned steps S8003, S8006 and/or do not remained unchanged by the state of the data latches group of the memory element of the checking of verifying voltage L1.

Such as, L1 (speech coding " 1000 ") checking and latch can include following operation:

BUS charges BUS=1, draws high TDL=1.BUS charges BUS=1, reads ADL, then draws high TDL=1；If ADL=1, then TDL=0；Otherwise TDL=1.Read BDL, CDL, DDL, TDL, SDL, then draw high BDL=1, CDL=1, DDL=1；If BDL=0, CDL=0, DDL=0, TDL=0, SDL=0 (wherein, SDL=0 represents that the voltage of memory element has reached verifying voltage L1), then BDL=1, CDL=1, DDL=1；Otherwise BDL=0, CDL=0, DDL=0.

Therefore, compared to Gray code, step S804 and S805 can be saved by speech coding so that operation decreased number, accelerates program speed, reduces power consumption simultaneously.

In method 800, the Gray code code word of verifying voltage L2 is " 1100 ", and method 800 also includes: step S808, to being programmed that memory element checking pulse L2 (that is, verifying voltage L2)；Step S809, to being programmed that memory element performs the latch of pulse L2；Step S810, detects first " 1 " (that is, detection ADL=1)；Step S811, detects second " 1 " (that is, detection BDL=1)；Step S812, detects two " 0 " (that is, detection CDL=DDL=0)；And step S813, above-mentioned steps S810-S812 will be met and the data latches group by the memory element of the checking of verifying voltage L2 is latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Further, above-mentioned steps S810-S812 will not be met and/or the state of data latches group not over the memory element of the checking of verifying voltage L2 remains unchanged.

Such as, L2 (Gray code " 1100 ") checking and latch can include following operation:

A) BUS charging BUS=1, draws high TDL=1.

B) BUS charging BUS=1, reads ADL, then draws high TDL=1.If ADL=1, then TDL=0；Otherwise TDL=1.

C) BUS charging BUS=1, reads BDL, then draws high TDL=1.If BDL=1, then TDL=0；Otherwise TDL=1.

D) BUS charging BUS=1, reads CDL, DDL, SDL, TDL, draws high CDL, DDL=1.If CDL=0, DDL=0, SDL=0, TDL=0, then CDL=1, DDL=1；Otherwise CDL=0, DDL=0.

In method 8000, the speech coding code word of verifying voltage L2 is " 1100 ", and method 8000 also includes: step S8008, to being programmed that memory element checking pulse L2 (that is, verifying voltage L2)；Step S8009, to being programmed that memory element performs the latch of pulse L2；Step S8010, detects first " 1 " (that is, detection ADL=1)；Step S8012, detects two " 0 " (that is, detection CDL=DDL=0)；And step S8013, above-mentioned steps S8010 and S8012 will be met and the data latches group by the memory element of the checking of verifying voltage L2 is latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Further, above-mentioned steps S8010, S8012 will not be met and/or the state of data latches group not over the memory element of the checking of verifying voltage L2 remains unchanged.

Such as, L2 (speech coding " 1100 ") checking and latch can include following operation:

BUS charges BUS=1, draws high TDL=1.BUS charges BUS=1, reads ADL, then draws high TDL=1, if ADL=1, then TDL=0, otherwise TDL=1.Read CDL, DDL, TDL, SDL, then draw high CDL=1, DDL=1；If CDL=0, DDL=0, TDL=0, SDL=0, then CDL=1, DDL=1, otherwise CDL=0, DDL=0.

Therefore, compared to Gray code, step S811 can be saved by speech coding so that operation decreased number, accelerates program speed, reduces power consumption simultaneously.

Referring to Fig. 8 B, in method 800, the Gray code code word of verifying voltage L3 is " 1000 ", and method 800 includes: step S814, to being programmed that memory element checking pulse L3 (that is, verifying voltage L3)；Step S815, to being programmed that memory element performs the latch of pulse L3；Step S816, detects first " 1 " (that is, detection ADL=1)；Step S817, detects three " 0 " (that is, detection BDL=CDL=DDL=0)；And step S818, above-mentioned steps S816-S817 will be met and the data latches group by the memory element of the checking of verifying voltage L3 is latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Further, above-mentioned steps S816-S817 will not be met and/or the state of data latches group not over the memory element of the checking of verifying voltage L3 remains unchanged.

Such as, L3 (Gray code " 1000 ") checking and latch can include following operation:

A) BUS is charged (that is, arranging BUS=1), draw high labelling latch (such as, TDL=1 is set).

C) BUS charging BUS=1, reads BDL, CDL, DDL, SDL, TDL, draws high BDL, CDL, DDL.If BDL=0, CDL=0, DDL=0, SDL=0, TDL=0, then BDL=1, CDL=1, DDL=1；Otherwise BDL=0, CDL=0, DDL=0.

In method 8000, the speech coding code word of verifying voltage L3 is " 1001 ", and method 8000 also includes: step S8014, to being programmed that memory element checking pulse L3 (that is, verifying voltage L3)；Step S8015, to being programmed that memory element performs the latch of pulse L3；Step S8016, detects first " 1 " (that is, detection ADL=1)；Step S8017, detects two " 0 " (that is, detection BDL=CDL=0)；And step S8018, above-mentioned steps S8016 and S8017 will be met and the data latches group by the memory element of the checking of verifying voltage L3 is latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Further, above-mentioned steps S8016, S8017 will not be met and/or the state of data latches group not over the memory element of the checking of verifying voltage L3 remains unchanged.

Such as, L3 (speech coding " 1001 ") checking and latch can include following operation:

BUS charges BUS=1, draws high TDL=1.BUS charges BUS=1, reads ADL, then draws high TDL=1, if ADL=1, then TDL=0, otherwise TDL=1.Read BDL, CDL, TDL, SDL, then draw high BDL=1, CDL=1；If BDL=0, CDL=0, TDL=0, SDL=0, then BDL=1, CDL=1, otherwise BDL=0, CDL=0.

In method 800, the Gray code code word of verifying voltage L4 is " 1010 ", and method 800 also includes: step S819, to being programmed that memory element checking pulse L4 (that is, verifying voltage L4)；Step S820, to being programmed that memory element performs the latch of pulse L4；Step S821, detects first " 1 " (that is, detection ADL=1)；Step S822, detects second " 1 " (that is, detection CDL=1)；Step S823, detects two " 0 " (that is, detection BDL=DDL=0)；And step S824, above-mentioned steps S821-S823 will be met and the data latches group by the memory element of the checking of verifying voltage L4 is latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Further, above-mentioned steps S821-S823 will not be met and/or the state of data latches group not over the memory element of the checking of verifying voltage L4 remains unchanged.

Such as, L4 (Gray code " 1010 ") checking and latch can include following operation:

A) BUS charging BUS=1, draws high TDL=1.

C) BUS charging BUS=1, reads CDL, then draws high TDL=1.If CDL=1, then TDL=0；Otherwise TDL=1.

D) BUS charging BUS=1, reads BDL, DDL, SDL, TDL, draws high BDL=1, DDL=1.If BDL=0, DDL=0, SDL=0, TDL=0, then BDL=1, DDL=1；Otherwise BDL=0, DDL=0.

In method 8000, the speech coding code word of verifying voltage L4 is " 1010 ", and method 8000 also includes: step S8019, to being programmed that memory element checking pulse L4 (that is, verifying voltage L4)；Step S8020, to being programmed that memory element performs the latch of pulse L4；Step S8021, detects first " 1 " (that is, detection ADL=1)；Step S8023, detects two " 0 " (that is, detection BDL=DDL=0)；And step S8024, above-mentioned steps S8021 and S8023 will be met and the data latches group by the memory element of the checking of verifying voltage L4 is latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Further, above-mentioned steps S8021, S8023 will not be met and/or the state of data latches group not over the memory element of the checking of verifying voltage L4 remains unchanged.

Such as, L4 (speech coding " 1010 ") checking and latch can include following operation:

BUS charges BUS=1, draws high TDL=1.BUS charges BUS=1, reads ADL, then draws high TDL=1, if ADL=1, then TDL=0；Otherwise TDL=1.Read BDL, DDL, TDL, SDL, then draw high BDL=1, DDL=1；If BDL=0, DDL=0, TDL=0, SDL=0, then BDL=1, DDL=1, otherwise BDL=0, DDL=0.

Therefore, compared to Gray code, step S822 can be saved by speech coding so that operation decreased number, accelerates program speed, reduces power consumption simultaneously.

Referring to Fig. 8 C, in method 800, the Gray code code word of verifying voltage L5 is " 1011 ", and method 800 also includes: step S825, to being programmed that memory element checking pulse L5 (that is, verifying voltage L5)；Step S826, to being programmed that memory element performs the latch of pulse L5；Step S827, detects first " 1 " (that is, detection ADL=1)；Step S828, detects second " 1 " (that is, detection CDL=1)；Step S829, the 3rd " 1 " of detection (that is, detection DDL=1)；Step S830, detects one " 0 " (that is, detection BDL=0)；And step S831, above-mentioned steps S827-S830 will be met and the data latches group by the memory element of the checking of verifying voltage L5 is latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Further, above-mentioned steps S827-S830 will not be met and/or the state of data latches group not over the memory element of the checking of verifying voltage L5 remains unchanged.

Such as, L5 (Gray code " 1011 ") checking and latch can include following operation:

A) BUS charging BUS=1, draws high TDL=1.

C) BUS charging BUS=1, reads CDL, then draws high TDL=1.If CDL=1, then TDL=0；Otherwise TDL=1

D) BUS charging BUS=1, reads DDL, then draws high TDL=1.If DDL=1, then TDL=0；Otherwise TDL=1.

E) BUS charging BUS=1, reads BDL, SDL, TDL, draws high BDL=1.If BDL=0, SDL=0, TDL=0, then BDL=1；Otherwise BDL=0.

In method 8000, the speech coding code word of verifying voltage L5 is " 1011 ", and method 8000 also includes: step S8025, to being programmed that memory element checking pulse L5 (that is, verifying voltage L5)；Step S8026, to being programmed that memory element performs the latch of pulse L5；Step S8027, detects first " 1 " (that is, detection ADL=1)；Step S8030, detects one " 0 " (that is, detection BDL=0)；And step S8031, above-mentioned steps S8027 and S8030 will be met and the data latches group by the memory element of the checking of verifying voltage L5 is latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Further, above-mentioned steps S8027, S8030 will not be met and/or the state of data latches group not over the memory element of the checking of verifying voltage L5 remains unchanged.

Such as, L5 (speech coding " 1011 ") checking and latch can include following operation:

BUS charges BUS=1, draws high TDL=1.BUS charges BUS=1, reads ADL, then draws high TDL=1, if ADL=1, then TDL=0；Otherwise TDL=1.Read BDL, TDL, SDL, then draw high BDL=1；If BDL=0, TDL=0, SDL=0, then BDL=1, otherwise BDL=0.

Therefore, compared to Gray code, step S828-S829 can be saved by speech coding so that operation decreased number, accelerates program speed, reduces power consumption simultaneously

In method 800, the Gray code code word of verifying voltage L6 is " 1001 ", and method 800 also includes: step S832, to being programmed that memory element checking pulse L6 (that is, verifying voltage L6)；Step S833, to being programmed that memory element performs the latch of pulse L6；Step S834, detects first " 1 " (that is, detection ADL=1)；Step S835, detects second " 1 " (that is, detection DDL=1)；Step S836, detects two " 0 " (that is, detection BDL=CDL=0)；And step S837, above-mentioned steps S834-S836 will be met and the data latches group by the memory element of the checking of verifying voltage L6 is latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Further, above-mentioned steps S834-S836 will not be met and/or the state of data latches group not over the memory element of the checking of verifying voltage L5 remains unchanged.

Such as, L6 (Gray code " 1001 ") checking and latch can include following operation:

A) BUS charging BUS=1, draws high TDL=1.

C) BUS charging BUS=1, reads DDL, then draws high TDL=1.If DDL=1, then TDL=0；Otherwise TDL=1.

D) BUS charging BUS=1, reads BDL, CDL, SDL, TDL, draws high BDL=1, CDL=1.If BDL=0, CDL=0, SDL=0, TDL=0, then BDL=1, CDL=1；Otherwise BDL=0, CDL=0.

In method 8000, the speech coding code word of verifying voltage L6 is " 1110 ", and method 8000 also includes: step S8032, to being programmed that memory element checking pulse L6 (that is, verifying voltage L6)；Step S8033, to being programmed that memory element performs the latch of pulse L6；Step S8034, detects first " 1 " (that is, detection ADL=1)；Step S8036, detects one " 0 " (that is, detection DDL=0)；And step S8037, above-mentioned steps S8034, S8036 will be met and the data latches group by the memory element of the checking of verifying voltage L6 is latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Further, above-mentioned steps S8034, S8036 will not be met and/or the state not over the data latches group of the memory element of verifying voltage L6 remains unchanged.

Such as, L6 (speech coding " 1110 ") checking and latch can include following operation:

BUS charges BUS=1, draws high TDL=1.BUS charges BUS=1, reads ADL, then draws high TDL=1, if ADL=1, then TDL=0；Otherwise TDL=1.Read DDL, TDL, SDL, then draw high DDL=1；If DDL=0, TDL=0, SDL=0, then DDL=1, otherwise DDL=0.

Therefore, compared to Gray code, step S835 can be saved by speech coding so that operation decreased number, accelerates program speed, reduces power consumption simultaneously.

Referring to Fig. 8 D, in method 800, the Gray code code word of verifying voltage L7 is " 1101 ", and method 800 includes: step S838, to being programmed that memory element checking pulse L7 (that is, verifying voltage L7)；Step S839, to being programmed that memory element performs the latch of pulse L7；Step S840, detects first " 1 " (that is, detection ADL=1)；Step S841, detects second " 1 " (that is, detection BDL=1)；Step S842, the 3rd " 1 " of detection (that is, detection DDL=1)；Step S843, detects one " 0 " (that is, detection CDL=0)；And step S844, above-mentioned steps S840-S843 will be met and the data latches group by the memory element of the checking of verifying voltage L7 is latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Further, above-mentioned steps S840-S843 will not be met and/or the state of data latches group not over the memory element of the checking of verifying voltage L7 remains unchanged.

Such as, L7 (Gray code " 1101 ") checking and latch can include following operation:

A) BUS charging BUS=1, draws high TDL=1.

E) BUS charging BUS=1, reads CDL, SDL, TDL, draws high CDL=1.If CDL=0, SDL=0, TDL=0, then CDL=1；Otherwise CDL=0.

In method 8000, the speech coding code word of verifying voltage L7 is " 1101 ", and method 8000 includes: step S8038, to being programmed that memory element checking pulse L7 (that is, verifying voltage L7)；Step S8039, to being programmed that memory element performs the latch of pulse L7；Step S8040, detects first " 1 " (that is, detection ADL=1)；Step S8043, detects one " 0 " (that is, detection CDL=0)；And step S8044, above-mentioned steps S8040, S8043 will be met and the data latches group by the memory element of the checking of verifying voltage L7 is latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Further, above-mentioned steps S8040, S8043 will not be met and/or the state of data latches group not over the memory element of the checking of verifying voltage L7 remains unchanged.

Such as, L7 (speech coding " 1101 ") checking and latch can include following operation:

BUS charges BUS=1, draws high TDL=1.BUS charges BUS=1, reads ADL, then draws high TDL=1, if ADL=1, then TDL=0；Otherwise TDL=1.Read CDL, TDL, SDL, then draw high CDL=1；If CDL=0, TDL=0, SDL=0, then CDL=1, otherwise CDL=0.

Therefore, compared to Gray code, step S841-S842 can be saved by speech coding so that operation decreased number, accelerates program speed, reduces power consumption simultaneously.

In method 800, the Gray code code word of verifying voltage L8 is " 0101 ", and method 800 also includes: step S845, to being programmed that memory element checking pulse L8 (that is, verifying voltage L8)；Step S846, to being programmed that memory element performs the latch of pulse L8；Step S847, detects first " 1 " (that is, detection BDL=1)；Step S848, detects second " 1 " (that is, detection DDL=1)；Step S849, detects two " 0 " (that is, detection ADL=CDL=0)；And step S850, above-mentioned steps S847-S849 will be met and the data latches group by the memory element of the checking of verifying voltage L8 is latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Further, above-mentioned steps S847-S849 will not be met and/or the state of data latches group not over the memory element of the checking of verifying voltage L8 remains unchanged.

Such as, L8 (Gray code " 0101 ") checking and latch can include following operation:

A) BUS charging BUS=1, draws high TDL=1.

B) BUS charging BUS=1, reads BDL, then draws high TDL=1.If BDL=1, then TDL=0；Otherwise TDL=1.

D) BUS charging BUS=1, reads ADL, CDL, SDL, TDL, draws high ADL=1, CDL=1.If ADL=0, CDL=0, SDL=0, TDL=0, then ADL=1, CDL=1；Otherwise ADL=0, CDL=0.

In method 8000, the speech coding code word of verifying voltage L8 is " 0000 ", and method 8000 also includes: step S8045, to being programmed that memory element checking pulse L8 (that is, verifying voltage L8)；Step S8046, to being programmed that memory element performs the latch of pulse L8；Step S8049, detects four " 0 " (that is, detection ADL=BDL=CDL=DDL=0)；And step S8050, above-mentioned steps S8049 will be met and the data latches group by the memory element of the checking of verifying voltage L8 is latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Further, above-mentioned steps S8049 will not be met and/or the state of data latches group not over the memory element of the checking of verifying voltage L8 remains unchanged.

Such as, L8 (speech coding " 0000 ") checking and latch can include following operation:

BUS charges BUS=1, draws high TDL=1, reads ADL, BDL, CDL, DDL, TDL, SDL, then draws high ADL=1, BDL=1, CDL=1, DDL=1.If ADL=0, BDL=0, CDL=0, DDL=0, TDL=0, SDL=0, then ADL=1, BDL=1, CDL=1, DDL=1；Otherwise ADL=0, BDL=0, CDL=0, DDL=0.

Therefore, compared to Gray code, step S847-S848 can be saved by speech coding so that operation decreased number, accelerates program speed, reduces power consumption simultaneously.

Referring to Fig. 8 E, in method 800, the Gray code code word of verifying voltage L9 is " 0001 ", and method 800 also includes: step S851, to being programmed that memory element checking pulse L9 (that is, verifying voltage L9)；Step S852, to being programmed that memory element performs the latch of pulse L9；Step S853, detects first " 1 " (that is, detection DDL=1)；Step S854, detects three " 0 " (that is, detection ADL=BDL=CDL=0)；And step S855, above-mentioned steps S853-S854 will be met and the data latches group by the memory element of the checking of verifying voltage L9 is latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Further, above-mentioned steps S853-S854 will not be met and/or the state of data latches group not over the memory element of the checking of verifying voltage L9 remains unchanged.

Such as, L9 (Gray code " 0001 ") checking and latch can include following operation:

A) BUS charging BUS=1, draws high TDL=1.

B) BUS charging BUS=1, reads DDL, then draws high TDL=1.If DDL=1, then TDL=0；Otherwise TDL=1.

C) BUS charging BUS=1, reads ADL, BDL, CDL, SDL, TDL, draws high ADL=1, BDL=1, CDL=1.If ADL=0, BDL=0, CDL=0, SDL=0, TDL=0, then ADL=1, BDL=1, CDL=1；Otherwise ADL=0, BDL=0, CDL=0.

In method 8000, the speech coding code word of verifying voltage L9 is " 0001 ", and method 8000 also includes: step S8051, to being programmed that memory element checking pulse L9 (that is, verifying voltage L9)；Step S8052, to being programmed that memory element performs the latch of pulse L9；Step S8054, detects three " 0 " (that is, detection ADL=BDL=CDL=0)；And step S8055, above-mentioned steps S8054 will be met and the data latches group by the memory element of the checking of verifying voltage L9 is latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Further, above-mentioned steps S8054 will not be met and/or the state of data latches group not over the memory element of the checking of verifying voltage L9 remains unchanged.

Such as, L9 (speech coding " 0001 ") checking and latch can include following operation:

BUS charges BUS=1, draws high TDL=1, reads ADL, BDL, CDL, TDL, SDL, then draws high ADL=1, BDL=1, CDL=1.If ADL=0, BDL=0, CDL=0, TDL=0, SDL=0, then ADL=1, BDL=1, CDL=1, otherwise ADL=0, BDL=0, CDL=0.

Therefore, compared to Gray code, step S853 can be saved by speech coding so that operation decreased number, accelerates program speed, reduces power consumption simultaneously.

In method 800, the Gray code code word of verifying voltage L10 is " 0011 ", and method 800 also includes: step S856, to being programmed that memory element checking pulse L10 (that is, verifying voltage L10)；Step S857, to being programmed that memory element performs the latch of pulse L10；Step S858, detects first " 1 " (that is, detection CDL=1)；Step S859, detects second " 1 " (that is, detection DDL=1)；Step S860, detects two " 0 " (that is, detection ADL=BDL=0)；And step S861, above-mentioned steps S858-S860 will be met and the data latches group by the memory element of the checking of verifying voltage L10 is latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Further, above-mentioned steps S858-S860 will not be met and/or the state of data latches group not over the memory element of the checking of verifying voltage L10 remains unchanged.

Such as, L10 (Gray code " 0011 ") checking and latch can include following operation:

A) BUS charging BUS=1, draws high TDL=1.

B) BUS charging BUS=1, reads CDL, then draws high TDL=1.If CDL=1, then TDL=0；Otherwise TDL=1.

D) BUS charging BUS=1, reads ADL, BDL, SDL, TDL, draws high ADL=1, BDL=1.If ADL=0, BDL=0, SDL=0, TDL=0, then ADL=1, BDL=1；Otherwise ADL=0, BDL=0.

In method 8000, the speech coding code word of verifying voltage L10 is " 0100 ", and method 8000 also includes: step S8056, to being programmed that memory element checking pulse L10 (that is, verifying voltage L10)；Step S8057, to being programmed that memory element performs the latch of pulse L10；Step S8060, detects three " 0 " (that is, detection ADL=CDL=DDl=0)；And step S8061, above-mentioned steps S8060 will be met and the data latches group by the memory element of the checking of verifying voltage L10 is latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Further, above-mentioned steps S8060 will not be met and/or the state of data latches group not over the memory element of the checking of verifying voltage L10 remains unchanged.

Such as, L10 (speech coding " 0100 ") checking and latch can include following operation:

BUS charges BUS=1, draws high TDL=1, reads ADL, CDL, DDL, TDL, SDL, then draws high ADL=1, CDL=1, DDL=1.If ADL=0, CDL=0, DDL=0, TDL=0, SDL=0, then ADL=1, CDL=1, DDL=1, otherwise ADL=0, CDL=0, DDL=0.

Therefore, compared to Gray code, step S858-S859 can be saved by speech coding so that operation decreased number, accelerates program speed, reduces power consumption simultaneously.

Referring to Fig. 8 F, in method 800, the Gray code code word of verifying voltage L11 is " 0010 ", and method 800 includes: step S862, to being programmed that memory element checking pulse L11 (that is, verifying voltage L11)；Step S863, to being programmed that memory element performs the latch of pulse L11；Step S864, detects first " 1 " (that is, detection CDL=1)；Step S865, detects three " 0 " (that is, detection ADL=BDL=DDL=0)；And step S866, above-mentioned steps S864-S865 will be met and the data latches group by the memory element of the checking of verifying voltage L11 is latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Further, above-mentioned steps S864-S865 will not be met and/or the state of data latches group not over the memory element of the checking of verifying voltage L11 remains unchanged.

Such as, L11 (Gray code " 0010 ") checking and latch can include following operation:

A) BUS charging BUS=1, draws high TDL=1.

C) BUS charging BUS=1, reads ADL, BDL, DDL, SDL, TDL, draws high ADL=1, BDL=1, DDL=1.If ADL=0, BDL=0, DDL=0, SDL=0, TDL=0, then ADL=1, BDL=1, DDL=1；Otherwise ADL=0, BDL=0, DDL=0.

In method 8000, the speech coding code word of verifying voltage L11 is " 0010 ", and method 8000 includes: step S8062, to being programmed that memory element checking pulse L11 (that is, verifying voltage L11)；Step S8063, to being programmed that memory element performs the latch of pulse L11；Step S8065, detects three " 0 " (that is, detection ADL=BDL=DDL=0)；And step S8066, above-mentioned steps S8066 will be met and the data latches group by the memory element of the checking of verifying voltage L11 is latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Further, above-mentioned steps S8066 will not be met and/or the state of data latches group not over the memory element of the checking of verifying voltage L11 remains unchanged.

Such as, L11 (speech coding " 0010 ") checking and latch can include following operation:

BUS charges BUS=1, draws high TDL=1, reads ADL, BDL, DDL, TDL, SDL, then draws high ADL=1, BDL=1, DDL=1.If ADL=0, BDL=0, DDL=0, TDL=0, SDL=0, then ADL=1, BDL=1, DDL=1, otherwise ADL=0, BDL=0, DDL=0.

Therefore, compared to Gray code, step S864 can be saved by speech coding so that operation decreased number, accelerates program speed, reduces power consumption simultaneously.

In method 800, the Gray code code word of verifying voltage L12 is " 0000 ", and method 800 also includes: step S867, to being programmed that memory element checking pulse L12 (that is, verifying voltage L12)；Step S868, to being programmed that memory element performs the latch of pulse L12；Step S869, detects four " 0 " (that is, detection ADL=BDL=CDL=DDL=0)；And step S870, above-mentioned steps S869 will be met and the data latches group by the memory element of the checking of verifying voltage L12 is latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Further, above-mentioned steps S869 will not be met and/or the state of data latches group not over the memory element of the checking of verifying voltage L12 remains unchanged.

Such as, L12 (Gray code " 0000 ") checking and latch can include following operation:

A) BUS charging BUS=1, draws high TDL=1.

B) BUS charging BUS=1, reads ADL, BDL, CDL, DDL, SDL, TDL, draws high ADL=1, BDL=1, CDL=1, DDL=1,.If ADL=0, BDL=0, CDL=0, DDL=0, SDL=0, TDL=0, then ADL=1, BDL=1, CDL=1, DDL=1；Otherwise ADL=0, BDL=0, CDL=0, DDL=0.

In method 8000, the speech coding code word of verifying voltage L12 is " 0011 ", and method 8000 also includes: step S8067, to being programmed that memory element checking pulse L12 (that is, verifying voltage L12)；Step S8068, to being programmed that memory element performs the latch of pulse L12；Step S8069, detects two " 0 " (that is, detection ADL=BDL=0)；And step S8070, above-mentioned steps S8069 will be met and the data latches group by the memory element of the checking of verifying voltage L12 is latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Further, above-mentioned steps S8069 will not be met and/or the state of data latches group not over the memory element of the checking of verifying voltage L12 remains unchanged.

Such as, L12 (speech coding " 0011 ") checking and latch can include following operation:

BUS charges BUS=1, draws high TDL=1, reads ADL, BDL, TDL, SDL, then draws high ADL=1, BDL=1.If ADL=0, BDL=0, TDL=0, SDL=0, then ADL=1, BDL=1, otherwise ADL=0, BDL=0.

Referring to Fig. 8 G, in method 800, the Gray code code word of verifying voltage L13 is " 0100 ", and method 800 includes: step S871, to being programmed that memory element checking pulse L13 (that is, verifying voltage L13)；Step S872, to being programmed that memory element performs the latch of pulse L13；Step S873, detects three " 0 " (that is, detection ADL=CDL=DDL=0)；And step S874, above-mentioned steps S873 will be met and the data latches group by the memory element of the checking of verifying voltage L13 is latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Further, above-mentioned steps S873 will not be met and/or the state of data latches group not over the memory element of the checking of verifying voltage L13 remains unchanged.

Such as, L13 (Gray code " 0100 ") checking and latch can include following operation:

A) BUS charging BUS=1, draws high TDL=1.

C) BUS charging BUS=1, reads ADL, CDL, DDL, SDL, TDL, draws high ADL=1, CDL=1, DDL=1.If ADL=0, CDL=0, DDL=0, SDL=0, TDL=0, then ADL=1, CDL=1, DDL=1；Otherwise ADL=0, CDL=0, DDL=0.

In method 8000, the speech coding code word of verifying voltage L13 is " 0101 ", and method 8000 includes: step S8071, to being programmed that memory element checking pulse L13 (that is, verifying voltage L13)；Step S8072, to being programmed that memory element performs the latch of pulse L13；Step S8073, detects two " 0 " (that is, detection ADL=CDL=0)；And step S8074, above-mentioned steps S8073 will be met and the data latches group by the memory element of the checking of verifying voltage L13 is latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Further, above-mentioned steps S8073 will not be met and/or the state of data latches group not over the memory element of the checking of verifying voltage L13 remains unchanged.

Such as, L13 (speech coding " 0101 ") checking and latch can include following operation:

BUS charges BUS=1, draws high TDL=1, reads ADL, CDL, TDL, SDL, then draws high ADL=1, CDL=1.If ADL=0, CDL=0, TDL=0, SDL=0, then ADL=1, CDL=1, otherwise ADL=0, CDL=0.

In method 800, the Gray code code word of verifying voltage L14 is " 0110 ", and method 800 also includes: step S875, to being programmed that memory element checking pulse L14 (that is, verifying voltage L14)；Step S876, to being programmed that memory element performs the latch of pulse L14；Step S877, detects two " 0 " (that is, detection ADL=DDL=0)；And step S878, above-mentioned steps S877 will be met and the data latches group by the memory element of the checking of verifying voltage L14 is latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Further, above-mentioned steps S877 will not be met and/or the state of data latches group not over the memory element of the checking of verifying voltage L14 remains unchanged.

Such as, L14 (Gray code " 0110 ") checking and latch can include following operation:

A) BUS charging BUS=1, draws high TDL=1.

D) BUS charging BUS=1, reads ADL, DDL, SDL, TDL, draws high ADL=1, DDL=1.If ADL=0, DDL=0, SDL=0, TDL=0, then ADL=1, DDL=1；Otherwise ADL=0, DDL=0.

In method 8000, the speech coding code word of verifying voltage L14 is " 0110 ", and method 8000 also includes: step S8075, to being programmed that memory element checking pulse L14 (that is, verifying voltage L14)；Step S8076, to being programmed that memory element performs the latch of pulse L14；Step S8077, detects two " 0 " (that is, detection ADL=DDL=0)；And step S8078, above-mentioned steps S8077 will be met and the data latches group by the memory element of the checking of verifying voltage L14 is latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Further, above-mentioned steps S8077 will not be met and/or the state of data latches group not over the memory element of the checking of verifying voltage L14 remains unchanged.

Such as, L14 (speech coding " 0110 ") checking and latch can include following operation:

BUS charges BUS=1, draws high TDL=1, reads ADL, DDL, TDL, SDL, then draws high ADL=1, DDL=1.If ADL=0, DDL=0, TDL=0, SDL=0, then ADL=1, DDL=1, otherwise ADL=0, DDL=0.

Referring to Fig. 8 H, in method 800, the Gray code code word of verifying voltage L15 is " 0111 ", and method 800 includes: step S879, to being programmed that memory element checking pulse L15 (that is, verifying voltage L15)；Step S880, to being programmed that memory element performs the latch of pulse L15；Step S881, detects one " 0 " (that is, detection ADL=0)；And step S882, above-mentioned steps S881 will be met and the data latches group by the memory element of the checking of verifying voltage L15 is latched as " 1111 "

(that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Further, above-mentioned steps S881 will not be met and/or the state of data latches group not over the memory element of the checking of verifying voltage L15 remains unchanged.

Such as, L15 (Gray code " 0111 ") checking and latch can include following operation:

A) BUS charging BUS=1, draws high TDL=1.

E) BUS charging BUS=1, reads ADL, SDL, TDL, draws high ADL=1.If ADL=0, SDL=0, TDL=0, then ADL=1；Otherwise ADL=0.

In method 8000, the speech coding code word of verifying voltage L15 is " 0111 ", and method 8000 includes: step S8079, to being programmed that memory element checking pulse L15 (that is, verifying voltage L15)；Step S8080, to being programmed that memory element performs the latch of pulse L15；Step S8081, detects one " 0 " (that is, detection ADL=0)；And step S8082, above-mentioned steps S8081 will be met and the data latches group by the memory element of the checking of verifying voltage L15 is latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Further, above-mentioned steps S8081 will not be met and/or the state of data latches group not over the memory element of the checking of verifying voltage L15 remains unchanged.

Such as, L15 (speech coding " 0111 ") checking and latch can include following operation:

BUS charges BUS=1, draws high TDL=1, reads ADL, TDL, SDL, then draws high ADL=1.If ADL=0, TDL=0, SDL=0, then ADL=1, otherwise ADL=0.

The schematic block diagram of many program bits device 1000 of a kind of nand memory that Figure 10 provides for disclosure embodiment.As shown in Figure 10, device 1000 can include writing module 1002, transcoding module 1004, data scanning module 1006, pre-programmed and authentication module 1007, programming module 1008, programming authentication module 1010, latches scan module 1012, confirm scan module 1014 and judge module 1016.

Writing module 1002 will be for being programmed that multi-bit data is written in data latches group, and described multi-bit data is Gray code codeword.Writing module 1002 can realize by the programmed instruction of storage in processor 402 run memory 404 in controller 102 as shown in Figure 4, and can perform the step S502 in many program bits method 500 of the nand memory according to disclosure embodiment and/or the step S552 in method 550.

Transcoding module 1004 is for being converted to speech coding code word by described multi-bit data from Gray code codeword.Transcoding module 1004 can realize by the programmed instruction of storage in processor 402 run memory 404 in controller 102 as shown in Figure 4, and can perform the step S504 in many program bits method 500 of the nand memory according to disclosure embodiment and/or the step S554 in method 550.

Data scanning module 1006 is used for determining in storage array to be needed to be programmed that memory element, wherein needs to be programmed that described memory element includes target threshold voltage and is not more than the memory element of described predetermined voltage more than the memory element of predetermined voltage and target threshold voltage.Such as, data scanning module 1006 is for scanning described data latches group to determine that data latches group that storage information is erasing state and storage information are not the data latches groups of erasing state, the memory element corresponding with the data latches group that storage information is erasing state is set to not programming state, and memory element corresponding for the data latches group with storage information not being erasing state is set to programming state, wherein it is desired to be programmed that described memory element is the memory element being set to programming state.Data scanning module 1006 can realize by the programmed instruction of storage in processor 402 run memory 404 in controller 102 as shown in Figure 4, and can perform the step S506 in many program bits method 500 of the nand memory according to disclosure embodiment and/or step S556 and the S558 in method 550.

Pre-programmed and authentication module 1007 are for being pre-programmed into intermediate state voltage by target threshold voltage more than each described memory element of described predetermined voltage.Programming module 1007 can realize by the programmed instruction of storage in processor 402 run memory 404 in controller 102 as shown in Figure 4, and can perform the step S508 in many program bits method 500 of the nand memory according to disclosure embodiment and/or the step S559 in method 550.

Programming module 1008 is for needing in storage array to be programmed that memory element is programmed.Such as, programming module 1008 is used for: each described memory element that target threshold voltage is not more than described predetermined voltage is programmed；And target threshold voltage is programmed more than each described memory element of described predetermined voltage.Programming module 1008 can realize by the programmed instruction of storage in processor 402 run memory 404 in controller 102 as shown in Figure 4, and can perform step S510 and the S515 in many program bits method 500 of the nand memory according to disclosure embodiment and/or S560 and the S572 in method 550.

Programming authentication module 1010 is for being programmed that each described memory element performs programming verification operation.Such as, programming authentication module 1010 is used for: target threshold voltage is not more than each described memory element of described predetermined voltage, performs programming verification operation；And to the target threshold voltage each described memory element more than described predetermined voltage, perform programming verification operation.Programming authentication module 1010 can realize by the programmed instruction of storage in processor 402 run memory 404 in controller 102 as shown in Figure 4, and the programming verification operation that can perform in programming verification operation, Fig. 6 B of method 600 in the step S510 in many program bits method 500 of the nand memory according to disclosure embodiment and step S562 and S574, Fig. 6 A in step S516, method 550 in programming verification operation, Fig. 7 A-7P of method 630 and the programming verification operation in Fig. 8 A-8H.

Latch scan module 1012 for being programmed that each described memory element performs to latch scan operation.Such as, latch scan module 1012 and be used for: target threshold voltage is not more than each described memory element of described predetermined voltage, perform to latch scan operation；And to the target threshold voltage each described memory element more than described predetermined voltage, perform to latch scan operation.Latch scan module 1012 can processor 402 run memory 404 in controller 102 as shown in Figure 4 realize by the programmed instruction of storage, and compiling of method 600 in step S512 and the S518 in many program bits method 500 of the nand memory according to disclosure embodiment, step S564 and S576, Fig. 6 A in method 550 can be performed latch the latch scan operation latched in scan operation and Fig. 8 A-8H latching in scan operation, Fig. 7 A-7P of method 630 in scan operation, Fig. 6 B.

Confirm that scan module 1014 is for being programmed that each described memory element performs to confirm scan operation.Such as, confirm that scan module 1014 is used for: target threshold voltage is not more than each described memory element of described predetermined voltage, perform to confirm scan operation；And to the target threshold voltage each described memory element more than described predetermined voltage, perform to confirm scan operation.Confirm that scan module 1014 can realize by the programmed instruction of storage in processor 402 run memory 404 in controller 102 as shown in Figure 4, and can perform step S514 and the S520 in many program bits method 500 of the nand memory according to disclosure embodiment, method 600 confirms the confirmation scan operation confirmed in scan operation and Fig. 7 A-7P of method 630 in scan operation, Fig. 6 B in step S566 and S578, Fig. 6 A in method 550.

Judge module 1016 is used for, at the one or more verifying voltages of use to being programmed that memory element performs programming verification operation, latches scan operation and after confirmation scan operation, it is determined that need to be programmed that in described memory element, whether also one or more memory element not yet reach respective target threshold voltage in this programming.If also having one or more memory element not yet to reach respective target threshold voltage in this programming, the one or more memory element is programmed by described programming module 1008 again；The one or more memory element is performed programming verification operation by described programming authentication module 1010；The one or more memory element is performed to latch scan operation by described latch scan module 1012；And the one or more memory element is performed to confirm scan operation by described confirmation scan module 1014.Described judge module 1016 can realize by the programmed instruction of storage in processor 402 run memory 404 in controller 102 as shown in Figure 4, and can perform the step S568 in many program bits method 550 of the nand memory according to disclosure embodiment, S570, S580 and S582.

In addition, according to disclosure embodiment, additionally provide a kind of storage medium, store programmed instruction on said storage, the corresponding steps of many program bits method and/or the additive method performing the nand memory of disclosure embodiment it is used for when described programmed instruction is run by computer or processor, and for realizing the corresponding module in many program bits device of the nand memory according to disclosure embodiment.Described storage medium such as can include the combination in any of the storage card of smart phone, the memory unit of panel computer, the hard disk of personal computer, read only memory (ROM), Erasable Programmable Read Only Memory EPROM (EPROM), portable compact disc read only memory (CD-ROM), USB storage or above-mentioned storage medium.

Although describing example embodiment by reference to accompanying drawing here, it should be understood that above-mentioned example embodiment is merely exemplary, and it is not intended to the scope of the present disclosure is limited to this.Those of ordinary skill in the art can make various changes and modifications wherein, without departing from the scope of the present disclosure and spirit.All such changes and modifications are intended to be included within the scope of the present disclosure required by claims.

Claims

1. many program bits method of nand memory, including:

To be programmed that multi-bit data write data bank of latches, described multi-bit data is Gray code codeword；

Described multi-bit data is converted to speech coding code word from described Gray code codeword；

Determine and storage array needs be programmed that memory element, it is necessary to be programmed that described memory element includes target threshold voltage and is not more than the memory element of described predetermined voltage more than the memory element of predetermined voltage and target threshold voltage；

Target threshold voltage is pre-programmed into intermediate state voltage more than each described memory element of described predetermined voltage；

The each described memory element that target threshold voltage is not more than described predetermined voltage is programmed；

Target threshold voltage is not more than each described memory element of described predetermined voltage:

Perform programming verification operation；

Perform to latch scan operation；And

Perform to confirm scan operation；

Target threshold voltage is programmed more than each described memory element of described predetermined voltage；And

To the target threshold voltage each described memory element more than described predetermined voltage:

Perform programming verification operation；

Perform to latch scan operation；And

Perform to confirm scan operation.

2. the method for claim 1, wherein, target threshold voltage is more than the memory element that the highest order that described memory element is speech coding code word is 0 of described predetermined voltage, and target threshold voltage is not more than the memory element that the highest order that described memory element is speech coding code word is 1 of described predetermined voltage.

3. the method for claim 1, wherein

Target threshold voltage is not more than each described memory element of described predetermined voltage, performs programming verification operation and include:

Select the first verifying voltage, and verify whether the voltage having enrolled each described memory element reaches described first verifying voltage；

Target threshold voltage is not more than each described memory element of described predetermined voltage, performs to latch scan operation and include:

Latch mode will be set to by the programming checking of described first verifying voltage and the data latches group of memory element that target threshold voltage is described first verifying voltage, and the programming checking of described first verifying voltage will do not passed through and/or target threshold voltage is not that the state of data latches group of memory element of described first verifying voltage remains unchanged；

Target threshold voltage is not more than each described memory element of described predetermined voltage, performs to confirm that scan operation includes:

It is the memory element of latch mode for data latches group, is judged that latch is set to successfully latch mode, and be not the memory element of latch mode for data latches group, judged that latch is set to latch unsuccessful state.

4. method as claimed in claim 3, wherein, latch mode will be set to by the data latches group of the memory element that programming is verified and target threshold voltage is described first verifying voltage of described first verifying voltage, and the programming checking of described first verifying voltage will do not passed through and/or target threshold voltage is not that the state of data latches group of memory element of described first verifying voltage remains unchanged, including:

Whether the highest order of the speech coding code word detecting data latches group storage corresponding to described memory element is " 1 ", quantity and the position of detecting " 0 " in the speech coding code word that in the speech coding code word of data latches group storage corresponding to described memory element, whether the quantity of " 0 " is corresponding with described first verifying voltage with position are consistent, and whether detect voltage verification latch corresponding to described memory element for passing through state；

If the highest order of the speech coding code word of the data latches group storage that described memory element is corresponding is " 1 ", in the speech coding code word that in the speech coding code word of the data latches group storage that described memory element is corresponding, the quantity of " 0 " is corresponding with described first verifying voltage with position, the quantity of " 0 " and position are consistent, and voltage verification latch corresponding to described memory element is by state, arranging the data latches group corresponding with described memory element is latch mode；And

If the highest order of the speech coding code word of the data latches group storage that described memory element is corresponding is not " 1 ", and/or the quantity of " 0 " and position are inconsistent in the speech coding code word that in the speech coding code word of data latches group storage corresponding to described memory element, the quantity of " 0 " is corresponding with described first verifying voltage with position, and/or voltage verification latch corresponding to described memory element is that the state keeping the data latches group corresponding with described memory element is constant not by state.

5. the method for claim 1, wherein

To the target threshold voltage each described memory element more than described predetermined voltage, perform programming verification operation and include:

Select the second verifying voltage, and verify whether the voltage having enrolled each described memory element reaches

To described second verifying voltage, described second verifying voltage is more than described intermediate state voltage；

To the target threshold voltage each described memory element more than described predetermined voltage, perform to latch scan operation and include:

Latch mode will be set to by the programming checking of described second verifying voltage and the data latches group of memory element that target threshold voltage is described second verifying voltage, and the programming checking of described second verifying voltage will do not passed through and/or target threshold voltage is not that the state of data latches group of memory element of described second verifying voltage remains unchanged；

To the target threshold voltage each described memory element more than described predetermined voltage, perform to confirm that scan operation includes:

6. method as claimed in claim 5, wherein, latch mode will be set to by the data latches group of the memory element that programming is verified and target threshold voltage is described second verifying voltage of described second verifying voltage, and the programming checking of described second verifying voltage will do not passed through and/or target threshold voltage is not that the state of data latches group of memory element of described second verifying voltage remains unchanged, including:

Quantity and the position of detecting " 0 " in the speech coding code word that in the speech coding code word of data latches group storage corresponding to described memory element, whether the quantity of " 0 " is corresponding with described second verifying voltage with position are consistent, and whether detect voltage verification latch corresponding to described memory element for passing through state；

If the quantity of " 0 " and position are consistent in the speech coding code word that in the speech coding code word of the data latches group storage that described memory element is corresponding, the quantity of " 0 " is corresponding with described second verifying voltage with position, and voltage verification latch corresponding to described memory element is by state, arranging the data latches group corresponding with described memory element is latch mode；And

If the quantity of " 0 " and position are inconsistent in the speech coding code word that in the speech coding code word of the data latches group storage that described memory element is corresponding, the quantity of " 0 " is corresponding with described second verifying voltage with position, and/or voltage verification latch corresponding to described memory element is that the state keeping the data latches group corresponding with described memory element is constant not by state.

7. the method for claim 1, wherein determine in storage array and need to be programmed that memory element includes:

Scan described data latches group to determine that data latches group that storage information is erasing state and storage information are not the data latches groups of erasing state；

The memory element corresponding with the data latches group that storage information is erasing state is set to not programming state；And

Memory element corresponding for the data latches group with storage information not being erasing state is set to programming state, wherein it is desired to be programmed that described memory element is the memory element being set to programming state.

8. the method for claim 1, wherein

Multiple electric pressures are encoded by described speech coding, wherein, the highest order of the speech coding code word that the highest order of the speech coding code word of the Part I electric pressure of described electric pressure is the Part II electric pressure of " 0 " and described electric pressure is " 1 ", and described Part I electric pressure is all higher than described Part II electric pressure；

For described Part I electric pressure or described Part II electric pressure:

The number of " 0 " that the speech coding code word that the number of " 0 " that the speech coding code word that low-voltage-grade is corresponding includes is corresponding no less than voltage levels includes；And

For including the electric pressure of equal " 0 " number, obtain the speech coding code word of described electric pressure by changing the data latches of the minimal number of the Gray code codeword corresponding with described electric pressure.

9. many program bits device of nand memory, including:

Writing module, for being programmed that multi-bit data is written in data latches group, described multi-bit data is Gray code codeword；

Transcoding module, for being converted to speech coding code word by described multi-bit data from described Gray code codeword；

Data scanning module, being used for determining in storage array needs to be programmed that memory element, it is necessary to be programmed that described memory element includes target threshold voltage and is not more than the memory element of described predetermined voltage more than the memory element of predetermined voltage and target threshold voltage；

Pre-programmed and authentication module, for being pre-programmed into intermediate state voltage by target threshold voltage more than the described memory element of described predetermined voltage；

Programming module, is programmed more than the described memory element of described predetermined voltage for the described memory element and target threshold voltage that target threshold voltage is not more than described predetermined voltage respectively；

Programming authentication module, performs programming verification operation for the described memory element and target threshold voltage that target threshold voltage is not more than described predetermined voltage respectively more than the described memory element of described predetermined voltage；

Latch scan module, perform to latch scan operation more than the described memory element of described predetermined voltage for the described memory element and target threshold voltage that target threshold voltage is not more than described predetermined voltage respectively；And

Confirm scan module, perform to confirm scan operation more than the described memory element of described predetermined voltage for the described memory element and target threshold voltage that target threshold voltage is not more than described predetermined voltage respectively.

10. device as claimed in claim 9, wherein, target threshold voltage is more than the memory element that the highest order that described memory element is speech coding code word is 0 of described predetermined voltage, and target threshold voltage is not more than the memory element that the highest order that described memory element is speech coding code word is 1 of described predetermined voltage.