CN105719693B - More program bits method and devices of nand memory - Google Patents

More program bits method and devices of nand memory Download PDF

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Publication number
CN105719693B
CN105719693B CN201610045632.9A CN201610045632A CN105719693B CN 105719693 B CN105719693 B CN 105719693B CN 201610045632 A CN201610045632 A CN 201610045632A CN 105719693 B CN105719693 B CN 105719693B
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China
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storage unit
voltage
verifying
latch
data latches
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CN105719693A (en
Inventor
靳旭
伍冬
吴华强
钱鹤
曹堪宇
朱一明
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Zhaoyi Innovation Technology Group Co ltd
Tsinghua University
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Tsinghua University
GigaDevice Semiconductor Beijing Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells

Abstract

Provide a kind of more program bits method and devices of nand memory.The described method includes: data latches group is written in programmed multi-bit data, the multi-bit data is Gray code codeword；The multi-bit data is converted into acceleration coding codeword from the Gray code codeword；To needing programmed storage unit to be programmed in storage array；Programming verification operation is executed to programmed each storage unit；Programmed each storage unit is executed and latches scan operation；And confirmation scan operation is executed to programmed each storage unit.The method is redesigned according to the structure of latch and is encoded, and reduces the quantity of redundant operation complicated in programming process, thus can accelerate the speed of programming, reduces power consumption.

Description

More program bits method and devices of nand memory
Technical field
The disclosure generally relates to a kind of more program bits method and device thereof of NAND (NAND gate) memory.
Background technique
Each storage unit of nand flash memory can store multi-bit data, i.e., each storage unit can store with accordingly The corresponding voltage class of more bits (bit) data.For example, each storage unit of nand flash memory can store the number of 4 bits According to that is, each storage unit storage 24A voltage class in=16 voltage class.It is carried out in nand flash memory storage unit It when storage, needs to encode stored multi-bit data, and Gray code usually can be used in order to reduce error rate.? In Gray code, it is different that the adjacent code of any two only has a bit, and also only has between maximum number and minimum number One bit is different.However, in the programming process of NAND-flash memory, Gray code not adaptive circuit structure, because And the operation in cataloged procedure is made to become complicated cumbersome.For example, in realizing cataloged procedure, since there is no bases for Gray code The circuit structure of coding optimizes, so being directly programmed the operation that will lead to bulk redundancy using Gray's code table, increases Power consumption and programming time.Moreover, the increase of the bit number with the storage of each storage unit, is directly programmed using Gray code The operation in cataloged procedure will be made to become more complicated the cumbersome and more power consumptions of increase and programming time.
Summary of the invention
Embodiment of the disclosure provides a kind of more program bits method and devices of nand memory, can be in programming It is preceding that coding remaps, to optimize programming process.
At least one embodiment of the disclosure provides a kind of more program bits methods of nand memory, comprising: will be by Data latches group is written in the multi-bit data of programming, and the multi-bit data is Gray code codeword；By the multi-bit data Acceleration coding codeword is converted to from the Gray code codeword；To needing programmed storage unit to be programmed in storage array； Programming verification operation is executed to programmed each storage unit；Programmed each storage unit is executed and latches scanning Operation；And confirmation scan operation is executed to programmed each storage unit.
At least one embodiment of the disclosure additionally provides a kind of more program bits devices of nand memory, comprising: writes Enter module, for programmed multi-bit data to be written in data latches group, the multi-bit data is Gray code code Word；Transcoding module, for the multi-bit data to be converted to acceleration coding codeword from the Gray code codeword；Program mould Block, for needing programmed storage unit to be programmed in storage array；Authentication module is programmed, for programmed each The storage unit executes programming verification operation；Scan module is latched, for executing lock to programmed each storage unit Deposit scan operation；And confirmation scan module, for executing confirmation scan operation to programmed each storage unit.
For example, the programming authentication module executes programming verification operation to programmed each storage unit, comprising: choosing It selects the first verifying voltage, and verifies and be incorporated into the voltage of each storage unit and whether reach first verifying voltage.Institute It states and latches scan module to programmed each storage unit execution latch scan operation, comprising: will be tested by described first The programming of card voltage is verified and target threshold voltage sets for the data latches group of the storage unit of first verifying voltage It is set to latch mode, and by the programming verifying and/or target threshold voltage not by first verifying voltage is not described The state of the data latches group of the storage unit of first verifying voltage remains unchanged.The confirmation scan module is to programmed Each storage unit executes confirmation scan operation, comprising: is the storage unit of latch mode for data latches group, by it Judge that latch is set as successfully latch mode, and be not the storage unit of latch mode for data latches group, by it Judge that latch is set as latching unsuccessful state.
For example, the latch scan module will pass through the programming verifying of first verifying voltage and target threshold voltage It is set as latch mode for the data latches of the storage unit of first verifying voltage, and will not tested by described first The programming verifying of card voltage and/or target threshold voltage are not the data latches of the storage unit of first verifying voltage State remains unchanged, comprising: detects " 0 " in the acceleration coding codeword of the corresponding data latches group storage of the storage unit The quantity of " 0 " and position are consistent in quantity and position acceleration coding codeword whether corresponding with first verifying voltage, and And whether detection voltage verification latch corresponding with the storage unit is to pass through state；If the storage unit is corresponding The acceleration corresponding with first verifying voltage of the quantity of " 0 " and position is compiled in the acceleration coding codeword of data latches group storage Code code word in " 0 " quantity and position it is consistent, and the corresponding voltage verification latch of the storage unit be by state, if Setting data latches group corresponding with the storage unit is latch mode；And the if corresponding data lock of the storage unit Quantity and position the acceleration coding codeword corresponding with first verifying voltage of " 0 " in the acceleration coding codeword of storage group storage In " 0 " quantity and position is inconsistent and/or the corresponding voltage verification latch of the storage unit is to protect not by state It is constant to hold data latches group state corresponding with the storage unit.
For example, the value of the voltage verification latch is " 1 " when the voltage verification latch is not pass through state； When the voltage verification latch is to pass through state, the value of the voltage verification latch is " 0 ".The latch scan module Detect in the acceleration coding codeword of the storage unit corresponding data latches group storage the quantity of " 0 " and position whether with it is described First verifying voltage is corresponding to accelerate the quantity of " 0 " and position in coding codeword consistent, and detects the storage unit pair Whether the voltage verification latch answered is to pass through state, comprising: is charged to bus；Read the storage unit and The value for accelerating the corresponding data latches in position of " 0 " in coding codeword corresponding with first verifying voltage, and read Take the value of voltage verification latch corresponding with the storage unit；Draw high the data latches being read, wherein if The value for the data latches being read and the value of the voltage verification latch are " 0 ", corresponding with storage unit is stated Data latches group be set as latch mode；If value and/or the voltage verification of the data latches being read At least one in the value of latch is not " 0 ", and data latches group state corresponding with the storage unit remains unchanged.
For example, the programming authentication module executes programming verification operation to programmed each storage unit, further includes: It selects the second verifying voltage, and verifies and be incorporated into the voltage of each storage unit and whether reach second verifying voltage. The latch scan module executes programmed each storage unit and latches scan operation, further includes: will pass through described the Two verifying voltages program verifying and target threshold voltage as the data latches of the storage unit of second verifying voltage Group is set to latch mode；It and by the programming verifying and/or target threshold voltage not by second verifying voltage is not institute The state for stating the data latches group of the storage unit of the second verifying voltage remains unchanged.The confirmation scan module is to being programmed Each storage unit execute confirmation scan operation, further includes: be the storage unit of latch mode for data latches group, Judged that latch is set as successfully latch mode；And be not the storage unit of latch mode for data latches group, Judged that latch is set as latching unsuccessful state.
For example, described device further include: data scanning module determines storage letter for scanning the data latches group Breath is the data latches group of erase status and stores the data latches group that information is not erase status, will be with storage information The corresponding storage unit of data latches group of erase status is set as not programming state, and will not be to wipe with storage information Except the corresponding storage unit of data latches group of state is set as programming state, wherein need the programmed storage Unit is the storage unit for being arranged to programming state.
For example, described device further include: judgment module is used in the one or more verifying voltages of use to programmed each After the storage unit executes programming verification operation, latches scan operation and confirmation scan operation, determines and need to be programmed Each storage unit in one or more storage units respective target threshold voltage has not yet been reached in this programming； Wherein, the programming module programs one or more of storage units again；The programming authentication module is to described One or more storage units execute programming verification operation；The latch scan module holds one or more of storage units Row latches scan operation；And the confirmation scan module executes confirmation scan operation to one or more of storage units.
At least one embodiment of the disclosure additionally provides a kind of storage medium, stores program on said storage Instruction, when described program instruction is run by computer or processor for executing the nand memory of embodiment of the disclosure More program bits methods, and for realizing more program bits devices of nand memory according to an embodiment of the present disclosure.
The more program bits method and devices for the nand memory that the embodiment of the present disclosure provides, according to the structure weight of latch New design coding, reduces the quantity of redundant operation complicated in programming process, thus can accelerate the speed of programming, reduces function Consumption.
Detailed description of the invention
Embodiment of the disclosure is described in more detail in conjunction with the accompanying drawings, the above-mentioned and other mesh of the disclosure , feature and advantage will be apparent.Attached drawing is used to provide to further understand the embodiment of the present disclosure, and constitutes A part of bright book is used to explain the disclosure together with embodiment of the disclosure, does not constitute the limitation to the disclosure.In attached drawing In, identical reference label typically represents same parts or step.
Fig. 1 is the schematic block diagram for the multiple bit unit storage array that the embodiment of the present disclosure provides；
Fig. 2 is the schematic block diagram for the sense amplifier that the embodiment of the present disclosure provides；
Fig. 3 is the exemplary structure for the latch that the embodiment of the present disclosure provides；
Fig. 4 is the schematic block diagram for the control circuit that the embodiment of the present disclosure provides；
Fig. 5 is a kind of schematic flow chart of the more program bits methods for nand memory that the embodiment of the present disclosure provides；
Fig. 6 A is the schematic flow chart of a kind of programming verifying that the embodiment of the present disclosure provides and the method latched；
Fig. 6 B is the illustrative profiles for four bit unit threshold voltages that the embodiment of the present disclosure provides；
Fig. 6 C is the programming pulse for four bit datas that the embodiment of the present disclosure provides and the illustrative profiles of verifying voltage；
Fig. 7 A-7M is the illustrative programming process for four bit datas that the embodiment of the present disclosure provides；
Fig. 8 A-8H is the programming verifying of the acceleration coding for four bit data of one kind that the embodiment of the present disclosure provides and latches Method schematic flow chart；
Fig. 9 is that illustrative four bit that the embodiment of the present disclosure provides accelerates coding code table；
Figure 10 is a kind of schematic block diagram of the more program bits devices for nand memory that the embodiment of the present disclosure provides.
Specific embodiment
In order to enable the purposes, technical schemes and advantages of the disclosure become apparent, root is described in detail below with reference to accompanying drawings According to the example embodiment of the disclosure.Obviously, described embodiment is only a part of this disclosure embodiment, rather than this public affairs The whole embodiments opened, it should be appreciated that the disclosure is not limited by example embodiment described herein.Based on described in the disclosure The embodiment of the present disclosure, those skilled in the art's obtained all other embodiment in the case where not making the creative labor It should all fall within the protection scope of the disclosure.
Embodiment of the disclosure provides a kind of more program bits method and devices of nand memory, can be in programming It is preceding that coding remaps, to optimize programming process.The more program bits for the nand memory that the embodiment of the present disclosure provides Method and device is redesigned according to the structure of latch and is encoded, multi-bit data is converted to accordingly from Gray code codeword Accelerate coding codeword, reduce the quantity of redundant operation complicated in programming process, thus the speed of programming can be accelerated, reduces Power consumption.The more program bits method and devices for the nand memory that the embodiment of the present disclosure provides, can be applied to be greater than or equal to The programming of two bits of data, for example, the programming of the multi-bit datas such as four bit datas, five bit datas and/or six bit datas.
In the embodiments of the present disclosure, nand memory can be two-dimentional nand memory, be also possible to three dimensional NAND storage Device, the disclosure do not limit this.Three dimensional NAND memory improves mistake of the plane nand memory in terms of more bit storages The problems such as narrow threshold value is distributed, serious floating gate couples, so that three dimensional NAND memory increases depositing for each storage unit Energy storage power is possibly realized.
Fig. 1 is a kind of schematic frame for system 100 including multiple bit unit storage array that the embodiment of the present disclosure provides Figure.As shown in Figure 1, system 100 may include peripheral circuit 101, line decoder 104, column decoder 106, storage array 108, Sense amplifier 110 and input/output interface 112.In some embodiments, system 100 also may include that other are not shown Component, for example, voltage-stablizer (voltage regulator), logic circuit (logic circuits) etc..
Peripheral circuit 101 is the circuit structure outside storage array 108.Peripheral circuit 101 may include control electricity Road 102.Control circuit 102 can control the address choice of storage array 108.For example, control circuit 102 can control capable decoding Device 104, so that line decoder 104 selects the row address of storage array 108 by wordline 114；Control circuit 102 can also be controlled Column decoder 106 processed, so that column decoder 106 selects the column address of storage array by bit line 116.Control circuit 102 is also It can control the programming process of storage array 108.For example, as described below, control circuit 102 can control Fig. 5 method 500, The execution of the method 800 and 8000 of the method 600 and Fig. 8 A-8H of Fig. 6 A.
Referring to fig. 4, control circuit 102 may include processor 402, memory 404 and other unshowned components.Control It can directly or indirectly be communicated with each other between each component of circuit 102 processed, for example, each component of control circuit 102 can be mutual Mutually send and receive data and/or signal.In another example can be connected by bus between each component of control circuit 102.One In a little embodiments, control circuit 102 may include one or more processors 402 and one or more memories 404.
Processor 402 can handle data-signal, may include various calculating structures, such as Complex Instruction Set Computer (CISC) structure, structure Reduced Instruction Set Computer (RISC) structure or a kind of structure for carrying out a variety of instruction set combinations.? In some embodiments, processor 402 is also possible to microprocessor, such as X 86 processor or arm processor, or can be number Word processing device (DSP) etc..Processor 402 can control other components in control circuit 102 to execute desired function.
Memory 404 can save the instruction and/or data of the execution of processor 402.For example, memory 404 may include One or more computer program products, the computer program product may include various forms of computer-readable storage mediums Matter, such as volatile memory and/or nonvolatile memory.The volatile memory for example may include that arbitrary access is deposited Reservoir (RAM) and/or cache memory (cache) etc..The nonvolatile memory for example may include read-only storage Device (ROM), hard disk, flash memory etc..It can store one or more computer programs on the computer readable storage medium to refer to It enables, processor 402 can run described program instruction, to realize in the embodiment of the present disclosure described below and (be realized by processor) More program bits functions and/or other desired functions.It can also be stored in the computer readable storage medium Various application programs and various data, such as application program use and/or the various data generated etc..
Referring to Fig. 1, storage array 108 voltage status can be used determine storage multi-bit data size.For example, Each storage unit of storage array 108 can store a multi-bit data, i.e., each storage unit can store more with this The corresponding voltage class of bit data.In another example Fig. 6 B shows the threshold voltage V of four bit memory cellsthDistribution, packet Include erase status (erase, ER), L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14 and L15 are total to 24=16 voltage class.According to the numerical values recited of stored multi-bit data, each storage unit can store voltage etc. One in grade.
Input/output interface 112 can provide input data to sense amplifier 110 and (need to be programmed into for example, providing The multi-bit data of storage array 108), and the output data of sense amplifier 110 is received (for example, receiving from storage array The data read in 108).Input/output interface 112 can be universal serial bus (universal serial bus, USB) Interface, thunder and lightning (thunderbolt) interface or other feasible interface types, the disclosure are not construed as limiting this.In some implementations In example, input/output interface 112 can also be used as a component of peripheral circuit 101.
In some embodiments, the threshold of the current value and the storage unit that are stored in the storage unit of storage array 108 Threshold voltage grade is corresponding, the current value that sense amplifier 110 can store the storage unit be converted to digital numerical value (for example, Multi-bit value).Sense amplifier 110 can be connected with one or more bit lines 116.
Fig. 2 shows the exemplary block diagrams 200 of sense amplifier 110.Sense amplifier 110 may include buffer lock Storage 202, data latches group 203, sensor circuit 214 and induction latch 216.Each component of sense amplifier 110 can To be connected with each other by bus 218.In some embodiments, the data of each data latches group 203 in sense amplifier 110 The number of latch is identical as the bit number for the numerical value that each storage unit stores；Alternatively, each data in sense amplifier 110 The number of data latches in latch group 203 is greater than the bit number of the numerical value of each storage unit storage.For example, storage battle array Each storage unit of column 108 can store the numerical value of four bits, and each data latches group 203 of sense amplifier 110 at least may be used To include four data latches, i.e., the first data latches 204 as shown in Figure 2, the second data latches 206, third number According to latch 208 and the 4th latch 210.Alternatively, each data latches group 203 of sense amplifier 110 can also include Other data latches, for example, ephemeral data latch 212 as shown in phantom in Figure 2.As shown in Fig. 2, sense amplifier The bus of 110 each latch links together.
In some embodiments, it is that unit is programmed that storage array 108, which is with " row ",；That is, by row to storage array 108 storage unit is programmed, and in the programming of every row, with a line the storage unit of programming in need will simultaneously It is programmed.Therefore, number including the induction latch 216 in sense amplifier 110 with include the one of storage array 108 The number of storage unit in row is identical；That is, respectively each storage unit in induction latch 216 and a line is one-to-one closes System.In addition, include the data latches group 203 in sense amplifier 110 number also with include in storage array 108 one The number of storage unit in row is identical；That is, each data latches group 203 and each storage unit in a line are one-to-one Relationship.
Fig. 3 shows the exemplary circuit diagram of latch 300.In the latch 300 of Fig. 3, " X " represents latch 300 The data of storage, " INVX " represent the anti-of the data of storage, and " SETX " represents storing data set signal, and " RETX " representative is deposited Data reset signal is stored up, VDD represents supply voltage, and READ represents read signal and " BUS " represents bus.Buffer lock in Fig. 2 Storage 202, sensitive latch 216, the first data latches 204, the second data latches 206, third data latches 208, The structure of 4th latch 210 and interim latch 212 can be same or similar with the structure of latch 300, herein not It repeats again.
Fig. 5 is a kind of schematic flow of the more program bits methods 500 for nand memory that the embodiment of the present disclosure provides Figure.In some embodiments, method 500 may include it is shown in fig. 5 some or all the step of (for example, step S502, Part or all in S504, S506, S508, S510, S512, S514, S516, S518, S520 and S522).Certainly, side Method 500 also may include other steps not shown in FIG. 5.In the following description, the sense amplifier of Fig. 2 will be combined Method 500 is described in detail in 110 structure.
Firstly, programmed multi-bit data is written in data latches group in step S502, wherein described more Bit data is Gray code codeword.In some embodiments, when the line storage unit to storage array 108 is programmed, By programmed each multi-bit data be respectively written into in the one-to-one data latches group 203 of the storage unit of the row. For example, then caching latches by input/output interface 112 by programmed each multi-bit data write-in caching latch 202 Programmed each multi-bit data is respectively written into corresponding each data latches group 203 by device 202.
In step 504, pre-processes the multi-bit and be accordingly converted to each multi-bit data from Gray code codeword Accelerate coding codeword.In some embodiments, before executing step 504, can establish multi-bit data Gray code code table, Accelerate coding code table and the Gray code code table and the transformational relation for accelerating coding code table.Gray code conversion is to accelerate to compile The process of code can satisfy following two condition: (1) code word being re-started arrangement according to the quantity of " 0 ", with including more " 0 " Code word come indicate lower voltage class (that is, low-voltage-grade it is corresponding accelerate coding codeword in include " 0 " number not The number of " 0 " for accelerating to include in coding codeword corresponding less than voltage levels)；And (2) for include equal " 0 " number Voltage class, obtained by converting the data latches of minimal number of corresponding with voltage class Gray code codeword The acceleration coding codeword of the voltage class (is being to add from Gray code conversion that is, for containing " 0 " voltage class equal in number During speed coding, make to need the number of the data latches changed minimum as far as possible).According to Gray code code table and accelerate The transformational relation of coding code table can be converted to each multi-bit data accordingly from Gray code codeword in step 504 Accelerate coding codeword.
For example, Fig. 9 shows the Gray code code table 900 of four bit datas, accelerates coding code table 950 and the Gray code Code table 900 and the transformational relation for accelerating coding code table 950.Filling shade partially illustrates when Gray code code table in Fig. 9 900 be converted to acceleration coding code table 950 when, the numerical value for the data latches for needing to change.For example, the Gray code of voltage class L1 Code word " 1110 ", which corresponds to, accelerates coding codeword " 0000 "；When corresponding four bit data of voltage class L1 from Gray code codeword " 1110 " are converted to when accelerating coding codeword " 0000 ", need that " 1 " that stores the first data latches 204 becomes " 0, " for the " 1 " of two data latches 206 storage becomes " 0 ", and " 1 " that third data latches 208 are stored becomes " 0 ".It needs Illustrate, accelerating coding code table 950 is the exemplary acceleration coding code table for meeting above-mentioned condition (1) and (2), other similar Acceleration coding code table also can satisfy condition (1) and (2), the disclosure is not construed as limiting this.
In step S506, the data latches group is scanned to determine that storage information is to wipe the data of (erase) state Latch group and storage information are not the data latches groups of erase status.For example, when the information of data latches group storage is When " 1111 ", the information of data latches group storage is the information of erase status；When data latches group storage information not When being " 1111 ", the information of data latches group storage is not the information of erase status.
It is the data latches group of erase status for storage information in step S508, it will be with the data latches group Corresponding storage unit is set as not programming state；It is not the data latches group of erase status for storage information, it will be with institute It states the corresponding storage unit of data latches group and is set as programming state.That is, when the information of data latches group storage is When " 1111 ", which is not programmed；When data latches group storage information not When being " 1111 ", which can be programmed.
In step S510, to needing programmed each storage unit to be programmed in storage array 108.For example, to depositing When one line storage unit of storage array 108 is programmed, the channel drain terminal of programmed storage unit can will be needed to be grounded, and The channel drain terminal for not needing the storage unit of programming is connect into supply voltage.In some embodiments, it is desirable to which programmed storage is single Member can be to be arranged to the storage unit of programming state in step S508, do not need programmed storage unit can for It is arranged to the storage unit of not programming state in step S508.
In some embodiments, incremental steps pulse program (ISPP) sequence of standard can be used to storage array 108 Storage unit be programmed.After the programming of each step, as shown in following step S512 and S514, one can be used Or scan operation is verified and latched to multiple verifying voltages to execute programming.It will be needed by the programming pulse voltage of stairstepping The voltage of the storage unit of programming is moved to target threshold voltage from erase status, the number of the programming pulse needed and every step Depending on the specific programming situation of verifying voltage number foundation after programming.After each programming pulse applies, require to make Verify whether current programming has successfully been successfully moved to the storage unit for the voltage of storage unit with verifying voltage Target threshold voltage.If the voltage of the storage unit has successfully been moved to target threshold voltage (the i.e. storage unit Program successfully), then it needs data latches group corresponding with the storage unit latching (as shown in following step S514), and It is marked accordingly (as shown in following step S516), to prevent the storage unit to be programmed again.
For example, with reference to Fig. 6 C, after each programming pulse of four bit datas, multiple verifying voltages can be used and carry out Verifying, and have corresponding latch operation after using the verifying of each verifying voltage.For example, using programming pulse PGMnInto After row programming, it can be verified first using verifying voltage VFY1 and carry out latch operation 671, then use verifying voltage VFY2 is verified and is carried out latch operation 672, and so on, until using next programming pulse PGMn+1It carries out next time It programs and carries out corresponding verification operation and latch operation.
In step 512, programming verification operation is executed.For example, can choose verifying voltage, and verify in step 512 Whether the voltage for being incorporated into each storage unit reaches the verifying voltage.The storage of the verifying voltage is had reached for voltage Corresponding voltage verification latch can be labeled as passing through state by unit；The verifying electricity is had not yet been reached for voltage Corresponding voltage verification latch can be labeled as not passing through state by the storage unit of pressure.The storage unit is corresponding Induction latch 216 or ephemeral data latch 212 corresponding with the storage unit can be used as the electricity of the storage unit Pressure verifying latch come using.
In step 514, executes and latch scan operation.For example, will be tested by the programming of the verifying voltage in step 514 Card and target threshold voltage are that the data latches group of the storage unit of the verifying voltage is set as latch mode；And it will It is not the data latch of the storage unit of the verifying voltage by the storage unit and/or target threshold voltage of programming verifying The state of device group remains unchanged.
In some embodiments, in step 514, it can detecte the corresponding data latches group storage of the storage unit Accelerate the quantity of " 0 " and the position quantity for accelerating " 0 " in coding codeword whether corresponding with the verifying voltage in coding codeword It is consistent with position, and detect whether voltage verification latch corresponding with the storage unit is to pass through state.If institute State the quantity of " 0 " and position and first verifying in the acceleration coding codeword of the corresponding data latches group storage of storage unit Voltage is corresponding to accelerate the quantity of " 0 " and position in coding codeword consistent, and the corresponding voltage verification lock of the storage unit Storage is by state, and it is latch mode that data latches group corresponding with the storage unit, which is arranged,.However, if described deposit The quantity of " 0 " and position and first verifying voltage in the acceleration coding codeword of the corresponding data latches group storage of storage unit The quantity of " 0 " and position is inconsistent and/or the corresponding voltage verification of the storage unit latches in corresponding acceleration coding codeword Device is to keep the state of the corresponding data latches group of the storage unit constant not by state.
For example, when the corresponding voltage verification latch of the storage unit is not pass through state, the voltage verification lock The value of storage is " 1 "；When the voltage verification latch is to pass through state, the value of the voltage verification latch is " 0 ".On It states operation and " detects the quantity of " 0 " and position in the acceleration coding codeword of the corresponding data latches group storage of the storage unit Whether with first verifying voltage it is corresponding accelerate coding codeword in " 0 " quantity and position it is consistent, and detect described in Whether the corresponding voltage verification latch of storage unit is to pass through state " it may include: to charge to bus；It is deposited described in reading The corresponding data latches in position of " 0 " in acceleration coding codeword storage unit and corresponding with the verifying voltage Value, and read the value of voltage verification latch corresponding with the storage unit；Then the data lock being read is drawn high Storage.If the value for the data latches being read and the value of the voltage verification latch are " 0 ", deposited with described The corresponding data latches group of storage unit is arranged to latch mode (that is, data latches group corresponding with the storage unit It is successfully drawn high as latch mode " 1111 ")；If value and/or the voltage verification of the data latches being read At least one in the value of latch is not " 0 " (that is, data latches group corresponding with the storage unit is not drawn successfully A height of latch mode " 1111 "), the state of data latches group corresponding with the storage unit remains unchanged.
In step S516, confirmation scan operation is executed.For example, being latched as depositing for latch mode for data latches group Storage unit, the storage unit is arranged judges latch to latch success status, to prevent the storage unit from continuing to compile Journey；The storage unit of latch mode is not latched as data latches group, the judgement that the storage unit is arranged is latched Device is to latch unsuccessful state.The corresponding induction latch 216 of storage unit or the storage unit are corresponding interim Data latches 212 can be used as the judgement latch come using.
In step S518, it is determined whether choose next verifying voltage to be programmed verifying.For example, if all tests Card voltage has been used to verify this programming or the voltage of all programmed storage units is not up in step S512 Verifying voltage, method 500 will no longer choose next verifying voltage be programmed verifying but then execute next step Rapid S520；Otherwise, method 500 can choose next verifying voltage to be programmed verifying, and return step S512.
In step S520, it is determined whether all programmings for needing programmed storage unit are completed.For example, in step Rapid S520, determine it is described need in programmed storage unit whether there are one or multiple storage units in this programming still Not up to respective target threshold voltage.If there are one or multiple storage units had not yet been reached in this programming it is respective Target threshold voltage, method 500 can be programmed next time with return step S510.If all storage units are in this volume Respective target threshold voltage is reached in journey, method 500 can move to step S522.
In step S522, since all storage units have reached respective target threshold voltage, method by programming 500 complete the programming to the multi-bit data.
What Fig. 6 A was that the embodiment of the present disclosure provides a kind of is programmed verifying and latch operation after one-time programming The schematic flow chart of method 600.Method 600 carries out step S512, S514, S516 and S518 of the method 500 in Fig. 5 Illustrative explanation.To being needed in storage array after programmed each storage unit is programmed in the step S510 of Fig. 5, The following steps of method 600 can be executed to be programmed verifying and latch operation.
Firstly, in step S602, select verifying voltage L1, and verify be incorporated into each storage unit voltage whether Reach the verifying voltage L1.
In step S604, the programming by verifying voltage L1 is verified and target threshold voltage is verifying voltage L1's Storage unit, it is latch mode (for example, the number can be set that data latches group corresponding with the storage unit, which is arranged, Information according to the storage of latch group is " 1111 ")；And in step S606, the storage unit is arranged judges latch for lock Success status is deposited, to prevent the storage unit from continuing to program.
In step S608, for the storage unit and/or target threshold voltage of the programming verifying of unverified voltage L1 It is not the storage unit of verifying voltage L1, keeps the state of data latches group corresponding with the storage unit constant；And And in step S610, the storage unit is arranged judges latch to latch unsuccessful state.
In step S612, verifying voltage L2 is selected, and is verified and has been incorporated into the voltage of each storage unit and whether reaches Verifying voltage L2.
In step S614, the programming by verifying voltage L2 is verified and target threshold voltage is verifying voltage L2's Storage unit, it is latch mode (for example, the data can be set that data latches corresponding with the storage unit, which are arranged, The information of latch group storage is " 1111 ")；And in step S616, the storage unit is arranged judges latch to latch Success status.
In step S618, for the storage unit and/or target threshold voltage of the programming verifying of unverified voltage L2 It is not the storage unit of verifying voltage L2, keeps the state of data latches corresponding with the storage unit constant；And In step S620, the storage unit is arranged judges latch to latch unsuccessful state.
In step S622, verifying voltage L3 is selected, and is verified and has been incorporated into the voltage of each storage unit and whether reaches Verifying voltage L3.Similarly, method 600 can also include the latch scan operation and confirmation scan operation to verifying voltage L3, And be programmed verifying using other verifying voltages, latch the operation for scanning and confirming scanning, the disclosure is no longer superfluous herein It states.
Fig. 7 A-7M is the illustrative programming process for four bit datas that the embodiment of the present disclosure provides.As shown in Figure 7 A, table Lattice 700 are shown: needing the targets threshold of programmed storage unit 1, storage unit 2, storage unit 3 and storage unit 4 Voltage is respectively L1, L2, L3 and L3；And storage unit 1, storage unit 2, storage unit 3 and storage unit 4 are corresponding The code word of data latches group storage is respectively and corresponding the accelerations coding codeword " 0000 " of L1, acceleration corresponding with L2 coding code Word " 0100 " and the corresponding acceleration coding codeword " 1000 " of L3 and acceleration coding codeword " 1000 " corresponding with L3.
Fig. 7 B shows voltage of each storage unit after first time programs, wherein storage unit 1 is programmed into voltage L1, storage unit 2 are programmed into voltage L2, and storage unit 3 is programmed into voltage L3 and storage unit 4 is programmed into voltage L1。
Fig. 7 C, which is shown, is programmed verifying to each storage unit using verifying voltage L1, and verification result is shown in table In 715.In conjunction with chart 710 and table 715 it is found that the voltage of each storage unit has reached verifying voltage L1, so with each The corresponding verifying voltage latch of storage unit is all set to pass through state.
Fig. 7 D shows the storage unit for latching that target threshold voltage is verifying voltage L1 (accelerating coding codeword " 0000 ") Process.Table 720 shows the voltage verification result of each storage unit and the code word of corresponding data latches group storage. Since the voltage that storage unit 1 is programmed into has passed through the verifying of voltage L1, and the target threshold voltage of storage unit 1 is equal to Verifying voltage L1 is (for example, the acceleration volume for accelerating coding codeword with verifying voltage L1 that the data latches group of storage unit 1 stores Code code word is identical, is " 0000 "), so the data latches group of storage unit 1 is latched as latch mode from " 0000 " " 1111 " (as shown in arrow 721), and storage unit 1 judges that the state of latch is arranged to latch successfully.However, i.e. The voltage for being programmed into storage unit 2, storage unit 3 and storage unit 4 passed the verifying of voltage L1, but due to The target threshold voltage of storage unit 2, storage unit 3 and storage unit 4 is not equal to verifying voltage L1 (for example, storage is single Member 2, the data latches group of storage unit 3 and storage unit 4 storage accelerations coding codeword all add with verifying voltage L1 Fast coding codeword is not identical), so the state of the data latches group of storage unit 2, storage unit 3 and storage unit 4 is equal It remains unchanged, and storage unit 2, storage unit 3 and storage unit 4 judge that the state of latch is arranged to latch not Success.Table 722 shows the result that above-mentioned latch target threshold voltage is verifying voltage L1.
Since (1) storage unit 2, storage unit 3 and storage unit 4 are not latched as respective targets threshold electricity Pressure, and the voltage of (2) storage unit 2, storage unit 3 and storage unit 4 is verified by the programming of last voltage L1, So also needing to choose next verifying voltage L2 carries out encoding verification.Fig. 7 E shows single to each storage using verifying voltage L2 Member is programmed verifying, and verification result is shown in table 727.In conjunction with chart 725 and table 727 it is found that storage unit 2 And the voltage of storage unit 3 has reached verifying voltage L2, so verifying corresponding with storage unit 2 and storage unit 3 Voltage latch is all set to pass through state；The voltage of storage unit 1 and storage unit 4 is not up to verifying voltage L2, institute It is all set to not pass through state with verifying voltage latch corresponding with storage unit 1 and storage unit 4.
Fig. 7 F shows the storage unit for latching that target threshold voltage is verifying voltage L2 (accelerating coding codeword " 0100 ") Process.Table 730 shows the voltage verification result of each storage unit and the code word of corresponding data latches group storage. Since storage unit 1 has successfully reached its target threshold voltage L1 and its data latches group is also successfully latched, so depositing Storage unit 1 can't impact storage unit 1 not over the verifying of verifying voltage L2.Due to the programming of storage unit 2 Voltage has passed through the verifying of voltage L2, and the target threshold voltage of storage unit 2 is equal to verifying voltage L2 (for example, storage is single The acceleration coding codeword of the data latches group storage of member 2 is identical as the acceleration coding codeword of verifying voltage L2, is " 0100 "), so the data latches group of storage unit 2 is latched as latch mode " 1111 " (such as 731 institute of arrow from " 0100 " Show), and storage unit 2 judges that the state of latch is arranged to latch successfully.Due to storage unit 3 and storage unit 4 target threshold voltage is not equal to verifying voltage L1 (for example, the data latches group of storage unit 3 and storage unit 4 is deposited The acceleration coding codeword of storage and the acceleration coding codeword of verifying voltage L2 are all different), and there is no by testing for storage unit 4 The programming verifying of voltage L2 is demonstrate,proved, so the state of the data latches group of storage unit 3 and storage unit 4 remains unchanged, And storage unit 3 and storage unit 4 to judge that the state of latch is arranged to latch unsuccessful.Table 732 is shown Above-mentioned latch target threshold voltage is the result of verifying voltage L2.
Since (1) storage unit 3 and storage unit 4 are not latched as respective target threshold voltage and (2) are deposited The voltage of storage unit 3 passes through the programming verifying of last voltage L2, is compiled so also needing to choose next verifying voltage L3 Code verifying.Fig. 7 G, which is shown, is programmed verifying to each storage unit using verifying voltage L3, and verification result is shown in table In 742.In conjunction with chart 740 and table 742 it is found that the voltage of storage unit 3 has reached verifying voltage L3, so single with storage First 3 corresponding verifying voltage latch are arranged to pass through state；The electricity of storage unit 1, storage unit 2 and storage unit 4 Pressure is not up to verifying voltage L3, so verifying voltage latch corresponding with storage unit 1, storage unit 2 and storage unit 4 It is all set to not pass through state.
Fig. 7 F shows the storage unit for latching that target threshold voltage is verifying voltage L3 (accelerating coding codeword " 1000 ") Process.Table 745 shows the voltage verification result of each storage unit and the code word of corresponding data latches group storage. Since storage unit 1 and storage unit 2 have successfully reached its respective target threshold voltage and its respective data latch Device group is also successfully latched, so storage unit 1 and storage unit 2 can't be to depositing not over the verifying of verifying voltage L3 Storage unit 1 and storage unit 2 impact.Since the program voltage of storage unit 3 has passed through the verifying of voltage L3, and store The target threshold voltage of unit 3 is equal to verifying voltage L3 (for example, the acceleration coding that the data latches group of storage unit 3 stores Code word is identical as the acceleration coding codeword of verifying voltage L3, is " 1000 "), thus the data latches group of storage unit 3 from " 1000 " are latched as latch mode " 1111 " (as shown in arrow 746), and the state quilt for judging latch of storage unit 3 It is set as latching successfully.Although the target threshold voltage of storage unit 4 is equal to verifying voltage L3 (for example, the data of storage unit 4 The acceleration coding codeword of latch group storage is identical as the acceleration coding codeword of verifying voltage L3), but the programming of storage unit 4 Voltage does not pass through the programming verifying of verifying voltage L3, so the state of the data latches group of storage unit 4 remains unchanged, And storage unit 4 to judge that the state of latch is arranged to latch unsuccessful.Table 747 shows above-mentioned latch target Threshold voltage is the result of verifying voltage L3.
Since (1) storage unit 4 is not latched as its target threshold voltage, and the voltage of (2) storage unit 4 does not have It is verified by the programming of last voltage L3, the programming of storage unit 4 is carried out so no longer choosing next verifying voltage L4 Verifying, but second is carried out to storage unit 4 and is programmed.Fig. 7 I shows the voltage L3 after storage unit 4 is programmed at second. Since when programming first time, storage unit 4 has passed through volume of the programming verifying of verifying voltage L1 without passing through verifying voltage L2 Journey verifying, so can directly be verified using verifying voltage L2 to storage unit 4 when second programs rather than from testing Card voltage L1 starts.
Fig. 7 J, which is shown, is programmed verifying to storage unit 4 using verifying voltage L2, and verification result is shown in table In 757.In conjunction with chart 755 and table 757 it is found that the voltage of storage unit 4 has reached verifying voltage L2, so single with storage First 4 corresponding verifying voltage latch are arranged to pass through state.
Fig. 7 K shows the process for latching the storage unit that target threshold voltage is verifying voltage L2.Table 760 is shown The voltage verification result of storage unit 4 and the code word of corresponding data latches group storage.Due to the target threshold of storage unit 4 Threshold voltage is not equal to verifying voltage L2, so the state of the data latches group of storage unit 4 remains unchanged, and storage unit 4 to judge that the state of latch is arranged to latch unsuccessful.It is to test that table 762, which shows above-mentioned latch target threshold voltage, Demonstrate,prove the result of voltage L2.
Since (1) storage unit 4 is not latched as its target threshold voltage, and the voltage of (2) storage unit 4 passes through The programming of last voltage L2 is verified, so also needing to choose next verifying voltage L3 carries out encoding verification.Fig. 7 L is shown Verifying is programmed to storage unit 4 using verifying voltage L3, verification result is shown in table 767.In conjunction with chart 765 with And table 767 is it is found that the voltage of storage unit 4 has reached verifying voltage L3, so verifying voltage corresponding with storage unit 4 is locked Storage is arranged to pass through state.
Fig. 7 M shows the storage unit for latching that target threshold voltage is verifying voltage L3 (accelerating coding codeword " 0100 ") Process.Table 770 shows the voltage verification result of storage unit 4 and the code word of corresponding data latches group storage. Since the voltage of storage unit 4 has passed through the verifying of verifying voltage L3, and the target threshold voltage of storage unit 4 is equal to verifying Voltage L3 is (for example, the acceleration coding code for accelerating coding codeword with verifying voltage L4 that the data latches group of storage unit 4 stores Word is identical, is " 1000 "), so the data latches group of storage unit 4 is latched as latch mode " 1111 " from " 1000 " (as shown in arrow 771), and storage unit 4 judges that the state of latch is arranged to latch successfully.Table 772 is shown Above-mentioned latch target threshold voltage is the result of verifying voltage L3.So far, storage unit 1, storage unit 2, storage unit 3 with And the corresponding each data latches group of storage unit 4 is successfully latched, to storage unit 1, storage unit 2, storage unit 3 with And the programming of storage unit 4 all terminates.
Fig. 8 A-8H is a kind of programming verifying for acceleration coding 950 based on Fig. 9 that the embodiment of the present disclosure provides and latches Method 8000 exemplary process diagram.As the programming verifying and the comparison of the method 8000 latched for accelerating coding, Fig. 8 A- The exemplary process diagram for the method 800 that the programming that 8H further comprises a kind of Gray code 900 based on Fig. 9 is verified and latched. For example, the programming verifying of Gray code 900 and the method 800 latched are shown on the left side of dotted line in Fig. 8 A-8H, accelerate The programming verifying of coding 950 and the method 8000 latched are shown on the right of dotted line.The verifying electricity of method 800 and method 8000 Pressure be be followed successively by according to the sequence from low-voltage to high voltage L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14 and L15.
For convenience described below, data latches group corresponding with programmed storage unit may include four Data latches ADL (Data Latch A), BDL (Data Latch B), CDL (Data Latch C) and DDL (Data Latch D), the code word of Gray code or accelerate each bit of the code word of coding be sequentially stored in data latches ADL, BDL, In CDL and DDL.For example, data latches ADL, BDL, CDL and DDL store " 1 " respectively, " 0 ", " 1 " for code word " 1010 ", " 0 " (that is, ADL=1, BDL=0, CDL=1, DDL=0).Induction latch can be expressed as SDL (Sensing Data Latch), ephemeral data latch can be expressed as TDL (Temporary Data Latch), and bus can be expressed as BUS.
In some embodiments, programming verifying and latch scan operation may include: (1) detection voltage verification the result is that It is no to pass through；(2) data latches group is compared by turn, judges the code word of the target threshold voltage of data latches group storage Whether be verifying voltage code word；(3) if having passed through the target threshold of the verifying of verifying voltage and the storage of data latches group The code word of threshold voltage is the code word of verifying voltage, i.e. the voltage of storage unit has reached target threshold voltage, then latches data Device group is set as latch mode " 1111 ".
In some embodiments, following step (1)-(3) detection data latch (for example, ADL) storage can be passed through " 0 " and " 1 ":
(1) it charges to bus B US, to label latch set, (TDL or SDL or other data latches be can be used as Mark latch use).
(2) read data latch ADL.If ADL=0, bus B US does not discharge, and label latch is still " 1 "；If ADL=1, then bus B US discharges, and marks latch by reset.
(3) label latch is drawn high again.If bus B US does not discharge in (2), label latch is still " 1 ", then exists The label latch success set being raised in step (3), to judge ADL=0；If bus B US is put in (2) Electricity marks latch by reset, then the label latch being raised in step (3) cannot succeed set, to judge ADL=1.
By above-mentioned steps (1)-(3) it is found that because bus B US discharges, needing one when detection data latch is " 1 " A " 1 " connects one " 1 " and is detected, and cannot detect more than two " 1 " simultaneously (that is, two data locks cannot be detected simultaneously Whether storage is " 1 ")；And detection data latch be " 0 " when, can directly detect detection in need " 0 " (that is, Can detect whether more than two data latches are " 0 " simultaneously).Therefore, accelerate coding can be by changing cataloged procedure In each code word each sequence, allow to faster be detected containing " 0 " a fairly large number of code word it is preceding (that is, with contain " 0 " A fairly large number of code word represents lower verifying voltage), and contain the code word of " 0 " negligible amounts it is rear (that is, with containing " 0 " quantity compared with Few code word represents higher verifying voltage), so as to save the redundant operation of detection " 1 ".Therefore, accelerate the programming of coding Speed can be accelerated, and power consumption can also reduce.
For example, with reference to the coding in Fig. 9, for encoding L1, L2, when detection, in order to current list Primitive encoding is distinguished with all units on the right side of it.Because " 0 " and " 1 " relationship of Gray code is indefinite, using When Gray code, if L1 (" 1110 ") distinguished with L2-L15, needs to detect ADL=1, then detect BDL=1, so After detect CDL=1, finally detect DDL=0.And after being recompiled using acceleration coding, code word corresponding for L1 " 0000 " can directly detect four " 0 " (that is, ADL=BDL=CDL=DDL=0) simultaneously.Similarly, for voltage L2, When using Gray code, if L2 (" 1100 ") distinguished with L3-L15, needs to detect ADL=1, then detect BDL= 1, then detect CDL=DDL=0.And after using acceleration coding to recode, code word " 0100 " corresponding for L2, Ke Yizhi It connects while detecting three " 0 " (that is, ADL=CDL=DDL=0) can just be such that L2 distinguishes with L3-L15, because in L3-L15 There is no ADL, CDL and DDL while being the code word of " 0 ".Therefore, accelerate coding that can save the redundant operation of detection " 1 ", programming Speed can be accelerated, and power consumption can also reduce.
Referring to Fig. 8 A, in method 800, the Gray code code word of verifying voltage L1 is " 1110 ", and method 800 includes: step Rapid S801 verifies pulse L1 (that is, verifying voltage L1) to programmed storage unit；Step S802, it is single to programmed storage Member executes the latch of pulse L1；Step S803, first " 1 " of detection (that is, detection ADL=1)；Step S804 detects second " 1 " (that is, detection BDL=1)；Step S805, detection third " 1 " (that is, detection CDL=1)；Step S806 detects one " 0 " (that is, detection DDL=0)；And step S807, above-mentioned steps S803-S806 will be met and by the verifying of verifying voltage L1 The data latches group of storage unit is latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL= 1, DDL=1)；Also, it will not meet above-mentioned steps S803-S806 or not by the storage unit of the verifying of verifying voltage L1 The state of data latches group remain unchanged.
For example, the verifying and latch of L1 (Gray code " 1110 ") may include following operation A)-E):
A) to BUS charging (that is, setting BUS=1), label latch (for example, setting flag latch TDL=1) is drawn high.
B) BUS charges (BUS=1), reads ADL, then draw high TDL=1.If ADL=1, then TDL=0；Otherwise TDL=1.
C) BUS charges (BUS=1), reads BDL, then draw high TDL=1.If BDL=1, TDL=0；Otherwise TDL=1.
D) BUS charging BUS=1, reads CDL, then draw high TDL=1.If CDL=1, then TDL=0；Otherwise TDL=1.
E) BUS charging BUS=1, reads DDL, SDL, TDL, draws high DDL=1.If DDL=0, SDL=0, TDL=0, then DDL =1；Otherwise DDL=0.
In method 8000, the acceleration coding codeword of verifying voltage L1 is " 0000 ", and method 8000 includes: step S8001, Pulse L1 (that is, verifying voltage L1) is verified to programmed storage unit；Step S8002 executes programmed storage unit The latch of pulse L1；Step S8006, four " 0 " of detection (that is, detection ADL=BDL=CDL=DDL=0)；And step S8007 will meet above-mentioned steps S8006 and is latched as by the data latches group of the storage unit of the verifying of verifying voltage L1 " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, on will be without meeting It states step S8006 and/or is not remained unchanged by the state of the data latches group of the storage unit of the verifying of verifying voltage L1.
For example, the verifying and latch of L1 (accelerating coding " 0000 ") may include following operation: BUS charging BUS=1 is read ADL, BDL, CDL, DDL, SDL, then ADL=1 is drawn high, BDL=1, CDL=1, DDL=1.If ADL=0, BDL=0, CDL=0, DDL=0, SDL=0 (wherein, SDL=0 indicates that the voltage of storage unit has reached verifying voltage L1), then successfully latch ADL= 1, BDL=1, CDL=1, DDL=1；Otherwise ADL=0, BDL=0, CDL=0, DDL=0.
Therefore, compared to Gray code, accelerate coding that can save step S803-S805, so that operation number is reduced, Accelerate program speed, while reducing power consumption.
In method 800, the Gray code code word of verifying voltage L2 is " 1100 ", method 800 further include: step S808, Pulse L2 (that is, verifying voltage L2) is verified to programmed storage unit；Step S809 executes arteries and veins to programmed storage unit Rush the latch of L2；Step S810, first " 1 " of detection (that is, detection ADL=1)；Step S811, second " 1 " of detection is (that is, inspection Survey BDL=1)；Step S812, two " 0 " of detection (that is, detection CDL=DDL=0)；And step S813, above-mentioned step will be met Rapid S810-S812 and " 1111 " are latched as (that is, several by the data latches group of the storage unit of the verifying of verifying voltage L2 ADL=1, BDL=1, CDL=1, DDL=1 are latched as according to latch group)；Also, it will not meet above-mentioned steps S810- It S812 and/or is remained unchanged not over the state of data latches group of the storage unit of the verifying of verifying voltage L2.
For example, the verifying and latch of L2 (Gray code " 1100 ") may include following operation:
A) BUS charging BUS=1, draws high TDL=1.
B) BUS charging BUS=1, reads ADL, then draw high TDL=1.If ADL=1, then TDL=0；Otherwise TDL=1.
C) BUS charging BUS=1, reads BDL, then draw high TDL=1.If BDL=1, then TDL=0；Otherwise TDL=1.
D) BUS charging BUS=1, reads CDL, DDL, SDL, TDL, draws high CDL, DDL=1.If CDL=0, DDL=0, SDL =0, TDL=0, then CDL=1, DDL=1；Otherwise CDL=0, DDL=0.
In method 8000, the acceleration coding codeword of verifying voltage L2 is " 0100 ", method 8000 further include: step S8008 verifies pulse L2 (that is, verifying voltage L2) to programmed storage unit；Step S8009, it is single to programmed storage Member executes the latch of pulse L2；Step S8012, three " 0 " of detection (that is, detection ADL=CDL=DDL=0)；And step S8013 will meet above-mentioned steps S8012 and be latched by the data latches group of the storage unit of the verifying of verifying voltage L2 For " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, will it not meet Above-mentioned steps S8012 and/or not over verifying voltage L2 verifying storage unit data latches group state keep It is constant.
For example, the verifying and latch of L2 (accelerating coding " 0100 ") may include following operation: BUS charging BUS=1 is read ADL, CDL, DDL, SDL, then ADL=1 is drawn high, CDL=1, DDL=1.If ADL=0, CDL=0, DDL=0, SDL=0 (its In, SDL=0 indicates that the voltage of storage unit has reached verifying voltage L2), then successfully latch ADL=1, CDL=1, DDL=1； Otherwise ADL=0, CDL=0, DDL=0.
Therefore, compared to Gray code, accelerate coding that can save step S810-S811, so that operation number is reduced, Accelerate program speed, while reducing power consumption.
Referring to Fig. 8 B, in method 800, the Gray code code word of verifying voltage L3 is " 1000 ", and method 800 includes: step Rapid S814 verifies pulse L3 (that is, verifying voltage L3) to programmed storage unit；Step S815, it is single to programmed storage Member executes the latch of pulse L3；Step S816, first " 1 " of detection (that is, detection ADL=1)；Step S817 detects three " 0 " (that is, detection BDL=CDL=DDL=0)；And step S818, above-mentioned steps S816-S817 will be met and by verifying electricity Press the data latches group of the storage unit of the verifying of L3 be latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, it will not meet above-mentioned steps S816-S817 and/or not over verifying voltage L3 The state of data latches group of storage unit of verifying remain unchanged.
For example, the verifying and latch of L3 (Gray code " 1000 ") may include following operation:
A) to BUS charging (that is, setting BUS=1), label latch (for example, setting TDL=1) is drawn high.
B) BUS charges (BUS=1), reads ADL, then draw high TDL=1.If ADL=1, then TDL=0；Otherwise TDL=1.
C) BUS charging BUS=1, reads BDL, CDL, DDL, SDL, TDL, draws high BDL, CDL, DDL.If BDL=0, CDL= 0, DDL=0, SDL=0, TDL=0, then BDL=1, CDL=1, DDL=1；Otherwise BDL=0, CDL=0, DDL=0.
In method 8000, the acceleration coding codeword of verifying voltage L3 is " 1000 ", method 8000 further include: step S8014 verifies pulse L3 (that is, verifying voltage L3) to programmed storage unit；Step S8015, it is single to programmed storage Member executes the latch of pulse L3；Step S8017, three " 0 " of detection (that is, detection BDL=CDL=DDL=0)；And step S8018 will meet above-mentioned steps S8017 and be latched by the data latches group of the storage unit of the verifying of verifying voltage L3 For " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, will it not meet Above-mentioned steps S8017 and/or not over verifying voltage L3 verifying storage unit data latches group state keep It is constant.
For example, the verifying and latch of L3 (accelerating coding " 1000 ") may include following operation: BUS charging BUS=1 is read BDL, CDL, DDL, SDL, then BDL=1 is drawn high, CDL=1, DDL=1.If BDL=0, CDL=0, DDL=0, SDL=0, then BDL=1, CDL=1, DDL=1, otherwise BDL=0, CDL=0, DDL=0.
Therefore, compared to Gray code, accelerate coding that can save step S816, so that operation number is reduced, accelerate Program speed, while reducing power consumption.
In method 800, the Gray code code word of verifying voltage L4 is " 1010 ", method 800 further include: step S819, Pulse L4 (that is, verifying voltage L4) is verified to programmed storage unit；Step S820 executes arteries and veins to programmed storage unit Rush the latch of L4；Step S821, first " 1 " of detection (that is, detection ADL=1)；Step S822, second " 1 " of detection is (that is, inspection Survey CDL=1)；Step S823, two " 0 " of detection (that is, detection BDL=DDL=0)；And step S824, above-mentioned step will be met Rapid S821-S823 and " 1111 " are latched as (that is, several by the data latches group of the storage unit of the verifying of verifying voltage L4 ADL=1, BDL=1, CDL=1, DDL=1 are latched as according to latch group)；Also, it will not meet above-mentioned steps S821- It S823 and/or is remained unchanged not over the state of data latches group of the storage unit of the verifying of verifying voltage L4.
For example, the verifying and latch of L4 (Gray code " 1010 ") may include following operation:
A) BUS charging BUS=1, draws high TDL=1.
B) BUS charging BUS=1, reads ADL, then draw high TDL=1.If ADL=1, then TDL=0；Otherwise TDL=1.
C) BUS charging BUS=1, reads CDL, then draw high TDL=1.If CDL=1, then TDL=0；Otherwise TDL=1.
D) BUS charging BUS=1, reads BDL, DDL, SDL, TDL, draws high BDL=1, DDL=1.If BDL=0, DDL=0, SDL=0, TDL=0, then BDL=1, DDL=1；Otherwise BDL=0, DDL=0.
In method 8000, the acceleration coding codeword of verifying voltage L4 is " 0010 ", method 8000 further include: step S8019 verifies pulse L4 (that is, verifying voltage L4) to programmed storage unit；Step S8020, it is single to programmed storage Member executes the latch of pulse L4；Step S8023, three " 0 " of detection (that is, detection ADL=BDL=DDL=0)；And step S8024 will meet above-mentioned steps S8023 and be latched by the data latches group of the storage unit of the verifying of verifying voltage L4 For " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, will it not meet Above-mentioned steps S8023 and/or not over verifying voltage L4 verifying storage unit data latches group state keep It is constant.
For example, the verifying and latch of L4 (accelerating coding " 0010 ") may include following operation: BUS charging BUS=1 is read ADL, BDL, DDL, SDL, then ADL=1 is drawn high, BDL=1, DDL=1.If ADL=0, BDL=0, DDL=0, SDL=0, then ADL=1, BDL=1, DDL=1, otherwise ADL=0, BDL=0, DDL=0.
Therefore, compared to Gray code, accelerate coding that can save step S821-S822, so that operation number is reduced, Accelerate program speed, while reducing power consumption.
Referring to Fig. 8 C, in method 800, the Gray code code word of verifying voltage L5 is " 1011 ", method 800 further include: Step S825 verifies pulse L5 (that is, verifying voltage L5) to programmed storage unit；Step S826, to programmed storage The latch of unit execution pulse L5；Step S827, first " 1 " of detection (that is, detection ADL=1)；Step S828, detection second A " 1 " (that is, detection CDL=1)；Step S829, detection third " 1 " (that is, detection DDL=1)；Step S830 detects one " 0 " (that is, detection BDL=0)；And step S831, above-mentioned steps S827-S830 and testing by verifying voltage L5 will be met The data latches group of the storage unit of card be latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, it will not meet above-mentioned steps S827-S830 and/or not over the verifying of verifying voltage L5 The state of data latches group of storage unit remain unchanged.
For example, the verifying and latch of L5 (Gray code " 1011 ") may include following operation:
A) BUS charging BUS=1, draws high TDL=1.
B) BUS charging BUS=1, reads ADL, then draw high TDL=1.If ADL=1, then TDL=0；Otherwise TDL=1.
C) BUS charging BUS=1, reads CDL, then draw high TDL=1.If CDL=1, then TDL=0；Otherwise TDL=1
D) BUS charging BUS=1, reads DDL, then draw high TDL=1.If DDL=1, then TDL=0；Otherwise TDL=1.
E) BUS charging BUS=1, reads BDL, SDL, TDL, draws high BDL=1.If BDL=0, SDL=0, TDL=0, then BDL =1；Otherwise BDL=0.
In method 8000, the acceleration coding codeword of verifying voltage L5 is " 0001 ", method 8000 further include: step S8025 verifies pulse L5 (that is, verifying voltage L5) to programmed storage unit；Step S8026, it is single to programmed storage Member executes the latch of pulse L5；Step S8030, three " 0 " of detection (that is, detection ADL=BDL=CDL=0)；And step S8031 will meet above-mentioned steps S8030 and be latched by the data latches group of the storage unit of the verifying of verifying voltage L5 For " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, will it not meet Above-mentioned steps S8030 and/or not over verifying voltage L5 verifying storage unit data latches group state keep It is constant.
For example, the verifying and latch of L5 (accelerating coding " 0001 ") may include following operation: BUS charging BUS=1 is read ADL, BDL, CDL, SDL, then ADL=1 is drawn high, BDL=1, CDL=1.If ADL=0, BDL=0, CDL=0, SDL=0, then ADL=1, BDL=1, CDL=1；Otherwise ADL=0, BDL=0, CDL=0.
Therefore, compared to Gray code, accelerate coding that can save step S827-S829, so that operation number is reduced, Accelerate program speed, while reducing power consumption.
In method 800, the Gray code code word of verifying voltage L6 is " 1001 ", method 800 further include: step S832, Pulse L6 (that is, verifying voltage L6) is verified to programmed storage unit；Step S833 executes arteries and veins to programmed storage unit Rush the latch of L6；Step S834, first " 1 " of detection (that is, detection ADL=1)；Step S835, second " 1 " of detection is (that is, inspection Survey DDL=1)；Step S836, two " 0 " of detection (that is, detection BDL=CDL=0)；And step S837, above-mentioned step will be met Rapid S834-S836 and " 1111 " are latched as (that is, several by the data latches group of the storage unit of the verifying of verifying voltage L6 ADL=1, BDL=1, CDL=1, DDL=1 are latched as according to latch group)；Also, it will not meet above-mentioned steps S834- It S836 and/or is remained unchanged not over the state of data latches group of the storage unit of the verifying of verifying voltage L5.
For example, the verifying and latch of L6 (Gray code " 1001 ") may include following operation:
A) BUS charging BUS=1, draws high TDL=1.
B) BUS charging BUS=1, reads ADL, then draw high TDL=1.If ADL=1, then TDL=0；Otherwise TDL=1.
C) BUS charging BUS=1, reads DDL, then draw high TDL=1.If DDL=1, then TDL=0；Otherwise TDL=1.
D) BUS charging BUS=1, reads BDL, CDL, SDL, TDL, draws high BDL=1, CDL=1.If BDL=0, CDL=0, SDL=0, TDL=0, then BDL=1, CDL=1；Otherwise BDL=0, CDL=0.
In method 8000, the acceleration coding codeword of verifying voltage L6 is " 1001 ", method 8000 further include: step S8032 verifies pulse L6 (that is, verifying voltage L6) to programmed storage unit；Step S8033, it is single to programmed storage Member executes the latch of pulse L6；Step S8036, two " 0 " of detection (that is, detection BDL=CDL=0)；And step S8037, it will Meet above-mentioned steps S8036 and " 1111 " are latched as by the data latches group of the storage unit of the verifying of verifying voltage L6 (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, it will not meet above-mentioned steps It S8036 and/or is remained unchanged not over the state of the data latches group of the storage unit of verifying voltage L6.
For example, the verifying and latch of L6 (accelerating coding " 1001 ") may include following operation:
BUS charging BUS=1, reads BDL, CDL, SDL, then draw high BDL=1, CDL=1.If BDL=0, CDL=0, SDL= 0, then BDL=1, CDL=1；Otherwise BDL=0, CDL=0.
Therefore, compared to Gray code, accelerate coding that can save step S834-S835, so that operation number is reduced, Accelerate program speed, while reducing power consumption.
Referring to Fig. 8 D, in method 800, the Gray code code word of verifying voltage L7 is " 1101 ", and method 800 includes: step Rapid S838 verifies pulse L7 (that is, verifying voltage L7) to programmed storage unit；Step S839, it is single to programmed storage Member executes the latch of pulse L7；Step S840, first " 1 " of detection (that is, detection ADL=1)；Step S841 detects second " 1 " (that is, detection BDL=1)；Step S842, detection third " 1 " (that is, detection DDL=1)；Step S843 detects one " 0 " (that is, detection CDL=0)；And step S844, above-mentioned steps S840-S843 will be met and by the verifying of verifying voltage L7 The data latches group of storage unit be latched as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL =1, DDL=1)；Also, it will not meet above-mentioned steps S840-S843 and/or deposited not over the verifying of verifying voltage L7 The state of the data latches group of storage unit remains unchanged.
For example, the verifying and latch of L7 (Gray code " 1101 ") may include following operation:
A) BUS charging BUS=1, draws high TDL=1.
B) BUS charging BUS=1, reads ADL, then draw high TDL=1.If ADL=1, then TDL=0；Otherwise TDL=1.
C) BUS charging BUS=1, reads BDL, then draw high TDL=1.If BDL=1, then TDL=0；Otherwise TDL=1.
D) BUS charging BUS=1, reads DDL, then draw high TDL=1.If DDL=1, then TDL=0；Otherwise TDL=1.
E) BUS charging BUS=1, reads CDL, SDL, TDL, draws high CDL=1.If CDL=0, SDL=0, TDL=0, then CDL =1；Otherwise CDL=0.
In method 8000, the acceleration coding codeword of verifying voltage L7 is " 1100 ", and method 8000 includes: step S8038, Pulse L7 (that is, verifying voltage L7) is verified to programmed storage unit；Step S8039 executes programmed storage unit The latch of pulse L7；Step S8043, two " 0 " of detection (that is, detection CDL=DDL=0)；And step S8044, it will be in satisfaction It states step S8043 and " 1111 " is latched as (that is, number by the data latches group of the storage unit of the verifying of verifying voltage L7 ADL=1, BDL=1, CDL=1, DDL=1 are latched as according to latch group)；Also, it will not meet above-mentioned steps S8043 And/or it is remained unchanged not over the state of data latches group of the storage unit of the verifying of verifying voltage L7.
For example, the verifying and latch of L7 (accelerating coding " 1100 ") may include following operation: BUS charging BUS=1 is read CDL, DDL, SDL, then CDL=1 is drawn high, DDL=1.If CDL=0, DDL=0, SDL=0, then CDL=1, DDL=1；Otherwise CDL=0, DDL=0.
Therefore, compared to Gray code, accelerate coding that can save step S840-S842, so that operation number is reduced, Accelerate program speed, while reducing power consumption.
In method 800, the Gray code code word of verifying voltage L8 is " 0101 ", method 800 further include: step S845, Pulse L8 (that is, verifying voltage L8) is verified to programmed storage unit；Step S846 executes arteries and veins to programmed storage unit Rush the latch of L8；Step S847, first " 1 " of detection (that is, detection BDL=1)；Step S848, second " 1 " of detection is (that is, inspection Survey DDL=1)；Step S849, two " 0 " of detection (that is, detection ADL=CDL=0)；And step S850, above-mentioned step will be met Rapid S847-S849 and " 1111 " are latched as (that is, several by the data latches group of the storage unit of the verifying of verifying voltage L8 ADL=1, BDL=1, CDL=1, DDL=1 are latched as according to latch group)；Also, it will not meet above-mentioned steps S847- It S849 and/or is remained unchanged not over the state of data latches group of the storage unit of the verifying of verifying voltage L8.
For example, the verifying and latch of L8 (Gray code " 0101 ") may include following operation:
A) BUS charging BUS=1, draws high TDL=1.
B) BUS charging BUS=1, reads BDL, then draw high TDL=1.If BDL=1, then TDL=0；Otherwise TDL=1.
C) BUS charging BUS=1, reads DDL, then draw high TDL=1.If DDL=1, then TDL=0；Otherwise TDL=1.
D) BUS charging BUS=1, reads ADL, CDL, SDL, TDL, draws high ADL=1, CDL=1.If ADL=0, CDL=0, SDL=0, TDL=0, then ADL=1, CDL=1；Otherwise ADL=0, CDL=0.
In method 8000, the acceleration coding codeword of verifying voltage L8 is " 0101 ", method 8000 further include: step S8045 verifies pulse L8 (that is, verifying voltage L8) to programmed storage unit；Step S8046, it is single to programmed storage Member executes the latch of pulse L8；Step S8049, two " 0 " of detection (that is, detection ADL=CDL=0)；And step S8050, it will Meet above-mentioned steps S8049 and " 1111 " are latched as by the data latches group of the storage unit of the verifying of verifying voltage L8 (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, it will not meet above-mentioned steps It S8049 and/or is remained unchanged not over the state of data latches group of the storage unit of the verifying of verifying voltage L8.
For example, the verifying and latch of L8 (accelerating coding " 0101 ") may include following operation: BUS charging BUS=1 is read ADL, CDL, SDL, then ADL=1 is drawn high, CDL=1.If ADL=0, CDL=0, SDL=0, then ADL=1, CDL=1；Otherwise ADL=0, CDL=0.
Therefore, compared to Gray code, accelerate coding that can save step S847-S848, so that operation number is reduced, Accelerate program speed, while reducing power consumption.
Referring to Fig. 8 E, in method 800, the Gray code code word of verifying voltage L9 is " 0001 ", method 800 further include: Step S851 verifies pulse L9 (that is, verifying voltage L9) to programmed storage unit；Step S852, to programmed storage The latch of unit execution pulse L9；Step S853, first " 1 " of detection (that is, detection DDL=1)；Step S854 detects three " 0 " (that is, detection ADL=BDL=CDL=0)；And step S855, above-mentioned steps S853-S854 will be met and pass through verifying The data latches group of the storage unit of the verifying of voltage L9 is latched as " 1111 " (that is, data latches group is latched as ADL= 1, BDL=1, CDL=1, DDL=1)；Also, it will not meet above-mentioned steps S853-S854 and/or not over verifying voltage The state of the data latches group of the storage unit of the verifying of L9 remains unchanged.
For example, the verifying and latch of L9 (Gray code " 0001 ") may include following operation:
A) BUS charging BUS=1, draws high TDL=1.
B) BUS charging BUS=1, reads DDL, then draw high TDL=1.If DDL=1, then TDL=0；Otherwise TDL=1.
C) BUS charging BUS=1, reads ADL, BDL, CDL, SDL, TDL, draws high ADL=1, BDL=1, CDL=1.If ADL =0, BDL=0, CDL=0, SDL=0, TDL=0, then ADL=1, BDL=1, CDL=1；Otherwise ADL=0, BDL=0, CDL =0.
In method 8000, the acceleration coding codeword of verifying voltage L9 is " 1010 ", method 8000 further include: step S8051 verifies pulse L9 (that is, verifying voltage L9) to programmed storage unit；Step S8052, it is single to programmed storage Member executes the latch of pulse L9；Step S8054, two " 0 " of detection (that is, detection BDL=DDL=0)；And step S8055, it will Meet above-mentioned steps S8054 and " 1111 " are latched as by the data latches group of the storage unit of the verifying of verifying voltage L9 (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, it will not meet above-mentioned steps It S8054 and/or is remained unchanged not over the state of data latches group of the storage unit of the verifying of verifying voltage L9.
For example, the verifying and latch of L9 (accelerating coding " 1010 ") may include following operation: BUS charging BUS=1 is read BDL, DDL, SDL, then BDL=1 is drawn high, DDL=1.If BDL=0, DDL=0, SDL=0, then BDL=1, DDL=1, otherwise BDL=0, DDL=0.
Therefore, compared to Gray code, accelerate coding that can save step S853, so that operation number is reduced, accelerate Program speed, while reducing power consumption.
In method 800, the Gray code code word of verifying voltage L10 is " 0011 ", method 800 further include: step S856, Pulse L10 (that is, verifying voltage L10) is verified to programmed storage unit；Step S857 executes programmed storage unit The latch of pulse L10；Step S858, first " 1 " of detection (that is, detection CDL=1)；Step S859 detects second " 1 " (that is, detection DDL=1)；Step S860, two " 0 " of detection (that is, detection ADL=BDL=0)；And step S861, it will meet It above-mentioned steps S858-S860 and is latched as by the data latches group of the storage unit of the verifying of verifying voltage L10 " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, on will be without meeting State step S858-S860 and/or not over verifying voltage L10 verifying storage unit data latches group state protect It holds constant.
For example, the verifying and latch of L10 (Gray code " 0011 ") may include following operation:
A) BUS charging BUS=1, draws high TDL=1.
B) BUS charging BUS=1, reads CDL, then draw high TDL=1.If CDL=1, then TDL=0；Otherwise TDL=1.
C) BUS charging BUS=1, reads DDL, then draw high TDL=1.If DDL=1, then TDL=0；Otherwise TDL=1.
D) BUS charging BUS=1, reads ADL, BDL, SDL, TDL, draws high ADL=1, BDL=1.If ADL=0, BDL=0, SDL=0, TDL=0, then ADL=1, BDL=1；Otherwise ADL=0, BDL=0.
In method 8000, the acceleration coding codeword of verifying voltage L10 is " 0011 ", method 8000 further include: step S8056 verifies pulse L10 (that is, verifying voltage L10) to programmed storage unit；Step S8057, to programmed storage The latch of unit execution pulse L10；Step S8060, two " 0 " of detection (that is, detection ADL=BDL=0)；And step S8061 will meet above-mentioned steps S8060 and be locked by the data latches group of the storage unit of the verifying of verifying voltage L10 Save as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, it will be without full Sufficient above-mentioned steps S8060 and/or not over verifying voltage L10 verifying storage unit data latches group state protect It holds constant.
For example, the verifying and latch of L10 (accelerating coding " 0011 ") may include following operation: BUS charging BUS=1 is read ADL, BDL, SDL, then ADL=1 is drawn high, BDL=1.If ADL=0, BDL=0, SDL=0, then ADL=1, BDL=1, otherwise ADL=0, BDL=0.
Therefore, compared to Gray code, accelerate coding that can save step S858-S859, so that operation number is reduced, Accelerate program speed, while reducing power consumption.
Referring to Fig. 8 F, in method 800, the Gray code code word of verifying voltage L11 is " 0010 ", and method 800 includes: step Rapid S862 verifies pulse L11 (that is, verifying voltage L11) to programmed storage unit；Step S863, to programmed storage The latch of unit execution pulse L11；Step S864, first " 1 " of detection (that is, detection CDL=1)；Step S865 detects three " 0 " (that is, detection ADL=BDL=DDL=0)；And step S866, above-mentioned steps S864-S865 will be met and pass through verifying The data latches group of the storage unit of the verifying of voltage L11 is latched as " 1111 " (that is, data latches group is latched as ADL =1, BDL=1, CDL=1, DDL=1)；Also, it will not meet above-mentioned steps S864-S865 and/or not over verifying electricity The state of the data latches group of the storage unit of the verifying of L11 is pressed to remain unchanged.
For example, the verifying and latch of L11 (Gray code " 0010 ") may include following operation:
A) BUS charging BUS=1, draws high TDL=1.
B) BUS charging BUS=1, reads CDL, then draw high TDL=1.If CDL=1, then TDL=0；Otherwise TDL=1.
C) BUS charging BUS=1, reads ADL, BDL, DDL, SDL, TDL, draws high ADL=1, BDL=1, DDL=1.If ADL =0, BDL=0, DDL=0, SDL=0, TDL=0, then ADL=1, BDL=1, DDL=1；Otherwise ADL=0, BDL=0, DDL =0.
In method 8000, the acceleration coding codeword of verifying voltage L11 is " 1011 ", and method 8000 includes: step S8062 verifies pulse L11 (that is, verifying voltage L11) to programmed storage unit；Step S8063, to programmed storage The latch of unit execution pulse L11；Step S8065, two " 0 " of detection (that is, detection ADL=DDL=0)；And step S8066 will meet above-mentioned steps S8066 and be locked by the data latches group of the storage unit of the verifying of verifying voltage L11 Save as " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, it will be without full Sufficient above-mentioned steps S8066 and/or not over verifying voltage L11 verifying storage unit data latches group state protect It holds constant.
For example, the verifying and latch of L11 (accelerating coding " 0110 ") may include following operation: BUS charging BUS=1 is read ADL, DDL, SDL, then ADL=1 is drawn high, DDL=1.If ADL=0, DDL=0, SDL=0, then ADL=1, DDL=1, otherwise ADL=0, DDL=0.
Therefore, compared to Gray code, accelerate coding that can save step S864, so that operation number is reduced, accelerate Program speed, while reducing power consumption.
In method 800, the Gray code code word of verifying voltage L12 is " 0000 ", method 800 further include: step S867, Pulse L12 (that is, verifying voltage L12) is verified to programmed storage unit；Step S868 executes programmed storage unit The latch of pulse L12；Step S869, four " 0 " of detection (that is, detection ADL=BDL=CDL=DDL=0)；And step S870 will meet above-mentioned steps S869 and be latched by the data latches group of the storage unit of the verifying of verifying voltage L12 For " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, will it not meet Above-mentioned steps S869 and/or not over verifying voltage L12 verifying storage unit data latches group state keep It is constant.
For example, the verifying and latch of L12 (Gray code " 0000 ") may include following operation:
A) BUS charging BUS=1, draws high TDL=1.
B) BUS charging BUS=1, reads ADL, BDL, CDL, DDL, SDL, TDL, draws high ADL=1, BDL=1, CDL=1, DDL=1,.If ADL=0, BDL=0, CDL=0, DDL=0, SDL=0, TDL=0, then ADL=1, BDL=1, CDL=1, DDL=1；Otherwise ADL=0, BDL=0, CDL=0, DDL=0.
In method 8000, the acceleration coding codeword of verifying voltage L12 is " 1011 ", method 8000 further include: step S8067 verifies pulse L12 (that is, verifying voltage L12) to programmed storage unit；Step S8068, to programmed storage The latch of unit execution pulse L12；Step S8069, one " 0 " of detection (that is, detection BDL=0)；And step S8070, it will expire Sufficient above-mentioned steps S8069 and " 1111 " are latched as by the data latches group of the storage unit of the verifying of verifying voltage L12 (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, it will not meet above-mentioned steps It S8069 and/or is remained unchanged not over the state of data latches group of the storage unit of the verifying of verifying voltage L12.
For example, the verifying and latch of L12 (accelerating coding " 1011 ") may include following operation: BUS charging BUS=1 is read BDL, SDL, then draw high BDL=1.If BDL=0, SDL=0, then BDL=1, otherwise BDL=0.
Referring to Fig. 8 G, in method 800, the Gray code code word of verifying voltage L13 is " 0100 ", and method 800 includes: step Rapid S871 verifies pulse L13 (that is, verifying voltage L13) to programmed storage unit；Step S872, to programmed storage The latch of unit execution pulse L13；Step S873, three " 0 " of detection (that is, detection ADL=CDL=DDL=0)；And step S874 will meet above-mentioned steps S873 and be latched by the data latches group of the storage unit of the verifying of verifying voltage L13 For " 1111 " (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, will it not meet Above-mentioned steps S873 and/or not over verifying voltage L13 verifying storage unit data latches group state keep It is constant.
For example, the verifying and latch of L13 (Gray code " 0100 ") may include following operation:
A) BUS charging BUS=1, draws high TDL=1.
B) BUS charging BUS=1, reads BDL, then draw high TDL=1.If BDL=1, then TDL=0；Otherwise TDL=1.
C) BUS charging BUS=1, reads ADL, CDL, DDL, SDL, TDL, draws high ADL=1, CDL=1, DDL=1.If ADL =0, CDL=0, DDL=0, SDL=0, TDL=0, then ADL=1, CDL=1, DDL=1；Otherwise ADL=0, CDL=0, DDL =0.
In method 8000, the acceleration coding codeword of verifying voltage L13 is " 1101 ", and method 8000 includes: step S8071 verifies pulse L13 (that is, verifying voltage L13) to programmed storage unit；Step S8072, to programmed storage The latch of unit execution pulse L13；Step S8073, one " 0 " of detection (that is, detection CDL=0)；And step S8074, it will expire Sufficient above-mentioned steps S8073 and " 1111 " are latched as by the data latches group of the storage unit of the verifying of verifying voltage L13 (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, it will not meet above-mentioned steps It S8073 and/or is remained unchanged not over the state of data latches group of the storage unit of the verifying of verifying voltage L13.
For example, the verifying and latch of L13 (accelerating coding " 1101 ") may include following operation: BUS charging BUS=1 is read CDL, SDL, then draw high CDL=1.If CDL=0, SDL=0, then CDL=1, otherwise CDL=0.
In method 800, the Gray code code word of verifying voltage L14 is " 0110 ", method 800 further include: step S875, Pulse L14 (that is, verifying voltage L14) is verified to programmed storage unit；Step S876 executes programmed storage unit The latch of pulse L14；Step S877, two " 0 " of detection (that is, detection ADL=DDL=0)；And step S878, it will be in satisfaction It states step S877 and " 1111 " is latched as (that is, number by the data latches group of the storage unit of the verifying of verifying voltage L14 ADL=1, BDL=1, CDL=1, DDL=1 are latched as according to latch group)；Also, will not meet above-mentioned steps S877 and/ Or it is remained unchanged not over the state of data latches group of the storage unit of the verifying of verifying voltage L14.
For example, the verifying and latch of L14 (Gray code " 0110 ") may include following operation:
A) BUS charging BUS=1, draws high TDL=1.
B) BUS charging BUS=1, reads BDL, then draw high TDL=1.If BDL=1, then TDL=0；Otherwise TDL=1.
C) BUS charging BUS=1, reads CDL, then draw high TDL=1.If CDL=1, then TDL=0；Otherwise TDL=1.
D) BUS charging BUS=1, reads ADL, DDL, SDL, TDL, draws high ADL=1, DDL=1.If ADL=0, DDL=0, SDL=0, TDL=0, then ADL=1, DDL=1；Otherwise ADL=0, DDL=0.
In method 8000, the acceleration coding codeword of verifying voltage L14 is " 1110 ", method 8000 further include: step S8075 verifies pulse L14 (that is, verifying voltage L14) to programmed storage unit；Step S8076, to programmed storage The latch of unit execution pulse L14；Step S8077, one " 0 " of detection (that is, detection DDL=0)；And step S8078, it will expire Sufficient above-mentioned steps S8077 and " 1111 " are latched as by the data latches group of the storage unit of the verifying of verifying voltage L14 (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, it will not meet above-mentioned steps It S8077 and/or is remained unchanged not over the state of data latches group of the storage unit of the verifying of verifying voltage L14.
For example, the verifying and latch of L14 (accelerating coding " 1110 ") may include following operation: BUS charging BUS=1 is read DDL, SDL, then draw high DDL=1.If DDL=0, SDL=0, then DDL=1, otherwise DDL=0.
Referring to Fig. 8 H, in method 800, the Gray code code word of verifying voltage L15 is " 0111 ", and method 800 includes: step Rapid S879 verifies pulse L15 (that is, verifying voltage L15) to programmed storage unit；Step S880, to programmed storage The latch of unit execution pulse L15；Step S881, one " 0 " of detection (that is, detection ADL=0)；And step S882, it will meet Above-mentioned steps S881 and by the data latches group of the storage unit of the verifying of verifying voltage L15 be latched as " 1111 " (that is, Data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, it will not meet above-mentioned steps S881 And/or it is remained unchanged not over the state of data latches group of the storage unit of the verifying of verifying voltage L15.
For example, the verifying and latch of L15 (Gray code " 0111 ") may include following operation:
A) BUS charging BUS=1, draws high TDL=1.
B) BUS charging BUS=1, reads BDL, then draw high TDL=1.If BDL=1, then TDL=0；Otherwise TDL=1.
C) BUS charging BUS=1, reads CDL, then draw high TDL=1.If CDL=1, then TDL=0；Otherwise TDL=1.
D) BUS charging BUS=1, reads DDL, then draw high TDL=1.If DDL=1, then TDL=0；Otherwise TDL=1.
E) BUS charging BUS=1, reads ADL, SDL, TDL, draws high ADL=1.If ADL=0, SDL=0, TDL=0, then ADL =1；Otherwise ADL=0.
In method 8000, the acceleration coding codeword of verifying voltage L15 is " 0111 ", and method 8000 includes: step S8079 verifies pulse L15 (that is, verifying voltage L15) to programmed storage unit；Step S8080, to programmed storage The latch of unit execution pulse L15；Step S8081, one " 0 " of detection (that is, detection ADL=0)；And step S8082, it will expire Sufficient above-mentioned steps S8081 and " 1111 " are latched as by the data latches group of the storage unit of the verifying of verifying voltage L15 (that is, data latches group is latched as ADL=1, BDL=1, CDL=1, DDL=1)；Also, it will not meet above-mentioned steps It S8081 and/or is remained unchanged not over the state of data latches group of the storage unit of the verifying of verifying voltage L15.
For example, the verifying and latch of L15 (accelerating coding " 0111 ") may include following operation: BUS charging BUS=1 is read ADL, SDL, then draw high ADL=1.If ADL=0, SDL=0, then ADL=1, otherwise ADL=0.
Figure 10 is a kind of schematic frame of the more program bits devices 1000 for nand memory that the embodiment of the present disclosure provides Figure.As shown in Figure 10, device 1000 may include writing module 1002, transcoding module 1004, data scanning module 1006, Programming module 1008, latches scan module 1012, confirmation scan module 1014 and judgment module at programming authentication module 1010 1016。
Writing module 1002 is for programmed multi-bit data to be written in data latches group, the multi-bit According to for Gray code codeword.Writing module 1002 can 402 run memory 404 of processor in controller 102 as shown in Figure 4 The program instruction of middle storage is realized, and can execute more program bits sides of the nand memory according to the embodiment of the present disclosure Step S502 in method 500.
Transcoding module 1004 is used to the multi-bit data being converted to acceleration coding codeword from Gray code codeword.It compiles The program that code conversion module 1004 can store in 402 run memory 404 of processor in controller 102 as shown in Figure 4 Instruction can execute the step in more program bits methods 500 according to the nand memory of the embodiment of the present disclosure to realize Rapid S504.
Data scanning module 1006 is used to scan the data latches group to determine that storage information is the number of erase status It is not the data latches group of erase status according to latch group and storage information, will be locked with storage information for the data of erase status The corresponding storage unit of storage group is set as not programming state, and the data latch that with storage information will not be erase status The corresponding storage unit of device group is set as programming state, wherein needing the programmed storage unit is to be arranged to compile The storage unit of journey state.Data scanning module 1006 can the operation of processor 402 in controller 102 as shown in Figure 4 deposit The program instruction stored in reservoir 404 realizes, and can execute more comparing according to the nand memory of the embodiment of the present disclosure Step S506 in special programmed method 500.
Programming module 1008 is used for needing programmed storage unit to be programmed in storage array.Programming module 1008 The program instruction that can store in 402 run memory 404 of processor in controller 102 as shown in Figure 4 realizes, and The step S510 in more program bits methods 500 according to the nand memory of the embodiment of the present disclosure can be executed.
Authentication module 1010 is programmed to be used to execute programming verification operation to programmed each storage unit.Programming verifying The program instruction that module 1010 can store in 402 run memory 404 of processor in controller 102 as shown in Figure 4 comes Realize, and can execute the step S512 in more program bits methods 500 according to the nand memory of the embodiment of the present disclosure, Behaviour is verified in the programming programmed in verification operation and Fig. 8 A-8H in Fig. 6 A in the programming verification operation, Fig. 7 A-7M of method 600 Make.
Scan module 1012 is latched to be used to execute latch scan operation to programmed each storage unit.Latch scanning The program instruction that module 1012 can store in 402 run memory 404 of processor in controller 102 as shown in Figure 4 comes Realize, and can execute the step S514 in more program bits methods 500 according to the nand memory of the embodiment of the present disclosure, The volume of method 600 latches scan operation, the latch scan operation in Fig. 7 A-7M and the latch scanning in Fig. 8 A-8H in Fig. 6 A Operation.
Confirm that scan module 1014 is used to execute confirmation scan operation to programmed each storage unit.Confirmation scanning The program instruction that module 1014 can store in 402 run memory 404 of processor in controller 102 as shown in Figure 4 comes Realize, and can execute the step S516 in more program bits methods 500 according to the nand memory of the embodiment of the present disclosure, The confirmation scan operation and the confirmation scan operation in Fig. 7 A-7M of method 600 in Fig. 6 A.
Judgment module 1016 is used for, and is being executed using one or more verifying voltages to programmed each storage unit After programming verification operation, latching scan operation and confirmation scan operation, determines and need programmed each storage unit In whether there are one or multiple storage units respective target threshold voltage has not yet been reached in this programming.If there are also one A or multiple storage units have not yet been reached respective target threshold voltage in this programming, and the programming module 1008 is to described One or more storage units are programmed again；The programming authentication module 1010 holds one or more of storage units Row programming verification operation；The latch scan module 1012 executes one or more of storage units and latches scan operation； And the confirmation scan module 1014 executes confirmation scan operation to one or more of storage units.The judgment module 1016 program instructions that can be stored in 402 run memory 404 of processor in controller 102 as shown in Figure 4 realize, And can execute the step S518 in more program bits methods 500 according to the nand memory of the embodiment of the present disclosure and S520。
In some implementations, the programming authentication module 1010 executes programming verifying to programmed each storage unit Operation, comprising: the first verifying voltage of selection, and verify and be incorporated into the voltage of each storage unit and whether reach described first Verifying voltage.The latch scan module 1012 executes programmed each storage unit and latches scan operation, comprising: will By the programming verifying of first verifying voltage and target threshold voltage is the storage unit of first verifying voltage Data latches group is set as latch mode；And by not by first verifying voltage programming verifying and/or target threshold Threshold voltage is not that the state of the data latches group of the storage unit of first verifying voltage remains unchanged.The confirmation scanning Module 1014 executes confirmation scan operation to programmed each storage unit, comprising: is to latch for data latches group The storage unit of state is judged that latch is set as successfully latch mode, and is not to latch for data latches group The storage unit of state is judged that latch is set as latching unsuccessful state.
For example, the latch scan module 1012 will pass through the programming verifying of first verifying voltage and targets threshold Voltage is that the data latches of the storage unit of first verifying voltage are set as latch mode, and will not pass through described the The programming verifying of one verifying voltage and/or target threshold voltage are not that the data of the storage unit of first verifying voltage latch The state of device remains unchanged, comprising: in the acceleration coding codeword for detecting the corresponding data latches group storage of the storage unit The quantity of " 0 " and the position quantity and position phase one for accelerating " 0 " in coding codeword whether corresponding with first verifying voltage It causes, and detects whether voltage verification latch corresponding with the storage unit is to pass through state；If the storage unit The quantity of " 0 " and position are corresponding with first verifying voltage in the acceleration coding codeword of corresponding data latches group storage Accelerate the quantity of " 0 " and position in coding codeword consistent, and the corresponding voltage verification latch of the storage unit is to pass through State, it is latch mode that data latches group corresponding with the storage unit, which is arranged,；And if the storage unit is corresponding Data latches group storage acceleration coding codeword in " 0 " the acceleration corresponding with first verifying voltage of quantity and position The quantity of " 0 " and position is inconsistent and/or the corresponding voltage verification latch of the storage unit is not pass through in coding codeword State keeps data latches group state corresponding with the storage unit constant.
For example, the value of the voltage verification latch is " 1 " when the voltage verification latch is not pass through state. When the voltage verification latch is to pass through state, the value of the voltage verification latch is " 0 ".The latch scan module In the acceleration coding codeword of the corresponding data latches group storage of the 1012 detection storage units quantity of " 0 " and position whether with First verifying voltage is corresponding to accelerate the quantity of " 0 " and position in coding codeword consistent, and it is single to detect the storage Whether the corresponding voltage verification latch of member is to pass through state, comprising: is charged to bus；Read the storage unit, And the value for accelerating the corresponding data latches in position of " 0 " in coding codeword corresponding with first verifying voltage, with And read the value of voltage verification latch corresponding with the storage unit；Draw high the data latches being read, wherein If the value for the data latches being read and the value of the voltage verification latch are " 0 ", and storage unit is stated Corresponding data latches group is set as latch mode；If value and/or the voltage of the data latches being read Verifying at least one in the value of latch is not " 0 ", and data latches group state corresponding with the storage unit remains unchanged.
For example, the programming authentication module 1010 executes programming verification operation to programmed each storage unit, also Include: selection the second verifying voltage, and verify be incorporated into each storage unit voltage whether reach it is described second verifying Voltage.The latch scan module 1012 executes programmed each storage unit and latches scan operation, further includes: will lead to The programming verifying of second verifying voltage and target threshold voltage are crossed as the number of the storage unit of second verifying voltage Latch mode is set to according to latch group；And the programming verifying of second verifying voltage and/or targets threshold electricity will not passed through Pressure is not that the state of the data latches group of the storage unit of second verifying voltage remains unchanged.The confirmation scan module 1014 pairs of programmed each storage units execute confirmation scan operation, further includes: are to latch shape for data latches group The storage unit of state is judged that latch is set as successfully latch mode；It and is not to latch shape for data latches group The storage unit of state is judged that latch is set as latching unsuccessful state.
In addition, additionally providing a kind of storage medium according to the embodiment of the present disclosure, storing program on said storage Instruction, when described program instruction is run by computer or processor for execute the embodiment of the present disclosure nand memory it is more The corresponding steps of program bits method and/or other methods, and for realizing according to the nand memory of the embodiment of the present disclosure More program bits devices in corresponding module.The storage medium for example may include the storage card of smart phone, plate electricity The storage unit of brain, the hard disk of personal computer, read-only memory (ROM), Erasable Programmable Read Only Memory EPROM (EPROM), Portable compact disc read-only memory (CD-ROM), any combination of USB storage or above-mentioned storage medium.
Although describing example embodiment by reference to attached drawing here, it should be understood that above example embodiment are only exemplary , and be not intended to the scope of the present disclosure limited to this.Those of ordinary skill in the art can carry out various changes wherein And modification, without departing from the scope of the present disclosure and spirit.All such changes and modifications are intended to be included in appended claims Within required the scope of the present disclosure.

Claims (14)

1. a kind of more program bits methods of nand memory, comprising:
Data latches group is written into programmed multi-bit data, the multi-bit data is Gray code codeword；
By accelerating coding that the multi-bit data is converted to acceleration coding codeword from the Gray code codeword；
To needing programmed storage unit to be programmed in storage array；
Programming verification operation is executed to programmed each storage unit；
Programmed each storage unit is executed and latches scan operation；And
Confirmation scan operation is executed to programmed each storage unit；
Wherein, the acceleration coding includes encoding to multiple voltage class, wherein the corresponding acceleration coding of low-voltage-grade The number of " 0 " that includes in code word is no less than the number of corresponding " 0 " for accelerating to include in coding codeword of voltage levels；And
For the voltage class including equal " 0 " number, by converting Gray code codeword corresponding with the voltage class most A small number of purpose data latches obtain the acceleration coding codeword of the voltage class.
2. the method for claim 1, wherein
Executing programming verification operation to programmed each storage unit includes:
It selects the first verifying voltage, and verifies and be incorporated into the voltage of each storage unit and whether reach the first verifying electricity Pressure；
Executing latch scan operation to programmed each storage unit includes:
By the storage by the programming verifying and target threshold voltage of first verifying voltage for first verifying voltage The data latches group of unit is set as latch mode, and will not by the programming verifying of first verifying voltage and/or Target threshold voltage is not that the state of the data latches group of the storage unit of first verifying voltage remains unchanged；
Executing confirmation scan operation to programmed each storage unit includes:
It is the storage unit of latch mode for data latches group, is judged that latch is set as successfully latch mode, with And be not the storage unit of latch mode for data latches group, judged that latch is set as latching unsuccessful state.
3. method according to claim 2, wherein the programming verifying of first verifying voltage and targets threshold will be passed through Voltage is that the data latches group of the storage unit of first verifying voltage is set as latch mode, and will not pass through described The programming verifying of first verifying voltage and/or target threshold voltage are not the data locks of the storage unit of first verifying voltage The state of storage group remains unchanged, comprising:
Whether detect in the acceleration coding codeword of the storage unit corresponding data latches group storage the quantity of " 0 " and position It is corresponding with first verifying voltage to accelerate the quantity of " 0 " and position in coding codeword consistent, and detect the storage Whether the corresponding voltage verification latch of unit is to pass through state；
If the quantity of " 0 " and position and institute in the acceleration coding codeword of the corresponding data latches group storage of the storage unit It is consistent to state the quantity of " 0 " and position in the corresponding acceleration coding codeword of the first verifying voltage, and the storage unit is corresponding Voltage verification latch is by state, and it is latch mode that data latches group corresponding with the storage unit, which is arranged,；And
If the quantity of " 0 " and position and institute in the acceleration coding codeword of the corresponding data latches group storage of the storage unit State that the first verifying voltage is corresponding to accelerate the quantity of " 0 " in coding codeword and position is inconsistent and/or the storage unit is corresponding Voltage verification latch be to keep the state of data latches group corresponding with the storage unit constant not by state.
4. method as claimed in claim 3, wherein
When the voltage verification latch is not pass through state, the value of the voltage verification latch is " 1 "；
When the voltage verification latch is to pass through state, the value of the voltage verification latch is " 0 "；And
Whether detect in the acceleration coding codeword of the storage unit corresponding data latches group storage the quantity of " 0 " and position It is corresponding with first verifying voltage to accelerate the quantity of " 0 " and position in coding codeword consistent, and detect the storage Whether the corresponding voltage verification latch of unit is to pass through state, comprising:
It charges to bus；
Read the storage unit and corresponding with the position of " 0 " in the acceleration coding codeword of first verifying voltage Data latches value, and read the value of corresponding with storage unit voltage verification latch；
The data latches being read are drawn high,
Wherein, if the value for the data latches being read and the value of the voltage verification latch are " 0 ", with institute It states the corresponding data latches group of storage unit and is arranged to latch mode；
If at least one in the value for the data latches being read and/or the value of the voltage verification latch is not The state of " 0 ", data latches group corresponding with the storage unit remains unchanged.
5. method according to claim 2, wherein
Programming verification operation is executed to programmed each storage unit further include:
It selects the second verifying voltage, and verifies and be incorporated into the voltage of each storage unit and whether reach the second verifying electricity Pressure；
Programmed each storage unit is executed and latches scan operation further include:
By the storage by the programming verifying and target threshold voltage of second verifying voltage for second verifying voltage The data latches group of unit is set as latch mode；And
It will not be second verifying voltage not by the programming verifying of second verifying voltage and/or target threshold voltage The state of the data latches group of storage unit remains unchanged；
Confirmation scan operation is executed to programmed each storage unit further include:
It is the storage unit of latch mode for data latches group, is judged that latch is set as successfully latch mode；With And
It is not the storage unit of latch mode for data latches group, is judged that latch is set as latching unsuccessful shape State.
6. the method according to any one of claims 1-5 needs programmed storage unit to carry out in storage array Before programming, further includes:
The data latches group is scanned to determine that store the data latches group that information is erase status is not with storage information The data latches group of erase status；
It will be that the corresponding storage unit of the data latches group of erase status is set as not programming state with storage information；And
It will not be that the corresponding storage unit of the data latches group of erase status is set as programming state with storage information, In, needing the programmed storage unit is to be arranged to the storage unit of programming state.
7. the method according to any one of claims 1-5, further includes:
Programming verification operation is being executed to programmed each storage unit using one or more verifying voltages, is latching and scans After operation and confirmation scan operation, the one or more storage units needed in programmed each storage unit are determined Respective target threshold voltage has not yet been reached in this programming；
One or more of storage units are programmed again；
Programming verification operation is executed to one or more of storage units；
One or more of storage units are executed and latch scan operation；And
Confirmation scan operation is executed to one or more of storage units.
8. a kind of more program bits devices of nand memory, comprising:
Writing module, for programmed multi-bit data to be written in data latches group, the multi-bit data is lattice Thunder code code word；
Transcoding module, for being compiled by accelerating coding that the multi-bit data is converted to acceleration from the Gray code codeword Code code word；
Programming module, for needing programmed storage unit to be programmed in storage array；
Authentication module is programmed, for executing programming verification operation to programmed each storage unit；
Scan module is latched, latches scan operation for executing to programmed each storage unit；And
Scan module is confirmed, for executing confirmation scan operation to programmed each storage unit；
Wherein, the acceleration coding includes encoding to multiple voltage class, wherein the corresponding acceleration coding of low-voltage-grade The number of " 0 " that includes in code word is no less than the number of corresponding " 0 " for accelerating to include in coding codeword of voltage levels；And
For the voltage class including equal " 0 " number, by converting Gray code codeword corresponding with the voltage class most A small number of purpose data latches obtain the acceleration coding codeword of the voltage class.
9. device as claimed in claim 8, wherein
The programming authentication module executes programming verification operation to programmed each storage unit, comprising:
It selects the first verifying voltage, and verifies and be incorporated into the voltage of each storage unit and whether reach the first verifying electricity Pressure；
The latch scan module executes programmed each storage unit and latches scan operation, comprising:
By the storage by the programming verifying and target threshold voltage of first verifying voltage for first verifying voltage The data latches group of unit is set as latch mode, and will not by the programming verifying of first verifying voltage and/or Target threshold voltage is not that the state of the data latches group of the storage unit of first verifying voltage remains unchanged；
The confirmation scan module executes confirmation scan operation to programmed each storage unit, comprising:
It is the storage unit of latch mode for data latches group, is judged that latch is set as successfully latch mode, with And be not the storage unit of latch mode for data latches group, judged that latch is set as latching unsuccessful state.
10. device as claimed in claim 9, wherein the latch scan module will pass through the volume of first verifying voltage Journey verifying and target threshold voltage are that the data latches of the storage unit of first verifying voltage are set as latch mode, It and will not be first verifying voltage not by the programming verifying of first verifying voltage and/or target threshold voltage The state of the data latches of storage unit remains unchanged, comprising:
Whether detect in the acceleration coding codeword of the storage unit corresponding data latches group storage the quantity of " 0 " and position It is corresponding with first verifying voltage to accelerate the quantity of " 0 " and position in coding codeword consistent, and detect and deposited with described Whether the corresponding voltage verification latch of storage unit is to pass through state；
If the quantity of " 0 " and position and institute in the acceleration coding codeword of the corresponding data latches group storage of the storage unit It is consistent to state the quantity of " 0 " and position in the corresponding acceleration coding codeword of the first verifying voltage, and the storage unit is corresponding Voltage verification latch is by state, and it is latch mode that data latches group corresponding with the storage unit, which is arranged,；And
If the quantity of " 0 " and position and institute in the acceleration coding codeword of the corresponding data latches group storage of the storage unit State that the first verifying voltage is corresponding to accelerate the quantity of " 0 " in coding codeword and position is inconsistent and/or the storage unit is corresponding Voltage verification latch be to keep data latches group state corresponding with the storage unit constant not by state.
11. device as claimed in claim 10, wherein
When the voltage verification latch is not pass through state, the value of the voltage verification latch is " 1 "；
When the voltage verification latch is to pass through state, the value of the voltage verification latch is " 0 "；And
The number for latching scan module and detecting " 0 " in the acceleration coding codeword of the corresponding data latches group of the storage unit The quantity of " 0 " and position are consistent in amount and position acceleration coding codeword whether corresponding with first verifying voltage, and Detect whether the corresponding voltage verification latch of the storage unit is to pass through state, comprising:
It charges to bus；
Read the storage unit and the position phase for accelerating " 0 " in coding codeword corresponding with first verifying voltage The value of corresponding data latches, and read the value of voltage verification latch corresponding with the storage unit；
The data latches being read are drawn high,
Wherein, if the value for the data latches being read and the value of the voltage verification latch are " 0 ", with institute It states the corresponding data latches group of storage unit and is set as latch mode；If the value for the data latches being read and/ Or at least one in the value of the voltage verification latch is not " 0 ", data latches group shape corresponding with the storage unit State remains unchanged.
12. device as claimed in claim 9, wherein
The programming authentication module executes programming verification operation to programmed each storage unit, further includes:
It selects the second verifying voltage, and verifies and be incorporated into the voltage of each storage unit and whether reach the second verifying electricity Pressure；
The latch scan module executes programmed each storage unit and latches scan operation, further includes:
By the storage by the programming verifying and target threshold voltage of second verifying voltage for second verifying voltage The data latches group of unit is set as latch mode；And
It will not be second verifying voltage not by the programming verifying of second verifying voltage and/or target threshold voltage The state of the data latches group of storage unit remains unchanged；
The confirmation scan module executes confirmation scan operation to programmed each storage unit, further includes:
It is the storage unit of latch mode for data latches group, is judged that latch is set as successfully latch mode；With And
It is not the storage unit of latch mode for data latches group, is judged that latch is set as latching unsuccessful shape State.
13. such as described in any item devices of claim 8-12, further includes:
Data scanning module determines that storage information is the data latches of erase status for scanning the data latches group Group and storage information are not the data latches groups of erase status, will be the data latches group phase of erase status with storage information Corresponding storage unit is set as not programming state, and will not be that the data latches group of erase status is opposite with storage information The storage unit answered is set as programming state, wherein needing the programmed storage unit is to be arranged to programming state Storage unit.
14. such as described in any item devices of claim 8-12, further includes:
Judgment module, for executing programming verifying to programmed each storage unit using one or more verifying voltages Operation after latching scan operation and confirmation scan operation, determines one needed in programmed each storage unit Or respective target threshold voltage has not yet been reached in multiple storage units in this programming；Wherein
The programming module programs one or more of storage units again；
The programming authentication module executes programming verification operation to one or more of storage units；
The latch scan module executes one or more of storage units and latches scan operation；And
The confirmation scan module executes confirmation scan operation to one or more of storage units.
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