CN105703750B - A kind of MLVDS driving circuit with conversion time control - Google Patents
A kind of MLVDS driving circuit with conversion time control Download PDFInfo
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- CN105703750B CN105703750B CN201410701628.4A CN201410701628A CN105703750B CN 105703750 B CN105703750 B CN 105703750B CN 201410701628 A CN201410701628 A CN 201410701628A CN 105703750 B CN105703750 B CN 105703750B
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Abstract
The invention discloses a kind of MLVDS driving circuits with conversion time control, it includes input data buffer circuit, driving stage circuit and output-stage circuit, and input data buffer circuit carries out buffered to input data, generates opposite polarity data-signal；Driving stage circuit carries out delay process to input signal by combinational logic, generates four groups for controlling the cmos signal of output stage, the signal control rear class switch of output is controlled for conversion time；Data-signal is mainly converted into the output of difference MLVDS signal by output-stage circuit, and the function of output conversion time control is realized by the Multi- Switch signal that prime generates, and is avoided output conversion time is too fast chip power noise is caused to increase, is improved noise margin.
Description
Technical field
The present invention relates to a kind of MLVDS driving circuits with conversion time control.
Background technique
The advantages that LVDS technology is with low-power consumption, high transfer rate and strong interference immunity, the heat being increasingly becoming in the communication technology
One of gate technique.LVDS bus is the same without image of Buddha RS-485 bus, so that multiple network nodes is interconnected composition one and communicates
Network, and the speed and power consumption of RS-485 bussing technique also limit it in the application of high-speed bus system, therefore multiple spot LVDS
I.e. MLVDS comes into being, and MLVDS professional standard TIA/EIA-899 has been issued in 2002.MLVDS driver needs to meet
The most slow conversion time of system bandwidth has under interested rate, and conversion time is the driving of unit time interval half
Device improves noise margin.
Summary of the invention
It is an object of the invention to overcome the deficiencies of the prior art and provide a kind of MLVDS drives with conversion time control
Dynamic circuit, realizes that the rise and fall time of output signal is controlled, and improves noise margin.
The purpose of the present invention is achieved through the following technical solutions: it includes input data buffer circuit, driving stage
Circuit and output-stage circuit, the input data buffer circuit connect driving stage circuit, for buffering to input signal, produce
Raw opposite polarity cmos signal, the driving stage circuit connection output-stage circuit, for generating the multichannel tool of control output stage
There is the control signal of phase delay relationship, the output-stage circuit output is terminated with resistance, for being converted to input signal
Rise fall time controllable MLVDS signal.
The driving stage circuit includes driving stage P1 circuit, driving stage P2 circuit, driving stage N1 circuit and driving stage N1 electricity
Road, P1 with P2 circuit structure is identical, N1 with N2 circuit structure is identical, CMOS letter P1 opposite with N2 output polarity with P2, N1
Number, and P1 and N1, P2 and N2 are the cmos signal with same time interval, for controlling the shutdown of output stage switch pipe or opening
It opens.
The output-stage circuit includes the first PMOS tube group and the second PMOS tube group, the first NMOS tube group and the second NMOS tube
Group；The first PMOS tube group includes the source electrode difference of PMOS tube MP11~MP18, MP11~MP18 that 8 sizes are gradually increased
Output stage OUTN is connected, the drain electrode of MP11~MP18 meets working power VDD respectively, and the grid of MP11~MP18 is separately connected correspondence
The signal output end for Vp11~Vp18 that driving stage P1 is generated；
The second PMOS tube group includes the source of PMOS tube MP21~MP28, MP21~MP28 that 8 sizes are gradually increased
Pole is separately connected output stage OUTP, and the drain electrode of MP21~MP28 meets working power VDD respectively, and the grid of MP21~MP28 connects respectively
Connect the signal output end for Vp21~Vp28 that corresponding driving stage P2 is generated；
The first NMOS tube group includes the source of NMOS tube MN11~MN18, MN11~MN18 that 8 sizes are gradually increased
Pole is separately connected output stage OUTN, and the drain electrode of MN11~MN18 is grounded respectively, and the grid of MN11~MN18 is separately connected corresponding drive
The signal output end for Vn11~Vn18 that dynamic grade N1 is generated；
The second NMOS tube group includes the source of NMOS tube MN21~MN28, MN21~MN28 that 8 sizes are gradually increased
Pole is separately connected output stage OUTP, and the drain electrode of MN21~MN28 is grounded respectively, and the grid of MN21~MN28 is separately connected corresponding drive
The signal output end for Vn21~Vn28 that dynamic grade N2 is generated.
The beneficial effects of the present invention are: a kind of MLVDS driving circuit with conversion time control, input data buffering electricity
Road carries out buffered to input data, generates opposite polarity data-signal；Driving stage circuit is by combinational logic to input
Signal carries out delay process, generates four groups for controlling the cmos signal of output stage, the signal control rear class switch of output is used for
Conversion time control；Data-signal is mainly converted into the output of difference MLVDS signal by output-stage circuit, is generated by prime more
Switching signal realizes the function of output conversion time control, avoids output conversion time is too fast chip power noise is caused to increase,
Improve noise margin.
Detailed description of the invention
Fig. 1 is circuit structure diagram of the present invention；
Fig. 2 driving stage circuit diagram；
Fig. 3 output-stage circuit figure；
Fig. 4 driving stage P1, N1 output signal diagram；
Fig. 5 driving stage P2, N2 output signal diagram.
Specific embodiment
Technical solution of the present invention is described in further detail with reference to the accompanying drawing, but protection scope of the present invention is not limited to
It is as described below.
As shown in Figure 1, it is a kind of with conversion time control MLVDS driving circuit, it include input data buffer circuit,
Driving stage circuit and output-stage circuit, the input data buffer circuit connect driving stage circuit, for carrying out to input signal
Buffering generates opposite polarity cmos signal, the driving stage circuit connection output-stage circuit, for generating control output stage
Multichannel has the control signal of phase delay relationship, and the output-stage circuit output is terminated with resistance, for turning input signal
It is changed to the controllable MLVDS signal of rise and fall time.
The driving stage circuit includes driving stage P1 circuit, driving stage P2 circuit, driving stage N1 circuit and driving stage N1 electricity
Road, P1 with P2 circuit structure is identical, N1 with N2 circuit structure is identical, CMOS letter P1 opposite with N2 output polarity with P2, N1
Number, and P1 and N1, P2 and N2 are the cmos signal with same time interval, for controlling the shutdown of output stage switch pipe or opening
It opens.
The output-stage circuit includes the first PMOS tube group and the second PMOS tube group, the first NMOS tube group and the second NMOS tube
Group；The first PMOS tube group includes the source electrode difference of PMOS tube MP11~MP18, MP11~MP18 that 8 sizes are gradually increased
Output stage OUTN is connected, the drain electrode of MP11~MP18 meets working power VDD respectively, and the grid of MP11~MP18 is separately connected correspondence
The signal output end for Vp11~Vp18 that driving stage P1 is generated；
The second PMOS tube group includes the source of PMOS tube MP21~MP28, MP21~MP28 that 8 sizes are gradually increased
Pole is separately connected output stage OUTP, and the drain electrode of MP21~MP28 meets working power VDD respectively, and the grid of MP21~MP28 connects respectively
Connect the signal output end for Vp21~Vp28 that corresponding driving stage P2 is generated；
The first NMOS tube group includes the source of NMOS tube MN11~MN18, MN11~MN18 that 8 sizes are gradually increased
Pole is separately connected output stage OUTN, and the drain electrode of MN11~MN18 is grounded respectively, and the grid of MN11~MN18 is separately connected corresponding drive
The signal output end for Vn11~Vn18 that dynamic grade N1 is generated；
The second NMOS tube group includes the source of NMOS tube MN21~MN28, MN21~MN28 that 8 sizes are gradually increased
Pole is separately connected output stage OUTP, and the drain electrode of MN21~MN28 is grounded respectively, and the grid of MN21~MN28 is separately connected corresponding drive
The signal output end for Vn21~Vn28 that dynamic grade N2 is generated.
Working principle of the present invention: the input signal cmos signal opposite by input data buffer circuit output polarity leads to
The Combinational Logic Control for grade of overdriving generates shutdown or unlatching that four groups of equally spaced signals are used to control rear class switching tube, with
Output stage electric current be stepped up or reduce, output signal rising and falling time can show slow variation, to reach
To the effect of control output rise and fall time.Wherein, resistance R is the resistance for terminating at output end, and resistance value is 50 Ω.Pass through control
System is so that flow through the current direction periodically-varied of resistance R, and then obtain opposite polarity MLVDS differential signal.
As shown in Fig. 2, driving stage circuit includes driving stage P1, driving stage N1, driving stage P2 and driving stage N2, wherein P1
And P2, N1 are identical as N2 circuit structure, since input data is opposite polarity signal, P1 and P2, N1 and N2 are polarity
Opposite cmos signal, and P1 and N1, P2 and N2 are the cmos signal with same time interval.
As shown in figure 3, PMOS tube parallel connection and multiple sizes that output-stage circuit is gradually increased by multiple sizes are gradually increased
NMOS tube parallel connection constitute.Wherein, PMOS tube size is gradually increased, i.e. MP11 < MP12 < MP13 < MP14 < MP15 < MP16
< MP17 < MP18, similarly, MP21~MP28, MN11~MN18, MN21~MN28 size be gradually increased, and MP11~MP18
Driving signal generated by driving stage P1, MP21~MP28 driving signal is generated by driving stage P2；The driving of MN11~MN18 is believed
It number is generated by driving stage N1, MN21~MN28 driving signal is generated by driving stage N2.It is terminated between its output end OUTN and OUTP
50 Ω resistance, electric current flow to the end OUTN by the end OUTP, and on the contrary then electric current flows to the end OUTP by the end OUTN.
As shown in figure 4, the signal for Vp11~Vp18 that driving stage P1 is generated, respectively drives the grid of MP11~MP18, drive
The signal for Vn11~Vn18 that dynamic grade N1 is generated, respectively drives the grid of MN11~MN18, it is assumed that requires OUTN output low at this time
Level, then MP11~MP18 pipe turns off, and MN11~MN18 pipe is opened, and the course of work is as follows: Vn11 first turns on MN11 pipe, together
When, Vp18 pipe turns off MP18, lags behind Vn18 since Vp12 lags behind Vp11, Vn17, pass through certain time interval,
MN12 pipe is opened, the shutdown of MP17 pipe, and so on, MP16, MP15, MP14, MP13, MP12, MP11 pipe successively turn off, MN13,
MN14, MN15, MN16, MN17, MN18 pipe are successively opened, and the end OUTN exports low level.I other words pipe sizing it is ascending by
It gradually opens, the pipe sizing simultaneously turned off is descending, with being stepped up for switching signal, exports rise or fall time meeting
Slow slope is showed, to reach the function of control output conversion time.
Similarly gained, as shown in figure 5, the signal for Vp21~Vp28 that driving stage P2 is generated, respectively drives MP21~MP28
Grid, driving stage N2 generate Vn21~Vn28 signal, respectively drive the grid of MN21~MN28, it is assumed that require at this time
OUTP exports low level, then MP21~MP28 pipe turns off, and MN21~MN28 pipe is opened, and the course of work is as follows: Vn21 is opened first
MN21 pipe is opened, meanwhile, Vp28 pipe turns off MP28, lags behind Vn28 since Vp22 lags behind Vp21, Vn27, passes through centainly
Time interval, MN22 pipe are opened, the shutdown of MP27 pipe, and so on, MP26, MP25, MP24, MP23, MP22, MP21 pipe successively close
Disconnected, MN23, MN24, MN25, MN26, MN27, MN28 pipe are successively opened, and the end OUTP exports low level.I other words pipe sizing by
It is small that gradually opening greatly, the pipe sizing simultaneously turned off is descending, with being stepped up for switching signal, output rise or under
The drop time can show slow slope, to reach the function of control output conversion time.
Claims (1)
1. it is a kind of with conversion time control MLVDS driving circuit, it is characterised in that: it include input data buffer circuit,
Driving stage circuit and output-stage circuit；The input data buffer circuit connects driving stage circuit, for carrying out to input signal
Buffering, generates opposite polarity cmos signal；The driving stage circuit connection output-stage circuit, for generating control output stage
Multichannel has the control signal of phase delay relationship；The output-stage circuit output is terminated with resistance, for turning input signal
It is changed to the controllable MLVDS signal of rise and fall time；
The output-stage circuit includes the first PMOS tube group and the second PMOS tube group, the first NMOS tube group and the second NMOS tube group；
The first PMOS tube group includes that the source electrode of PMOS tube MP11~MP18, MP11~MP18 that 8 sizes are gradually increased connect respectively
Output stage OUTN is met, the drain electrode of MP11~MP18 meets working power VDD respectively, and the grid of MP11~MP18 is separately connected corresponding drive
The signal output end for Vp11~Vp18 that dynamic grade P1 is generated；
The second PMOS tube group includes the source electrode point of PMOS tube MP21~MP28, MP21~MP28 that 8 sizes are gradually increased
Not Lian Jie the drain electrode of output stage OUTP, MP21~MP28 meet working power VDD respectively, the grid of MP21~MP28 is separately connected pair
The signal output end for the Vp21~Vp28 for answering driving stage P2 to generate；
The first NMOS tube group includes the source electrode point of NMOS tube MN11~MN18, MN11~MN18 that 8 sizes are gradually increased
Not Lian Jie the drain electrode of output stage OUTN, MN11~MN18 be grounded respectively, the grid of MN11~MN18 is separately connected corresponding driving stage
The signal output end for Vn11~Vn18 that N1 is generated；
The second NMOS tube group includes the source electrode point of NMOS tube MN21~MN28, MN21~MN28 that 8 sizes are gradually increased
Not Lian Jie the drain electrode of output stage OUTP, MN21~MN28 be grounded respectively, the grid of MN21~MN28 is separately connected corresponding driving stage
The signal output end for Vn21~Vn28 that N2 is generated；
The driving stage circuit includes driving stage P1 circuit, driving stage P2 circuit, driving stage N1 circuit and driving stage N1 circuit,
P1 with P2 circuit structure is identical, N1 with N2 circuit structure is identical, cmos signal P1 opposite with N2 output polarity with P2, N1, and
P1 and N1, P2 and N2 output are the cmos signal with same time interval, for controlling the shutdown of output stage switch pipe or opening
It opens.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410701628.4A CN105703750B (en) | 2014-11-28 | 2014-11-28 | A kind of MLVDS driving circuit with conversion time control |
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| CN201410701628.4A CN105703750B (en) | 2014-11-28 | 2014-11-28 | A kind of MLVDS driving circuit with conversion time control |
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| CN105703750A CN105703750A (en) | 2016-06-22 |
| CN105703750B true CN105703750B (en) | 2019-01-11 |
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| CN108023464B (en) * | 2017-12-26 | 2023-12-19 | 上海数明半导体有限公司 | Ultralow standby power consumption circuit for motor driving chip |
| CN115688652B (en) * | 2022-10-31 | 2023-06-09 | 正心元科技(杭州)有限公司 | Time sequence optimization method and device based on output conversion constraint and computer equipment |
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| US7786955B2 (en) * | 2004-12-22 | 2010-08-31 | Lg Electronics Inc. | Plasma display apparatus |
| CN101192183B (en) * | 2007-01-10 | 2010-09-01 | 中兴通讯股份有限公司 | Implementing method and device of digital one-board test tool equipment |
| CN101616035B (en) * | 2009-07-22 | 2011-10-05 | 浪潮电子信息产业股份有限公司 | Method for computer testing and network monitoring |
| CN103218331B (en) * | 2012-12-07 | 2015-11-11 | 浙江大学 | Synchronous mode is adopted to switch and the self-adjusting bus unit of frame priority and method |
| CN204206140U (en) * | 2014-11-28 | 2015-03-11 | 成都振芯科技股份有限公司 | A kind of have the MLVDS drive circuit controlled change-over time |
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