CN105680674A - Transmission circuit and memory circuit - Google Patents
Transmission circuit and memory circuit Download PDFInfo
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- CN105680674A CN105680674A CN201610236349.4A CN201610236349A CN105680674A CN 105680674 A CN105680674 A CN 105680674A CN 201610236349 A CN201610236349 A CN 201610236349A CN 105680674 A CN105680674 A CN 105680674A
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- voltage
- nmos tube
- transmission unit
- couples
- transmission
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
Abstract
The invention provides a transmission circuit and a memory circuit. The transmission circuit comprises a transmission unit, wherein a control end of the transmission unit receives a first voltage, and the transmission unit is suitable for transmitting a second voltage from an input end of the transmission unit to an output end of the transmission unit under the control of the first voltage; a first boost unit suitable for boosting the second voltage so as to obtain the first voltage; a load MOS tube, wherein a drain electrode of the load MOS tube is coupled with the control end of the transmission unit, a grid electrode of the load MOS tube receives a third voltage, and the third voltage is larger than a power supply voltage and smaller than the first voltage. According to the scheme provided by the invention, the voltage transmission stability of the transmission circuit in a memory is improved, and implementation is relatively easy.
Description
Technical field
The present invention relates to electronic technology field, particularly to a kind of transmission circuit and memory circuitry.
Background technology
Flash memory (Flash) is a kind of long-life non-volatile memorizer, remain to keep stored data message under powering-off state, remain to during due to its power-off preserve data, flash memory is usually used to preserve configuration information, such as preservation data etc. in the pole plate program of computer, personal digital assistant, digital camera. Flash memory can also be counted as Electrical Erasable read only memory (ElectricallyErasableProgrammableRead-OnlyMemory, EEPROM) mutation, and flash memory and EEPROM the difference is that, EEPROM can carry out deleting and rewrite in byte-level rather than whole chip is erasable, and most of chip of flash memory needs block to wipe.
Can include reading, programming and erasing to the operation of flash memory. In a flash memory, erasing voltage is generally 8V, and program voltage is generally 12V, and this requires that transmission voltage is that high-tension transmission circuit of 12V has stability, otherwise by impact to for the memorizer of flash memory be operated time stability. Transmission circuit in existing memorizer is generally adopted metal-oxide-semiconductor, for NMOS tube, if by high voltage that transmission voltage is 12V from the source electrode of NMOS tube transmit to its drain time, it is necessary to the grid of described NMOS tube is applied to be higher than the voltage of 12V so that the V of described NMOS tubeGSMore than its threshold voltage VTH, its source electrode of guarantee transmits to the effective of voltage of its drain electrode.
But, the problem that the voltage transmission stability of the transmission circuit that prior art is faced with in memorizer is poor.
Summary of the invention
Present invention solves the technical problem that the voltage transmission stability being how to improve the transmission circuit in memorizer.
For solving above-mentioned technical problem, the embodiment of the present invention provides a kind of transmission circuit, including: transmission unit, the control termination of described transmission unit receives the first voltage, described transmission unit is suitable under the control of described first voltage, and from the input of described transmission unit, the second voltage is transmitted the outfan to described transmission unit; First boosting unit, is suitable to described second voltage is boosted, to obtain described first voltage;Load metal-oxide-semiconductor, the drain electrode of described load metal-oxide-semiconductor couples the control end of described transmission unit, and the grid of described load metal-oxide-semiconductor receives tertiary voltage; Wherein, described tertiary voltage is more than supply voltage and less than described first voltage.
Alternatively, described transmission circuit also includes the second boosting unit, and described second boosting unit includes the boosting subelement of multiple cascade, is used for generating described second voltage.
Alternatively, described tertiary voltage boost described in any level subelement outfan provide.
Alternatively, described boosting subelement includes: the first switch, the first NMOS tube, the first electric capacity and phase inverter, wherein, first end of described first switch couples the first end of described boosting subelement, second end of described first switch couples the outfan of the source electrode of described first NMOS tube, the first end of described first electric capacity and described boosting subelement, and the control of described first switch receives the first clock; The grid of described first NMOS tube couples the drain electrode of described first NMOS tube and couples power supply; Second end of described first electric capacity couples the outfan of described phase inverter; The input input of described phase inverter has second clock.
Alternatively, the source electrode of described load metal-oxide-semiconductor is via switch element ground connection, and the control of described switch element terminates to receive and enables signal, under the effect of described enable signal, and the path on the source electrode formation of described load metal-oxide-semiconductor or disconnection and ground.
Alternatively, described switch element includes: the second NMOS tube, and the grid of described second NMOS tube couples the control end of described switch element, the source ground of described second NMOS tube, and the drain electrode of described 2nd NMOS couples the source electrode of described load metal-oxide-semiconductor.
Alternatively, described transmission unit includes: the 3rd NMOS tube, the grid of described 3rd NMOS tube couples the control end of described transmission unit, and the drain electrode of described 3rd NMOS tube couples the input of described transmission unit, and the source electrode of described 3rd NMOS tube couples the outfan of described transmission unit.
Alternatively, described first boosting unit is charge pump circuit.
Alternatively, described tertiary voltage range for described first voltage 20% to 80% between.
For solving above-mentioned technical problem, the embodiment of the present invention also provides for a kind of memory circuitry, including above-described transmission circuit.
Compared with prior art, the technical scheme of the embodiment of the present invention has the advantages that
The present embodiment is by controlling the size of tertiary voltage, described tertiary voltage is more than supply voltage and less than described first voltage, pressure reduction between the grid of the load metal-oxide-semiconductor in the present embodiment and drain electrode is minimized, such that it is able to be effectively reduced the GIDL electric current of load metal-oxide-semiconductor described in transmission circuit, advantageously reduce the electric leakage of the node residing for described first voltage of described load metal-oxide-semiconductor, the stability making described first voltage strengthens, thus the voltage transmission stability of the transmission circuit improved in memorizer.
Furthermore, the present embodiment, by producing described tertiary voltage for the second boosting unit producing described second voltage in memory circuitry, there is no and is required to be described tertiary voltage and additionally introduces reference voltage source, be easier to implement.
Accompanying drawing explanation
Fig. 1 is the schematic block diagram of the transmission circuit in a kind of existing memory circuitry.
Fig. 2 is the structured flowchart of a kind of transmission circuit of the embodiment of the present invention.
Fig. 3 is the structured flowchart of embodiment of the present invention another kind transmission circuit.
Fig. 4 is the structured flowchart of another transmission circuit of the embodiment of the present invention.
Fig. 5 is the structured flowchart of the second boosting unit described in the embodiment of the present invention.
Fig. 6 is the circuit diagram of the second boosting unit described in the embodiment of the present invention.
Detailed description of the invention
As described in the background section, the problem that the voltage transmission stability of the transmission circuit that prior art is faced with in memorizer is poor.
Prior art has been analyzed by present inventor. Fig. 1 is the schematic block diagram of the transmission circuit in a kind of existing memory circuitry. As it is shown in figure 1, in the prior art, transmission circuit 100 may include that the first boosting unit 11, transmission unit 12 and load metal-oxide-semiconductor MN1. Wherein, the control termination of described transmission unit 12 receives the first voltage V1, and described transmission unit 12 is suitable under the control of described first voltage V1, and from the input of described transmission unit 12, second voltage V2 is transmitted the outfan to described transmission unit; Described first boosting unit 11 is suitable to described second voltage V2 is boosted, to obtain described first voltage V1; The drain electrode of described load metal-oxide-semiconductor MN1 couples the control end of described transmission unit 12, and the grid of described load metal-oxide-semiconductor MN1 receives supply voltage Vddq. Wherein, described transmission unit 12 can be NMOS tube, and described first boosting unit 11 can be electric charge pump.
In metal-oxide-semiconductor, grid induced drain leakage current (Gated-induceDrainLeakage, GIDL) is bigger to the reliability effect of metal-oxide-semiconductor. As the grid leak crossover region place drain-to-gate voltage V in metal-oxide-semiconductorDGTime very big, in crossover region near interface silicon, electronics occurs band-to-band-tunneling to form electric current between valence band and conduction band, generally this electric current is referred to as GIDL tunnelling current. Along with gate oxide is more and more thinner, GIDL tunnelling current sharply increases.
In described transmission circuit 100, supply voltage Vddq is received owing to the grid of described load metal-oxide-semiconductor MN1 terminate, it is typically in memory circuitry, the voltage of supply voltage Vddq is relatively low, such as 1.5V, this will make the grid of load metal-oxide-semiconductor MN1 bigger with the pressure reduction of drain electrode, the GIDL electric current of load metal-oxide-semiconductor MN1 will be higher, this will make the drain voltage of load metal-oxide-semiconductor MN1 produce bigger leakage current so that the drain voltage (i.e. described first voltage V1) of load metal-oxide-semiconductor MN1 is pulled low. And the described first too low transmission stability that can affect described transmission unit (NMOS tube) of voltage V1, thus affecting the operational stability of memory circuitry.
Analyze it can be seen that the transmission circuit in memorizer is faced with the problem that voltage transmission stability is poor in prior art according to above.
The embodiment of the present invention proposes a kind of transmission circuit, by controlling the size of tertiary voltage, pressure reduction between the grid of the load metal-oxide-semiconductor in the present embodiment and drain electrode is minimized, such that it is able to be effectively reduced the GIDL electric current of load metal-oxide-semiconductor described in transmission circuit, make the electric leakage of the node residing for described first voltage of described load metal-oxide-semiconductor, the stability making described first voltage strengthens, thus the voltage transmission stability of the transmission circuit improved in memorizer.
Understandable for enabling the above-mentioned purpose of the present invention, feature and beneficial effect to become apparent from, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
Fig. 2 is the structured flowchart of a kind of transmission circuit of the embodiment of the present invention.
As in figure 2 it is shown, the transmission circuit 200 of the embodiment of the present invention may include that transmission unit the 22, first boosting unit 21 and load metal-oxide-semiconductor MN1 (only with NMOS tube for exemplifying in figure).
The control termination of described transmission unit 22 receives the first voltage V1, and described transmission unit 22 is suitable under the control of described first voltage V1, and from the input of described transmission unit 22, second voltage V2 is transmitted the outfan to described transmission unit 22; Wherein, through transmission, the voltage of the outfan of described transmission unit 22 is designated as voltage VPP.
Described first boosting unit 21 is suitable to described second voltage V2 is boosted, to obtain described first voltage V1.
The drain electrode of described load metal-oxide-semiconductor MN1 couples the control end of described transmission unit 22, and the grid of described load metal-oxide-semiconductor MN1 receives tertiary voltage V3.
Wherein, described tertiary voltage V3 is more than supply voltage and less than described first voltage V1.
It should be noted that described supply voltage Vddq is the voltage in the power supply source of each circuit unit in described transmission circuit 200, circuit devcie offer electric energy.
In being embodied as, described tertiary voltage V3 may range from described first voltage V1 20% to 80% between.
Fig. 3 is the structured flowchart of embodiment of the present invention another kind transmission circuit 200.
As shown in Figure 3, in the embodiment of the present invention, the source electrode of described load metal-oxide-semiconductor MN1 can via switch element 23 ground connection, and the control termination of described switch element 23 is received and enabled signal ENB, under the effect of described enable signal ENB, the path on the source electrode formation of described load metal-oxide-semiconductor MN1 or disconnection and ground. When enabling signal ENB and making the source electrode of load metal-oxide-semiconductor MN1 and the path on ground turn on, described first voltage V1 is pulled low, and transmission unit 22 turns off; When enabling signal ENB and making the source electrode of load metal-oxide-semiconductor MN1 and the path on ground disconnect, described first voltage V1 makes described transmission unit 22 turn on, and completes the transmission to described second voltage V2.
Fig. 4 is the structured flowchart of another transmission circuit 200 of the embodiment of the present invention.
As shown in Figure 4, in being embodied as, described switch element 23 may include that the second NMOS tube MN2, the grid of described second NMOS tube MN2 couples the control end of described switch element 23, the source ground of described second NMOS tube MN2, the drain electrode of described 2nd NMOS couples the source electrode of load metal-oxide-semiconductor MN1.
It should be noted that, described switch element 23 is only for described second NMOS tube MN2, but it is not limited thereto, described switch element 23 can also adopt other switching devices, such as PMOS, audion, or the combination of other any controlled electrical parts opened or turn off or electrical part, the present embodiment does not carry out particular restriction.
In being embodied as, described transmission unit 22 may include that the 3rd NMOS tube MN3, the grid of described 3rd NMOS tube MN3 couples the control end of described transmission unit 22, the drain electrode of described 3rd NMOS tube MN3 couples the input of described transmission unit 22, and the source electrode of described 3rd NMOS tube MN3 couples the outfan of described transmission unit 22.
It should be noted that, described transmission unit 22 is only for described 3rd NMOS tube MN3, described transmission unit 22 can also adopt other controlled and that voltage signal is transmitted circuit units to realize, such as transmission gate, and it is possible to its control signal is adjusted by detailed description of the invention according to described transmission unit 22 accordingly.
In being embodied as, described first boosting unit 21 can be charge pump circuit. Additionally, described first boosting unit 21 can also be any DC-to-dc change-over circuit with boost function; Further, the parameter such as ripple of the described first voltage V1 that described first boosting unit 21 is exported by the present embodiment does not carry out particular restriction.
In the embodiment of the present invention, described transmission circuit 200 can also include the second boosting unit. Fig. 5 is the structured flowchart of the second boosting unit described in the embodiment of the present invention, as it is shown in figure 5, described second boosting unit can include the boosting subelement of multiple cascade, it is used for generating described second voltage V2, in Figure 5, with the subelement 241 of boosting, 242,243 ...., 244 for example.
Fig. 6 is the circuit diagram of the second boosting unit described in the embodiment of the present invention.
As shown in Figure 5 and Figure 6, in being embodied as, described tertiary voltage V3 can boost described in any level subelement outfan provide.
Described second boosting unit in the embodiment of the present invention can be charge pump circuit, and described second boosting subelement can include the substructure unit of multiple cascade.
Illustrate for boosting subelement 243 in scheming. Described boosting subelement may include that the first switch SW3, the first NMOS tube N3, the first electric capacity C3 and phase inverter INV3.
Wherein, first end of described first switch SW3 couples the first end of described boosting subelement 243, second end of described first switch SW3 couples the outfan of the source electrode of described first NMOS tube N3, first end of described first electric capacity C3 and described boosting subelement 243, and the control of described first switch SW3 receives the first clock (not shown). The grid of described first NMOS tube N3 couples the drain electrode of described first NMOS tube N3 and couples power supply Vddq. Second end of described first electric capacity C3 couples the outfan of described phase inverter INV3. The input input of described phase inverter INV3 has second clock CK3.
In being embodied as, the boosting subelement of cascade 241,242,243 ...., 244 export the pump voltage gradually risen respectively. Controlled by the first clock in boosting subelement each described and second clock, electric capacity in boosting subelement can be enabled by the low level of described second clock signal and be driven, and described first clock can pass through to control the opening or turning off of switch of described boosting subelement, and then control voltage that described boosting subelement exports to the transmission of the boosting subelement of next stage.
Furthermore, the present embodiment is produced described tertiary voltage V3 by producing second boosting unit of described second voltage V2 in memory circuitry, there is no and is required to be described tertiary voltage V3 and additionally introduces reference voltage source, is easier to implement.
The embodiment of the invention also discloses a kind of memory circuitry, including above-described transmission circuit 200.
Although present disclosure is as above, but the present invention is not limited to this. Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a transmission circuit, it is characterised in that including:
Transmission unit, the control termination of described transmission unit receives the first voltage, and described transmission unit is suitable under the control of described first voltage, and from the input of described transmission unit, the second voltage is transmitted the outfan to described transmission unit;
First boosting unit, is suitable to described second voltage is boosted, to obtain described first voltage;
Load metal-oxide-semiconductor, the drain electrode of described load metal-oxide-semiconductor couples the control end of described transmission unit, and the grid of described load metal-oxide-semiconductor receives tertiary voltage;
Wherein, described tertiary voltage is more than supply voltage and less than described first voltage.
2. transmission circuit according to claim 1, it is characterised in that also including the second boosting unit, described second boosting unit includes the boosting subelement of multiple cascade, is used for generating described second voltage.
3. transmission circuit according to claim 2, it is characterised in that described tertiary voltage boost described in any level subelement outfan provide.
4. transmission circuit according to claim 2, it is characterised in that described boosting subelement includes: the first switch, the first NMOS tube, the first electric capacity and phase inverter, wherein,
First end of described first switch couples the first end of described boosting subelement, second end of described first switch couples the outfan of the source electrode of described first NMOS tube, the first end of described first electric capacity and described boosting subelement, and the control of described first switch receives the first clock;
The grid of described first NMOS tube couples the drain electrode of described first NMOS tube and couples power supply;
Second end of described first electric capacity couples the outfan of described phase inverter;
The input input of described phase inverter has second clock.
5. transmission circuit according to claim 1, it is characterized in that, the source electrode of described load metal-oxide-semiconductor is via switch element ground connection, and the control termination of described switch element is received and enabled signal, under the effect of described enable signal, the path on the source electrode formation of described load metal-oxide-semiconductor or disconnection and ground.
6. transmission circuit according to claim 5, it is characterized in that, described switch element includes: the second NMOS tube, the grid of described second NMOS tube couples the control end of described switch element, the source ground of described second NMOS tube, the drain electrode of described 2nd NMOS couples the source electrode of described load metal-oxide-semiconductor.
7. transmission circuit according to claim 1, it is characterized in that, described transmission unit includes: the 3rd NMOS tube, the grid of described 3rd NMOS tube couples the control end of described transmission unit, the drain electrode of described 3rd NMOS tube couples the input of described transmission unit, and the source electrode of described 3rd NMOS tube couples the outfan of described transmission unit.
8. transmission circuit according to claim 1, it is characterised in that described first boosting unit is charge pump circuit.
9. the transmission circuit according to any one of claim 1 to 8, it is characterised in that described tertiary voltage range for described first voltage 20% to 80% between.
10. a memory circuitry, it is characterised in that include the transmission circuit described in any one of claim 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610236349.4A CN105680674B (en) | 2016-04-15 | 2016-04-15 | Transmission circuit and memory circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610236349.4A CN105680674B (en) | 2016-04-15 | 2016-04-15 | Transmission circuit and memory circuit |
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| Publication Number | Publication Date |
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| CN105680674A true CN105680674A (en) | 2016-06-15 |
| CN105680674B CN105680674B (en) | 2019-02-01 |
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| CN201610236349.4A Active CN105680674B (en) | 2016-04-15 | 2016-04-15 | Transmission circuit and memory circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106026722A (en) * | 2016-06-28 | 2016-10-12 | 北京智芯微电子科技有限公司 | Rectification circuit and ultrahigh frequency tag with rectification circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102624222A (en) * | 2012-03-27 | 2012-08-01 | 上海宏力半导体制造有限公司 | Charge pump and charge pump system |
| CN103236789A (en) * | 2013-04-24 | 2013-08-07 | 上海宏力半导体制造有限公司 | Charge pump output voltage regulating circuit and storage device |
| JP2013188085A (en) * | 2012-03-09 | 2013-09-19 | Seiko Instruments Inc | Step-up circuit |
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2016
- 2016-04-15 CN CN201610236349.4A patent/CN105680674B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013188085A (en) * | 2012-03-09 | 2013-09-19 | Seiko Instruments Inc | Step-up circuit |
| CN102624222A (en) * | 2012-03-27 | 2012-08-01 | 上海宏力半导体制造有限公司 | Charge pump and charge pump system |
| CN103236789A (en) * | 2013-04-24 | 2013-08-07 | 上海宏力半导体制造有限公司 | Charge pump output voltage regulating circuit and storage device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106026722A (en) * | 2016-06-28 | 2016-10-12 | 北京智芯微电子科技有限公司 | Rectification circuit and ultrahigh frequency tag with rectification circuit |
| CN106026722B (en) * | 2016-06-28 | 2018-03-27 | 北京智芯微电子科技有限公司 | A kind of rectification circuit and the superfrequency label with the rectification circuit |
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| CN105680674B (en) | 2019-02-01 |
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